@W: MT532 :"d:\projects\libero_11_0_0_23\mathblock_widemult_exmp\multsynopysis_impl\extended_adder_2_input\component\work\dotp_multadd\dotp_multadd_0\dotp_multadd_dotp_multadd_0_hard_mult_addsub.vhd":113:4:113:5|Found signal identified as System clock which controls 0 sequential elements including dotp_multadd_0.U0.  Using this clock, which has no specified timing constraint, can adversely impact design performance. 
