Project Settings
Project Name Counter_44bit_syn Implementation Name synthesis
Top Module work.Counter_44bit Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
Compile InputComplete 10 36 0 - 0m:00s - 5/21/2014
7:31:39 PM
Pre-mappingComplete 3 2 0 0m:00s 0m:00s 133MB 5/21/2014
7:31:41 PM
Map & OptimizeComplete 13 1 0 0m:00s 0m:01s 133MB 5/21/2014
7:31:43 PM

Area Summary
Sequential Cells 53 DSP Blocks (MACC) (dsp_used) 1
I/O Cells 93 Global Clock Buffers 2
LUTs (total_luts) 46

Timing Summary
Clock NameReq FreqEst FreqSlack
Counter_44bit|CLK652.7 MHz554.8 MHz-0.270
System1.0 MHzNANA

Optimizations Summary
Combined Clock Conversion 1 / 0