Synopsys Generic Technology Mapper, Version mapact, Build 976R, Built May 23 2013 12:10:32 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version H-2013.03M-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 57MB) @N:MF249 : | Running in 32-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 58MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 60MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 78MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 78MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 78MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 78MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 78MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 78MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 78MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 78MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 78MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 78MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ @N:FP130 : | Promoting Net CLK_c on CLKINT I_1 @N:FP130 : | Promoting Net RSTN_c on CLKINT I_2 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 78MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 78MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 22 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId0001 CLK port 22 INA_r[10] ======================================================================================= ===== Gated/Generated Clocks ===== ************** None ************** ---------------------------------- ================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base D:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\BarrelShifter\synthesis\BarrelShifter_18bit.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 78MB) Writing EDIF Netlist and constraint files H-2013.03M-1 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 76MB peak: 78MB) @W:MT420 : | Found inferred clock BarrelShifter_18bit|CLK with period 10.00ns. Please declare a user-defined clock on object "p:CLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Oct 04 14:44:02 2013 # Top view: BarrelShifter_18bit Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 8.934 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------- BarrelShifter_18bit|CLK 100.0 MHz 938.4 MHz 10.000 1.066 8.934 inferred Inferred_clkgroup_0 System 100.0 MHz 1029.4 MHz 10.000 0.971 9.029 system system_clkgroup =============================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------- System System | 10.000 9.029 | No paths - | No paths - | No paths - BarrelShifter_18bit|CLK System | 10.000 8.934 | No paths - | No paths - | No paths - ======================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: BarrelShifter_18bit|CLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------- INA_r[0] BarrelShifter_18bit|CLK SLE Q INA_r[0] 0.094 8.934 INA_r[1] BarrelShifter_18bit|CLK SLE Q INA_r[1] 0.094 8.934 INA_r[2] BarrelShifter_18bit|CLK SLE Q INA_r[2] 0.094 8.934 INA_r[3] BarrelShifter_18bit|CLK SLE Q INA_r[3] 0.094 8.934 INA_r[4] BarrelShifter_18bit|CLK SLE Q INA_r[4] 0.094 8.934 INA_r[5] BarrelShifter_18bit|CLK SLE Q INA_r[5] 0.094 8.934 INA_r[6] BarrelShifter_18bit|CLK SLE Q INA_r[6] 0.094 8.934 INA_r[7] BarrelShifter_18bit|CLK SLE Q INA_r[7] 0.094 8.934 INA_r[8] BarrelShifter_18bit|CLK SLE Q INA_r[8] 0.094 8.934 INA_r[9] BarrelShifter_18bit|CLK SLE Q INA_r[9] 0.094 8.934 ======================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------- U1.Mult18x18_barrShift_0.U0 BarrelShifter_18bit|CLK MACC B[0] INA_r[0] 10.000 8.934 U1.Mult18x18_barrShift_0.U0 BarrelShifter_18bit|CLK MACC B[0] INA_r[0] 10.000 8.934 U1.Mult18x18_barrShift_0.U0 BarrelShifter_18bit|CLK MACC B[1] INA_r[1] 10.000 8.934 U1.Mult18x18_barrShift_0.U0 BarrelShifter_18bit|CLK MACC B[1] INA_r[1] 10.000 8.934 U1.Mult18x18_barrShift_0.U0 BarrelShifter_18bit|CLK MACC B[2] INA_r[2] 10.000 8.934 U1.Mult18x18_barrShift_0.U0 BarrelShifter_18bit|CLK MACC B[2] INA_r[2] 10.000 8.934 U1.Mult18x18_barrShift_0.U0 BarrelShifter_18bit|CLK MACC B[3] INA_r[3] 10.000 8.934 U1.Mult18x18_barrShift_0.U0 BarrelShifter_18bit|CLK MACC B[3] INA_r[3] 10.000 8.934 U1.Mult18x18_barrShift_0.U0 BarrelShifter_18bit|CLK MACC B[4] INA_r[4] 10.000 8.934 U1.Mult18x18_barrShift_0.U0 BarrelShifter_18bit|CLK MACC B[4] INA_r[4] 10.000 8.934 ============================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 1.066 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 8.934 Number of logic level(s): 0 Starting point: INA_r[0] / Q Ending point: U1.Mult18x18_barrShift_0.U0 / B[0] The start point is clocked by BarrelShifter_18bit|CLK [rising] on pin CLK The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ INA_r[0] SLE Q Out 0.094 0.094 - INA_r[0] Net - - 0.971 - 1 U1.Mult18x18_barrShift_0.U0 MACC B[0] In - 1.066 - ========================================================================================== Total path delay (propagation time + setup) of 1.066 is 0.094(8.8%) logic and 0.971(91.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------- U0.Mult18x18_0.U0 System MACC CDOUT[0] CDOUT[0] 0.000 9.029 U0.Mult18x18_0.U0 System MACC CDOUT[0] CDOUT[0] 0.000 9.029 U0.Mult18x18_0.U0 System MACC CDOUT[1] CDOUT[1] 0.000 9.029 U0.Mult18x18_0.U0 System MACC CDOUT[1] CDOUT[1] 0.000 9.029 U0.Mult18x18_0.U0 System MACC CDOUT[2] CDOUT[2] 0.000 9.029 U0.Mult18x18_0.U0 System MACC CDOUT[2] CDOUT[2] 0.000 9.029 U0.Mult18x18_0.U0 System MACC CDOUT[3] CDOUT[3] 0.000 9.029 U0.Mult18x18_0.U0 System MACC CDOUT[3] CDOUT[3] 0.000 9.029 U0.Mult18x18_0.U0 System MACC CDOUT[4] CDOUT[4] 0.000 9.029 U0.Mult18x18_0.U0 System MACC CDOUT[4] CDOUT[4] 0.000 9.029 ======================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------- U1.Mult18x18_barrShift_0.U0 System MACC CDIN[0] CDOUT_0[0] 10.000 9.029 U1.Mult18x18_barrShift_0.U0 System MACC CDIN[0] CDOUT_0[0] 10.000 9.029 U1.Mult18x18_barrShift_0.U0 System MACC CDIN[1] CDOUT_0[1] 10.000 9.029 U1.Mult18x18_barrShift_0.U0 System MACC CDIN[1] CDOUT_0[1] 10.000 9.029 U1.Mult18x18_barrShift_0.U0 System MACC CDIN[2] CDOUT_0[2] 10.000 9.029 U1.Mult18x18_barrShift_0.U0 System MACC CDIN[2] CDOUT_0[2] 10.000 9.029 U1.Mult18x18_barrShift_0.U0 System MACC CDIN[3] CDOUT_0[3] 10.000 9.029 U1.Mult18x18_barrShift_0.U0 System MACC CDIN[3] CDOUT_0[3] 10.000 9.029 U1.Mult18x18_barrShift_0.U0 System MACC CDIN[4] CDOUT_0[4] 10.000 9.029 U1.Mult18x18_barrShift_0.U0 System MACC CDIN[4] CDOUT_0[4] 10.000 9.029 ==================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 0.971 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 9.029 Number of logic level(s): 0 Starting point: U0.Mult18x18_0.U0 / CDOUT[0] Ending point: U1.Mult18x18_barrShift_0.U0 / CDIN[0] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------- U0.Mult18x18_0.U0 MACC CDOUT[0] Out 0.000 0.000 - CDOUT[0] Net - - 0.971 - 1 U1.Mult18x18_barrShift_0.U0 MACC CDIN[0] In - 0.971 - ============================================================================================== Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for BarrelShifter_18bit Mapping to part: m2s050fbga896-1 Cell usage: CLKINT 2 uses Sequential Cells: SLE 18 uses Registers not packed on I/O Pads: 18 DSP Blocks: 2 MACC: 2 Mults I/O ports: 38 I/O primitives: 38 INBUF 20 uses OUTBUF 18 uses Global Clock Buffers: 2 Total LUTs: 0 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 33MB peak: 78MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Fri Oct 04 14:44:02 2013 ###########################################################]