Project Settings Project Name Adder_Sub_88bit_syn Implementation Name synthesis Top Module work.Adder_Sub_88bit Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time Compile Input Complete 12 1 0 - 0m:01s - 5/21/2014 7:15:59 PM Pre-mapping Complete 3 1 0 0m:00s 0m:00s 134MB 5/21/2014 7:16:00 PM Map & Optimize Complete 11 1 0 0m:01s 0m:01s 134MB 5/21/2014 7:16:02 PM Area Summary Sequential Cells 160 DSP Blocks (MACC) (dsp_used) 2 I/O Cells 250 Global Clock Buffers 2 LUTs (total_luts) 0 Timing Summary Clock Name Req Freq Est Freq Slack Adder_Sub_88bit|CLK 1.0 MHz 938.4 MHz 998.934 System 1211.1 MHz 1029.4 MHz -0.146 Optimizations Summary Combined Clock Conversion 1 / 0