@N|Running in 64-bit mode
@N: CD720 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ns
@N:"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Adder_Sub_88bit\hdl\Adder_Sub_88bit.vhd":27:7:27:21|Top entity is set to Adder_Sub_88bit.
@N: CD231 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vhd2008\std1164.vhd":913:16:913:17|Using onehot encoding for type mvl9plus ('U'="1000000000")
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Adder_Sub_88bit\hdl\Adder_Sub_88bit.vhd":27:7:27:21|Synthesizing work.adder_sub_88bit.addersub88bit_arch 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Adder_Sub_88bit\component\work\MultAdder_w_Din\MultAdder_w_Din.vhd":17:7:17:21|Synthesizing work.multadder_w_din.rtl 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Adder_Sub_88bit\component\work\MultAdder_w_Din\MultAdder_w_Din_0\MultAdder_w_Din_MultAdder_w_Din_0_HARD_MULT_ADDSUB.vhd":8:7:8:56|Synthesizing work.multadder_w_din_multadder_w_din_0_hard_mult_addsub.def_arch 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":575:10:575:12|Synthesizing smartfusion2.vcc.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":569:10:569:12|Synthesizing smartfusion2.gnd.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":695:10:695:13|Synthesizing smartfusion2.macc.syn_black_box 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Adder_Sub_88bit\component\work\MultAdder\MultAdder.vhd":17:7:17:15|Synthesizing work.multadder.rtl 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Adder_Sub_88bit\component\work\MultAdder\MultAdder_0\MultAdder_MultAdder_0_HARD_MULT_ADDSUB.vhd":8:7:8:44|Synthesizing work.multadder_multadder_0_hard_mult_addsub.def_arch 

