m255
K3
13
cModel Technology
Z0 dD:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Adder_Sub_88bit\simulation
Eadder_sub_88bit
Z1 w1381093675
Z2 DPx3 std 6 textio 0 22 5>J:;AW>W0[[dW0I6EN1Q0
Z3 DPx4 ieee 14 std_logic_1164 0 22 5=aWaoGZSMWIcH0i^f`XF1
Z4 dD:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Adder_Sub_88bit\simulation
Z5 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Adder_Sub_88bit/synthesis/Adder_Sub_88bit.vhd
Z6 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Adder_Sub_88bit/synthesis/Adder_Sub_88bit.vhd
l0
L684
VgUR<c<NEP1G3k[=6:Jcog3
Z7 OW;C;10.1c;51
31
Z8 !s108 1381093747.529000
Z9 !s90 -reportprogress|300|-93|-explicit|-work|postsynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Adder_Sub_88bit/synthesis/Adder_Sub_88bit.vhd|
Z10 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Adder_Sub_88bit/synthesis/Adder_Sub_88bit.vhd|
Z11 o-93 -explicit -work postsynth -O0
!s100 G]Ez7TiWX8^ob4N3Blb^20
!i10b 1
Adef_arch
Z12 DEx4 work 15 multadder_w_din 0 22 nKe6`ORO48Xl8KFRbOI8[1
Z13 DEx4 work 9 multadder 0 22 [iB]3Aj`D6ON;gbfl1_6S3
R2
R3
DEx4 work 15 adder_sub_88bit 0 22 gUR<c<NEP1G3k[=6:Jcog3
l904
L698
VLF_[;C2OUU==z8h<Sbd5z2
R7
31
R8
R9
R10
R11
!s100 MNjTXW3^Xb]=U_:0K=d3H0
!i10b 1
Eadder_sub_88bit_testbench
Z14 w1381093545
Z15 DPx4 ieee 15 std_logic_arith 0 22 4`Y?g_lkdn;7UL9IiJck01
Z16 DPx4 ieee 18 std_logic_unsigned 0 22 RYmj;=TK`k=k>D@Cz`zoB3
R2
R3
R4
Z17 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Adder_Sub_88bit/stimulus/Adder_Sub_88bit_testbench.vhd
Z18 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Adder_Sub_88bit/stimulus/Adder_Sub_88bit_testbench.vhd
l0
L21
VWVj8U_2Az2lS?SXB>HJ[c1
!s100 Jk_2z40VoH0z6XCMfFOU63
R7
31
!i10b 1
Z19 !s108 1381093753.941000
Z20 !s90 -reportprogress|300|-93|-explicit|-work|postsynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Adder_Sub_88bit/stimulus/Adder_Sub_88bit_testbench.vhd|
Z21 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/Adder_Sub_88bit/stimulus/Adder_Sub_88bit_testbench.vhd|
R11
Abehavioral
R15
R16
R2
R3
DEx4 work 25 adder_sub_88bit_testbench 0 22 WVj8U_2Az2lS?SXB>HJ[c1
l64
L24
V9Q?O8Dje55N=>Ug6<o98Y0
!s100 8ge<VjLhm=9fTN7I<Bzm31
R7
31
!i10b 1
R19
R20
R21
R11
Emultadder
R1
R2
R3
R4
R5
R6
l0
L232
V[iB]3Aj`D6ON;gbfl1_6S3
R7
31
R8
R9
R10
R11
!s100 g=VDEiW=cC0TAhidjlo@e0
!i10b 1
Adef_arch
Z22 DEx4 work 38 multadder_multadder_0_hard_mult_addsub 0 22 i]AL3[3MabjUP^ZKAc8ch2
R2
R3
R13
l272
L245
VIXnSIGb[NS_j>ERJ^OJb23
R7
31
R8
R9
R10
R11
!s100 emiQmUDFd@lngN=jZc`7A2
!i10b 1
Emultadder_multadder_0_hard_mult_addsub
R1
R2
R3
R4
R5
R6
l0
L8
Vi]AL3[3MabjUP^ZKAc8ch2
R7
31
R8
R9
R10
R11
!s100 C:_G4anCP2UM`iWfKfi6C0
!i10b 1
Adef_arch
R2
R3
R22
l100
L21
VdKB7ZCDI]8TnJKm?H^K:91
R7
31
R8
R9
R10
R11
!s100 oWk;DAm^3:ndH@Zne@?]n0
!i10b 1
Emultadder_w_din
R1
R2
R3
R4
R5
R6
l0
L573
VnKe6`ORO48Xl8KFRbOI8[1
R7
31
R8
R9
R10
R11
!s100 4Gm1knk4eiEbojBaiRGUi2
!i10b 1
Adef_arch
Z23 DEx4 work 50 multadder_w_din_multadder_w_din_0_hard_mult_addsub 0 22 0d2[D@;aSKCdiK2?RKAXo2
R2
R3
R12
l614
L586
VY;Vo@WQfeZWk?NiWFajL:0
R7
31
R8
R9
R10
R11
!s100 f@b]cFn0J0;oNUEg45>lH2
!i10b 1
Emultadder_w_din_multadder_w_din_0_hard_mult_addsub
R1
R2
R3
R4
R5
R6
l0
L356
V0d2[D@;aSKCdiK2?RKAXo2
R7
31
R8
R9
R10
R11
!s100 6H=MKz<3mdGD2@@[9XM<M1
!i10b 1
Adef_arch
R2
R3
R23
l449
L370
V]Lo5?O7WdB^>SRjTQ`IbT3
R7
31
R8
R9
R10
R11
!s100 `34g0zT]bJR[DIeneZJbf3
!i10b 1
