Project Settings Project Name ASLL_ASRL_syn Implementation Name synthesis Top Module work.ASLL_ASRL Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time Compile Input Complete 9 2 0 - 0m:01s - 5/21/2014 6:05:35 PM Pre-mapping Complete 3 1 0 0m:00s 0m:00s 133MB 5/21/2014 6:05:36 PM Map & Optimize Complete 11 1 0 0m:00s 0m:01s 133MB 5/21/2014 6:05:38 PM Area Summary Sequential Cells 17 DSP Blocks (MACC) (dsp_used) 1 I/O Cells 55 Global Clock Buffers 2 LUTs (total_luts) 0 Timing Summary Clock Name Req Freq Est Freq Slack ASLL_ASRL|CLK 1.0 MHz 934.0 MHz 998.929 System 1.0 MHz NA NA Optimizations Summary Combined Clock Conversion 1 / 0