#Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014 #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1 #OS: Windows 7 6.1 #Hostname: W764-TADIGADAPA #Implementation: synthesis $ Start of Compile #Wed May 21 18:05:34 2014 Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014 @N: : | Running in 64-bit mode Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : ASLL_ASRL.vhd(25) | Top entity is set to ASLL_ASRL. VHDL syntax check successful! @N:CD630 : ASLL_ASRL.vhd(25) | Synthesizing work.asll_asrl.asll_ashl_arch @N:CD630 : Mult18x18.vhd(17) | Synthesizing work.mult18x18.rtl @N:CD630 : Mult18x18_Mult18x18_0_HARD_MULT.vhd(8) | Synthesizing work.mult18x18_mult18x18_0_hard_mult.def_arch @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box Post processing for smartfusion2.vcc.syn_black_box @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box Post processing for smartfusion2.gnd.syn_black_box @N:CD630 : smartfusion2.vhd(695) | Synthesizing smartfusion2.macc.syn_black_box Post processing for smartfusion2.macc.syn_black_box Post processing for work.mult18x18_mult18x18_0_hard_mult.def_arch Post processing for work.mult18x18.rtl Post processing for work.asll_asrl.asll_ashl_arch @W:CL260 : ASLL_ASRL.vhd(90) | Pruning register bit 17 of SHIFT_VAL(17 downto 0) @W:CL247 : ASLL_ASRL.vhd(29) | Input port bit 17 of shift_inp(17 downto 0) is unused @END At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed May 21 18:05:35 2014 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09M-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Linked File: DSP Printing clock summary report in "D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\ASLL_ASRL_18bit\synthesis\ASLL_ASRL_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB) syn_allowed_resources : blockrams=69 set on top level netlist ASLL_ASRL Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group -------------------------------------------------------------------------------- ASLL_ASRL|CLK 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 System 1.0 MHz 1000.000 system system_clkgroup ================================================================================ @W:MT530 : mult18x18_mult18x18_0_hard_mult.vhd(104) | Found inferred clock ASLL_ASRL|CLK which controls 17 sequential elements including U0.Mult18x18_0.U0. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\ASLL_ASRL_18bit\synthesis\ASLL_ASRL.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 133MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed May 21 18:05:36 2014 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09M-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ @N:FP130 : | Promoting Net RSTN_c on CLKINT I_1 @N:FP130 : | Promoting Net CLK_c on CLKINT I_2 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 19 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId0001 CLK port 19 SHIFT_VAL[0] ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\ASLL_ASRL_18bit\synthesis\ASLL_ASRL.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF I-2013.09M-SP1 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) @W:MT420 : | Found inferred clock ASLL_ASRL|CLK with period 1000.00ns. Please declare a user-defined clock on object "p:CLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Wed May 21 18:05:38 2014 # Top view: ASLL_ASRL Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 998.929 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------- ASLL_ASRL|CLK 1.0 MHz 934.0 MHz 1000.000 1.071 998.929 inferred Autoconstr_clkgroup_0 System 1.0 MHz NA 1000.000 NA NA system system_clkgroup ========================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------- ASLL_ASRL|CLK System | 1000.000 998.929 | No paths - | No paths - | No paths - =============================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: ASLL_ASRL|CLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------ SHIFT_VAL[16] ASLL_ASRL|CLK SLE Q SHIFT_VAL[16] 0.094 998.929 SHIFT_VAL[0] ASLL_ASRL|CLK SLE Q SHIFT_VAL[0] 0.094 998.934 SHIFT_VAL[1] ASLL_ASRL|CLK SLE Q SHIFT_VAL[1] 0.094 998.934 SHIFT_VAL[2] ASLL_ASRL|CLK SLE Q SHIFT_VAL[2] 0.094 998.934 SHIFT_VAL[3] ASLL_ASRL|CLK SLE Q SHIFT_VAL[3] 0.094 998.934 SHIFT_VAL[4] ASLL_ASRL|CLK SLE Q SHIFT_VAL[4] 0.094 998.934 SHIFT_VAL[5] ASLL_ASRL|CLK SLE Q SHIFT_VAL[5] 0.094 998.934 SHIFT_VAL[6] ASLL_ASRL|CLK SLE Q SHIFT_VAL[6] 0.094 998.934 SHIFT_VAL[7] ASLL_ASRL|CLK SLE Q SHIFT_VAL[7] 0.094 998.934 SHIFT_VAL[8] ASLL_ASRL|CLK SLE Q SHIFT_VAL[8] 0.094 998.934 ========================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------- U0.Mult18x18_0.U0 ASLL_ASRL|CLK MACC B[16] SHIFT_VAL[16] 1000.000 998.929 U0.Mult18x18_0.U0 ASLL_ASRL|CLK MACC B[16] SHIFT_VAL[16] 1000.000 998.929 U0.Mult18x18_0.U0 ASLL_ASRL|CLK MACC B[17] SHIFT_VAL[16] 1000.000 998.929 U0.Mult18x18_0.U0 ASLL_ASRL|CLK MACC B[17] SHIFT_VAL[16] 1000.000 998.929 U0.Mult18x18_0.U0 ASLL_ASRL|CLK MACC B[0] SHIFT_VAL[0] 1000.000 998.934 U0.Mult18x18_0.U0 ASLL_ASRL|CLK MACC B[0] SHIFT_VAL[0] 1000.000 998.934 U0.Mult18x18_0.U0 ASLL_ASRL|CLK MACC B[1] SHIFT_VAL[1] 1000.000 998.934 U0.Mult18x18_0.U0 ASLL_ASRL|CLK MACC B[1] SHIFT_VAL[1] 1000.000 998.934 U0.Mult18x18_0.U0 ASLL_ASRL|CLK MACC B[2] SHIFT_VAL[2] 1000.000 998.934 U0.Mult18x18_0.U0 ASLL_ASRL|CLK MACC B[2] SHIFT_VAL[2] 1000.000 998.934 ================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 1000.000 - Propagation time: 1.071 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 998.929 Number of logic level(s): 0 Starting point: SHIFT_VAL[16] / Q Ending point: U0.Mult18x18_0.U0 / B[16] The start point is clocked by ASLL_ASRL|CLK [rising] on pin CLK The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------- SHIFT_VAL[16] SLE Q Out 0.094 0.094 - SHIFT_VAL[16] Net - - 0.977 - 2 U0.Mult18x18_0.U0 MACC B[16] In - 1.071 - ================================================================================= Total path delay (propagation time + setup) of 1.071 is 0.094(8.8%) logic and 0.977(91.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for ASLL_ASRL Mapping to part: m2s050fbga896-1 Cell usage: CLKINT 2 uses Sequential Cells: SLE 17 uses DSP Blocks: 1 MACC: 1 Mult I/O ports: 56 I/O primitives: 55 INBUF 19 uses OUTBUF 36 uses Global Clock Buffers: 2 Total LUTs: 0 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 133MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed May 21 18:05:38 2014 ###########################################################]