@W: CL260 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\ASLL_ASRL_18bit\hdl\ASLL_ASRL.vhd":90:1:90:2|Pruning register bit 17 of SHIFT_VAL(17 downto 0)  
@W: CL247 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\ASLL_ASRL_18bit\hdl\ASLL_ASRL.vhd":29:1:29:9|Input port bit 17 of shift_inp(17 downto 0) is unused 

