@N|Running in 64-bit mode
@N: CD720 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\ASLL_ASRL_18bit\hdl\ASLL_ASRL.vhd":25:7:25:15|Top entity is set to ASLL_ASRL.
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\ASLL_ASRL_18bit\hdl\ASLL_ASRL.vhd":25:7:25:15|Synthesizing work.asll_asrl.asll_ashl_arch 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\ASLL_ASRL_18bit\component\work\Mult18x18\Mult18x18.vhd":17:7:17:15|Synthesizing work.mult18x18.rtl 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\ASLL_ASRL_18bit\component\work\Mult18x18\Mult18x18_0\Mult18x18_Mult18x18_0_HARD_MULT.vhd":8:7:8:37|Synthesizing work.mult18x18_mult18x18_0_hard_mult.def_arch 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":575:10:575:12|Synthesizing smartfusion2.vcc.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":569:10:569:12|Synthesizing smartfusion2.gnd.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":695:10:695:13|Synthesizing smartfusion2.macc.syn_black_box 

