m255
K3
13
cModel Technology
Z0 dD:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\ASLL_ASRL_18bit\simulation
Easll_asrl
Z1 w1380890944
Z2 DPx3 std 6 textio 0 22 5>J:;AW>W0[[dW0I6EN1Q0
Z3 DPx4 ieee 14 std_logic_1164 0 22 5=aWaoGZSMWIcH0i^f`XF1
Z4 dD:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\ASLL_ASRL_18bit\simulation
Z5 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/ASLL_ASRL_18bit/synthesis/ASLL_ASRL.vhd
Z6 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/ASLL_ASRL_18bit/synthesis/ASLL_ASRL.vhd
l0
L321
VeJClo]hVSbR5gDR;TN<:h2
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31
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Z9 !s90 -reportprogress|300|-93|-explicit|-work|postsynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/ASLL_ASRL_18bit/synthesis/ASLL_ASRL.vhd|
Z10 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/ASLL_ASRL_18bit/synthesis/ASLL_ASRL.vhd|
Z11 o-93 -explicit -work postsynth -O0
!s100 ;[ZJJN4@7L<dGRK>P??JE3
!i10b 1
Adef_arch
Z12 DEx4 work 9 mult18x18 0 22 ?6eoE9^IlaIemon:]H;Xk2
R2
R3
DEx4 work 9 asll_asrl 0 22 eJClo]hVSbR5gDR;TN<:h2
l419
L332
VfSacKO1G>Y17R;X1XVfMd1
R7
31
R8
R9
R10
R11
!s100 n3gdXdm=FEk`@b]8U9I9Z0
!i10b 1
Easll_asrl_testbench
Z13 w1380890787
R2
R3
R4
Z14 8D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/ASLL_ASRL_18bit/stimulus/ASLL_ASRL_TESTBENCH.vhd
Z15 FD:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/ASLL_ASRL_18bit/stimulus/ASLL_ASRL_TESTBENCH.vhd
l0
L21
VWW5A?>lm12cHNgVFHlEM52
!s100 a7`K@BaP?hS8QY3Y1JKe]2
R7
31
!i10b 1
Z16 !s108 1380890963.814000
Z17 !s90 -reportprogress|300|-93|-explicit|-work|postsynth|D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/ASLL_ASRL_18bit/stimulus/ASLL_ASRL_TESTBENCH.vhd|
Z18 !s107 D:/Mathblock/SF2 DSP Application Notes/DSP Reference Guide/Ref. Guide Design Examples/VHDL/ASLL_ASRL_18bit/stimulus/ASLL_ASRL_TESTBENCH.vhd|
R11
Aasll_asrl_arch
R2
R3
DEx4 work 19 asll_asrl_testbench 0 22 WW5A?>lm12cHNgVFHlEM52
l50
L24
Vnf;I=kX_@KESALJL=KzJ_2
!s100 aUiJ8^>nk5EeM3PAcdKHT0
R7
31
!i10b 1
R16
R17
R18
R11
Emult18x18
R1
R2
R3
R4
R5
R6
l0
L232
V?6eoE9^IlaIemon:]H;Xk2
R7
31
R8
R9
R10
R11
!s100 ]W>TmEhGX68n^A<[YnzJz2
!i10b 1
Adef_arch
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R2
R3
R12
l268
L243
VBjbnBE:o4m<VmXifGjfeA3
R7
31
R8
R9
R10
R11
!s100 Emb2BdTHkN?e[XPUd35BN3
!i10b 1
Emult18x18_mult18x18_0_hard_mult
R1
R2
R3
R4
R5
R6
l0
L8
VV8XgocHjOOY?9GDNfKGQ:2
R7
31
R8
R9
R10
R11
!s100 Hz1kgZTRJ]2cHgS67h0bJ0
!i10b 1
Adef_arch
R2
R3
R19
l99
L19
V:`SLLLUeO4@3;QV7ngL>02
R7
31
R8
R9
R10
R11
!s100 ?aK]b=j6UCOF5l1SN[3@J2
!i10b 1
