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    Synopsys Generic Technology Pre-mapping, Version mapact, Build 976R, Built May 23 2013 12:10:32
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version H-2013.03M-1

    Mapper Startup Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 57MB)

    Linked File: SF2
    Printing clock  summary report in "D:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Adder_Sub_88bit\synthesis\Adder_Sub_88bit_scck.rpt" file
    @N:MF249 :  | Running in 32-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 59MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 59MB)

    Start loading timing files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 59MB)

    Finished loading timing files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 61MB)

    Clock Summary
    **************

    Start                   Requested     Requested     Clock        Clock
    Clock                   Frequency     Period        Type         Group
    --------------------------------------------------------------------------------------
    Adder_Sub_88bit|CLK     1.0 MHz       1000.000      inferred     Autoconstr_clkgroup_0
    ======================================================================================

    @W:MT530 : multadder_multadder_0_hard_mult_addsub.vhd(112) | Found inferred clock Adder_Sub_88bit|CLK which controls 160 sequential elements including U0.MultAdder_0.U0. This clock has no specified timing constraint which may adversely impact design performance.

    syn_allowed_resources : blockrams=69  set on top level netlist Adder_Sub_88bit
    Finished Pre Mapping Phase.@N: BN225 |Writing default property annotation file D:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Adder_Sub_88bit\synthesis\Adder_Sub_88bit.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:01s; Memory used current: 44MB peak: 78MB)

    Process took 0h:00m:11s realtime, 0h:00m:01s cputime
    # Mon Oct 07 03:40:35 2013

    ###########################################################]

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