--------------------------------------------------------------------------------
-- Company:
--
-- File: Fourinput_42bitAdder_TestBench.vhd
--
-- File history:
--
-- Description	  : Provides stimuls vectors to the Fourinput_42bit_Adder
--				
-- Targeted device: Family		:: SmartFusion2  
-- 					  Die		:: M2S050T
--					  Package	:: 896 FBGA
--		Author	  : PHANIKIRAN T
--------------------------------------------------------------------------------


LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY Fourinput_42bit_Adder_TestBench IS
END Fourinput_42bit_Adder_TestBench;

ARCHITECTURE behavioral OF Fourinput_42bit_Adder_TestBench IS



COMPONENT Fourinput_42bit_Adder IS
PORT (
    CLK 		: IN STD_LOGIC;
    RSTN 		: IN STD_LOGIC;

-- inputs
	INP_A 		: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
	INP_B 		: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
	INP_88b		: IN STD_LOGIC_VECTOR(87 DOWNTO 0);

	INP_D 		: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
	INP_E 		: IN STD_LOGIC_VECTOR(17 DOWNTO 0);

-- Output

   	RESULT	 	: OUT STD_LOGIC_VECTOR(43 DOWNTO 0);
	OVERFLOW_O	: OUT STD_LOGIC;
	RES1		: OUT STD_LOGIC_VECTOR(43 DOWNTO 0)

	);
END COMPONENT Fourinput_42bit_Adder;

CONSTANT clk_period : time := 10 ns;

SIGNAL clk			: STD_LOGIC:= '0';
SIGNAL reset_n		: STD_LOGIC:= '0';
SIGNAL  INP_A 		: STD_LOGIC_VECTOR(17 DOWNTO 0):=(OTHERS=> '0');
SIGNAL	INP_B 		: STD_LOGIC_VECTOR(17 DOWNTO 0):=(OTHERS=> '0');
SIGNAL	INP_88b		: STD_LOGIC_VECTOR(43 DOWNTO 0):=(OTHERS=> '0');
SIGNAL	INP_D 		: STD_LOGIC_VECTOR(17 DOWNTO 0):=(OTHERS=> '0');
SIGNAL	INP_E 		: STD_LOGIC_VECTOR(17 DOWNTO 0):=(OTHERS=> '0');

SIGNAL RESULT		: STD_LOGIC_VECTOR(43 DOWNTO 0);
SIGNAL RES1			: STD_LOGIC_VECTOR(43 DOWNTO 0);
SIGNAL OVERFLOW_O	: STD_LOGIC;

SIGNAL stop 		: STD_LOGIC := '0';	


BEGIN


UUT: Fourinput_42bit_Adder
		port map(	

				CLK 	=> CLK,
				RSTN 	=> reset_n,
				-- inputs
				INP_A		=> INP_A,	
				INP_B 		=> INP_B,
				INP_C 		=> INP_C,
				INP_D 		=> INP_D,
				INP_E 		=> INP_E,
				INP_F 		=> INP_F,

				-- Output
			   	RESULT	 	=> RESULT,
				OVERFLOW_O	=> OVERFLOW_O,
				RES1		=> RES1
         		);

--- Clock and Reset Generation 

 clk_proc : PROCESS
   			BEGIN
				IF(stop = '0')THEN
					clk <= '0';
    			    WAIT FOR clk_period/2;
					clk <= '1';
					WAIT FOR clk_period/2;
				ELSE
					clk <= '0';
				END IF;
			END PROCESS;

 stim_proc: PROCESS
			BEGIN
				reset_n <='0';
					WAIT FOR 20 ns;
				reset_n	<='1';
					WAIT;
			END PROCESS;


PROCESS
BEGIN
		WAIT UNTIL(reset_n ='1');
		WAIT UNTIL rising_edge(clk);
	INP_A	<= "011111111111111111";--1FFFF
	INP_B	<= "011111111111111111";--1FFFF
	INP_C	<= "00111111111111111111111111111111111111111111";--3FFFFFFFFFF
	INP_D	<= "011111111111111111";--1FFFF
	INP_E	<= "011111111111111111";--1FFFF
	INP_F	<= "00011111111111111111111111111111111111111111";--1FFFFFFFFFF


	--WAIT UNTIL rising_edge(clk);
	WAIT UNTIL rising_edge(clk);

	INP_A	<= "001111111111111111";--ABCD
	INP_B	<= "001111111111111111";--6789
	INP_C	<= "00000011000010101011110011011110111111101101";--030ABCDEFED
	INP_D	<= "001111111111111111";--6789
	INP_E	<= "001111111111111111";--ABCD
	INP_F	<= "00000011000010101011110011011110111111101101";--030ABCDEFED
		WAIT UNTIL rising_edge(clk);--61E292B744

		WAIT UNTIL rising_edge(clk);
		WAIT FOR 500 ns;
		WAIT UNTIL rising_edge(clk);
			stop <=  '1';
		
		report "TEST FINISHED!"
		severity failure;
		--wait;
END PROCESS;

end behavioral;

