`

    #Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014
    #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1
    #OS: Windows 7 6.1
    #Hostname: W764-TADIGADAPA

    #Implementation: synthesis

    $ Start of Compile
    #Wed May 21 18:17:19 2014

    Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    @N: : Mult32x32_SingleMACC.vhd(23) | Top entity is set to Mult32x32_SingleMACC.
    VHDL syntax check successful!
    @N:CD630 : Mult32x32_SingleMACC.vhd(23) | Synthesizing work.mult32x32_singlemacc.mult32x32_sf2_arch
    @N:CD231 : Mult32x32_SingleMACC.vhd(67) | Using onehot encoding for type state (idle="100000000")
    @W:CD638 : Mult32x32_SingleMACC.vhd(83) | Signal cdin is undriven
    @N:CD630 : acc_0.vhd(17) | Synthesizing work.acc_0.rtl
    @N:CD630 : acc_0_acc_0_0_HARD_MULT_ACC.vhd(8) | Synthesizing work.acc_0_acc_0_0_hard_mult_acc.def_arch
    @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box
    Post processing for smartfusion2.vcc.syn_black_box
    @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box
    Post processing for smartfusion2.gnd.syn_black_box
    @N:CD630 : smartfusion2.vhd(695) | Synthesizing smartfusion2.macc.syn_black_box
    Post processing for smartfusion2.macc.syn_black_box
    Post processing for work.acc_0_acc_0_0_hard_mult_acc.def_arch
    Post processing for work.acc_0.rtl
    Post processing for work.mult32x32_singlemacc.mult32x32_sf2_arch
    @N:CL201 : Mult32x32_SingleMACC.vhd(98) | Trying to extract state machine for register Curr_State
    Extracted state machine for register Curr_State
    State machine has 9 reachable states with original encodings of:
       000000001
       000000010
       000000100
       000001000
       000010000
       000100000
       001000000
       010000000
       100000000
    @END

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 18:17:19 2014

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Linked File: DSP
    Printing clock  summary report in "D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Wide Multiplier\Mult32x32\synthesis\Mult32x32_SingleMACC_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    syn_allowed_resources : blockrams=69  set on top level netlist Mult32x32_SingleMACC

    Clock Summary
    **************

    Start                        Requested     Requested     Clock        Clock
    Clock                        Frequency     Period        Type         Group
    -----------------------------------------------------------------------------------------
    Mult32x32_SingleMACC|clk     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
    System                       1.0 MHz       1000.000      system       system_clkgroup
    =========================================================================================

    @W:MT530 : acc_0_acc_0_0_hard_mult_acc.vhd(111) | Found inferred clock Mult32x32_SingleMACC|clk which controls 111 sequential elements including U1.acc_0_0.U0. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Wide Multiplier\Mult32x32\synthesis\Mult32x32_SingleMACC.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 133MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 18:17:21 2014

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Available hyper_sources - for debug and ip models
    	None Found

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Encoding state machine Curr_State[0:8] (view:work.Mult32x32_SingleMACC(mult32x32_sf2_arch))
    original code -> new code
       000000001 -> 0000
       000000010 -> 0001
       000000100 -> 0010
       000001000 -> 0011
       000010000 -> 0100
       000100000 -> 0101
       001000000 -> 0110
       010000000 -> 0111
       100000000 -> 1000
    @W:BN132 : mult32x32_singlemacc.vhd(181) | Removing instance mul_result_valid,  because it is equivalent to instance Curr_State[3]

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    @N:FP130 :  | Promoting Net reset_n_c on CLKINT  I_793
    @N:FP130 :  | Promoting Net clk_c on CLKINT  I_794

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    1 non-gated/non-generated clock tree(s) driving 107 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId0001        clk                 port                   107        Curr_State[0]
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Writing Analyst data base D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Wide Multiplier\Mult32x32\synthesis\Mult32x32_SingleMACC.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    I-2013.09M-SP1

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB)

    @W:MT420 :  | Found inferred clock Mult32x32_SingleMACC|clk with period 10.00ns. Please declare a user-defined clock on object "p:clk"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed May 21 18:17:22 2014
    #

    Top view:               Mult32x32_SingleMACC
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: 6.870

                                 Requested     Estimated     Requested     Estimated               Clock        Clock
    Starting Clock               Frequency     Frequency     Period        Period        Slack     Type         Group
    -------------------------------------------------------------------------------------------------------------------------------
    Mult32x32_SingleMACC|clk     100.0 MHz     319.5 MHz     10.000        3.130         6.870     inferred     Inferred_clkgroup_0
    System                       100.0 MHz     723.7 MHz     10.000        1.382         8.618     system       system_clkgroup
    ===============================================================================================================================

    Clock Relationships
    *******************

    Clocks                                              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ------------------------------------------------------------------------------------------------------------------------------------------
    Starting                  Ending                    |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    ------------------------------------------------------------------------------------------------------------------------------------------
    System                    Mult32x32_SingleMACC|clk  |  10.000      8.618  |  No paths    -      |  No paths    -      |  No paths    -
    Mult32x32_SingleMACC|clk  System                    |  10.000      7.337  |  No paths    -      |  No paths    -      |  No paths    -
    Mult32x32_SingleMACC|clk  Mult32x32_SingleMACC|clk  |  10.000      6.870  |  No paths    -      |  No paths    -      |  No paths    -
    ==========================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: Mult32x32_SingleMACC|clk
    ====================================

    Starting Points with Worst Slack
    ********************************

                      Starting                                                        Arrival
    Instance          Reference                    Type     Pin     Net               Time        Slack
                      Clock
    ---------------------------------------------------------------------------------------------------
    Curr_State[0]     Mult32x32_SingleMACC|clk     SLE      Q       Curr_State[0]     0.108       6.870
    Curr_State[1]     Mult32x32_SingleMACC|clk     SLE      Q       Curr_State[1]     0.108       7.140
    Curr_State[2]     Mult32x32_SingleMACC|clk     SLE      Q       Curr_State[2]     0.108       7.220
    Curr_State[3]     Mult32x32_SingleMACC|clk     SLE      Q       Curr_State[3]     0.108       7.552
    A0[0]             Mult32x32_SingleMACC|clk     SLE      Q       A0[0]             0.108       8.775
    A0[1]             Mult32x32_SingleMACC|clk     SLE      Q       A0[1]             0.108       8.775
    A0[2]             Mult32x32_SingleMACC|clk     SLE      Q       A0[2]             0.108       8.775
    A0[3]             Mult32x32_SingleMACC|clk     SLE      Q       A0[3]             0.108       8.775
    A0[4]             Mult32x32_SingleMACC|clk     SLE      Q       A0[4]             0.108       8.775
    A0[5]             Mult32x32_SingleMACC|clk     SLE      Q       A0[5]             0.108       8.775
    ===================================================================================================

    Ending Points with Worst Slack
    ******************************

                 Starting                                                  Required
    Instance     Reference                    Type     Pin     Net         Time         Slack
                 Clock
    -----------------------------------------------------------------------------------------
    A0[0]        Mult32x32_SingleMACC|clk     SLE      D       A0_4[0]     9.745        6.870
    A0[1]        Mult32x32_SingleMACC|clk     SLE      D       A0_4[1]     9.745        6.870
    A0[2]        Mult32x32_SingleMACC|clk     SLE      D       A0_4[2]     9.745        6.870
    A0[3]        Mult32x32_SingleMACC|clk     SLE      D       A0_4[3]     9.745        6.870
    A0[4]        Mult32x32_SingleMACC|clk     SLE      D       A0_4[4]     9.745        6.870
    A0[5]        Mult32x32_SingleMACC|clk     SLE      D       A0_4[5]     9.745        6.870
    A0[6]        Mult32x32_SingleMACC|clk     SLE      D       A0_4[6]     9.745        6.870
    A0[7]        Mult32x32_SingleMACC|clk     SLE      D       A0_4[7]     9.745        6.870
    A0[8]        Mult32x32_SingleMACC|clk     SLE      D       A0_4[8]     9.745        6.870
    A0[9]        Mult32x32_SingleMACC|clk     SLE      D       A0_4[9]     9.745        6.870
    =========================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.255
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.745

        - Propagation time:                      2.875
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     6.870

        Number of logic level(s):                2
        Starting point:                          Curr_State[0] / Q
        Ending point:                            A0[0] / D
        The start point is clocked by            Mult32x32_SingleMACC|clk [rising] on pin CLK
        The end   point is clocked by            Mult32x32_SingleMACC|clk [rising] on pin CLK

    Instance / Net                     Pin      Pin               Arrival     No. of
    Name                      Type     Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------
    Curr_State[0]             SLE      Q        Out     0.108     0.108       -
    Curr_State[0]             Net      -        -       1.163     -           28
    Curr_State_RNIFOE2[2]     CFG3     C        In      -         1.271       -
    Curr_State_RNIFOE2[2]     CFG3     Y        Out     0.230     1.501       -
    A0_4_sn_N_3               Net      -        -       1.062     -           34
    A0_4[0]                   CFG4     B        In      -         2.563       -
    A0_4[0]                   CFG4     Y        Out     0.153     2.716       -
    A0_4[0]                   Net      -        -       0.159     -           1
    A0[0]                     SLE      D        In      -         2.875       -
    ====================================================================================
    Total path delay (propagation time + setup) of 3.130 is 0.747(23.9%) logic and 2.383(76.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                      Starting                                 Arrival
    Instance          Reference     Type     Pin      Net      Time        Slack
                      Clock
    ----------------------------------------------------------------------------
    U1.acc_0_0.U0     System        MACC     P[0]     P[0]     0.000       8.618
    U1.acc_0_0.U0     System        MACC     P[0]     P[0]     0.000       8.618
    U1.acc_0_0.U0     System        MACC     P[1]     P[1]     0.000       8.618
    U1.acc_0_0.U0     System        MACC     P[1]     P[1]     0.000       8.618
    U1.acc_0_0.U0     System        MACC     P[2]     P[2]     0.000       8.618
    U1.acc_0_0.U0     System        MACC     P[2]     P[2]     0.000       8.618
    U1.acc_0_0.U0     System        MACC     P[3]     P[3]     0.000       8.618
    U1.acc_0_0.U0     System        MACC     P[3]     P[3]     0.000       8.618
    U1.acc_0_0.U0     System        MACC     P[4]     P[4]     0.000       8.618
    U1.acc_0_0.U0     System        MACC     P[4]     P[4]     0.000       8.618
    ============================================================================

    Ending Points with Worst Slack
    ******************************

                  Starting                                Required
    Instance      Reference     Type     Pin     Net      Time         Slack
                  Clock
    ------------------------------------------------------------------------
    Result[0]     System        SLE      D       P[0]     9.745        8.618
    Result[1]     System        SLE      D       P[1]     9.745        8.618
    Result[2]     System        SLE      D       P[2]     9.745        8.618
    Result[3]     System        SLE      D       P[3]     9.745        8.618
    Result[4]     System        SLE      D       P[4]     9.745        8.618
    Result[5]     System        SLE      D       P[5]     9.745        8.618
    Result[6]     System        SLE      D       P[6]     9.745        8.618
    Result[7]     System        SLE      D       P[7]     9.745        8.618
    Result[8]     System        SLE      D       P[8]     9.745        8.618
    Result[9]     System        SLE      D       P[9]     9.745        8.618
    ========================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.255
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.745

        - Propagation time:                      1.126
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 8.618

        Number of logic level(s):                0
        Starting point:                          U1.acc_0_0.U0 / P[0]
        Ending point:                            Result[0] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Mult32x32_SingleMACC|clk [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    U1.acc_0_0.U0      MACC     P[0]     Out     0.000     0.000       -
    P[0]               Net      -        -       1.126     -           3
    Result[0]          SLE      D        In      -         1.126       -
    =============================================================================
    Total path delay (propagation time + setup) of 1.382 is 0.255(18.5%) logic and 1.126(81.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    ---------------------------------------
    Resource Usage Report for Mult32x32_SingleMACC

    Mapping to part: m2s050tfbga896std
    Cell usage:
    CLKINT          2 uses
    CFG2           3 uses
    CFG3           7 uses
    CFG4           37 uses

    Sequential Cells:
    SLE            105 uses

    DSP Blocks:    1
     MACC:         1 Mult

    I/O ports: 132
    I/O primitives: 132
    INBUF          67 uses
    OUTBUF         65 uses

    Global Clock Buffers: 2

    Total LUTs:    47

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 134MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 18:17:22 2014

    ###########################################################]

`