----------------------------------------------------------------------
-- Created by Actel SmartDesign Fri Oct 04 18:14:13 2013
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic 
-- clock and reset pins connected.  If your design has special
-- clock/reset or testbench driver requirements then you should 
-- copy this file and modify it. 
----------------------------------------------------------------------

--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: SLL_SRL_TESTBENCH.vhd
-- File history:
--      <Revision number>: <Date>: <Comments>
--      <Revision number>: <Date>: <Comments>
--      <Revision number>: <Date>: <Comments>
--
-- Description: 
--
-- <Description here>
--
-- Targeted device: <Family::SmartFusion2> <Die::M2S050> <Package::896 FBGA>
-- Author: <Name>
--
--------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity SLL_SRL_TESTBENCH is
end SLL_SRL_TESTBENCH;

architecture behavioral of SLL_SRL_TESTBENCH is

    constant SYSCLK_PERIOD : time := 100 ns;

    signal SYSCLK : std_logic := '0';
    signal NSYSRESET : std_logic := '0';

    component ASLL_ASRL
        -- ports
        port( 
            -- Inputs
            CLK : in std_logic;
            RSTN : in std_logic;
            SHIFT_INP : in std_logic_vector(17 downto 0);

            -- Outputs
            ASLL_OP : out std_logic_vector(17 downto 0);
            ASRL_OP : out std_logic_vector(17 downto 0)

            -- Inouts

        );
    end component;

begin

    process
        variable vhdl_initial : BOOLEAN := TRUE;

    begin
        if ( vhdl_initial ) then
            -- Assert Reset
            NSYSRESET <= '0';
            wait for ( SYSCLK_PERIOD * 10 );
            
            NSYSRESET <= '1';
            wait;
        end if;
    end process;

    -- 10MHz Clock Driver
    SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );

    -- Instantiate Unit Under Test:  ASLL_ASRL
    ASLL_ASRL_0 : ASLL_ASRL
        -- port map
        port map( 
            -- Inputs
            CLK => SYSCLK,
            RSTN => NSYSRESET,
            SHIFT_INP => (others=> '0'),

            -- Outputs
            ASLL_OP => open,
            ASRL_OP => open

            -- Inouts

        );

end behavioral;

