--------------------------------------------------------------------------------
-- Company:
--
-- File			: Counter_44bit.vhd
-- File history	: VER 1.0
--      
-- Description: 
--		This design illustrates the implementation of 44-bit up down cntr and count by M  using
--       mathblock.

-- 		Targeted device: <Family :: SmartFusion2>
--					   		<Die :: M2S050> 
--						<Package :: 896 FBGA>
-- Author	: PHANIKIRAN T
--------------------------------------------------------------------------------


LIBRARY IEEE;

USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;

ENTITY Counter_44bit IS
PORT (
    CLK 		: IN STD_LOGIC;
    RSTN 		: IN STD_LOGIC;

-- Input
	LD			: IN STD_LOGIC;
	UP_DN		: IN STD_LOGIC;

	CNTBY_LDINP	: IN STD_LOGIC;-- Need to assert always to perform this operation
	LOAD_INP	: IN STD_LOGIC_VECTOR(43 DOWNTO 0);


-- Output
   	CNTR_O	 	: OUT STD_LOGIC_VECTOR(43 DOWNTO 0)
	
	);
END Counter_44bit;


ARCHITECTURE  Cntr44bit_Arch OF Counter_44bit IS

 -- COMPONENT DECLARATIONS

COMPONENT MultAcc IS
    -- Port list
    port(
        -- Inputs
        A0       : in  std_logic_vector(17 downto 0);
        B0       : in  std_logic_vector(17 downto 0);
        C        : in  std_logic_vector(43 downto 0);
        CLK      : in  std_logic;
        C_ACLR_N : in  std_logic;
        C_EN     : in  std_logic;
        C_SCLR_N : in  std_logic;
        P_ACLR_N : in  std_logic;
        P_EN     : in  std_logic;
        P_SCLR_N : in  std_logic;
        -- Outputs
        CDOUT    : out std_logic_vector(43 downto 0);
        P        : out std_logic_vector(43 downto 0)
        );
END COMPONENT MultAcc;

 -- SIGNAL DECLARATIONS


SIGNAL C_in	: STD_LOGIC_VECTOR(43 DOWNTO 0);
SIGNAL A	: STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL B	: STD_LOGIC_VECTOR(17 DOWNTO 0);

SIGNAL DFF0	: STD_LOGIC;
SIGNAL DFF1	: STD_LOGIC;

SIGNAL LDEN	: STD_LOGIC;

BEGIN

PROCESS(CLK,RSTN)
BEGIN
	IF(RSTN ='0')THEN
		DFF0	<= '0';
		DFF1	<= '0';
	ELSE
		IF(rising_edge(CLK))THEN
			DFF0 <= LD;
			DFF1 <= DFF0;
		END IF;
	END IF;
END PROCESS;


LDEN <= NOT DFF1 AND DFF0;

PROCESS(CLK,RSTN)
BEGIN
	IF(RSTN ='0')THEN
		C_in	<= (OTHERS =>'0');
	ELSE
		IF(rising_edge(CLK))THEN
			IF(CNTBY_LDINP = '1' OR LDEN = '1')THEN
				C_in <= LOAD_INP;
			ELSE
				C_in <= (OTHERS =>'0');
			END IF;	
		END IF;
	END IF;
END PROCESS;


PROCESS(CLK,RSTN)
BEGIN
	IF(RSTN ='0')THEN
		A <= (OTHERS => '0');
		B <= (OTHERS => '0');
	ELSE
		IF(rising_edge(CLK))THEN
			IF(CNTBY_LDINP = '1')THEN
				A <= (OTHERS => '0');
				B <= (OTHERS => '0');
			ELSIF(UP_DN ='1')THEN
				A <= "000000000000000001";
				B <= "000000000000000001";
			END IF;	
		END IF;
	END IF;
END PROCESS;


 UUT :MultAcc
	port map
		(
        -- Inputs
        A0    	 => A,
        B0       => B,
        C        => C_in,
        CLK      => CLK,
        C_ACLR_N => RSTN,
        C_EN     => '1',
        C_SCLR_N => '1',
        P_ACLR_N => RSTN,
        P_EN     => '1',
        P_SCLR_N => '1',
        -- Outputs
        CDOUT    => OPEN,
        P        => CNTR_O
		);

END Cntr44bit_Arch;
