`

    #Build: Synplify Pro G-2012.09M-SP1 , Build 013R, Feb 15 2013
    #install: \\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_G201209MSP1
    #OS: Windows 7 6.1
    #Hostname: W7-TADIGADAPAP

    #Implementation: synthesis

    $ Start of Compile
    #Thu Apr 25 20:57:00 2013

    Synopsys VHDL Compiler, version comp201209rcp1, Build 245R, built Feb 20 2013
    @N: :  | Running in 32-bit mode
    Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

    @N:CD720 : std.vhd(146) | Setting time resolution to ns
    @N: : Math32x32.vhd(12) | Top entity is set to Mult32x32_SF2.
    File \\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_G201209MSP1\lib\generic\smartfusion2.vhd changed - recompiling
    File D:\Projects\Libero_11_0_0_23\Mathblock_widemult_exmp\synopysis_impl\Mult32x32\component\work\acc_0\acc_0.vhd changed - recompiling
    File D:\Projects\Libero_11_0_0_23\Mathblock_widemult_exmp\synopysis_impl\Mult32x32\hdl\Math32x32.vhd changed - recompiling
    File \\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_G201209MSP1\lib\vhd2008\signed.vhd changed - recompiling
    VHDL syntax check successful!

    Compiler output is up to date.  No re-compile necessary

    @N:CD231 : std1164.vhd(913) | Using onehot encoding for type mvl9plus ('U'="1000000000")
    @N:CD630 : Math32x32.vhd(12) | Synthesizing work.mult32x32_sf2.mult32x32_sf2_arch
    @N:CD231 : Math32x32.vhd(58) | Using onehot encoding for type state (idle="100000000")
    @W:CD638 : Math32x32.vhd(74) | Signal cdin is undriven
    @N:CD630 : acc_0.vhd(17) | Synthesizing work.acc_0.rtl
    @N:CD630 : acc_0_acc_0_0_HARD_MULT_ACC.vhd(8) | Synthesizing work.acc_0_acc_0_0_hard_mult_acc.def_arch
    @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box
    Post processing for smartfusion2.vcc.syn_black_box
    @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box
    Post processing for smartfusion2.gnd.syn_black_box
    @N:CD630 : smartfusion2.vhd(695) | Synthesizing smartfusion2.macc.syn_black_box
    Post processing for smartfusion2.macc.syn_black_box
    Post processing for work.acc_0_acc_0_0_hard_mult_acc.def_arch
    Post processing for work.acc_0.rtl
    Post processing for work.mult32x32_sf2.mult32x32_sf2_arch
    @N:CL201 : Math32x32.vhd(89) | Trying to extract state machine for register Curr_State
    Extracted state machine for register Curr_State
    State machine has 9 reachable states with original encodings of:
       000000001
       000000010
       000000100
       000001000
       000010000
       000100000
       001000000
       010000000
       100000000
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Thu Apr 25 20:57:00 2013

    ###########################################################]

`
@A: : | premap output is up to date. No run necessary. To force a re-synthesis, select [Resynthesize All] in menu [Run]. Click link to view previous log file. Premap Report Linked File: Mult32x32_SF2_premap.srr @A: : | fpga_mapper output is up to date. No run necessary. To force a re-synthesis, select [Resynthesize All] in menu [Run]. Click link to view previous log file. Map & Optimize Report Linked File: Mult32x32_SF2_fpga_mapper.srr