@W: MT530 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\filters\semi- parallel fir filters\two multiplier 8-tap fir\twomult_8tap_fir\component\work\multadder\multadder_0\multadder_multadder_0_hard_mult_addsub.vhd":108:4:108:5|Found inferred clock TwoMult_8_tap_FIR|clk which controls 124 sequential elements including U0.multadder_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
