Project Settings
Project Name | Transpose_FIR_syn | Implementation Name | synthesis
Top Module | work.Transpose_FIR | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
Compile Input | Complete | 10 | 46 | 0 | - | 0m:00s | - | 5/21/2014 8:12:45 PM
Pre-mapping | Complete | 3 | 1 | 0 | 0m:00s | 0m:00s | 135MB | 5/21/2014 8:12:47 PM
Map & Optimize | Complete | 11 | 1 | 0 | 0m:01s | 0m:01s | 134MB | 5/21/2014 8:12:49 PM
Area Summary
Sequential Cells | 18 | DSP Blocks (MACC) (dsp_used) | 16
I/O Cells | 64 | Global Clock Buffers | 2
LUTs (total_luts) | 0 |  |
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
Transpose_FIR|Clk | 1.0 MHz | 920.7 MHz | 998.914
System | 1211.1 MHz | 1029.4 MHz | -0.146
Optimizations Summary
Combined Clock Conversion | 1 / 0 |  |