@W: MT530 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\wide multiplier\mult32x32_multipliemacc\hdl\mult32x32_multiplemacc.vhd":67:4:67:5|Found inferred clock Mult32x32_multipleMACC|clk which controls 256 sequential elements including Mul_result[63:0]. This clock has no specified timing constraint which may adversely impact design performance. 
