@W: MT530 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\accumulator_88bit\component\work\multadder\multadder_0\multadder_multadder_0_hard_mult_acc.vhd":112:4:112:5|Found inferred clock Accumulator_88bit|CLK which controls 176 sequential elements including U0.MultAdder_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
