@W: MT530 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\extended adder\extended_adder_2_input\component\work\dotp_multadd\dotp_multadd_0\dotp_multadd_dotp_multadd_0_hard_mult_addsub.vhd":113:4:113:5|Found inferred clock Extended_adder_2_input|clk which controls 52 sequential elements including U0.dotp_multadd_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
