-- Version: v11.1 SP2 11.1.2.19

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Mult18x18_Mult18x18_0_HARD_MULT is

    port( CDOUT : out   std_logic_vector(43 downto 0);
          INA_c : in    std_logic_vector(17 downto 1);
          CLK_c : in    std_logic
        );

end Mult18x18_Mult18x18_0_HARD_MULT;

architecture DEF_ARCH of Mult18x18_Mult18x18_0_HARD_MULT is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;
    signal nc34, nc9, nc13, nc23, nc33, nc16, nc26, nc27, nc17, 
        nc36, nc37, nc5, nc4, nc42, nc41, nc25, nc15, nc35, nc28, 
        nc18, nc38, nc1, nc2, nc22, nc12, nc21, nc11, nc3, nc32, 
        nc40, nc31, nc44, nc7, nc6, nc19, nc29, nc39, nc8, nc43, 
        nc20, nc10, nc24, nc14, nc30 : std_logic;

begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    U0 : MACC
      port map(CLK(1) => CLK_c, CLK(0) => CLK_c, A(17) => 
        GND_net_1, A(16) => GND_net_1, A(15) => GND_net_1, A(14)
         => GND_net_1, A(13) => GND_net_1, A(12) => GND_net_1, 
        A(11) => GND_net_1, A(10) => GND_net_1, A(9) => GND_net_1, 
        A(8) => GND_net_1, A(7) => GND_net_1, A(6) => GND_net_1, 
        A(5) => VCC_net_1, A(4) => GND_net_1, A(3) => GND_net_1, 
        A(2) => GND_net_1, A(1) => GND_net_1, A(0) => GND_net_1, 
        A_EN(1) => VCC_net_1, A_EN(0) => VCC_net_1, A_ARST_N(1)
         => VCC_net_1, A_ARST_N(0) => VCC_net_1, A_SRST_N(1) => 
        VCC_net_1, A_SRST_N(0) => VCC_net_1, B(17) => GND_net_1, 
        B(16) => INA_c(17), B(15) => INA_c(16), B(14) => 
        INA_c(15), B(13) => INA_c(14), B(12) => INA_c(13), B(11)
         => INA_c(12), B(10) => INA_c(11), B(9) => INA_c(10), 
        B(8) => INA_c(9), B(7) => INA_c(8), B(6) => INA_c(7), 
        B(5) => INA_c(6), B(4) => INA_c(5), B(3) => INA_c(4), 
        B(2) => INA_c(3), B(1) => INA_c(2), B(0) => INA_c(1), 
        B_EN(1) => VCC_net_1, B_EN(0) => VCC_net_1, B_ARST_N(1)
         => VCC_net_1, B_ARST_N(0) => VCC_net_1, B_SRST_N(1) => 
        VCC_net_1, B_SRST_N(0) => VCC_net_1, C(43) => GND_net_1, 
        C(42) => GND_net_1, C(41) => GND_net_1, C(40) => 
        GND_net_1, C(39) => GND_net_1, C(38) => GND_net_1, C(37)
         => GND_net_1, C(36) => GND_net_1, C(35) => GND_net_1, 
        C(34) => GND_net_1, C(33) => GND_net_1, C(32) => 
        GND_net_1, C(31) => GND_net_1, C(30) => GND_net_1, C(29)
         => GND_net_1, C(28) => GND_net_1, C(27) => GND_net_1, 
        C(26) => GND_net_1, C(25) => GND_net_1, C(24) => 
        GND_net_1, C(23) => GND_net_1, C(22) => GND_net_1, C(21)
         => GND_net_1, C(20) => GND_net_1, C(19) => GND_net_1, 
        C(18) => GND_net_1, C(17) => GND_net_1, C(16) => 
        GND_net_1, C(15) => GND_net_1, C(14) => GND_net_1, C(13)
         => GND_net_1, C(12) => GND_net_1, C(11) => GND_net_1, 
        C(10) => GND_net_1, C(9) => GND_net_1, C(8) => GND_net_1, 
        C(7) => GND_net_1, C(6) => GND_net_1, C(5) => GND_net_1, 
        C(4) => GND_net_1, C(3) => GND_net_1, C(2) => GND_net_1, 
        C(1) => GND_net_1, C(0) => GND_net_1, C_EN(1) => 
        VCC_net_1, C_EN(0) => VCC_net_1, C_ARST_N(1) => VCC_net_1, 
        C_ARST_N(0) => VCC_net_1, C_SRST_N(1) => VCC_net_1, 
        C_SRST_N(0) => VCC_net_1, P_EN(1) => VCC_net_1, P_EN(0)
         => VCC_net_1, P_ARST_N(1) => VCC_net_1, P_ARST_N(0) => 
        VCC_net_1, P_SRST_N(1) => VCC_net_1, P_SRST_N(0) => 
        VCC_net_1, FDBKSEL => GND_net_1, FDBKSEL_EN => VCC_net_1, 
        FDBKSEL_AL_N => VCC_net_1, FDBKSEL_SL_N => VCC_net_1, 
        CDSEL => GND_net_1, CDSEL_EN => VCC_net_1, CDSEL_AL_N => 
        VCC_net_1, CDSEL_SL_N => VCC_net_1, ARSHFT17 => GND_net_1, 
        ARSHFT17_EN => VCC_net_1, ARSHFT17_AL_N => VCC_net_1, 
        ARSHFT17_SL_N => VCC_net_1, SUB => GND_net_1, SUB_EN => 
        VCC_net_1, SUB_AL_N => VCC_net_1, SUB_SL_N => VCC_net_1, 
        CARRYIN => GND_net_1, SIMD => GND_net_1, DOTP => 
        GND_net_1, OVFL_CARRYOUT_SEL => GND_net_1, A_BYPASS(1)
         => VCC_net_1, A_BYPASS(0) => VCC_net_1, B_BYPASS(1) => 
        GND_net_1, B_BYPASS(0) => GND_net_1, C_BYPASS(1) => 
        VCC_net_1, C_BYPASS(0) => VCC_net_1, P_BYPASS(1) => 
        VCC_net_1, P_BYPASS(0) => VCC_net_1, FDBKSEL_BYPASS => 
        VCC_net_1, FDBKSEL_AD => GND_net_1, FDBKSEL_SD_N => 
        VCC_net_1, CDSEL_BYPASS => VCC_net_1, CDSEL_AD => 
        GND_net_1, CDSEL_SD_N => VCC_net_1, ARSHFT17_BYPASS => 
        VCC_net_1, ARSHFT17_AD => GND_net_1, ARSHFT17_SD_N => 
        VCC_net_1, SUB_BYPASS => VCC_net_1, SUB_AD => GND_net_1, 
        SUB_SD_N => VCC_net_1, CDIN(43) => GND_net_1, CDIN(42)
         => GND_net_1, CDIN(41) => GND_net_1, CDIN(40) => 
        GND_net_1, CDIN(39) => GND_net_1, CDIN(38) => GND_net_1, 
        CDIN(37) => GND_net_1, CDIN(36) => GND_net_1, CDIN(35)
         => GND_net_1, CDIN(34) => GND_net_1, CDIN(33) => 
        GND_net_1, CDIN(32) => GND_net_1, CDIN(31) => GND_net_1, 
        CDIN(30) => GND_net_1, CDIN(29) => GND_net_1, CDIN(28)
         => GND_net_1, CDIN(27) => GND_net_1, CDIN(26) => 
        GND_net_1, CDIN(25) => GND_net_1, CDIN(24) => GND_net_1, 
        CDIN(23) => GND_net_1, CDIN(22) => GND_net_1, CDIN(21)
         => GND_net_1, CDIN(20) => GND_net_1, CDIN(19) => 
        GND_net_1, CDIN(18) => GND_net_1, CDIN(17) => GND_net_1, 
        CDIN(16) => GND_net_1, CDIN(15) => GND_net_1, CDIN(14)
         => GND_net_1, CDIN(13) => GND_net_1, CDIN(12) => 
        GND_net_1, CDIN(11) => GND_net_1, CDIN(10) => GND_net_1, 
        CDIN(9) => GND_net_1, CDIN(8) => GND_net_1, CDIN(7) => 
        GND_net_1, CDIN(6) => GND_net_1, CDIN(5) => GND_net_1, 
        CDIN(4) => GND_net_1, CDIN(3) => GND_net_1, CDIN(2) => 
        GND_net_1, CDIN(1) => GND_net_1, CDIN(0) => GND_net_1, 
        CDOUT(43) => CDOUT(43), CDOUT(42) => CDOUT(42), CDOUT(41)
         => CDOUT(41), CDOUT(40) => CDOUT(40), CDOUT(39) => 
        CDOUT(39), CDOUT(38) => CDOUT(38), CDOUT(37) => CDOUT(37), 
        CDOUT(36) => CDOUT(36), CDOUT(35) => CDOUT(35), CDOUT(34)
         => CDOUT(34), CDOUT(33) => CDOUT(33), CDOUT(32) => 
        CDOUT(32), CDOUT(31) => CDOUT(31), CDOUT(30) => CDOUT(30), 
        CDOUT(29) => CDOUT(29), CDOUT(28) => CDOUT(28), CDOUT(27)
         => CDOUT(27), CDOUT(26) => CDOUT(26), CDOUT(25) => 
        CDOUT(25), CDOUT(24) => CDOUT(24), CDOUT(23) => CDOUT(23), 
        CDOUT(22) => CDOUT(22), CDOUT(21) => CDOUT(21), CDOUT(20)
         => CDOUT(20), CDOUT(19) => CDOUT(19), CDOUT(18) => 
        CDOUT(18), CDOUT(17) => CDOUT(17), CDOUT(16) => CDOUT(16), 
        CDOUT(15) => CDOUT(15), CDOUT(14) => CDOUT(14), CDOUT(13)
         => CDOUT(13), CDOUT(12) => CDOUT(12), CDOUT(11) => 
        CDOUT(11), CDOUT(10) => CDOUT(10), CDOUT(9) => CDOUT(9), 
        CDOUT(8) => CDOUT(8), CDOUT(7) => CDOUT(7), CDOUT(6) => 
        CDOUT(6), CDOUT(5) => CDOUT(5), CDOUT(4) => CDOUT(4), 
        CDOUT(3) => CDOUT(3), CDOUT(2) => CDOUT(2), CDOUT(1) => 
        CDOUT(1), CDOUT(0) => CDOUT(0), P(43) => nc34, P(42) => 
        nc9, P(41) => nc13, P(40) => nc23, P(39) => nc33, P(38)
         => nc16, P(37) => nc26, P(36) => nc27, P(35) => nc17, 
        P(34) => nc36, P(33) => nc37, P(32) => nc5, P(31) => nc4, 
        P(30) => nc42, P(29) => nc41, P(28) => nc25, P(27) => 
        nc15, P(26) => nc35, P(25) => nc28, P(24) => nc18, P(23)
         => nc38, P(22) => nc1, P(21) => nc2, P(20) => nc22, 
        P(19) => nc12, P(18) => nc21, P(17) => nc11, P(16) => nc3, 
        P(15) => nc32, P(14) => nc40, P(13) => nc31, P(12) => 
        nc44, P(11) => nc7, P(10) => nc6, P(9) => nc19, P(8) => 
        nc29, P(7) => nc39, P(6) => nc8, P(5) => nc43, P(4) => 
        nc20, P(3) => nc10, P(2) => nc24, P(1) => nc14, P(0) => 
        nc30, OVFL_CARRYOUT => OPEN);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Mult18x18 is

    port( CDOUT : out   std_logic_vector(43 downto 0);
          INA_c : in    std_logic_vector(17 downto 1);
          CLK_c : in    std_logic
        );

end Mult18x18;

architecture DEF_ARCH of Mult18x18 is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component Mult18x18_Mult18x18_0_HARD_MULT
    port( CDOUT : out   std_logic_vector(43 downto 0);
          INA_c : in    std_logic_vector(17 downto 1) := (others => 'U');
          CLK_c : in    std_logic := 'U'
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

    for all : Mult18x18_Mult18x18_0_HARD_MULT
	Use entity work.Mult18x18_Mult18x18_0_HARD_MULT(DEF_ARCH);
begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    Mult18x18_0 : Mult18x18_Mult18x18_0_HARD_MULT
      port map(CDOUT(43) => CDOUT(43), CDOUT(42) => CDOUT(42), 
        CDOUT(41) => CDOUT(41), CDOUT(40) => CDOUT(40), CDOUT(39)
         => CDOUT(39), CDOUT(38) => CDOUT(38), CDOUT(37) => 
        CDOUT(37), CDOUT(36) => CDOUT(36), CDOUT(35) => CDOUT(35), 
        CDOUT(34) => CDOUT(34), CDOUT(33) => CDOUT(33), CDOUT(32)
         => CDOUT(32), CDOUT(31) => CDOUT(31), CDOUT(30) => 
        CDOUT(30), CDOUT(29) => CDOUT(29), CDOUT(28) => CDOUT(28), 
        CDOUT(27) => CDOUT(27), CDOUT(26) => CDOUT(26), CDOUT(25)
         => CDOUT(25), CDOUT(24) => CDOUT(24), CDOUT(23) => 
        CDOUT(23), CDOUT(22) => CDOUT(22), CDOUT(21) => CDOUT(21), 
        CDOUT(20) => CDOUT(20), CDOUT(19) => CDOUT(19), CDOUT(18)
         => CDOUT(18), CDOUT(17) => CDOUT(17), CDOUT(16) => 
        CDOUT(16), CDOUT(15) => CDOUT(15), CDOUT(14) => CDOUT(14), 
        CDOUT(13) => CDOUT(13), CDOUT(12) => CDOUT(12), CDOUT(11)
         => CDOUT(11), CDOUT(10) => CDOUT(10), CDOUT(9) => 
        CDOUT(9), CDOUT(8) => CDOUT(8), CDOUT(7) => CDOUT(7), 
        CDOUT(6) => CDOUT(6), CDOUT(5) => CDOUT(5), CDOUT(4) => 
        CDOUT(4), CDOUT(3) => CDOUT(3), CDOUT(2) => CDOUT(2), 
        CDOUT(1) => CDOUT(1), CDOUT(0) => CDOUT(0), INA_c(17) => 
        INA_c(17), INA_c(16) => INA_c(16), INA_c(15) => INA_c(15), 
        INA_c(14) => INA_c(14), INA_c(13) => INA_c(13), INA_c(12)
         => INA_c(12), INA_c(11) => INA_c(11), INA_c(10) => 
        INA_c(10), INA_c(9) => INA_c(9), INA_c(8) => INA_c(8), 
        INA_c(7) => INA_c(7), INA_c(6) => INA_c(6), INA_c(5) => 
        INA_c(5), INA_c(4) => INA_c(4), INA_c(3) => INA_c(3), 
        INA_c(2) => INA_c(2), INA_c(1) => INA_c(1), CLK_c => 
        CLK_c);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Mult18x18_barrShift_Mult18x18_barrShift_0_HARD_MULT_ADDSUB is

    port( RESULT  : out   std_logic_vector(17 downto 0);
          CDOUT_0 : in    std_logic_vector(43 downto 0);
          INA_r   : in    std_logic_vector(17 downto 0);
          CLK_c   : in    std_logic
        );

end Mult18x18_barrShift_Mult18x18_barrShift_0_HARD_MULT_ADDSUB;

architecture DEF_ARCH of 
        Mult18x18_barrShift_Mult18x18_barrShift_0_HARD_MULT_ADDSUB is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;
    signal nc47, nc34, nc70, nc60, nc64, nc9, nc13, nc23, nc55, 
        nc33, nc16, nc26, nc45, nc58, nc63, nc27, nc17, nc36, 
        nc48, nc37, nc5, nc52, nc51, nc66, nc67, nc4, nc42, nc41, 
        nc59, nc25, nc15, nc35, nc49, nc28, nc18, nc65, nc38, nc1, 
        nc2, nc50, nc22, nc12, nc21, nc11, nc54, nc68, nc3, nc32, 
        nc40, nc31, nc44, nc7, nc6, nc62, nc61, nc19, nc29, nc53, 
        nc39, nc8, nc43, nc69, nc56, nc20, nc10, nc57, nc24, nc14, 
        nc46, nc30 : std_logic;

begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    U0 : MACC
      port map(CLK(1) => CLK_c, CLK(0) => CLK_c, A(17) => 
        GND_net_1, A(16) => GND_net_1, A(15) => GND_net_1, A(14)
         => GND_net_1, A(13) => GND_net_1, A(12) => GND_net_1, 
        A(11) => GND_net_1, A(10) => GND_net_1, A(9) => GND_net_1, 
        A(8) => GND_net_1, A(7) => GND_net_1, A(6) => GND_net_1, 
        A(5) => VCC_net_1, A(4) => GND_net_1, A(3) => GND_net_1, 
        A(2) => GND_net_1, A(1) => GND_net_1, A(0) => GND_net_1, 
        A_EN(1) => VCC_net_1, A_EN(0) => VCC_net_1, A_ARST_N(1)
         => VCC_net_1, A_ARST_N(0) => VCC_net_1, A_SRST_N(1) => 
        VCC_net_1, A_SRST_N(0) => VCC_net_1, B(17) => INA_r(17), 
        B(16) => INA_r(16), B(15) => INA_r(15), B(14) => 
        INA_r(14), B(13) => INA_r(13), B(12) => INA_r(12), B(11)
         => INA_r(11), B(10) => INA_r(10), B(9) => INA_r(9), B(8)
         => INA_r(8), B(7) => INA_r(7), B(6) => INA_r(6), B(5)
         => INA_r(5), B(4) => INA_r(4), B(3) => INA_r(3), B(2)
         => INA_r(2), B(1) => INA_r(1), B(0) => INA_r(0), B_EN(1)
         => VCC_net_1, B_EN(0) => VCC_net_1, B_ARST_N(1) => 
        VCC_net_1, B_ARST_N(0) => VCC_net_1, B_SRST_N(1) => 
        VCC_net_1, B_SRST_N(0) => VCC_net_1, C(43) => GND_net_1, 
        C(42) => GND_net_1, C(41) => GND_net_1, C(40) => 
        GND_net_1, C(39) => GND_net_1, C(38) => GND_net_1, C(37)
         => GND_net_1, C(36) => GND_net_1, C(35) => GND_net_1, 
        C(34) => GND_net_1, C(33) => GND_net_1, C(32) => 
        GND_net_1, C(31) => GND_net_1, C(30) => GND_net_1, C(29)
         => GND_net_1, C(28) => GND_net_1, C(27) => GND_net_1, 
        C(26) => GND_net_1, C(25) => GND_net_1, C(24) => 
        GND_net_1, C(23) => GND_net_1, C(22) => GND_net_1, C(21)
         => GND_net_1, C(20) => GND_net_1, C(19) => GND_net_1, 
        C(18) => GND_net_1, C(17) => GND_net_1, C(16) => 
        GND_net_1, C(15) => GND_net_1, C(14) => GND_net_1, C(13)
         => GND_net_1, C(12) => GND_net_1, C(11) => GND_net_1, 
        C(10) => GND_net_1, C(9) => GND_net_1, C(8) => GND_net_1, 
        C(7) => GND_net_1, C(6) => GND_net_1, C(5) => GND_net_1, 
        C(4) => GND_net_1, C(3) => GND_net_1, C(2) => GND_net_1, 
        C(1) => GND_net_1, C(0) => GND_net_1, C_EN(1) => 
        VCC_net_1, C_EN(0) => VCC_net_1, C_ARST_N(1) => VCC_net_1, 
        C_ARST_N(0) => VCC_net_1, C_SRST_N(1) => VCC_net_1, 
        C_SRST_N(0) => VCC_net_1, P_EN(1) => VCC_net_1, P_EN(0)
         => VCC_net_1, P_ARST_N(1) => VCC_net_1, P_ARST_N(0) => 
        VCC_net_1, P_SRST_N(1) => VCC_net_1, P_SRST_N(0) => 
        VCC_net_1, FDBKSEL => GND_net_1, FDBKSEL_EN => VCC_net_1, 
        FDBKSEL_AL_N => VCC_net_1, FDBKSEL_SL_N => VCC_net_1, 
        CDSEL => VCC_net_1, CDSEL_EN => VCC_net_1, CDSEL_AL_N => 
        VCC_net_1, CDSEL_SL_N => VCC_net_1, ARSHFT17 => VCC_net_1, 
        ARSHFT17_EN => VCC_net_1, ARSHFT17_AL_N => VCC_net_1, 
        ARSHFT17_SL_N => VCC_net_1, SUB => GND_net_1, SUB_EN => 
        VCC_net_1, SUB_AL_N => VCC_net_1, SUB_SL_N => VCC_net_1, 
        CARRYIN => GND_net_1, SIMD => GND_net_1, DOTP => 
        GND_net_1, OVFL_CARRYOUT_SEL => GND_net_1, A_BYPASS(1)
         => VCC_net_1, A_BYPASS(0) => VCC_net_1, B_BYPASS(1) => 
        VCC_net_1, B_BYPASS(0) => VCC_net_1, C_BYPASS(1) => 
        VCC_net_1, C_BYPASS(0) => VCC_net_1, P_BYPASS(1) => 
        GND_net_1, P_BYPASS(0) => GND_net_1, FDBKSEL_BYPASS => 
        VCC_net_1, FDBKSEL_AD => GND_net_1, FDBKSEL_SD_N => 
        VCC_net_1, CDSEL_BYPASS => VCC_net_1, CDSEL_AD => 
        GND_net_1, CDSEL_SD_N => VCC_net_1, ARSHFT17_BYPASS => 
        VCC_net_1, ARSHFT17_AD => GND_net_1, ARSHFT17_SD_N => 
        VCC_net_1, SUB_BYPASS => VCC_net_1, SUB_AD => GND_net_1, 
        SUB_SD_N => VCC_net_1, CDIN(43) => CDOUT_0(43), CDIN(42)
         => CDOUT_0(42), CDIN(41) => CDOUT_0(41), CDIN(40) => 
        CDOUT_0(40), CDIN(39) => CDOUT_0(39), CDIN(38) => 
        CDOUT_0(38), CDIN(37) => CDOUT_0(37), CDIN(36) => 
        CDOUT_0(36), CDIN(35) => CDOUT_0(35), CDIN(34) => 
        CDOUT_0(34), CDIN(33) => CDOUT_0(33), CDIN(32) => 
        CDOUT_0(32), CDIN(31) => CDOUT_0(31), CDIN(30) => 
        CDOUT_0(30), CDIN(29) => CDOUT_0(29), CDIN(28) => 
        CDOUT_0(28), CDIN(27) => CDOUT_0(27), CDIN(26) => 
        CDOUT_0(26), CDIN(25) => CDOUT_0(25), CDIN(24) => 
        CDOUT_0(24), CDIN(23) => CDOUT_0(23), CDIN(22) => 
        CDOUT_0(22), CDIN(21) => CDOUT_0(21), CDIN(20) => 
        CDOUT_0(20), CDIN(19) => CDOUT_0(19), CDIN(18) => 
        CDOUT_0(18), CDIN(17) => CDOUT_0(17), CDIN(16) => 
        CDOUT_0(16), CDIN(15) => CDOUT_0(15), CDIN(14) => 
        CDOUT_0(14), CDIN(13) => CDOUT_0(13), CDIN(12) => 
        CDOUT_0(12), CDIN(11) => CDOUT_0(11), CDIN(10) => 
        CDOUT_0(10), CDIN(9) => CDOUT_0(9), CDIN(8) => CDOUT_0(8), 
        CDIN(7) => CDOUT_0(7), CDIN(6) => CDOUT_0(6), CDIN(5) => 
        CDOUT_0(5), CDIN(4) => CDOUT_0(4), CDIN(3) => CDOUT_0(3), 
        CDIN(2) => CDOUT_0(2), CDIN(1) => CDOUT_0(1), CDIN(0) => 
        CDOUT_0(0), CDOUT(43) => nc47, CDOUT(42) => nc34, 
        CDOUT(41) => nc70, CDOUT(40) => nc60, CDOUT(39) => nc64, 
        CDOUT(38) => nc9, CDOUT(37) => nc13, CDOUT(36) => nc23, 
        CDOUT(35) => nc55, CDOUT(34) => nc33, CDOUT(33) => nc16, 
        CDOUT(32) => nc26, CDOUT(31) => nc45, CDOUT(30) => nc58, 
        CDOUT(29) => nc63, CDOUT(28) => nc27, CDOUT(27) => nc17, 
        CDOUT(26) => nc36, CDOUT(25) => nc48, CDOUT(24) => nc37, 
        CDOUT(23) => nc5, CDOUT(22) => nc52, CDOUT(21) => nc51, 
        CDOUT(20) => nc66, CDOUT(19) => nc67, CDOUT(18) => nc4, 
        CDOUT(17) => nc42, CDOUT(16) => nc41, CDOUT(15) => nc59, 
        CDOUT(14) => nc25, CDOUT(13) => nc15, CDOUT(12) => nc35, 
        CDOUT(11) => nc49, CDOUT(10) => nc28, CDOUT(9) => nc18, 
        CDOUT(8) => nc65, CDOUT(7) => nc38, CDOUT(6) => nc1, 
        CDOUT(5) => nc2, CDOUT(4) => nc50, CDOUT(3) => nc22, 
        CDOUT(2) => nc12, CDOUT(1) => nc21, CDOUT(0) => nc11, 
        P(43) => nc54, P(42) => nc68, P(41) => nc3, P(40) => nc32, 
        P(39) => nc40, P(38) => nc31, P(37) => nc44, P(36) => nc7, 
        P(35) => nc6, P(34) => nc62, P(33) => nc61, P(32) => nc19, 
        P(31) => nc29, P(30) => nc53, P(29) => nc39, P(28) => nc8, 
        P(27) => nc43, P(26) => nc69, P(25) => nc56, P(24) => 
        nc20, P(23) => nc10, P(22) => nc57, P(21) => nc24, P(20)
         => nc14, P(19) => nc46, P(18) => nc30, P(17) => 
        RESULT(17), P(16) => RESULT(16), P(15) => RESULT(15), 
        P(14) => RESULT(14), P(13) => RESULT(13), P(12) => 
        RESULT(12), P(11) => RESULT(11), P(10) => RESULT(10), 
        P(9) => RESULT(9), P(8) => RESULT(8), P(7) => RESULT(7), 
        P(6) => RESULT(6), P(5) => RESULT(5), P(4) => RESULT(4), 
        P(3) => RESULT(3), P(2) => RESULT(2), P(1) => RESULT(1), 
        P(0) => RESULT(0), OVFL_CARRYOUT => OPEN);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Mult18x18_barrShift is

    port( RESULT : out   std_logic_vector(17 downto 0);
          CDOUT  : in    std_logic_vector(43 downto 0);
          INA_r  : in    std_logic_vector(17 downto 0);
          CLK_c  : in    std_logic
        );

end Mult18x18_barrShift;

architecture DEF_ARCH of Mult18x18_barrShift is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component 
        Mult18x18_barrShift_Mult18x18_barrShift_0_HARD_MULT_ADDSUB
    port( RESULT  : out   std_logic_vector(17 downto 0);
          CDOUT_0 : in    std_logic_vector(43 downto 0) := (others => 'U');
          INA_r   : in    std_logic_vector(17 downto 0) := (others => 'U');
          CLK_c   : in    std_logic := 'U'
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

    for all : Mult18x18_barrShift_Mult18x18_barrShift_0_HARD_MULT_ADDSUB
	Use entity work.
        Mult18x18_barrShift_Mult18x18_barrShift_0_HARD_MULT_ADDSUB(DEF_ARCH);
begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    Mult18x18_barrShift_0 : 
        Mult18x18_barrShift_Mult18x18_barrShift_0_HARD_MULT_ADDSUB
      port map(RESULT(17) => RESULT(17), RESULT(16) => RESULT(16), 
        RESULT(15) => RESULT(15), RESULT(14) => RESULT(14), 
        RESULT(13) => RESULT(13), RESULT(12) => RESULT(12), 
        RESULT(11) => RESULT(11), RESULT(10) => RESULT(10), 
        RESULT(9) => RESULT(9), RESULT(8) => RESULT(8), RESULT(7)
         => RESULT(7), RESULT(6) => RESULT(6), RESULT(5) => 
        RESULT(5), RESULT(4) => RESULT(4), RESULT(3) => RESULT(3), 
        RESULT(2) => RESULT(2), RESULT(1) => RESULT(1), RESULT(0)
         => RESULT(0), CDOUT_0(43) => CDOUT(43), CDOUT_0(42) => 
        CDOUT(42), CDOUT_0(41) => CDOUT(41), CDOUT_0(40) => 
        CDOUT(40), CDOUT_0(39) => CDOUT(39), CDOUT_0(38) => 
        CDOUT(38), CDOUT_0(37) => CDOUT(37), CDOUT_0(36) => 
        CDOUT(36), CDOUT_0(35) => CDOUT(35), CDOUT_0(34) => 
        CDOUT(34), CDOUT_0(33) => CDOUT(33), CDOUT_0(32) => 
        CDOUT(32), CDOUT_0(31) => CDOUT(31), CDOUT_0(30) => 
        CDOUT(30), CDOUT_0(29) => CDOUT(29), CDOUT_0(28) => 
        CDOUT(28), CDOUT_0(27) => CDOUT(27), CDOUT_0(26) => 
        CDOUT(26), CDOUT_0(25) => CDOUT(25), CDOUT_0(24) => 
        CDOUT(24), CDOUT_0(23) => CDOUT(23), CDOUT_0(22) => 
        CDOUT(22), CDOUT_0(21) => CDOUT(21), CDOUT_0(20) => 
        CDOUT(20), CDOUT_0(19) => CDOUT(19), CDOUT_0(18) => 
        CDOUT(18), CDOUT_0(17) => CDOUT(17), CDOUT_0(16) => 
        CDOUT(16), CDOUT_0(15) => CDOUT(15), CDOUT_0(14) => 
        CDOUT(14), CDOUT_0(13) => CDOUT(13), CDOUT_0(12) => 
        CDOUT(12), CDOUT_0(11) => CDOUT(11), CDOUT_0(10) => 
        CDOUT(10), CDOUT_0(9) => CDOUT(9), CDOUT_0(8) => CDOUT(8), 
        CDOUT_0(7) => CDOUT(7), CDOUT_0(6) => CDOUT(6), 
        CDOUT_0(5) => CDOUT(5), CDOUT_0(4) => CDOUT(4), 
        CDOUT_0(3) => CDOUT(3), CDOUT_0(2) => CDOUT(2), 
        CDOUT_0(1) => CDOUT(1), CDOUT_0(0) => CDOUT(0), INA_r(17)
         => INA_r(17), INA_r(16) => INA_r(16), INA_r(15) => 
        INA_r(15), INA_r(14) => INA_r(14), INA_r(13) => INA_r(13), 
        INA_r(12) => INA_r(12), INA_r(11) => INA_r(11), INA_r(10)
         => INA_r(10), INA_r(9) => INA_r(9), INA_r(8) => INA_r(8), 
        INA_r(7) => INA_r(7), INA_r(6) => INA_r(6), INA_r(5) => 
        INA_r(5), INA_r(4) => INA_r(4), INA_r(3) => INA_r(3), 
        INA_r(2) => INA_r(2), INA_r(1) => INA_r(1), INA_r(0) => 
        INA_r(0), CLK_c => CLK_c);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity BarrelShifter_18bit is

    port( INA      : in    std_logic_vector(17 downto 0);
          SHIFT_OP : out   std_logic_vector(17 downto 0);
          CLK      : in    std_logic;
          RSTN     : in    std_logic
        );

end BarrelShifter_18bit;

architecture DEF_ARCH of BarrelShifter_18bit is 

  component Mult18x18
    port( CDOUT : out   std_logic_vector(43 downto 0);
          INA_c : in    std_logic_vector(17 downto 1) := (others => 'U');
          CLK_c : in    std_logic := 'U'
        );
  end component;

  component INBUF
    generic (IOSTD:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component OUTBUF
    generic (IOSTD:string := "");

    port( D   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component Mult18x18_barrShift
    port( RESULT : out   std_logic_vector(17 downto 0);
          CDOUT  : in    std_logic_vector(43 downto 0) := (others => 'U');
          INA_r  : in    std_logic_vector(17 downto 0) := (others => 'U');
          CLK_c  : in    std_logic := 'U'
        );
  end component;

  component CLKINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal \CDOUT[0]\, \CDOUT[1]\, \CDOUT[2]\, \CDOUT[3]\, 
        \CDOUT[4]\, \CDOUT[5]\, \CDOUT[6]\, \CDOUT[7]\, 
        \CDOUT[8]\, \CDOUT[9]\, \CDOUT[10]\, \CDOUT[11]\, 
        \CDOUT[12]\, \CDOUT[13]\, \CDOUT[14]\, \CDOUT[15]\, 
        \CDOUT[16]\, \CDOUT[17]\, \CDOUT[18]\, \CDOUT[19]\, 
        \CDOUT[20]\, \CDOUT[21]\, \CDOUT[22]\, \CDOUT[23]\, 
        \CDOUT[24]\, \CDOUT[25]\, \CDOUT[26]\, \CDOUT[27]\, 
        \CDOUT[28]\, \CDOUT[29]\, \CDOUT[30]\, \CDOUT[31]\, 
        \CDOUT[32]\, \CDOUT[33]\, \CDOUT[34]\, \CDOUT[35]\, 
        \CDOUT[36]\, \CDOUT[37]\, \CDOUT[38]\, \CDOUT[39]\, 
        \CDOUT[40]\, \CDOUT[41]\, \CDOUT[42]\, \CDOUT[43]\, 
        \INA_r[0]_net_1\, \INA_r[1]_net_1\, \INA_r[2]_net_1\, 
        \INA_r[3]_net_1\, \INA_r[4]_net_1\, \INA_r[5]_net_1\, 
        \INA_r[6]_net_1\, \INA_r[7]_net_1\, \INA_r[8]_net_1\, 
        \INA_r[9]_net_1\, \INA_r[10]_net_1\, \INA_r[11]_net_1\, 
        \INA_r[12]_net_1\, \INA_r[13]_net_1\, \INA_r[14]_net_1\, 
        \INA_r[15]_net_1\, \INA_r[16]_net_1\, \INA_r[17]_net_1\, 
        \RESULT[0]\, \RESULT[1]\, \RESULT[2]\, \RESULT[3]\, 
        \RESULT[4]\, \RESULT[5]\, \RESULT[6]\, \RESULT[7]\, 
        \RESULT[8]\, \RESULT[9]\, \RESULT[10]\, \RESULT[11]\, 
        \RESULT[12]\, \RESULT[13]\, \RESULT[14]\, \RESULT[15]\, 
        \RESULT[16]\, \RESULT[17]\, VCC_net_1, GND_net_1, CLK_c, 
        RSTN_c, \INA_c[0]\, \INA_c[1]\, \INA_c[2]\, \INA_c[3]\, 
        \INA_c[4]\, \INA_c[5]\, \INA_c[6]\, \INA_c[7]\, 
        \INA_c[8]\, \INA_c[9]\, \INA_c[10]\, \INA_c[11]\, 
        \INA_c[12]\, \INA_c[13]\, \INA_c[14]\, \INA_c[15]\, 
        \INA_c[16]\, \INA_c[17]\, \CLK_ibuf\, \RSTN_ibuf\
         : std_logic;

    for all : Mult18x18
	Use entity work.Mult18x18(DEF_ARCH);
    for all : Mult18x18_barrShift
	Use entity work.Mult18x18_barrShift(DEF_ARCH);
begin 


    U0 : Mult18x18
      port map(CDOUT(43) => \CDOUT[43]\, CDOUT(42) => \CDOUT[42]\, 
        CDOUT(41) => \CDOUT[41]\, CDOUT(40) => \CDOUT[40]\, 
        CDOUT(39) => \CDOUT[39]\, CDOUT(38) => \CDOUT[38]\, 
        CDOUT(37) => \CDOUT[37]\, CDOUT(36) => \CDOUT[36]\, 
        CDOUT(35) => \CDOUT[35]\, CDOUT(34) => \CDOUT[34]\, 
        CDOUT(33) => \CDOUT[33]\, CDOUT(32) => \CDOUT[32]\, 
        CDOUT(31) => \CDOUT[31]\, CDOUT(30) => \CDOUT[30]\, 
        CDOUT(29) => \CDOUT[29]\, CDOUT(28) => \CDOUT[28]\, 
        CDOUT(27) => \CDOUT[27]\, CDOUT(26) => \CDOUT[26]\, 
        CDOUT(25) => \CDOUT[25]\, CDOUT(24) => \CDOUT[24]\, 
        CDOUT(23) => \CDOUT[23]\, CDOUT(22) => \CDOUT[22]\, 
        CDOUT(21) => \CDOUT[21]\, CDOUT(20) => \CDOUT[20]\, 
        CDOUT(19) => \CDOUT[19]\, CDOUT(18) => \CDOUT[18]\, 
        CDOUT(17) => \CDOUT[17]\, CDOUT(16) => \CDOUT[16]\, 
        CDOUT(15) => \CDOUT[15]\, CDOUT(14) => \CDOUT[14]\, 
        CDOUT(13) => \CDOUT[13]\, CDOUT(12) => \CDOUT[12]\, 
        CDOUT(11) => \CDOUT[11]\, CDOUT(10) => \CDOUT[10]\, 
        CDOUT(9) => \CDOUT[9]\, CDOUT(8) => \CDOUT[8]\, CDOUT(7)
         => \CDOUT[7]\, CDOUT(6) => \CDOUT[6]\, CDOUT(5) => 
        \CDOUT[5]\, CDOUT(4) => \CDOUT[4]\, CDOUT(3) => 
        \CDOUT[3]\, CDOUT(2) => \CDOUT[2]\, CDOUT(1) => 
        \CDOUT[1]\, CDOUT(0) => \CDOUT[0]\, INA_c(17) => 
        \INA_c[17]\, INA_c(16) => \INA_c[16]\, INA_c(15) => 
        \INA_c[15]\, INA_c(14) => \INA_c[14]\, INA_c(13) => 
        \INA_c[13]\, INA_c(12) => \INA_c[12]\, INA_c(11) => 
        \INA_c[11]\, INA_c(10) => \INA_c[10]\, INA_c(9) => 
        \INA_c[9]\, INA_c(8) => \INA_c[8]\, INA_c(7) => 
        \INA_c[7]\, INA_c(6) => \INA_c[6]\, INA_c(5) => 
        \INA_c[5]\, INA_c(4) => \INA_c[4]\, INA_c(3) => 
        \INA_c[3]\, INA_c(2) => \INA_c[2]\, INA_c(1) => 
        \INA_c[1]\, CLK_c => CLK_c);
    
    \INA_ibuf[5]\ : INBUF
      port map(PAD => INA(5), Y => \INA_c[5]\);
    
    \INA_ibuf[15]\ : INBUF
      port map(PAD => INA(15), Y => \INA_c[15]\);
    
    \INA_r[15]\ : SLE
      port map(D => \INA_c[15]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[15]_net_1\);
    
    \SHIFT_OP_obuf[6]\ : OUTBUF
      port map(D => \RESULT[6]\, PAD => SHIFT_OP(6));
    
    \INA_r[3]\ : SLE
      port map(D => \INA_c[3]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[3]_net_1\);
    
    \INA_r[17]\ : SLE
      port map(D => \INA_c[17]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[17]_net_1\);
    
    \INA_r[13]\ : SLE
      port map(D => \INA_c[13]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[13]_net_1\);
    
    \INA_r[14]\ : SLE
      port map(D => \INA_c[14]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[14]_net_1\);
    
    \INA_ibuf[3]\ : INBUF
      port map(PAD => INA(3), Y => \INA_c[3]\);
    
    \INA_r[6]\ : SLE
      port map(D => \INA_c[6]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[6]_net_1\);
    
    \SHIFT_OP_obuf[4]\ : OUTBUF
      port map(D => \RESULT[4]\, PAD => SHIFT_OP(4));
    
    \INA_r[10]\ : SLE
      port map(D => \INA_c[10]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[10]_net_1\);
    
    \INA_r[0]\ : SLE
      port map(D => \INA_c[0]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[0]_net_1\);
    
    \INA_ibuf[1]\ : INBUF
      port map(PAD => INA(1), Y => \INA_c[1]\);
    
    \SHIFT_OP_obuf[11]\ : OUTBUF
      port map(D => \RESULT[11]\, PAD => SHIFT_OP(11));
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    U1 : Mult18x18_barrShift
      port map(RESULT(17) => \RESULT[17]\, RESULT(16) => 
        \RESULT[16]\, RESULT(15) => \RESULT[15]\, RESULT(14) => 
        \RESULT[14]\, RESULT(13) => \RESULT[13]\, RESULT(12) => 
        \RESULT[12]\, RESULT(11) => \RESULT[11]\, RESULT(10) => 
        \RESULT[10]\, RESULT(9) => \RESULT[9]\, RESULT(8) => 
        \RESULT[8]\, RESULT(7) => \RESULT[7]\, RESULT(6) => 
        \RESULT[6]\, RESULT(5) => \RESULT[5]\, RESULT(4) => 
        \RESULT[4]\, RESULT(3) => \RESULT[3]\, RESULT(2) => 
        \RESULT[2]\, RESULT(1) => \RESULT[1]\, RESULT(0) => 
        \RESULT[0]\, CDOUT(43) => \CDOUT[43]\, CDOUT(42) => 
        \CDOUT[42]\, CDOUT(41) => \CDOUT[41]\, CDOUT(40) => 
        \CDOUT[40]\, CDOUT(39) => \CDOUT[39]\, CDOUT(38) => 
        \CDOUT[38]\, CDOUT(37) => \CDOUT[37]\, CDOUT(36) => 
        \CDOUT[36]\, CDOUT(35) => \CDOUT[35]\, CDOUT(34) => 
        \CDOUT[34]\, CDOUT(33) => \CDOUT[33]\, CDOUT(32) => 
        \CDOUT[32]\, CDOUT(31) => \CDOUT[31]\, CDOUT(30) => 
        \CDOUT[30]\, CDOUT(29) => \CDOUT[29]\, CDOUT(28) => 
        \CDOUT[28]\, CDOUT(27) => \CDOUT[27]\, CDOUT(26) => 
        \CDOUT[26]\, CDOUT(25) => \CDOUT[25]\, CDOUT(24) => 
        \CDOUT[24]\, CDOUT(23) => \CDOUT[23]\, CDOUT(22) => 
        \CDOUT[22]\, CDOUT(21) => \CDOUT[21]\, CDOUT(20) => 
        \CDOUT[20]\, CDOUT(19) => \CDOUT[19]\, CDOUT(18) => 
        \CDOUT[18]\, CDOUT(17) => \CDOUT[17]\, CDOUT(16) => 
        \CDOUT[16]\, CDOUT(15) => \CDOUT[15]\, CDOUT(14) => 
        \CDOUT[14]\, CDOUT(13) => \CDOUT[13]\, CDOUT(12) => 
        \CDOUT[12]\, CDOUT(11) => \CDOUT[11]\, CDOUT(10) => 
        \CDOUT[10]\, CDOUT(9) => \CDOUT[9]\, CDOUT(8) => 
        \CDOUT[8]\, CDOUT(7) => \CDOUT[7]\, CDOUT(6) => 
        \CDOUT[6]\, CDOUT(5) => \CDOUT[5]\, CDOUT(4) => 
        \CDOUT[4]\, CDOUT(3) => \CDOUT[3]\, CDOUT(2) => 
        \CDOUT[2]\, CDOUT(1) => \CDOUT[1]\, CDOUT(0) => 
        \CDOUT[0]\, INA_r(17) => \INA_r[17]_net_1\, INA_r(16) => 
        \INA_r[16]_net_1\, INA_r(15) => \INA_r[15]_net_1\, 
        INA_r(14) => \INA_r[14]_net_1\, INA_r(13) => 
        \INA_r[13]_net_1\, INA_r(12) => \INA_r[12]_net_1\, 
        INA_r(11) => \INA_r[11]_net_1\, INA_r(10) => 
        \INA_r[10]_net_1\, INA_r(9) => \INA_r[9]_net_1\, INA_r(8)
         => \INA_r[8]_net_1\, INA_r(7) => \INA_r[7]_net_1\, 
        INA_r(6) => \INA_r[6]_net_1\, INA_r(5) => 
        \INA_r[5]_net_1\, INA_r(4) => \INA_r[4]_net_1\, INA_r(3)
         => \INA_r[3]_net_1\, INA_r(2) => \INA_r[2]_net_1\, 
        INA_r(1) => \INA_r[1]_net_1\, INA_r(0) => 
        \INA_r[0]_net_1\, CLK_c => CLK_c);
    
    RSTN_ibuf : INBUF
      port map(PAD => RSTN, Y => \RSTN_ibuf\);
    
    \INA_r[8]\ : SLE
      port map(D => \INA_c[8]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[8]_net_1\);
    
    \INA_r[4]\ : SLE
      port map(D => \INA_c[4]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[4]_net_1\);
    
    RSTN_ibuf_RNICTO9 : CLKINT
      port map(A => \RSTN_ibuf\, Y => RSTN_c);
    
    \INA_ibuf[17]\ : INBUF
      port map(PAD => INA(17), Y => \INA_c[17]\);
    
    \INA_r[9]\ : SLE
      port map(D => \INA_c[9]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[9]_net_1\);
    
    \INA_ibuf[13]\ : INBUF
      port map(PAD => INA(13), Y => \INA_c[13]\);
    
    \INA_r[5]\ : SLE
      port map(D => \INA_c[5]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[5]_net_1\);
    
    \SHIFT_OP_obuf[17]\ : OUTBUF
      port map(D => \RESULT[17]\, PAD => SHIFT_OP(17));
    
    \SHIFT_OP_obuf[14]\ : OUTBUF
      port map(D => \RESULT[14]\, PAD => SHIFT_OP(14));
    
    \INA_ibuf[0]\ : INBUF
      port map(PAD => INA(0), Y => \INA_c[0]\);
    
    \SHIFT_OP_obuf[2]\ : OUTBUF
      port map(D => \RESULT[2]\, PAD => SHIFT_OP(2));
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    \SHIFT_OP_obuf[7]\ : OUTBUF
      port map(D => \RESULT[7]\, PAD => SHIFT_OP(7));
    
    \SHIFT_OP_obuf[1]\ : OUTBUF
      port map(D => \RESULT[1]\, PAD => SHIFT_OP(1));
    
    \INA_ibuf[8]\ : INBUF
      port map(PAD => INA(8), Y => \INA_c[8]\);
    
    \INA_ibuf[12]\ : INBUF
      port map(PAD => INA(12), Y => \INA_c[12]\);
    
    \SHIFT_OP_obuf[8]\ : OUTBUF
      port map(D => \RESULT[8]\, PAD => SHIFT_OP(8));
    
    \SHIFT_OP_obuf[10]\ : OUTBUF
      port map(D => \RESULT[10]\, PAD => SHIFT_OP(10));
    
    \INA_ibuf[11]\ : INBUF
      port map(PAD => INA(11), Y => \INA_c[11]\);
    
    \SHIFT_OP_obuf[12]\ : OUTBUF
      port map(D => \RESULT[12]\, PAD => SHIFT_OP(12));
    
    \SHIFT_OP_obuf[0]\ : OUTBUF
      port map(D => \RESULT[0]\, PAD => SHIFT_OP(0));
    
    \SHIFT_OP_obuf[5]\ : OUTBUF
      port map(D => \RESULT[5]\, PAD => SHIFT_OP(5));
    
    \SHIFT_OP_obuf[13]\ : OUTBUF
      port map(D => \RESULT[13]\, PAD => SHIFT_OP(13));
    
    \INA_ibuf[2]\ : INBUF
      port map(PAD => INA(2), Y => \INA_c[2]\);
    
    \INA_ibuf[7]\ : INBUF
      port map(PAD => INA(7), Y => \INA_c[7]\);
    
    CLK_ibuf_RNIVQ04 : CLKINT
      port map(A => \CLK_ibuf\, Y => CLK_c);
    
    \INA_r[16]\ : SLE
      port map(D => \INA_c[16]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[16]_net_1\);
    
    \INA_r[7]\ : SLE
      port map(D => \INA_c[7]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[7]_net_1\);
    
    \INA_ibuf[14]\ : INBUF
      port map(PAD => INA(14), Y => \INA_c[14]\);
    
    \INA_ibuf[10]\ : INBUF
      port map(PAD => INA(10), Y => \INA_c[10]\);
    
    \INA_r[11]\ : SLE
      port map(D => \INA_c[11]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[11]_net_1\);
    
    \INA_ibuf[4]\ : INBUF
      port map(PAD => INA(4), Y => \INA_c[4]\);
    
    \INA_r[2]\ : SLE
      port map(D => \INA_c[2]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[2]_net_1\);
    
    \INA_r[1]\ : SLE
      port map(D => \INA_c[1]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[1]_net_1\);
    
    \SHIFT_OP_obuf[16]\ : OUTBUF
      port map(D => \RESULT[16]\, PAD => SHIFT_OP(16));
    
    \SHIFT_OP_obuf[9]\ : OUTBUF
      port map(D => \RESULT[9]\, PAD => SHIFT_OP(9));
    
    \SHIFT_OP_obuf[3]\ : OUTBUF
      port map(D => \RESULT[3]\, PAD => SHIFT_OP(3));
    
    \SHIFT_OP_obuf[15]\ : OUTBUF
      port map(D => \RESULT[15]\, PAD => SHIFT_OP(15));
    
    CLK_ibuf : INBUF
      port map(PAD => CLK, Y => \CLK_ibuf\);
    
    \INA_ibuf[6]\ : INBUF
      port map(PAD => INA(6), Y => \INA_c[6]\);
    
    \INA_r[12]\ : SLE
      port map(D => \INA_c[12]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \INA_r[12]_net_1\);
    
    \INA_ibuf[9]\ : INBUF
      port map(PAD => INA(9), Y => \INA_c[9]\);
    
    \INA_ibuf[16]\ : INBUF
      port map(PAD => INA(16), Y => \INA_c[16]\);
    

end DEF_ARCH; 
