@W: MT530 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\extended adder\extended_adder_3_input\component\work\dotp_multadd1\dotp_multadd1_0\dotp_multadd1_dotp_multadd1_0_hard_mult_addsub.vhd":102:4:102:5|Found inferred clock Extended_adder_3_input|clk which controls 48 sequential elements including U0.dotp_multadd1_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
