--------------------------------------------------------------------------------
-- Company:
--
-- File			: Fourinput_42bit_Adder.vhd
-- File history	: VER 1.0
--      
-- Description: 
--		This design illustrates the implementation of 4-input 42 bit addition using
--      two mathblocks.
--
--      Even though 6-inputs are provided INP_A,INP_B  are considered as one input
--		to the adder(i.e. INP_A and INP_B are multiplier inputs and the result is input 
--		to the adder) and similarly INP_D, INP_E are considered as one input adder. 
--		
-- 		Targeted device: <Family :: SmartFusion2>
--					   		<Die :: M2S050> 
--						<Package :: 896 FBGA>
-- Author	: PHANIKIRAN T
--------------------------------------------------------------------------------


LIBRARY IEEE;

USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;

ENTITY Fourinput_42bit_Adder IS
PORT (
    CLK 		: IN STD_LOGIC;
    RSTN 		: IN STD_LOGIC;

-- inputs
	INP_A 		: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
	INP_B 		: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
	INP_C 		: IN STD_LOGIC_VECTOR(43 DOWNTO 0);

	INP_D 		: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
	INP_E 		: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
	INP_F 		: IN STD_LOGIC_VECTOR(43 DOWNTO 0);

-- Output

   	RESULT	 	: OUT STD_LOGIC_VECTOR(43 DOWNTO 0);
	OVERFLOW_O	: OUT STD_LOGIC;
	RES1		: OUT STD_LOGIC_VECTOR(43 DOWNTO 0)

	);
END Fourinput_42bit_Adder;


ARCHITECTURE  Adder42bit_Arch OF Fourinput_42bit_Adder IS

 -- COMPONENT DECLARATIONS

COMPONENT MultAdder IS
    -- Port list
    port(
        -- Inputs
        A0        : in  std_logic_vector(17 downto 0);
        A0_ACLR_N : in  std_logic;
        A0_EN     : in  std_logic;
        A0_SCLR_N : in  std_logic;
        B0        : in  std_logic_vector(17 downto 0);
        B0_ACLR_N : in  std_logic;
        B0_EN     : in  std_logic;
        B0_SCLR_N : in  std_logic;
        C         : in  std_logic_vector(43 downto 0);
        CLK       : in  std_logic;
        C_ACLR_N  : in  std_logic;
        C_EN      : in  std_logic;
        C_SCLR_N  : in  std_logic;
        P_ACLR_N  : in  std_logic;
        P_EN      : in  std_logic;
        P_SCLR_N  : in  std_logic;
        -- Outputs
        CARRYOUT  : out std_logic;
        CDOUT     : out std_logic_vector(43 downto 0);
        P         : out std_logic_vector(43 downto 0)
        );
END COMPONENT MultAdder;

COMPONENT MultAdder_w_Din is
    -- Port list
    port(
        -- Inputs
        A0        : in  std_logic_vector(17 downto 0);
        A0_ACLR_N : in  std_logic;
        A0_EN     : in  std_logic;
        A0_SCLR_N : in  std_logic;
        B0        : in  std_logic_vector(17 downto 0);
        B0_ACLR_N : in  std_logic;
        B0_EN     : in  std_logic;
        B0_SCLR_N : in  std_logic;
        C         : in  std_logic_vector(43 downto 0);
		CARRYIN   : in  std_logic;
        CDIN      : in  std_logic_vector(43 downto 0);
        CLK       : in  std_logic;
        C_ACLR_N  : in  std_logic;
        C_EN      : in  std_logic;
        C_SCLR_N  : in  std_logic;
        P_ACLR_N  : in  std_logic;
        P_EN      : in  std_logic;
        P_SCLR_N  : in  std_logic;
        -- Outputs
        CDOUT     : out std_logic_vector(43 downto 0);
        OVERFLOW  : out std_logic;
        P         : out std_logic_vector(43 downto 0)
        );
END COMPONENT MultAdder_w_Din;



 -- SIGNAL DECLARATIONS

SIGNAL D_in		: STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL E_in		: STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL F_in		: STD_LOGIC_VECTOR(43 DOWNTO 0);


SIGNAL CDIN_0 	: STD_LOGIC_VECTOR(43 DOWNTO 0);
SIGNAL CARRYIN	: STD_LOGIC;

BEGIN



PROCESS(RSTN,CLK)
BEGIN
	IF(RSTN = '0')THEN
		D_in <= (OTHERS => '0');
		E_in <= (OTHERS => '0');
		F_in <= (OTHERS => '0');
	ELSE
		IF(rising_edge(CLK))THEN
			D_in 	<= INP_D;
			E_in 	<= INP_E;
			F_in 	<= INP_F;
		END IF;
	END IF;
END PROCESS;

-- Port list
 U0 : MultAdder
		port map
		(
        A0        => INP_A,
        A0_ACLR_N => RSTN,
        A0_EN     => '1',
        A0_SCLR_N => '1',
        B0        => INP_B,
        B0_ACLR_N => RSTN,
        B0_EN     => '1',
        B0_SCLR_N => '1',
        C         => INP_C,
        CLK       => CLK,
        C_ACLR_N  => RSTN,
        C_EN      => '1',
        C_SCLR_N  => '1',
        P_ACLR_N  => RSTN,
        P_EN      => '1',
        P_SCLR_N  => '1',
        -- Outputs
        CARRYOUT  => CARRYIN,
        CDOUT     => CDIN_0,
        P         => RES1
        );



U1:MultAdder_w_Din
	port map(
        -- Inputs
    	A0        => D_in,
        A0_ACLR_N => RSTN,
        A0_EN     => '1',
        A0_SCLR_N => '1',
        B0        => E_in,
        B0_ACLR_N => RSTN,
        B0_EN     => '1',
        B0_SCLR_N => '1',
        C         => F_in,
		CARRYIN	  => CARRYIN,		
        CDIN      => CDIN_0,
        CLK       => CLK,
        C_ACLR_N  => RSTN, 
        C_EN      => '1',
        C_SCLR_N  => '1',
        P_ACLR_N  => RSTN,
        P_EN      => '1',
        P_SCLR_N  => '1',
        -- Outputs
        CDOUT     => OPEN,
        OVERFLOW  => OVERFLOW_O,
        P         => RESULT
        );



END Adder42bit_Arch;
