@W: CD275 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Fourinput_42bit_Adder\component\work\MultAdder\MultAdder_0\MultAdder_MultAdder_0_HARD_MULT_ADDSUB.vhd":35:12:35:15|Component declarations with different initial values are not supported.  Port cdin of component macc may have been given a different initial value in two different component declarations

