-- Version: v11.1 SP2 11.1.2.19

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity MultAdder_MultAdder_0_HARD_MULT_ADDSUB is

    port( RES1      : out   std_logic_vector(43 downto 0);
          INP_A_c   : in    std_logic_vector(17 downto 0);
          INP_B_c   : in    std_logic_vector(17 downto 0);
          INP_88b_c : in    std_logic_vector(43 downto 0);
          CARRYIN   : out   std_logic;
          RSTN_c    : in    std_logic;
          CLK_c     : in    std_logic
        );

end MultAdder_MultAdder_0_HARD_MULT_ADDSUB;

architecture DEF_ARCH of MultAdder_MultAdder_0_HARD_MULT_ADDSUB is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;
    signal nc34, nc9, nc13, nc23, nc33, nc16, nc26, nc27, nc17, 
        nc36, nc37, nc5, nc4, nc42, nc41, nc25, nc15, nc35, nc28, 
        nc18, nc38, nc1, nc2, nc22, nc12, nc21, nc11, nc3, nc32, 
        nc40, nc31, nc44, nc7, nc6, nc19, nc29, nc39, nc8, nc43, 
        nc20, nc10, nc24, nc14, nc30 : std_logic;

begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    U0 : MACC
      port map(CLK(1) => CLK_c, CLK(0) => CLK_c, A(17) => 
        INP_A_c(17), A(16) => INP_A_c(16), A(15) => INP_A_c(15), 
        A(14) => INP_A_c(14), A(13) => INP_A_c(13), A(12) => 
        INP_A_c(12), A(11) => INP_A_c(11), A(10) => INP_A_c(10), 
        A(9) => INP_A_c(9), A(8) => INP_A_c(8), A(7) => 
        INP_A_c(7), A(6) => INP_A_c(6), A(5) => INP_A_c(5), A(4)
         => INP_A_c(4), A(3) => INP_A_c(3), A(2) => INP_A_c(2), 
        A(1) => INP_A_c(1), A(0) => INP_A_c(0), A_EN(1) => 
        VCC_net_1, A_EN(0) => VCC_net_1, A_ARST_N(1) => RSTN_c, 
        A_ARST_N(0) => RSTN_c, A_SRST_N(1) => VCC_net_1, 
        A_SRST_N(0) => VCC_net_1, B(17) => INP_B_c(17), B(16) => 
        INP_B_c(16), B(15) => INP_B_c(15), B(14) => INP_B_c(14), 
        B(13) => INP_B_c(13), B(12) => INP_B_c(12), B(11) => 
        INP_B_c(11), B(10) => INP_B_c(10), B(9) => INP_B_c(9), 
        B(8) => INP_B_c(8), B(7) => INP_B_c(7), B(6) => 
        INP_B_c(6), B(5) => INP_B_c(5), B(4) => INP_B_c(4), B(3)
         => INP_B_c(3), B(2) => INP_B_c(2), B(1) => INP_B_c(1), 
        B(0) => INP_B_c(0), B_EN(1) => VCC_net_1, B_EN(0) => 
        VCC_net_1, B_ARST_N(1) => RSTN_c, B_ARST_N(0) => RSTN_c, 
        B_SRST_N(1) => VCC_net_1, B_SRST_N(0) => VCC_net_1, C(43)
         => INP_88b_c(43), C(42) => INP_88b_c(42), C(41) => 
        INP_88b_c(41), C(40) => INP_88b_c(40), C(39) => 
        INP_88b_c(39), C(38) => INP_88b_c(38), C(37) => 
        INP_88b_c(37), C(36) => INP_88b_c(36), C(35) => 
        INP_88b_c(35), C(34) => INP_88b_c(34), C(33) => 
        INP_88b_c(33), C(32) => INP_88b_c(32), C(31) => 
        INP_88b_c(31), C(30) => INP_88b_c(30), C(29) => 
        INP_88b_c(29), C(28) => INP_88b_c(28), C(27) => 
        INP_88b_c(27), C(26) => INP_88b_c(26), C(25) => 
        INP_88b_c(25), C(24) => INP_88b_c(24), C(23) => 
        INP_88b_c(23), C(22) => INP_88b_c(22), C(21) => 
        INP_88b_c(21), C(20) => INP_88b_c(20), C(19) => 
        INP_88b_c(19), C(18) => INP_88b_c(18), C(17) => 
        INP_88b_c(17), C(16) => INP_88b_c(16), C(15) => 
        INP_88b_c(15), C(14) => INP_88b_c(14), C(13) => 
        INP_88b_c(13), C(12) => INP_88b_c(12), C(11) => 
        INP_88b_c(11), C(10) => INP_88b_c(10), C(9) => 
        INP_88b_c(9), C(8) => INP_88b_c(8), C(7) => INP_88b_c(7), 
        C(6) => INP_88b_c(6), C(5) => INP_88b_c(5), C(4) => 
        INP_88b_c(4), C(3) => INP_88b_c(3), C(2) => INP_88b_c(2), 
        C(1) => INP_88b_c(1), C(0) => INP_88b_c(0), C_EN(1) => 
        VCC_net_1, C_EN(0) => VCC_net_1, C_ARST_N(1) => RSTN_c, 
        C_ARST_N(0) => RSTN_c, C_SRST_N(1) => VCC_net_1, 
        C_SRST_N(0) => VCC_net_1, P_EN(1) => VCC_net_1, P_EN(0)
         => VCC_net_1, P_ARST_N(1) => RSTN_c, P_ARST_N(0) => 
        RSTN_c, P_SRST_N(1) => VCC_net_1, P_SRST_N(0) => 
        VCC_net_1, FDBKSEL => GND_net_1, FDBKSEL_EN => VCC_net_1, 
        FDBKSEL_AL_N => VCC_net_1, FDBKSEL_SL_N => VCC_net_1, 
        CDSEL => GND_net_1, CDSEL_EN => VCC_net_1, CDSEL_AL_N => 
        VCC_net_1, CDSEL_SL_N => VCC_net_1, ARSHFT17 => GND_net_1, 
        ARSHFT17_EN => VCC_net_1, ARSHFT17_AL_N => VCC_net_1, 
        ARSHFT17_SL_N => VCC_net_1, SUB => GND_net_1, SUB_EN => 
        VCC_net_1, SUB_AL_N => VCC_net_1, SUB_SL_N => VCC_net_1, 
        CARRYIN => GND_net_1, SIMD => GND_net_1, DOTP => 
        GND_net_1, OVFL_CARRYOUT_SEL => VCC_net_1, A_BYPASS(1)
         => GND_net_1, A_BYPASS(0) => GND_net_1, B_BYPASS(1) => 
        GND_net_1, B_BYPASS(0) => GND_net_1, C_BYPASS(1) => 
        GND_net_1, C_BYPASS(0) => GND_net_1, P_BYPASS(1) => 
        GND_net_1, P_BYPASS(0) => GND_net_1, FDBKSEL_BYPASS => 
        VCC_net_1, FDBKSEL_AD => GND_net_1, FDBKSEL_SD_N => 
        VCC_net_1, CDSEL_BYPASS => VCC_net_1, CDSEL_AD => 
        GND_net_1, CDSEL_SD_N => VCC_net_1, ARSHFT17_BYPASS => 
        VCC_net_1, ARSHFT17_AD => GND_net_1, ARSHFT17_SD_N => 
        VCC_net_1, SUB_BYPASS => VCC_net_1, SUB_AD => GND_net_1, 
        SUB_SD_N => VCC_net_1, CDIN(43) => GND_net_1, CDIN(42)
         => GND_net_1, CDIN(41) => GND_net_1, CDIN(40) => 
        GND_net_1, CDIN(39) => GND_net_1, CDIN(38) => GND_net_1, 
        CDIN(37) => GND_net_1, CDIN(36) => GND_net_1, CDIN(35)
         => GND_net_1, CDIN(34) => GND_net_1, CDIN(33) => 
        GND_net_1, CDIN(32) => GND_net_1, CDIN(31) => GND_net_1, 
        CDIN(30) => GND_net_1, CDIN(29) => GND_net_1, CDIN(28)
         => GND_net_1, CDIN(27) => GND_net_1, CDIN(26) => 
        GND_net_1, CDIN(25) => GND_net_1, CDIN(24) => GND_net_1, 
        CDIN(23) => GND_net_1, CDIN(22) => GND_net_1, CDIN(21)
         => GND_net_1, CDIN(20) => GND_net_1, CDIN(19) => 
        GND_net_1, CDIN(18) => GND_net_1, CDIN(17) => GND_net_1, 
        CDIN(16) => GND_net_1, CDIN(15) => GND_net_1, CDIN(14)
         => GND_net_1, CDIN(13) => GND_net_1, CDIN(12) => 
        GND_net_1, CDIN(11) => GND_net_1, CDIN(10) => GND_net_1, 
        CDIN(9) => GND_net_1, CDIN(8) => GND_net_1, CDIN(7) => 
        GND_net_1, CDIN(6) => GND_net_1, CDIN(5) => GND_net_1, 
        CDIN(4) => GND_net_1, CDIN(3) => GND_net_1, CDIN(2) => 
        GND_net_1, CDIN(1) => GND_net_1, CDIN(0) => GND_net_1, 
        CDOUT(43) => nc34, CDOUT(42) => nc9, CDOUT(41) => nc13, 
        CDOUT(40) => nc23, CDOUT(39) => nc33, CDOUT(38) => nc16, 
        CDOUT(37) => nc26, CDOUT(36) => nc27, CDOUT(35) => nc17, 
        CDOUT(34) => nc36, CDOUT(33) => nc37, CDOUT(32) => nc5, 
        CDOUT(31) => nc4, CDOUT(30) => nc42, CDOUT(29) => nc41, 
        CDOUT(28) => nc25, CDOUT(27) => nc15, CDOUT(26) => nc35, 
        CDOUT(25) => nc28, CDOUT(24) => nc18, CDOUT(23) => nc38, 
        CDOUT(22) => nc1, CDOUT(21) => nc2, CDOUT(20) => nc22, 
        CDOUT(19) => nc12, CDOUT(18) => nc21, CDOUT(17) => nc11, 
        CDOUT(16) => nc3, CDOUT(15) => nc32, CDOUT(14) => nc40, 
        CDOUT(13) => nc31, CDOUT(12) => nc44, CDOUT(11) => nc7, 
        CDOUT(10) => nc6, CDOUT(9) => nc19, CDOUT(8) => nc29, 
        CDOUT(7) => nc39, CDOUT(6) => nc8, CDOUT(5) => nc43, 
        CDOUT(4) => nc20, CDOUT(3) => nc10, CDOUT(2) => nc24, 
        CDOUT(1) => nc14, CDOUT(0) => nc30, P(43) => RES1(43), 
        P(42) => RES1(42), P(41) => RES1(41), P(40) => RES1(40), 
        P(39) => RES1(39), P(38) => RES1(38), P(37) => RES1(37), 
        P(36) => RES1(36), P(35) => RES1(35), P(34) => RES1(34), 
        P(33) => RES1(33), P(32) => RES1(32), P(31) => RES1(31), 
        P(30) => RES1(30), P(29) => RES1(29), P(28) => RES1(28), 
        P(27) => RES1(27), P(26) => RES1(26), P(25) => RES1(25), 
        P(24) => RES1(24), P(23) => RES1(23), P(22) => RES1(22), 
        P(21) => RES1(21), P(20) => RES1(20), P(19) => RES1(19), 
        P(18) => RES1(18), P(17) => RES1(17), P(16) => RES1(16), 
        P(15) => RES1(15), P(14) => RES1(14), P(13) => RES1(13), 
        P(12) => RES1(12), P(11) => RES1(11), P(10) => RES1(10), 
        P(9) => RES1(9), P(8) => RES1(8), P(7) => RES1(7), P(6)
         => RES1(6), P(5) => RES1(5), P(4) => RES1(4), P(3) => 
        RES1(3), P(2) => RES1(2), P(1) => RES1(1), P(0) => 
        RES1(0), OVFL_CARRYOUT => CARRYIN);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity MultAdder is

    port( RES1      : out   std_logic_vector(43 downto 0);
          INP_A_c   : in    std_logic_vector(17 downto 0);
          INP_B_c   : in    std_logic_vector(17 downto 0);
          INP_88b_c : in    std_logic_vector(43 downto 0);
          CARRYIN   : out   std_logic;
          RSTN_c    : in    std_logic;
          CLK_c     : in    std_logic
        );

end MultAdder;

architecture DEF_ARCH of MultAdder is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component MultAdder_MultAdder_0_HARD_MULT_ADDSUB
    port( RES1      : out   std_logic_vector(43 downto 0);
          INP_A_c   : in    std_logic_vector(17 downto 0) := (others => 'U');
          INP_B_c   : in    std_logic_vector(17 downto 0) := (others => 'U');
          INP_88b_c : in    std_logic_vector(43 downto 0) := (others => 'U');
          CARRYIN   : out   std_logic;
          RSTN_c    : in    std_logic := 'U';
          CLK_c     : in    std_logic := 'U'
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

    for all : MultAdder_MultAdder_0_HARD_MULT_ADDSUB
	Use entity work.MultAdder_MultAdder_0_HARD_MULT_ADDSUB(DEF_ARCH);
begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    MultAdder_0 : MultAdder_MultAdder_0_HARD_MULT_ADDSUB
      port map(RES1(43) => RES1(43), RES1(42) => RES1(42), 
        RES1(41) => RES1(41), RES1(40) => RES1(40), RES1(39) => 
        RES1(39), RES1(38) => RES1(38), RES1(37) => RES1(37), 
        RES1(36) => RES1(36), RES1(35) => RES1(35), RES1(34) => 
        RES1(34), RES1(33) => RES1(33), RES1(32) => RES1(32), 
        RES1(31) => RES1(31), RES1(30) => RES1(30), RES1(29) => 
        RES1(29), RES1(28) => RES1(28), RES1(27) => RES1(27), 
        RES1(26) => RES1(26), RES1(25) => RES1(25), RES1(24) => 
        RES1(24), RES1(23) => RES1(23), RES1(22) => RES1(22), 
        RES1(21) => RES1(21), RES1(20) => RES1(20), RES1(19) => 
        RES1(19), RES1(18) => RES1(18), RES1(17) => RES1(17), 
        RES1(16) => RES1(16), RES1(15) => RES1(15), RES1(14) => 
        RES1(14), RES1(13) => RES1(13), RES1(12) => RES1(12), 
        RES1(11) => RES1(11), RES1(10) => RES1(10), RES1(9) => 
        RES1(9), RES1(8) => RES1(8), RES1(7) => RES1(7), RES1(6)
         => RES1(6), RES1(5) => RES1(5), RES1(4) => RES1(4), 
        RES1(3) => RES1(3), RES1(2) => RES1(2), RES1(1) => 
        RES1(1), RES1(0) => RES1(0), INP_A_c(17) => INP_A_c(17), 
        INP_A_c(16) => INP_A_c(16), INP_A_c(15) => INP_A_c(15), 
        INP_A_c(14) => INP_A_c(14), INP_A_c(13) => INP_A_c(13), 
        INP_A_c(12) => INP_A_c(12), INP_A_c(11) => INP_A_c(11), 
        INP_A_c(10) => INP_A_c(10), INP_A_c(9) => INP_A_c(9), 
        INP_A_c(8) => INP_A_c(8), INP_A_c(7) => INP_A_c(7), 
        INP_A_c(6) => INP_A_c(6), INP_A_c(5) => INP_A_c(5), 
        INP_A_c(4) => INP_A_c(4), INP_A_c(3) => INP_A_c(3), 
        INP_A_c(2) => INP_A_c(2), INP_A_c(1) => INP_A_c(1), 
        INP_A_c(0) => INP_A_c(0), INP_B_c(17) => INP_B_c(17), 
        INP_B_c(16) => INP_B_c(16), INP_B_c(15) => INP_B_c(15), 
        INP_B_c(14) => INP_B_c(14), INP_B_c(13) => INP_B_c(13), 
        INP_B_c(12) => INP_B_c(12), INP_B_c(11) => INP_B_c(11), 
        INP_B_c(10) => INP_B_c(10), INP_B_c(9) => INP_B_c(9), 
        INP_B_c(8) => INP_B_c(8), INP_B_c(7) => INP_B_c(7), 
        INP_B_c(6) => INP_B_c(6), INP_B_c(5) => INP_B_c(5), 
        INP_B_c(4) => INP_B_c(4), INP_B_c(3) => INP_B_c(3), 
        INP_B_c(2) => INP_B_c(2), INP_B_c(1) => INP_B_c(1), 
        INP_B_c(0) => INP_B_c(0), INP_88b_c(43) => INP_88b_c(43), 
        INP_88b_c(42) => INP_88b_c(42), INP_88b_c(41) => 
        INP_88b_c(41), INP_88b_c(40) => INP_88b_c(40), 
        INP_88b_c(39) => INP_88b_c(39), INP_88b_c(38) => 
        INP_88b_c(38), INP_88b_c(37) => INP_88b_c(37), 
        INP_88b_c(36) => INP_88b_c(36), INP_88b_c(35) => 
        INP_88b_c(35), INP_88b_c(34) => INP_88b_c(34), 
        INP_88b_c(33) => INP_88b_c(33), INP_88b_c(32) => 
        INP_88b_c(32), INP_88b_c(31) => INP_88b_c(31), 
        INP_88b_c(30) => INP_88b_c(30), INP_88b_c(29) => 
        INP_88b_c(29), INP_88b_c(28) => INP_88b_c(28), 
        INP_88b_c(27) => INP_88b_c(27), INP_88b_c(26) => 
        INP_88b_c(26), INP_88b_c(25) => INP_88b_c(25), 
        INP_88b_c(24) => INP_88b_c(24), INP_88b_c(23) => 
        INP_88b_c(23), INP_88b_c(22) => INP_88b_c(22), 
        INP_88b_c(21) => INP_88b_c(21), INP_88b_c(20) => 
        INP_88b_c(20), INP_88b_c(19) => INP_88b_c(19), 
        INP_88b_c(18) => INP_88b_c(18), INP_88b_c(17) => 
        INP_88b_c(17), INP_88b_c(16) => INP_88b_c(16), 
        INP_88b_c(15) => INP_88b_c(15), INP_88b_c(14) => 
        INP_88b_c(14), INP_88b_c(13) => INP_88b_c(13), 
        INP_88b_c(12) => INP_88b_c(12), INP_88b_c(11) => 
        INP_88b_c(11), INP_88b_c(10) => INP_88b_c(10), 
        INP_88b_c(9) => INP_88b_c(9), INP_88b_c(8) => 
        INP_88b_c(8), INP_88b_c(7) => INP_88b_c(7), INP_88b_c(6)
         => INP_88b_c(6), INP_88b_c(5) => INP_88b_c(5), 
        INP_88b_c(4) => INP_88b_c(4), INP_88b_c(3) => 
        INP_88b_c(3), INP_88b_c(2) => INP_88b_c(2), INP_88b_c(1)
         => INP_88b_c(1), INP_88b_c(0) => INP_88b_c(0), CARRYIN
         => CARRYIN, RSTN_c => RSTN_c, CLK_c => CLK_c);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity MultAdder_w_Din_MultAdder_w_Din_0_HARD_MULT_ADDSUB is

    port( RES2    : out   std_logic_vector(43 downto 0);
          D_in    : in    std_logic_vector(17 downto 0);
          E_in    : in    std_logic_vector(17 downto 0);
          F_in    : in    std_logic_vector(43 downto 0);
          RSTN_c  : in    std_logic;
          CLK_c   : in    std_logic;
          CARRYIN : in    std_logic
        );

end MultAdder_w_Din_MultAdder_w_Din_0_HARD_MULT_ADDSUB;

architecture DEF_ARCH of 
        MultAdder_w_Din_MultAdder_w_Din_0_HARD_MULT_ADDSUB is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;
    signal nc34, nc9, nc13, nc23, nc33, nc16, nc26, nc27, nc17, 
        nc36, nc37, nc5, nc4, nc42, nc41, nc25, nc15, nc35, nc28, 
        nc18, nc38, nc1, nc2, nc22, nc12, nc21, nc11, nc3, nc32, 
        nc40, nc31, nc44, nc7, nc6, nc19, nc29, nc39, nc8, nc43, 
        nc20, nc10, nc24, nc14, nc30 : std_logic;

begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    U0 : MACC
      port map(CLK(1) => CLK_c, CLK(0) => CLK_c, A(17) => 
        D_in(17), A(16) => D_in(16), A(15) => D_in(15), A(14) => 
        D_in(14), A(13) => D_in(13), A(12) => D_in(12), A(11) => 
        D_in(11), A(10) => D_in(10), A(9) => D_in(9), A(8) => 
        D_in(8), A(7) => D_in(7), A(6) => D_in(6), A(5) => 
        D_in(5), A(4) => D_in(4), A(3) => D_in(3), A(2) => 
        D_in(2), A(1) => D_in(1), A(0) => D_in(0), A_EN(1) => 
        VCC_net_1, A_EN(0) => VCC_net_1, A_ARST_N(1) => RSTN_c, 
        A_ARST_N(0) => RSTN_c, A_SRST_N(1) => VCC_net_1, 
        A_SRST_N(0) => VCC_net_1, B(17) => E_in(17), B(16) => 
        E_in(16), B(15) => E_in(15), B(14) => E_in(14), B(13) => 
        E_in(13), B(12) => E_in(12), B(11) => E_in(11), B(10) => 
        E_in(10), B(9) => E_in(9), B(8) => E_in(8), B(7) => 
        E_in(7), B(6) => E_in(6), B(5) => E_in(5), B(4) => 
        E_in(4), B(3) => E_in(3), B(2) => E_in(2), B(1) => 
        E_in(1), B(0) => E_in(0), B_EN(1) => VCC_net_1, B_EN(0)
         => VCC_net_1, B_ARST_N(1) => RSTN_c, B_ARST_N(0) => 
        RSTN_c, B_SRST_N(1) => VCC_net_1, B_SRST_N(0) => 
        VCC_net_1, C(43) => F_in(43), C(42) => F_in(42), C(41)
         => F_in(41), C(40) => F_in(40), C(39) => F_in(39), C(38)
         => F_in(38), C(37) => F_in(37), C(36) => F_in(36), C(35)
         => F_in(35), C(34) => F_in(34), C(33) => F_in(33), C(32)
         => F_in(32), C(31) => F_in(31), C(30) => F_in(30), C(29)
         => F_in(29), C(28) => F_in(28), C(27) => F_in(27), C(26)
         => F_in(26), C(25) => F_in(25), C(24) => F_in(24), C(23)
         => F_in(23), C(22) => F_in(22), C(21) => F_in(21), C(20)
         => F_in(20), C(19) => F_in(19), C(18) => F_in(18), C(17)
         => F_in(17), C(16) => F_in(16), C(15) => F_in(15), C(14)
         => F_in(14), C(13) => F_in(13), C(12) => F_in(12), C(11)
         => F_in(11), C(10) => F_in(10), C(9) => F_in(9), C(8)
         => F_in(8), C(7) => F_in(7), C(6) => F_in(6), C(5) => 
        F_in(5), C(4) => F_in(4), C(3) => F_in(3), C(2) => 
        F_in(2), C(1) => F_in(1), C(0) => F_in(0), C_EN(1) => 
        VCC_net_1, C_EN(0) => VCC_net_1, C_ARST_N(1) => RSTN_c, 
        C_ARST_N(0) => RSTN_c, C_SRST_N(1) => VCC_net_1, 
        C_SRST_N(0) => VCC_net_1, P_EN(1) => VCC_net_1, P_EN(0)
         => VCC_net_1, P_ARST_N(1) => RSTN_c, P_ARST_N(0) => 
        RSTN_c, P_SRST_N(1) => VCC_net_1, P_SRST_N(0) => 
        VCC_net_1, FDBKSEL => GND_net_1, FDBKSEL_EN => VCC_net_1, 
        FDBKSEL_AL_N => VCC_net_1, FDBKSEL_SL_N => VCC_net_1, 
        CDSEL => GND_net_1, CDSEL_EN => VCC_net_1, CDSEL_AL_N => 
        VCC_net_1, CDSEL_SL_N => VCC_net_1, ARSHFT17 => GND_net_1, 
        ARSHFT17_EN => VCC_net_1, ARSHFT17_AL_N => VCC_net_1, 
        ARSHFT17_SL_N => VCC_net_1, SUB => GND_net_1, SUB_EN => 
        VCC_net_1, SUB_AL_N => VCC_net_1, SUB_SL_N => VCC_net_1, 
        CARRYIN => CARRYIN, SIMD => GND_net_1, DOTP => GND_net_1, 
        OVFL_CARRYOUT_SEL => GND_net_1, A_BYPASS(1) => GND_net_1, 
        A_BYPASS(0) => GND_net_1, B_BYPASS(1) => GND_net_1, 
        B_BYPASS(0) => GND_net_1, C_BYPASS(1) => GND_net_1, 
        C_BYPASS(0) => GND_net_1, P_BYPASS(1) => GND_net_1, 
        P_BYPASS(0) => GND_net_1, FDBKSEL_BYPASS => VCC_net_1, 
        FDBKSEL_AD => GND_net_1, FDBKSEL_SD_N => VCC_net_1, 
        CDSEL_BYPASS => VCC_net_1, CDSEL_AD => GND_net_1, 
        CDSEL_SD_N => VCC_net_1, ARSHFT17_BYPASS => VCC_net_1, 
        ARSHFT17_AD => GND_net_1, ARSHFT17_SD_N => VCC_net_1, 
        SUB_BYPASS => VCC_net_1, SUB_AD => GND_net_1, SUB_SD_N
         => VCC_net_1, CDIN(43) => GND_net_1, CDIN(42) => 
        GND_net_1, CDIN(41) => GND_net_1, CDIN(40) => GND_net_1, 
        CDIN(39) => GND_net_1, CDIN(38) => GND_net_1, CDIN(37)
         => GND_net_1, CDIN(36) => GND_net_1, CDIN(35) => 
        GND_net_1, CDIN(34) => GND_net_1, CDIN(33) => GND_net_1, 
        CDIN(32) => GND_net_1, CDIN(31) => GND_net_1, CDIN(30)
         => GND_net_1, CDIN(29) => GND_net_1, CDIN(28) => 
        GND_net_1, CDIN(27) => GND_net_1, CDIN(26) => GND_net_1, 
        CDIN(25) => GND_net_1, CDIN(24) => GND_net_1, CDIN(23)
         => GND_net_1, CDIN(22) => GND_net_1, CDIN(21) => 
        GND_net_1, CDIN(20) => GND_net_1, CDIN(19) => GND_net_1, 
        CDIN(18) => GND_net_1, CDIN(17) => GND_net_1, CDIN(16)
         => GND_net_1, CDIN(15) => GND_net_1, CDIN(14) => 
        GND_net_1, CDIN(13) => GND_net_1, CDIN(12) => GND_net_1, 
        CDIN(11) => GND_net_1, CDIN(10) => GND_net_1, CDIN(9) => 
        GND_net_1, CDIN(8) => GND_net_1, CDIN(7) => GND_net_1, 
        CDIN(6) => GND_net_1, CDIN(5) => GND_net_1, CDIN(4) => 
        GND_net_1, CDIN(3) => GND_net_1, CDIN(2) => GND_net_1, 
        CDIN(1) => GND_net_1, CDIN(0) => GND_net_1, CDOUT(43) => 
        nc34, CDOUT(42) => nc9, CDOUT(41) => nc13, CDOUT(40) => 
        nc23, CDOUT(39) => nc33, CDOUT(38) => nc16, CDOUT(37) => 
        nc26, CDOUT(36) => nc27, CDOUT(35) => nc17, CDOUT(34) => 
        nc36, CDOUT(33) => nc37, CDOUT(32) => nc5, CDOUT(31) => 
        nc4, CDOUT(30) => nc42, CDOUT(29) => nc41, CDOUT(28) => 
        nc25, CDOUT(27) => nc15, CDOUT(26) => nc35, CDOUT(25) => 
        nc28, CDOUT(24) => nc18, CDOUT(23) => nc38, CDOUT(22) => 
        nc1, CDOUT(21) => nc2, CDOUT(20) => nc22, CDOUT(19) => 
        nc12, CDOUT(18) => nc21, CDOUT(17) => nc11, CDOUT(16) => 
        nc3, CDOUT(15) => nc32, CDOUT(14) => nc40, CDOUT(13) => 
        nc31, CDOUT(12) => nc44, CDOUT(11) => nc7, CDOUT(10) => 
        nc6, CDOUT(9) => nc19, CDOUT(8) => nc29, CDOUT(7) => nc39, 
        CDOUT(6) => nc8, CDOUT(5) => nc43, CDOUT(4) => nc20, 
        CDOUT(3) => nc10, CDOUT(2) => nc24, CDOUT(1) => nc14, 
        CDOUT(0) => nc30, P(43) => RES2(43), P(42) => RES2(42), 
        P(41) => RES2(41), P(40) => RES2(40), P(39) => RES2(39), 
        P(38) => RES2(38), P(37) => RES2(37), P(36) => RES2(36), 
        P(35) => RES2(35), P(34) => RES2(34), P(33) => RES2(33), 
        P(32) => RES2(32), P(31) => RES2(31), P(30) => RES2(30), 
        P(29) => RES2(29), P(28) => RES2(28), P(27) => RES2(27), 
        P(26) => RES2(26), P(25) => RES2(25), P(24) => RES2(24), 
        P(23) => RES2(23), P(22) => RES2(22), P(21) => RES2(21), 
        P(20) => RES2(20), P(19) => RES2(19), P(18) => RES2(18), 
        P(17) => RES2(17), P(16) => RES2(16), P(15) => RES2(15), 
        P(14) => RES2(14), P(13) => RES2(13), P(12) => RES2(12), 
        P(11) => RES2(11), P(10) => RES2(10), P(9) => RES2(9), 
        P(8) => RES2(8), P(7) => RES2(7), P(6) => RES2(6), P(5)
         => RES2(5), P(4) => RES2(4), P(3) => RES2(3), P(2) => 
        RES2(2), P(1) => RES2(1), P(0) => RES2(0), OVFL_CARRYOUT
         => OPEN);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity MultAdder_w_Din is

    port( RES2    : out   std_logic_vector(43 downto 0);
          D_in    : in    std_logic_vector(17 downto 0);
          E_in    : in    std_logic_vector(17 downto 0);
          F_in    : in    std_logic_vector(43 downto 0);
          RSTN_c  : in    std_logic;
          CLK_c   : in    std_logic;
          CARRYIN : in    std_logic
        );

end MultAdder_w_Din;

architecture DEF_ARCH of MultAdder_w_Din is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component MultAdder_w_Din_MultAdder_w_Din_0_HARD_MULT_ADDSUB
    port( RES2    : out   std_logic_vector(43 downto 0);
          D_in    : in    std_logic_vector(17 downto 0) := (others => 'U');
          E_in    : in    std_logic_vector(17 downto 0) := (others => 'U');
          F_in    : in    std_logic_vector(43 downto 0) := (others => 'U');
          RSTN_c  : in    std_logic := 'U';
          CLK_c   : in    std_logic := 'U';
          CARRYIN : in    std_logic := 'U'
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

    for all : MultAdder_w_Din_MultAdder_w_Din_0_HARD_MULT_ADDSUB
	Use entity work.
        MultAdder_w_Din_MultAdder_w_Din_0_HARD_MULT_ADDSUB(DEF_ARCH);
begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    MultAdder_w_Din_0 : 
        MultAdder_w_Din_MultAdder_w_Din_0_HARD_MULT_ADDSUB
      port map(RES2(43) => RES2(43), RES2(42) => RES2(42), 
        RES2(41) => RES2(41), RES2(40) => RES2(40), RES2(39) => 
        RES2(39), RES2(38) => RES2(38), RES2(37) => RES2(37), 
        RES2(36) => RES2(36), RES2(35) => RES2(35), RES2(34) => 
        RES2(34), RES2(33) => RES2(33), RES2(32) => RES2(32), 
        RES2(31) => RES2(31), RES2(30) => RES2(30), RES2(29) => 
        RES2(29), RES2(28) => RES2(28), RES2(27) => RES2(27), 
        RES2(26) => RES2(26), RES2(25) => RES2(25), RES2(24) => 
        RES2(24), RES2(23) => RES2(23), RES2(22) => RES2(22), 
        RES2(21) => RES2(21), RES2(20) => RES2(20), RES2(19) => 
        RES2(19), RES2(18) => RES2(18), RES2(17) => RES2(17), 
        RES2(16) => RES2(16), RES2(15) => RES2(15), RES2(14) => 
        RES2(14), RES2(13) => RES2(13), RES2(12) => RES2(12), 
        RES2(11) => RES2(11), RES2(10) => RES2(10), RES2(9) => 
        RES2(9), RES2(8) => RES2(8), RES2(7) => RES2(7), RES2(6)
         => RES2(6), RES2(5) => RES2(5), RES2(4) => RES2(4), 
        RES2(3) => RES2(3), RES2(2) => RES2(2), RES2(1) => 
        RES2(1), RES2(0) => RES2(0), D_in(17) => D_in(17), 
        D_in(16) => D_in(16), D_in(15) => D_in(15), D_in(14) => 
        D_in(14), D_in(13) => D_in(13), D_in(12) => D_in(12), 
        D_in(11) => D_in(11), D_in(10) => D_in(10), D_in(9) => 
        D_in(9), D_in(8) => D_in(8), D_in(7) => D_in(7), D_in(6)
         => D_in(6), D_in(5) => D_in(5), D_in(4) => D_in(4), 
        D_in(3) => D_in(3), D_in(2) => D_in(2), D_in(1) => 
        D_in(1), D_in(0) => D_in(0), E_in(17) => E_in(17), 
        E_in(16) => E_in(16), E_in(15) => E_in(15), E_in(14) => 
        E_in(14), E_in(13) => E_in(13), E_in(12) => E_in(12), 
        E_in(11) => E_in(11), E_in(10) => E_in(10), E_in(9) => 
        E_in(9), E_in(8) => E_in(8), E_in(7) => E_in(7), E_in(6)
         => E_in(6), E_in(5) => E_in(5), E_in(4) => E_in(4), 
        E_in(3) => E_in(3), E_in(2) => E_in(2), E_in(1) => 
        E_in(1), E_in(0) => E_in(0), F_in(43) => F_in(43), 
        F_in(42) => F_in(42), F_in(41) => F_in(41), F_in(40) => 
        F_in(40), F_in(39) => F_in(39), F_in(38) => F_in(38), 
        F_in(37) => F_in(37), F_in(36) => F_in(36), F_in(35) => 
        F_in(35), F_in(34) => F_in(34), F_in(33) => F_in(33), 
        F_in(32) => F_in(32), F_in(31) => F_in(31), F_in(30) => 
        F_in(30), F_in(29) => F_in(29), F_in(28) => F_in(28), 
        F_in(27) => F_in(27), F_in(26) => F_in(26), F_in(25) => 
        F_in(25), F_in(24) => F_in(24), F_in(23) => F_in(23), 
        F_in(22) => F_in(22), F_in(21) => F_in(21), F_in(20) => 
        F_in(20), F_in(19) => F_in(19), F_in(18) => F_in(18), 
        F_in(17) => F_in(17), F_in(16) => F_in(16), F_in(15) => 
        F_in(15), F_in(14) => F_in(14), F_in(13) => F_in(13), 
        F_in(12) => F_in(12), F_in(11) => F_in(11), F_in(10) => 
        F_in(10), F_in(9) => F_in(9), F_in(8) => F_in(8), F_in(7)
         => F_in(7), F_in(6) => F_in(6), F_in(5) => F_in(5), 
        F_in(4) => F_in(4), F_in(3) => F_in(3), F_in(2) => 
        F_in(2), F_in(1) => F_in(1), F_in(0) => F_in(0), RSTN_c
         => RSTN_c, CLK_c => CLK_c, CARRYIN => CARRYIN);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Adder_Sub_88bit is

    port( INP_A   : in    std_logic_vector(17 downto 0);
          INP_B   : in    std_logic_vector(17 downto 0);
          INP_88b : in    std_logic_vector(87 downto 0);
          INP_D   : in    std_logic_vector(17 downto 0);
          INP_E   : in    std_logic_vector(17 downto 0);
          RESULT  : out   std_logic_vector(87 downto 0);
          CLK     : in    std_logic;
          RSTN    : in    std_logic
        );

end Adder_Sub_88bit;

architecture DEF_ARCH of Adder_Sub_88bit is 

  component INBUF
    generic (IOSTD:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component OUTBUF
    generic (IOSTD:string := "");

    port( D   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component CLKINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component MultAdder
    port( RES1      : out   std_logic_vector(43 downto 0);
          INP_A_c   : in    std_logic_vector(17 downto 0) := (others => 'U');
          INP_B_c   : in    std_logic_vector(17 downto 0) := (others => 'U');
          INP_88b_c : in    std_logic_vector(43 downto 0) := (others => 'U');
          CARRYIN   : out   std_logic;
          RSTN_c    : in    std_logic := 'U';
          CLK_c     : in    std_logic := 'U'
        );
  end component;

  component MultAdder_w_Din
    port( RES2    : out   std_logic_vector(43 downto 0);
          D_in    : in    std_logic_vector(17 downto 0) := (others => 'U');
          E_in    : in    std_logic_vector(17 downto 0) := (others => 'U');
          F_in    : in    std_logic_vector(43 downto 0) := (others => 'U');
          RSTN_c  : in    std_logic := 'U';
          CLK_c   : in    std_logic := 'U';
          CARRYIN : in    std_logic := 'U'
        );
  end component;

    signal \RES1[0]\, \RES1[1]\, \RES1[2]\, \RES1[3]\, \RES1[4]\, 
        \RES1[5]\, \RES1[6]\, \RES1[7]\, \RES1[8]\, \RES1[9]\, 
        \RES1[10]\, \RES1[11]\, \RES1[12]\, \RES1[13]\, 
        \RES1[14]\, \RES1[15]\, \RES1[16]\, \RES1[17]\, 
        \RES1[18]\, \RES1[19]\, \RES1[20]\, \RES1[21]\, 
        \RES1[22]\, \RES1[23]\, \RES1[24]\, \RES1[25]\, 
        \RES1[26]\, \RES1[27]\, \RES1[28]\, \RES1[29]\, 
        \RES1[30]\, \RES1[31]\, \RES1[32]\, \RES1[33]\, 
        \RES1[34]\, \RES1[35]\, \RES1[36]\, \RES1[37]\, 
        \RES1[38]\, \RES1[39]\, \RES1[40]\, \RES1[41]\, 
        \RES1[42]\, \RES1[43]\, \RES2[0]\, \RES2[1]\, \RES2[2]\, 
        \RES2[3]\, \RES2[4]\, \RES2[5]\, \RES2[6]\, \RES2[7]\, 
        \RES2[8]\, \RES2[9]\, \RES2[10]\, \RES2[11]\, \RES2[12]\, 
        \RES2[13]\, \RES2[14]\, \RES2[15]\, \RES2[16]\, 
        \RES2[17]\, \RES2[18]\, \RES2[19]\, \RES2[20]\, 
        \RES2[21]\, \RES2[22]\, \RES2[23]\, \RES2[24]\, 
        \RES2[25]\, \RES2[26]\, \RES2[27]\, \RES2[28]\, 
        \RES2[29]\, \RES2[30]\, \RES2[31]\, \RES2[32]\, 
        \RES2[33]\, \RES2[34]\, \RES2[35]\, \RES2[36]\, 
        \RES2[37]\, \RES2[38]\, \RES2[39]\, \RES2[40]\, 
        \RES2[41]\, \RES2[42]\, \RES2[43]\, CARRYIN, 
        \D_in[0]_net_1\, \D_in[1]_net_1\, \D_in[2]_net_1\, 
        \D_in[3]_net_1\, \D_in[4]_net_1\, \D_in[5]_net_1\, 
        \D_in[6]_net_1\, \D_in[7]_net_1\, \D_in[8]_net_1\, 
        \D_in[9]_net_1\, \D_in[10]_net_1\, \D_in[11]_net_1\, 
        \D_in[12]_net_1\, \D_in[13]_net_1\, \D_in[14]_net_1\, 
        \D_in[15]_net_1\, \D_in[16]_net_1\, \D_in[17]_net_1\, 
        \E_in[0]_net_1\, \E_in[1]_net_1\, \E_in[2]_net_1\, 
        \E_in[3]_net_1\, \E_in[4]_net_1\, \E_in[5]_net_1\, 
        \E_in[6]_net_1\, \E_in[7]_net_1\, \E_in[8]_net_1\, 
        \E_in[9]_net_1\, \E_in[10]_net_1\, \E_in[11]_net_1\, 
        \E_in[12]_net_1\, \E_in[13]_net_1\, \E_in[14]_net_1\, 
        \E_in[15]_net_1\, \E_in[16]_net_1\, \E_in[17]_net_1\, 
        \F_in[0]_net_1\, \F_in[1]_net_1\, \F_in[2]_net_1\, 
        \F_in[3]_net_1\, \F_in[4]_net_1\, \F_in[5]_net_1\, 
        \F_in[6]_net_1\, \F_in[7]_net_1\, \F_in[8]_net_1\, 
        \F_in[9]_net_1\, \F_in[10]_net_1\, \F_in[11]_net_1\, 
        \F_in[12]_net_1\, \F_in[13]_net_1\, \F_in[14]_net_1\, 
        \F_in[15]_net_1\, \F_in[16]_net_1\, \F_in[17]_net_1\, 
        \F_in[18]_net_1\, \F_in[19]_net_1\, \F_in[20]_net_1\, 
        \F_in[21]_net_1\, \F_in[22]_net_1\, \F_in[23]_net_1\, 
        \F_in[24]_net_1\, \F_in[25]_net_1\, \F_in[26]_net_1\, 
        \F_in[27]_net_1\, \F_in[28]_net_1\, \F_in[29]_net_1\, 
        \F_in[30]_net_1\, \F_in[31]_net_1\, \F_in[32]_net_1\, 
        \F_in[33]_net_1\, \F_in[34]_net_1\, \F_in[35]_net_1\, 
        \F_in[36]_net_1\, \F_in[37]_net_1\, \F_in[38]_net_1\, 
        \F_in[39]_net_1\, \F_in[40]_net_1\, \F_in[41]_net_1\, 
        \F_in[42]_net_1\, \F_in[43]_net_1\, VCC_net_1, GND_net_1, 
        \D_in_r[0]_net_1\, \D_in_r[1]_net_1\, \D_in_r[2]_net_1\, 
        \D_in_r[3]_net_1\, \D_in_r[4]_net_1\, \D_in_r[5]_net_1\, 
        \D_in_r[6]_net_1\, \D_in_r[7]_net_1\, \D_in_r[8]_net_1\, 
        \D_in_r[9]_net_1\, \D_in_r[10]_net_1\, \D_in_r[11]_net_1\, 
        \D_in_r[12]_net_1\, \D_in_r[13]_net_1\, 
        \D_in_r[14]_net_1\, \D_in_r[15]_net_1\, 
        \D_in_r[16]_net_1\, \D_in_r[17]_net_1\, \E_in_r[0]_net_1\, 
        \E_in_r[1]_net_1\, \E_in_r[2]_net_1\, \E_in_r[3]_net_1\, 
        \E_in_r[4]_net_1\, \E_in_r[5]_net_1\, \E_in_r[6]_net_1\, 
        \E_in_r[7]_net_1\, \E_in_r[8]_net_1\, \E_in_r[9]_net_1\, 
        \E_in_r[10]_net_1\, \E_in_r[11]_net_1\, 
        \E_in_r[12]_net_1\, \E_in_r[13]_net_1\, 
        \E_in_r[14]_net_1\, \E_in_r[15]_net_1\, 
        \E_in_r[16]_net_1\, \E_in_r[17]_net_1\, \F_in_r[0]_net_1\, 
        \F_in_r[1]_net_1\, \F_in_r[2]_net_1\, \F_in_r[3]_net_1\, 
        \F_in_r[4]_net_1\, \F_in_r[5]_net_1\, \F_in_r[6]_net_1\, 
        \F_in_r[7]_net_1\, \F_in_r[8]_net_1\, \F_in_r[9]_net_1\, 
        \F_in_r[10]_net_1\, \F_in_r[11]_net_1\, 
        \F_in_r[12]_net_1\, \F_in_r[13]_net_1\, 
        \F_in_r[14]_net_1\, \F_in_r[15]_net_1\, 
        \F_in_r[16]_net_1\, \F_in_r[17]_net_1\, 
        \F_in_r[18]_net_1\, \F_in_r[19]_net_1\, 
        \F_in_r[20]_net_1\, \F_in_r[21]_net_1\, 
        \F_in_r[22]_net_1\, \F_in_r[23]_net_1\, 
        \F_in_r[24]_net_1\, \F_in_r[25]_net_1\, 
        \F_in_r[26]_net_1\, \F_in_r[27]_net_1\, 
        \F_in_r[28]_net_1\, \F_in_r[29]_net_1\, 
        \F_in_r[30]_net_1\, \F_in_r[31]_net_1\, 
        \F_in_r[32]_net_1\, \F_in_r[33]_net_1\, 
        \F_in_r[34]_net_1\, \F_in_r[35]_net_1\, 
        \F_in_r[36]_net_1\, \F_in_r[37]_net_1\, 
        \F_in_r[38]_net_1\, \F_in_r[39]_net_1\, 
        \F_in_r[40]_net_1\, \F_in_r[41]_net_1\, 
        \F_in_r[42]_net_1\, \F_in_r[43]_net_1\, CLK_c, RSTN_c, 
        \INP_A_c[0]\, \INP_A_c[1]\, \INP_A_c[2]\, \INP_A_c[3]\, 
        \INP_A_c[4]\, \INP_A_c[5]\, \INP_A_c[6]\, \INP_A_c[7]\, 
        \INP_A_c[8]\, \INP_A_c[9]\, \INP_A_c[10]\, \INP_A_c[11]\, 
        \INP_A_c[12]\, \INP_A_c[13]\, \INP_A_c[14]\, 
        \INP_A_c[15]\, \INP_A_c[16]\, \INP_A_c[17]\, \INP_B_c[0]\, 
        \INP_B_c[1]\, \INP_B_c[2]\, \INP_B_c[3]\, \INP_B_c[4]\, 
        \INP_B_c[5]\, \INP_B_c[6]\, \INP_B_c[7]\, \INP_B_c[8]\, 
        \INP_B_c[9]\, \INP_B_c[10]\, \INP_B_c[11]\, \INP_B_c[12]\, 
        \INP_B_c[13]\, \INP_B_c[14]\, \INP_B_c[15]\, 
        \INP_B_c[16]\, \INP_B_c[17]\, \INP_88b_c[0]\, 
        \INP_88b_c[1]\, \INP_88b_c[2]\, \INP_88b_c[3]\, 
        \INP_88b_c[4]\, \INP_88b_c[5]\, \INP_88b_c[6]\, 
        \INP_88b_c[7]\, \INP_88b_c[8]\, \INP_88b_c[9]\, 
        \INP_88b_c[10]\, \INP_88b_c[11]\, \INP_88b_c[12]\, 
        \INP_88b_c[13]\, \INP_88b_c[14]\, \INP_88b_c[15]\, 
        \INP_88b_c[16]\, \INP_88b_c[17]\, \INP_88b_c[18]\, 
        \INP_88b_c[19]\, \INP_88b_c[20]\, \INP_88b_c[21]\, 
        \INP_88b_c[22]\, \INP_88b_c[23]\, \INP_88b_c[24]\, 
        \INP_88b_c[25]\, \INP_88b_c[26]\, \INP_88b_c[27]\, 
        \INP_88b_c[28]\, \INP_88b_c[29]\, \INP_88b_c[30]\, 
        \INP_88b_c[31]\, \INP_88b_c[32]\, \INP_88b_c[33]\, 
        \INP_88b_c[34]\, \INP_88b_c[35]\, \INP_88b_c[36]\, 
        \INP_88b_c[37]\, \INP_88b_c[38]\, \INP_88b_c[39]\, 
        \INP_88b_c[40]\, \INP_88b_c[41]\, \INP_88b_c[42]\, 
        \INP_88b_c[43]\, \INP_88b_c[44]\, \INP_88b_c[45]\, 
        \INP_88b_c[46]\, \INP_88b_c[47]\, \INP_88b_c[48]\, 
        \INP_88b_c[49]\, \INP_88b_c[50]\, \INP_88b_c[51]\, 
        \INP_88b_c[52]\, \INP_88b_c[53]\, \INP_88b_c[54]\, 
        \INP_88b_c[55]\, \INP_88b_c[56]\, \INP_88b_c[57]\, 
        \INP_88b_c[58]\, \INP_88b_c[59]\, \INP_88b_c[60]\, 
        \INP_88b_c[61]\, \INP_88b_c[62]\, \INP_88b_c[63]\, 
        \INP_88b_c[64]\, \INP_88b_c[65]\, \INP_88b_c[66]\, 
        \INP_88b_c[67]\, \INP_88b_c[68]\, \INP_88b_c[69]\, 
        \INP_88b_c[70]\, \INP_88b_c[71]\, \INP_88b_c[72]\, 
        \INP_88b_c[73]\, \INP_88b_c[74]\, \INP_88b_c[75]\, 
        \INP_88b_c[76]\, \INP_88b_c[77]\, \INP_88b_c[78]\, 
        \INP_88b_c[79]\, \INP_88b_c[80]\, \INP_88b_c[81]\, 
        \INP_88b_c[82]\, \INP_88b_c[83]\, \INP_88b_c[84]\, 
        \INP_88b_c[85]\, \INP_88b_c[86]\, \INP_88b_c[87]\, 
        \INP_D_c[0]\, \INP_D_c[1]\, \INP_D_c[2]\, \INP_D_c[3]\, 
        \INP_D_c[4]\, \INP_D_c[5]\, \INP_D_c[6]\, \INP_D_c[7]\, 
        \INP_D_c[8]\, \INP_D_c[9]\, \INP_D_c[10]\, \INP_D_c[11]\, 
        \INP_D_c[12]\, \INP_D_c[13]\, \INP_D_c[14]\, 
        \INP_D_c[15]\, \INP_D_c[16]\, \INP_D_c[17]\, \INP_E_c[0]\, 
        \INP_E_c[1]\, \INP_E_c[2]\, \INP_E_c[3]\, \INP_E_c[4]\, 
        \INP_E_c[5]\, \INP_E_c[6]\, \INP_E_c[7]\, \INP_E_c[8]\, 
        \INP_E_c[9]\, \INP_E_c[10]\, \INP_E_c[11]\, \INP_E_c[12]\, 
        \INP_E_c[13]\, \INP_E_c[14]\, \INP_E_c[15]\, 
        \INP_E_c[16]\, \INP_E_c[17]\, \CLK_ibuf\, \RSTN_ibuf\
         : std_logic;

    for all : MultAdder
	Use entity work.MultAdder(DEF_ARCH);
    for all : MultAdder_w_Din
	Use entity work.MultAdder_w_Din(DEF_ARCH);
begin 


    \INP_88b_ibuf[87]\ : INBUF
      port map(PAD => INP_88b(87), Y => \INP_88b_c[87]\);
    
    \F_in[39]\ : SLE
      port map(D => \F_in_r[39]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[39]_net_1\);
    
    \D_in_r[9]\ : SLE
      port map(D => \INP_D_c[9]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[9]_net_1\);
    
    \RESULT_obuf[60]\ : OUTBUF
      port map(D => \RES2[16]\, PAD => RESULT(60));
    
    \RESULT_obuf[15]\ : OUTBUF
      port map(D => \RES1[15]\, PAD => RESULT(15));
    
    \D_in[0]\ : SLE
      port map(D => \D_in_r[0]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[0]_net_1\);
    
    \INP_A_ibuf[4]\ : INBUF
      port map(PAD => INP_A(4), Y => \INP_A_c[4]\);
    
    \D_in[16]\ : SLE
      port map(D => \D_in_r[16]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[16]_net_1\);
    
    \INP_88b_ibuf[33]\ : INBUF
      port map(PAD => INP_88b(33), Y => \INP_88b_c[33]\);
    
    \INP_D_ibuf[15]\ : INBUF
      port map(PAD => INP_D(15), Y => \INP_D_c[15]\);
    
    \INP_88b_ibuf[44]\ : INBUF
      port map(PAD => INP_88b(44), Y => \INP_88b_c[44]\);
    
    \E_in_r[15]\ : SLE
      port map(D => \INP_E_c[15]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[15]_net_1\);
    
    \RESULT_obuf[38]\ : OUTBUF
      port map(D => \RES1[38]\, PAD => RESULT(38));
    
    \E_in_r[10]\ : SLE
      port map(D => \INP_E_c[10]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[10]_net_1\);
    
    \E_in[0]\ : SLE
      port map(D => \E_in_r[0]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[0]_net_1\);
    
    \E_in_r[5]\ : SLE
      port map(D => \INP_E_c[5]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[5]_net_1\);
    
    \F_in_r[38]\ : SLE
      port map(D => \INP_88b_c[82]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[38]_net_1\);
    
    \INP_88b_ibuf[70]\ : INBUF
      port map(PAD => INP_88b(70), Y => \INP_88b_c[70]\);
    
    \RESULT_obuf[21]\ : OUTBUF
      port map(D => \RES1[21]\, PAD => RESULT(21));
    
    \INP_B_ibuf[13]\ : INBUF
      port map(PAD => INP_B(13), Y => \INP_B_c[13]\);
    
    \F_in[6]\ : SLE
      port map(D => \F_in_r[6]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[6]_net_1\);
    
    \RESULT_obuf[62]\ : OUTBUF
      port map(D => \RES2[18]\, PAD => RESULT(62));
    
    \RESULT_obuf[34]\ : OUTBUF
      port map(D => \RES1[34]\, PAD => RESULT(34));
    
    \INP_88b_ibuf[20]\ : INBUF
      port map(PAD => INP_88b(20), Y => \INP_88b_c[20]\);
    
    \RESULT_obuf[45]\ : OUTBUF
      port map(D => \RES2[1]\, PAD => RESULT(45));
    
    \F_in_r[25]\ : SLE
      port map(D => \INP_88b_c[69]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[25]_net_1\);
    
    \F_in[26]\ : SLE
      port map(D => \F_in_r[26]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[26]_net_1\);
    
    \RESULT_obuf[73]\ : OUTBUF
      port map(D => \RES2[29]\, PAD => RESULT(73));
    
    \RESULT_obuf[29]\ : OUTBUF
      port map(D => \RES1[29]\, PAD => RESULT(29));
    
    \INP_E_ibuf[9]\ : INBUF
      port map(PAD => INP_E(9), Y => \INP_E_c[9]\);
    
    \INP_88b_ibuf[14]\ : INBUF
      port map(PAD => INP_88b(14), Y => \INP_88b_c[14]\);
    
    \F_in_r[5]\ : SLE
      port map(D => \INP_88b_c[49]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[5]_net_1\);
    
    \D_in_r[13]\ : SLE
      port map(D => \INP_D_c[13]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[13]_net_1\);
    
    \F_in[36]\ : SLE
      port map(D => \F_in_r[36]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[36]_net_1\);
    
    \INP_E_ibuf[3]\ : INBUF
      port map(PAD => INP_E(3), Y => \INP_E_c[3]\);
    
    \INP_D_ibuf[1]\ : INBUF
      port map(PAD => INP_D(1), Y => \INP_D_c[1]\);
    
    \INP_88b_ibuf[75]\ : INBUF
      port map(PAD => INP_88b(75), Y => \INP_88b_c[75]\);
    
    \RESULT_obuf[26]\ : OUTBUF
      port map(D => \RES1[26]\, PAD => RESULT(26));
    
    \RESULT_obuf[18]\ : OUTBUF
      port map(D => \RES1[18]\, PAD => RESULT(18));
    
    \INP_A_ibuf[14]\ : INBUF
      port map(PAD => INP_A(14), Y => \INP_A_c[14]\);
    
    \INP_88b_ibuf[25]\ : INBUF
      port map(PAD => INP_88b(25), Y => \INP_88b_c[25]\);
    
    \F_in[27]\ : SLE
      port map(D => \F_in_r[27]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[27]_net_1\);
    
    \F_in[37]\ : SLE
      port map(D => \F_in_r[37]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[37]_net_1\);
    
    \RESULT_obuf[53]\ : OUTBUF
      port map(D => \RES2[9]\, PAD => RESULT(53));
    
    \INP_88b_ibuf[60]\ : INBUF
      port map(PAD => INP_88b(60), Y => \INP_88b_c[60]\);
    
    \E_in_r[14]\ : SLE
      port map(D => \INP_E_c[14]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[14]_net_1\);
    
    \INP_88b_ibuf[8]\ : INBUF
      port map(PAD => INP_88b(8), Y => \INP_88b_c[8]\);
    
    \INP_A_ibuf[13]\ : INBUF
      port map(PAD => INP_A(13), Y => \INP_A_c[13]\);
    
    \E_in[14]\ : SLE
      port map(D => \E_in_r[14]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[14]_net_1\);
    
    \D_in_r[0]\ : SLE
      port map(D => \INP_D_c[0]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[0]_net_1\);
    
    \INP_D_ibuf[5]\ : INBUF
      port map(PAD => INP_D(5), Y => \INP_D_c[5]\);
    
    \RESULT_obuf[14]\ : OUTBUF
      port map(D => \RES1[14]\, PAD => RESULT(14));
    
    \INP_88b_ibuf[9]\ : INBUF
      port map(PAD => INP_88b(9), Y => \INP_88b_c[9]\);
    
    \INP_88b_ibuf[77]\ : INBUF
      port map(PAD => INP_88b(77), Y => \INP_88b_c[77]\);
    
    \D_in[2]\ : SLE
      port map(D => \D_in_r[2]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[2]_net_1\);
    
    \RESULT_obuf[81]\ : OUTBUF
      port map(D => \RES2[37]\, PAD => RESULT(81));
    
    \INP_E_ibuf[10]\ : INBUF
      port map(PAD => INP_E(10), Y => \INP_E_c[10]\);
    
    \RESULT_obuf[9]\ : OUTBUF
      port map(D => \RES1[9]\, PAD => RESULT(9));
    
    \INP_88b_ibuf[27]\ : INBUF
      port map(PAD => INP_88b(27), Y => \INP_88b_c[27]\);
    
    \E_in[17]\ : SLE
      port map(D => \E_in_r[17]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[17]_net_1\);
    
    \D_in[5]\ : SLE
      port map(D => \D_in_r[5]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[5]_net_1\);
    
    \RESULT_obuf[2]\ : OUTBUF
      port map(D => \RES1[2]\, PAD => RESULT(2));
    
    \INP_A_ibuf[16]\ : INBUF
      port map(PAD => INP_A(16), Y => \INP_A_c[16]\);
    
    \INP_88b_ibuf[65]\ : INBUF
      port map(PAD => INP_88b(65), Y => \INP_88b_c[65]\);
    
    \D_in_r[17]\ : SLE
      port map(D => \INP_D_c[17]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[17]_net_1\);
    
    \D_in_r[16]\ : SLE
      port map(D => \INP_D_c[16]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[16]_net_1\);
    
    \F_in_r[15]\ : SLE
      port map(D => \INP_88b_c[59]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[15]_net_1\);
    
    \RESULT_obuf[75]\ : OUTBUF
      port map(D => \RES2[31]\, PAD => RESULT(75));
    
    \E_in[2]\ : SLE
      port map(D => \E_in_r[2]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[2]_net_1\);
    
    \INP_D_ibuf[6]\ : INBUF
      port map(PAD => INP_D(6), Y => \INP_D_c[6]\);
    
    \RESULT_obuf[48]\ : OUTBUF
      port map(D => \RES2[4]\, PAD => RESULT(48));
    
    \INP_88b_ibuf[34]\ : INBUF
      port map(PAD => INP_88b(34), Y => \INP_88b_c[34]\);
    
    \INP_88b_ibuf[0]\ : INBUF
      port map(PAD => INP_88b(0), Y => \INP_88b_c[0]\);
    
    \E_in_r[2]\ : SLE
      port map(D => \INP_E_c[2]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[2]_net_1\);
    
    \RESULT_obuf[86]\ : OUTBUF
      port map(D => \RES2[42]\, PAD => RESULT(86));
    
    \F_in_r[30]\ : SLE
      port map(D => \INP_88b_c[74]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[30]_net_1\);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    \D_in[9]\ : SLE
      port map(D => \D_in_r[9]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[9]_net_1\);
    
    \D_in[3]\ : SLE
      port map(D => \D_in_r[3]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[3]_net_1\);
    
    \INP_D_ibuf[7]\ : INBUF
      port map(PAD => INP_D(7), Y => \INP_D_c[7]\);
    
    \INP_88b_ibuf[59]\ : INBUF
      port map(PAD => INP_88b(59), Y => \INP_88b_c[59]\);
    
    \E_in[5]\ : SLE
      port map(D => \E_in_r[5]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[5]_net_1\);
    
    \RESULT_obuf[5]\ : OUTBUF
      port map(D => \RES1[5]\, PAD => RESULT(5));
    
    \INP_E_ibuf[1]\ : INBUF
      port map(PAD => INP_E(1), Y => \INP_E_c[1]\);
    
    \INP_88b_ibuf[67]\ : INBUF
      port map(PAD => INP_88b(67), Y => \INP_88b_c[67]\);
    
    \INP_88b_ibuf[40]\ : INBUF
      port map(PAD => INP_88b(40), Y => \INP_88b_c[40]\);
    
    \RESULT_obuf[44]\ : OUTBUF
      port map(D => \RES2[0]\, PAD => RESULT(44));
    
    \INP_A_ibuf[9]\ : INBUF
      port map(PAD => INP_A(9), Y => \INP_A_c[9]\);
    
    \RESULT_obuf[55]\ : OUTBUF
      port map(D => \RES2[11]\, PAD => RESULT(55));
    
    \INP_B_ibuf[4]\ : INBUF
      port map(PAD => INP_B(4), Y => \INP_B_c[4]\);
    
    \RESULT_obuf[37]\ : OUTBUF
      port map(D => \RES1[37]\, PAD => RESULT(37));
    
    \F_in_r[2]\ : SLE
      port map(D => \INP_88b_c[46]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[2]_net_1\);
    
    \INP_A_ibuf[3]\ : INBUF
      port map(PAD => INP_A(3), Y => \INP_A_c[3]\);
    
    \RESULT_obuf[6]\ : OUTBUF
      port map(D => \RES1[6]\, PAD => RESULT(6));
    
    \D_in_r[5]\ : SLE
      port map(D => \INP_D_c[5]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[5]_net_1\);
    
    \E_in[9]\ : SLE
      port map(D => \E_in_r[9]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[9]_net_1\);
    
    \E_in[3]\ : SLE
      port map(D => \E_in_r[3]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[3]_net_1\);
    
    \F_in_r[34]\ : SLE
      port map(D => \INP_88b_c[78]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[34]_net_1\);
    
    \INP_E_ibuf[5]\ : INBUF
      port map(PAD => INP_E(5), Y => \INP_E_c[5]\);
    
    \RESULT_obuf[30]\ : OUTBUF
      port map(D => \RES1[30]\, PAD => RESULT(30));
    
    \F_in_r[36]\ : SLE
      port map(D => \INP_88b_c[80]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[36]_net_1\);
    
    \INP_88b_ibuf[45]\ : INBUF
      port map(PAD => INP_88b(45), Y => \INP_88b_c[45]\);
    
    \INP_88b_ibuf[10]\ : INBUF
      port map(PAD => INP_88b(10), Y => \INP_88b_c[10]\);
    
    \F_in[41]\ : SLE
      port map(D => \F_in_r[41]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[41]_net_1\);
    
    RSTN_ibuf_RNICTO9 : CLKINT
      port map(A => \RSTN_ibuf\, Y => RSTN_c);
    
    \F_in_r[27]\ : SLE
      port map(D => \INP_88b_c[71]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[27]_net_1\);
    
    \INP_88b_ibuf[58]\ : INBUF
      port map(PAD => INP_88b(58), Y => \INP_88b_c[58]\);
    
    \E_in_r[7]\ : SLE
      port map(D => \INP_E_c[7]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[7]_net_1\);
    
    \INP_D_ibuf[8]\ : INBUF
      port map(PAD => INP_D(8), Y => \INP_D_c[8]\);
    
    \RESULT_obuf[78]\ : OUTBUF
      port map(D => \RES2[34]\, PAD => RESULT(78));
    
    \INP_E_ibuf[6]\ : INBUF
      port map(PAD => INP_E(6), Y => \INP_E_c[6]\);
    
    \RESULT_obuf[17]\ : OUTBUF
      port map(D => \RES1[17]\, PAD => RESULT(17));
    
    \INP_88b_ibuf[47]\ : INBUF
      port map(PAD => INP_88b(47), Y => \INP_88b_c[47]\);
    
    \F_in[12]\ : SLE
      port map(D => \F_in_r[12]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[12]_net_1\);
    
    \E_in_r[8]\ : SLE
      port map(D => \INP_E_c[8]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[8]_net_1\);
    
    \D_in[10]\ : SLE
      port map(D => \D_in_r[10]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[10]_net_1\);
    
    \F_in[13]\ : SLE
      port map(D => \F_in_r[13]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[13]_net_1\);
    
    \INP_88b_ibuf[15]\ : INBUF
      port map(PAD => INP_88b(15), Y => \INP_88b_c[15]\);
    
    \RESULT_obuf[23]\ : OUTBUF
      port map(D => \RES1[23]\, PAD => RESULT(23));
    
    \INP_E_ibuf[7]\ : INBUF
      port map(PAD => INP_E(7), Y => \INP_E_c[7]\);
    
    \F_in_r[7]\ : SLE
      port map(D => \INP_88b_c[51]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[7]_net_1\);
    
    \RESULT_obuf[74]\ : OUTBUF
      port map(D => \RES2[30]\, PAD => RESULT(74));
    
    \RESULT_obuf[32]\ : OUTBUF
      port map(D => \RES1[32]\, PAD => RESULT(32));
    
    \RESULT_obuf[10]\ : OUTBUF
      port map(D => \RES1[10]\, PAD => RESULT(10));
    
    \RESULT_obuf[58]\ : OUTBUF
      port map(D => \RES2[14]\, PAD => RESULT(58));
    
    \E_in[15]\ : SLE
      port map(D => \E_in_r[15]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[15]_net_1\);
    
    \D_in[7]\ : SLE
      port map(D => \D_in_r[7]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[7]_net_1\);
    
    \F_in_r[33]\ : SLE
      port map(D => \INP_88b_c[77]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[33]_net_1\);
    
    \F_in[25]\ : SLE
      port map(D => \F_in_r[25]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[25]_net_1\);
    
    \F_in_r[8]\ : SLE
      port map(D => \INP_88b_c[52]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[8]_net_1\);
    
    \F_in[35]\ : SLE
      port map(D => \F_in_r[35]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[35]_net_1\);
    
    \D_in[4]\ : SLE
      port map(D => \D_in_r[4]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[4]_net_1\);
    
    \INP_A_ibuf[1]\ : INBUF
      port map(PAD => INP_A(1), Y => \INP_A_c[1]\);
    
    \INP_88b_ibuf[17]\ : INBUF
      port map(PAD => INP_88b(17), Y => \INP_88b_c[17]\);
    
    \D_in[17]\ : SLE
      port map(D => \D_in_r[17]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[17]_net_1\);
    
    \RESULT_obuf[61]\ : OUTBUF
      port map(D => \RES2[17]\, PAD => RESULT(61));
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \RESULT_obuf[54]\ : OUTBUF
      port map(D => \RES2[10]\, PAD => RESULT(54));
    
    \INP_88b_ibuf[56]\ : INBUF
      port map(PAD => INP_88b(56), Y => \INP_88b_c[56]\);
    
    \INP_88b_ibuf[30]\ : INBUF
      port map(PAD => INP_88b(30), Y => \INP_88b_c[30]\);
    
    \F_in[14]\ : SLE
      port map(D => \F_in_r[14]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[14]_net_1\);
    
    \INP_88b_ibuf[79]\ : INBUF
      port map(PAD => INP_88b(79), Y => \INP_88b_c[79]\);
    
    \F_in_r[17]\ : SLE
      port map(D => \INP_88b_c[61]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[17]_net_1\);
    
    \E_in[7]\ : SLE
      port map(D => \E_in_r[7]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[7]_net_1\);
    
    \RESULT_obuf[7]\ : OUTBUF
      port map(D => \RES1[7]\, PAD => RESULT(7));
    
    \RESULT_obuf[47]\ : OUTBUF
      port map(D => \RES2[3]\, PAD => RESULT(47));
    
    \INP_E_ibuf[16]\ : INBUF
      port map(PAD => INP_E(16), Y => \INP_E_c[16]\);
    
    \F_in_r[28]\ : SLE
      port map(D => \INP_88b_c[72]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[28]_net_1\);
    
    \F_in[8]\ : SLE
      port map(D => \F_in_r[8]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[8]_net_1\);
    
    \D_in_r[2]\ : SLE
      port map(D => \INP_D_c[2]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[2]_net_1\);
    
    \INP_A_ibuf[5]\ : INBUF
      port map(PAD => INP_A(5), Y => \INP_A_c[5]\);
    
    \INP_A_ibuf[15]\ : INBUF
      port map(PAD => INP_A(15), Y => \INP_A_c[15]\);
    
    \E_in[4]\ : SLE
      port map(D => \E_in_r[4]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[4]_net_1\);
    
    \RESULT_obuf[69]\ : OUTBUF
      port map(D => \RES2[25]\, PAD => RESULT(69));
    
    \INP_88b_ibuf[86]\ : INBUF
      port map(PAD => INP_88b(86), Y => \INP_88b_c[86]\);
    
    \INP_88b_ibuf[29]\ : INBUF
      port map(PAD => INP_88b(29), Y => \INP_88b_c[29]\);
    
    \F_in_r[39]\ : SLE
      port map(D => \INP_88b_c[83]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[39]_net_1\);
    
    \RESULT_obuf[12]\ : OUTBUF
      port map(D => \RES1[12]\, PAD => RESULT(12));
    
    \INP_E_ibuf[8]\ : INBUF
      port map(PAD => INP_E(8), Y => \INP_E_c[8]\);
    
    \INP_88b_ibuf[52]\ : INBUF
      port map(PAD => INP_88b(52), Y => \INP_88b_c[52]\);
    
    \D_in[12]\ : SLE
      port map(D => \D_in_r[12]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[12]_net_1\);
    
    \RESULT_obuf[40]\ : OUTBUF
      port map(D => \RES1[40]\, PAD => RESULT(40));
    
    \RESULT_obuf[66]\ : OUTBUF
      port map(D => \RES2[22]\, PAD => RESULT(66));
    
    \RESULT_obuf[83]\ : OUTBUF
      port map(D => \RES2[39]\, PAD => RESULT(83));
    
    \INP_88b_ibuf[82]\ : INBUF
      port map(PAD => INP_88b(82), Y => \INP_88b_c[82]\);
    
    \F_in[21]\ : SLE
      port map(D => \F_in_r[21]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[21]_net_1\);
    
    \RESULT_obuf[25]\ : OUTBUF
      port map(D => \RES1[25]\, PAD => RESULT(25));
    
    \F_in[31]\ : SLE
      port map(D => \F_in_r[31]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[31]_net_1\);
    
    \INP_88b_ibuf[35]\ : INBUF
      port map(PAD => INP_88b(35), Y => \INP_88b_c[35]\);
    
    \INP_D_ibuf[0]\ : INBUF
      port map(PAD => INP_D(0), Y => \INP_D_c[0]\);
    
    \INP_A_ibuf[6]\ : INBUF
      port map(PAD => INP_A(6), Y => \INP_A_c[6]\);
    
    \INP_88b_ibuf[3]\ : INBUF
      port map(PAD => INP_88b(3), Y => \INP_88b_c[3]\);
    
    \INP_B_ibuf[9]\ : INBUF
      port map(PAD => INP_B(9), Y => \INP_B_c[9]\);
    
    \INP_A_ibuf[11]\ : INBUF
      port map(PAD => INP_A(11), Y => \INP_A_c[11]\);
    
    \INP_88b_ibuf[78]\ : INBUF
      port map(PAD => INP_88b(78), Y => \INP_88b_c[78]\);
    
    \INP_88b_ibuf[69]\ : INBUF
      port map(PAD => INP_88b(69), Y => \INP_88b_c[69]\);
    
    \INP_B_ibuf[3]\ : INBUF
      port map(PAD => INP_B(3), Y => \INP_B_c[3]\);
    
    \INP_A_ibuf[7]\ : INBUF
      port map(PAD => INP_A(7), Y => \INP_A_c[7]\);
    
    \INP_88b_ibuf[28]\ : INBUF
      port map(PAD => INP_88b(28), Y => \INP_88b_c[28]\);
    
    \F_in_r[40]\ : SLE
      port map(D => \INP_88b_c[84]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[40]_net_1\);
    
    \INP_88b_ibuf[37]\ : INBUF
      port map(PAD => INP_88b(37), Y => \INP_88b_c[37]\);
    
    \E_in_r[17]\ : SLE
      port map(D => \INP_E_c[17]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[17]_net_1\);
    
    \E_in[13]\ : SLE
      port map(D => \E_in_r[13]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[13]_net_1\);
    
    \D_in_r[7]\ : SLE
      port map(D => \INP_D_c[7]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[7]_net_1\);
    
    \RESULT_obuf[42]\ : OUTBUF
      port map(D => \RES1[42]\, PAD => RESULT(42));
    
    \INP_B_ibuf[14]\ : INBUF
      port map(PAD => INP_B(14), Y => \INP_B_c[14]\);
    
    \INP_88b_ibuf[4]\ : INBUF
      port map(PAD => INP_88b(4), Y => \INP_88b_c[4]\);
    
    CLK_ibuf : INBUF
      port map(PAD => CLK, Y => \CLK_ibuf\);
    
    \F_in_r[18]\ : SLE
      port map(D => \INP_88b_c[62]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[18]_net_1\);
    
    \D_in[6]\ : SLE
      port map(D => \D_in_r[6]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[6]_net_1\);
    
    \RESULT_obuf[77]\ : OUTBUF
      port map(D => \RES2[33]\, PAD => RESULT(77));
    
    \D_in_r[14]\ : SLE
      port map(D => \INP_D_c[14]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[14]_net_1\);
    
    \INP_A_ibuf[10]\ : INBUF
      port map(PAD => INP_A(10), Y => \INP_A_c[10]\);
    
    \INP_88b_ibuf[51]\ : INBUF
      port map(PAD => INP_88b(51), Y => \INP_88b_c[51]\);
    
    \D_in_r[8]\ : SLE
      port map(D => \INP_D_c[8]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[8]_net_1\);
    
    \RESULT_obuf[85]\ : OUTBUF
      port map(D => \RES2[41]\, PAD => RESULT(85));
    
    \INP_88b_ibuf[81]\ : INBUF
      port map(PAD => INP_88b(81), Y => \INP_88b_c[81]\);
    
    \RESULT_obuf[70]\ : OUTBUF
      port map(D => \RES2[26]\, PAD => RESULT(70));
    
    \INP_88b_ibuf[68]\ : INBUF
      port map(PAD => INP_88b(68), Y => \INP_88b_c[68]\);
    
    \D_in[15]\ : SLE
      port map(D => \D_in_r[15]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[15]_net_1\);
    
    \F_in_r[20]\ : SLE
      port map(D => \INP_88b_c[64]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[20]_net_1\);
    
    \E_in[6]\ : SLE
      port map(D => \E_in_r[6]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[6]_net_1\);
    
    \RESULT_obuf[57]\ : OUTBUF
      port map(D => \RES2[13]\, PAD => RESULT(57));
    
    \RESULT_obuf[28]\ : OUTBUF
      port map(D => \RES1[28]\, PAD => RESULT(28));
    
    \D_in_r[11]\ : SLE
      port map(D => \INP_D_c[11]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[11]_net_1\);
    
    \INP_A_ibuf[8]\ : INBUF
      port map(PAD => INP_A(8), Y => \INP_A_c[8]\);
    
    \INP_E_ibuf[0]\ : INBUF
      port map(PAD => INP_E(0), Y => \INP_E_c[0]\);
    
    \INP_88b_ibuf[49]\ : INBUF
      port map(PAD => INP_88b(49), Y => \INP_88b_c[49]\);
    
    \INP_88b_ibuf[76]\ : INBUF
      port map(PAD => INP_88b(76), Y => \INP_88b_c[76]\);
    
    \E_in_r[13]\ : SLE
      port map(D => \INP_E_c[13]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[13]_net_1\);
    
    \F_in[10]\ : SLE
      port map(D => \F_in_r[10]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[10]_net_1\);
    
    \INP_D_ibuf[2]\ : INBUF
      port map(PAD => INP_D(2), Y => \INP_D_c[2]\);
    
    \E_in_r[3]\ : SLE
      port map(D => \INP_E_c[3]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[3]_net_1\);
    
    \RESULT_obuf[50]\ : OUTBUF
      port map(D => \RES2[6]\, PAD => RESULT(50));
    
    \E_in_r[4]\ : SLE
      port map(D => \INP_E_c[4]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[4]_net_1\);
    
    \INP_88b_ibuf[26]\ : INBUF
      port map(PAD => INP_88b(26), Y => \INP_88b_c[26]\);
    
    \F_in_r[31]\ : SLE
      port map(D => \INP_88b_c[75]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[31]_net_1\);
    
    \F_in[1]\ : SLE
      port map(D => \F_in_r[1]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[1]_net_1\);
    
    \RESULT_obuf[24]\ : OUTBUF
      port map(D => \RES1[24]\, PAD => RESULT(24));
    
    \RESULT_obuf[1]\ : OUTBUF
      port map(D => \RES1[1]\, PAD => RESULT(1));
    
    \INP_D_ibuf[12]\ : INBUF
      port map(PAD => INP_D(12), Y => \INP_D_c[12]\);
    
    \INP_88b_ibuf[72]\ : INBUF
      port map(PAD => INP_88b(72), Y => \INP_88b_c[72]\);
    
    \INP_B_ibuf[1]\ : INBUF
      port map(PAD => INP_B(1), Y => \INP_B_c[1]\);
    
    \F_in_r[32]\ : SLE
      port map(D => \INP_88b_c[76]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[32]_net_1\);
    
    \INP_88b_ibuf[22]\ : INBUF
      port map(PAD => INP_88b(22), Y => \INP_88b_c[22]\);
    
    \RESULT_obuf[72]\ : OUTBUF
      port map(D => \RES2[28]\, PAD => RESULT(72));
    
    \INP_88b_ibuf[53]\ : INBUF
      port map(PAD => INP_88b(53), Y => \INP_88b_c[53]\);
    
    \F_in_r[24]\ : SLE
      port map(D => \INP_88b_c[68]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[24]_net_1\);
    
    \E_in_r[12]\ : SLE
      port map(D => \INP_E_c[12]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[12]_net_1\);
    
    \INP_E_ibuf[17]\ : INBUF
      port map(PAD => INP_E(17), Y => \INP_E_c[17]\);
    
    \F_in_r[26]\ : SLE
      port map(D => \INP_88b_c[70]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[26]_net_1\);
    
    \INP_E_ibuf[13]\ : INBUF
      port map(PAD => INP_E(13), Y => \INP_E_c[13]\);
    
    \F_in_r[3]\ : SLE
      port map(D => \INP_88b_c[47]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[3]_net_1\);
    
    \F_in[18]\ : SLE
      port map(D => \F_in_r[18]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[18]_net_1\);
    
    \INP_88b_ibuf[19]\ : INBUF
      port map(PAD => INP_88b(19), Y => \INP_88b_c[19]\);
    
    \F_in_r[4]\ : SLE
      port map(D => \INP_88b_c[48]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[4]_net_1\);
    
    \F_in[19]\ : SLE
      port map(D => \F_in_r[19]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[19]_net_1\);
    
    \INP_D_ibuf[13]\ : INBUF
      port map(PAD => INP_D(13), Y => \INP_D_c[13]\);
    
    \INP_88b_ibuf[83]\ : INBUF
      port map(PAD => INP_88b(83), Y => \INP_88b_c[83]\);
    
    \INP_B_ibuf[5]\ : INBUF
      port map(PAD => INP_B(5), Y => \INP_B_c[5]\);
    
    \F_in_r[43]\ : SLE
      port map(D => \INP_88b_c[87]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[43]_net_1\);
    
    \INP_88b_ibuf[48]\ : INBUF
      port map(PAD => INP_88b(48), Y => \INP_88b_c[48]\);
    
    \F_in[42]\ : SLE
      port map(D => \F_in_r[42]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[42]_net_1\);
    
    \INP_88b_ibuf[66]\ : INBUF
      port map(PAD => INP_88b(66), Y => \INP_88b_c[66]\);
    
    \F_in[43]\ : SLE
      port map(D => \F_in_r[43]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[43]_net_1\);
    
    \E_in[11]\ : SLE
      port map(D => \E_in_r[11]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[11]_net_1\);
    
    \RESULT_obuf[31]\ : OUTBUF
      port map(D => \RES1[31]\, PAD => RESULT(31));
    
    \INP_88b_ibuf[1]\ : INBUF
      port map(PAD => INP_88b(1), Y => \INP_88b_c[1]\);
    
    \RESULT_obuf[52]\ : OUTBUF
      port map(D => \RES2[8]\, PAD => RESULT(52));
    
    \RESULT_obuf[63]\ : OUTBUF
      port map(D => \RES2[19]\, PAD => RESULT(63));
    
    \F_in_r[10]\ : SLE
      port map(D => \INP_88b_c[54]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[10]_net_1\);
    
    \F_in[0]\ : SLE
      port map(D => \F_in_r[0]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[0]_net_1\);
    
    \INP_E_ibuf[12]\ : INBUF
      port map(PAD => INP_E(12), Y => \INP_E_c[12]\);
    
    \INP_88b_ibuf[62]\ : INBUF
      port map(PAD => INP_88b(62), Y => \INP_88b_c[62]\);
    
    \RESULT_obuf[8]\ : OUTBUF
      port map(D => \RES1[8]\, PAD => RESULT(8));
    
    \RESULT_obuf[39]\ : OUTBUF
      port map(D => \RES1[39]\, PAD => RESULT(39));
    
    \RESULT_obuf[84]\ : OUTBUF
      port map(D => \RES2[40]\, PAD => RESULT(84));
    
    \INP_B_ibuf[6]\ : INBUF
      port map(PAD => INP_B(6), Y => \INP_B_c[6]\);
    
    \D_in[14]\ : SLE
      port map(D => \D_in_r[14]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[14]_net_1\);
    
    \INP_A_ibuf[17]\ : INBUF
      port map(PAD => INP_A(17), Y => \INP_A_c[17]\);
    
    \INP_88b_ibuf[71]\ : INBUF
      port map(PAD => INP_88b(71), Y => \INP_88b_c[71]\);
    
    \E_in_r[11]\ : SLE
      port map(D => \INP_E_c[11]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[11]_net_1\);
    
    \INP_E_ibuf[2]\ : INBUF
      port map(PAD => INP_E(2), Y => \INP_E_c[2]\);
    
    \INP_88b_ibuf[18]\ : INBUF
      port map(PAD => INP_88b(18), Y => \INP_88b_c[18]\);
    
    \RESULT_obuf[36]\ : OUTBUF
      port map(D => \RES1[36]\, PAD => RESULT(36));
    
    \INP_A_ibuf[0]\ : INBUF
      port map(PAD => INP_A(0), Y => \INP_A_c[0]\);
    
    \INP_88b_ibuf[21]\ : INBUF
      port map(PAD => INP_88b(21), Y => \INP_88b_c[21]\);
    
    \F_in_r[23]\ : SLE
      port map(D => \INP_88b_c[67]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[23]_net_1\);
    
    \INP_B_ibuf[7]\ : INBUF
      port map(PAD => INP_B(7), Y => \INP_B_c[7]\);
    
    \INP_D_ibuf[10]\ : INBUF
      port map(PAD => INP_D(10), Y => \INP_D_c[10]\);
    
    \F_in_r[14]\ : SLE
      port map(D => \INP_88b_c[58]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[14]_net_1\);
    
    \F_in_r[16]\ : SLE
      port map(D => \INP_88b_c[60]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[16]_net_1\);
    
    \F_in[16]\ : SLE
      port map(D => \F_in_r[16]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[16]_net_1\);
    
    \RESULT_obuf[11]\ : OUTBUF
      port map(D => \RES1[11]\, PAD => RESULT(11));
    
    \INP_88b_ibuf[39]\ : INBUF
      port map(PAD => INP_88b(39), Y => \INP_88b_c[39]\);
    
    \INP_D_ibuf[16]\ : INBUF
      port map(PAD => INP_D(16), Y => \INP_D_c[16]\);
    
    \INP_88b_ibuf[46]\ : INBUF
      port map(PAD => INP_88b(46), Y => \INP_88b_c[46]\);
    
    \INP_B_ibuf[15]\ : INBUF
      port map(PAD => INP_B(15), Y => \INP_B_c[15]\);
    
    \RESULT_obuf[19]\ : OUTBUF
      port map(D => \RES1[19]\, PAD => RESULT(19));
    
    \D_in_r[15]\ : SLE
      port map(D => \INP_D_c[15]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[15]_net_1\);
    
    \RESULT_obuf[65]\ : OUTBUF
      port map(D => \RES2[21]\, PAD => RESULT(65));
    
    \INP_D_ibuf[11]\ : INBUF
      port map(PAD => INP_D(11), Y => \INP_D_c[11]\);
    
    \RESULT_obuf[27]\ : OUTBUF
      port map(D => \RES1[27]\, PAD => RESULT(27));
    
    \F_in[17]\ : SLE
      port map(D => \F_in_r[17]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[17]_net_1\);
    
    \RESULT_obuf[3]\ : OUTBUF
      port map(D => \RES1[3]\, PAD => RESULT(3));
    
    \INP_88b_ibuf[42]\ : INBUF
      port map(PAD => INP_88b(42), Y => \INP_88b_c[42]\);
    
    \F_in_r[29]\ : SLE
      port map(D => \INP_88b_c[73]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[29]_net_1\);
    
    \D_in_r[12]\ : SLE
      port map(D => \INP_D_c[12]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[12]_net_1\);
    
    \INP_88b_ibuf[61]\ : INBUF
      port map(PAD => INP_88b(61), Y => \INP_88b_c[61]\);
    
    \RESULT_obuf[16]\ : OUTBUF
      port map(D => \RES1[16]\, PAD => RESULT(16));
    
    \D_in_r[3]\ : SLE
      port map(D => \INP_D_c[3]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[3]_net_1\);
    
    \D_in_r[4]\ : SLE
      port map(D => \INP_D_c[4]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[4]_net_1\);
    
    \RESULT_obuf[20]\ : OUTBUF
      port map(D => \RES1[20]\, PAD => RESULT(20));
    
    \INP_B_ibuf[17]\ : INBUF
      port map(PAD => INP_B(17), Y => \INP_B_c[17]\);
    
    \E_in_r[1]\ : SLE
      port map(D => \INP_E_c[1]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[1]_net_1\);
    
    \INP_88b_ibuf[73]\ : INBUF
      port map(PAD => INP_88b(73), Y => \INP_88b_c[73]\);
    
    \INP_B_ibuf[8]\ : INBUF
      port map(PAD => INP_B(8), Y => \INP_B_c[8]\);
    
    \F_in[22]\ : SLE
      port map(D => \F_in_r[22]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[22]_net_1\);
    
    \INP_88b_ibuf[54]\ : INBUF
      port map(PAD => INP_88b(54), Y => \INP_88b_c[54]\);
    
    \INP_88b_ibuf[16]\ : INBUF
      port map(PAD => INP_88b(16), Y => \INP_88b_c[16]\);
    
    \F_in[32]\ : SLE
      port map(D => \F_in_r[32]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[32]_net_1\);
    
    \F_in[23]\ : SLE
      port map(D => \F_in_r[23]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[23]_net_1\);
    
    \INP_88b_ibuf[23]\ : INBUF
      port map(PAD => INP_88b(23), Y => \INP_88b_c[23]\);
    
    \F_in[33]\ : SLE
      port map(D => \F_in_r[33]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[33]_net_1\);
    
    \E_in_r[6]\ : SLE
      port map(D => \INP_E_c[6]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[6]_net_1\);
    
    \INP_88b_ibuf[38]\ : INBUF
      port map(PAD => INP_88b(38), Y => \INP_88b_c[38]\);
    
    \RESULT_obuf[41]\ : OUTBUF
      port map(D => \RES1[41]\, PAD => RESULT(41));
    
    \INP_88b_ibuf[84]\ : INBUF
      port map(PAD => INP_88b(84), Y => \INP_88b_c[84]\);
    
    \E_in_r[16]\ : SLE
      port map(D => \INP_E_c[16]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[16]_net_1\);
    
    \F_in[2]\ : SLE
      port map(D => \F_in_r[2]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[2]_net_1\);
    
    \F_in_r[13]\ : SLE
      port map(D => \INP_88b_c[57]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[13]_net_1\);
    
    \INP_88b_ibuf[12]\ : INBUF
      port map(PAD => INP_88b(12), Y => \INP_88b_c[12]\);
    
    \F_in_r[1]\ : SLE
      port map(D => \INP_88b_c[45]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[1]_net_1\);
    
    \E_in[10]\ : SLE
      port map(D => \E_in_r[10]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[10]_net_1\);
    
    \INP_D_ibuf[14]\ : INBUF
      port map(PAD => INP_D(14), Y => \INP_D_c[14]\);
    
    \RESULT_obuf[49]\ : OUTBUF
      port map(D => \RES2[5]\, PAD => RESULT(49));
    
    \INP_A_ibuf[2]\ : INBUF
      port map(PAD => INP_A(2), Y => \INP_A_c[2]\);
    
    \F_in_r[35]\ : SLE
      port map(D => \INP_88b_c[79]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[35]_net_1\);
    
    \F_in[5]\ : SLE
      port map(D => \F_in_r[5]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[5]_net_1\);
    
    \RESULT_obuf[0]\ : OUTBUF
      port map(D => \RES1[0]\, PAD => RESULT(0));
    
    \F_in_r[6]\ : SLE
      port map(D => \INP_88b_c[50]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[6]_net_1\);
    
    \INP_A_ibuf[12]\ : INBUF
      port map(PAD => INP_A(12), Y => \INP_A_c[12]\);
    
    \INP_88b_ibuf[6]\ : INBUF
      port map(PAD => INP_88b(6), Y => \INP_88b_c[6]\);
    
    \D_in[8]\ : SLE
      port map(D => \D_in_r[8]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[8]_net_1\);
    
    \INP_D_ibuf[4]\ : INBUF
      port map(PAD => INP_D(4), Y => \INP_D_c[4]\);
    
    \RESULT_obuf[87]\ : OUTBUF
      port map(D => \RES2[43]\, PAD => RESULT(87));
    
    \RESULT_obuf[46]\ : OUTBUF
      port map(D => \RES2[2]\, PAD => RESULT(46));
    
    \RESULT_obuf[22]\ : OUTBUF
      port map(D => \RES1[22]\, PAD => RESULT(22));
    
    \F_in_r[41]\ : SLE
      port map(D => \INP_88b_c[85]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[41]_net_1\);
    
    \F_in[24]\ : SLE
      port map(D => \F_in_r[24]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[24]_net_1\);
    
    \INP_88b_ibuf[63]\ : INBUF
      port map(PAD => INP_88b(63), Y => \INP_88b_c[63]\);
    
    \INP_88b_ibuf[41]\ : INBUF
      port map(PAD => INP_88b(41), Y => \INP_88b_c[41]\);
    
    \F_in[34]\ : SLE
      port map(D => \F_in_r[34]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[34]_net_1\);
    
    \F_in_r[19]\ : SLE
      port map(D => \INP_88b_c[63]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[19]_net_1\);
    
    \RESULT_obuf[68]\ : OUTBUF
      port map(D => \RES2[24]\, PAD => RESULT(68));
    
    \F_in[9]\ : SLE
      port map(D => \F_in_r[9]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[9]_net_1\);
    
    \RESULT_obuf[80]\ : OUTBUF
      port map(D => \RES2[36]\, PAD => RESULT(80));
    
    \F_in_r[42]\ : SLE
      port map(D => \INP_88b_c[86]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[42]_net_1\);
    
    \F_in[3]\ : SLE
      port map(D => \F_in_r[3]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[3]_net_1\);
    
    \INP_B_ibuf[12]\ : INBUF
      port map(PAD => INP_B(12), Y => \INP_B_c[12]\);
    
    \INP_88b_ibuf[2]\ : INBUF
      port map(PAD => INP_88b(2), Y => \INP_88b_c[2]\);
    
    \E_in[8]\ : SLE
      port map(D => \E_in_r[8]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[8]_net_1\);
    
    \F_in[40]\ : SLE
      port map(D => \F_in_r[40]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[40]_net_1\);
    
    U0 : MultAdder
      port map(RES1(43) => \RES1[43]\, RES1(42) => \RES1[42]\, 
        RES1(41) => \RES1[41]\, RES1(40) => \RES1[40]\, RES1(39)
         => \RES1[39]\, RES1(38) => \RES1[38]\, RES1(37) => 
        \RES1[37]\, RES1(36) => \RES1[36]\, RES1(35) => 
        \RES1[35]\, RES1(34) => \RES1[34]\, RES1(33) => 
        \RES1[33]\, RES1(32) => \RES1[32]\, RES1(31) => 
        \RES1[31]\, RES1(30) => \RES1[30]\, RES1(29) => 
        \RES1[29]\, RES1(28) => \RES1[28]\, RES1(27) => 
        \RES1[27]\, RES1(26) => \RES1[26]\, RES1(25) => 
        \RES1[25]\, RES1(24) => \RES1[24]\, RES1(23) => 
        \RES1[23]\, RES1(22) => \RES1[22]\, RES1(21) => 
        \RES1[21]\, RES1(20) => \RES1[20]\, RES1(19) => 
        \RES1[19]\, RES1(18) => \RES1[18]\, RES1(17) => 
        \RES1[17]\, RES1(16) => \RES1[16]\, RES1(15) => 
        \RES1[15]\, RES1(14) => \RES1[14]\, RES1(13) => 
        \RES1[13]\, RES1(12) => \RES1[12]\, RES1(11) => 
        \RES1[11]\, RES1(10) => \RES1[10]\, RES1(9) => \RES1[9]\, 
        RES1(8) => \RES1[8]\, RES1(7) => \RES1[7]\, RES1(6) => 
        \RES1[6]\, RES1(5) => \RES1[5]\, RES1(4) => \RES1[4]\, 
        RES1(3) => \RES1[3]\, RES1(2) => \RES1[2]\, RES1(1) => 
        \RES1[1]\, RES1(0) => \RES1[0]\, INP_A_c(17) => 
        \INP_A_c[17]\, INP_A_c(16) => \INP_A_c[16]\, INP_A_c(15)
         => \INP_A_c[15]\, INP_A_c(14) => \INP_A_c[14]\, 
        INP_A_c(13) => \INP_A_c[13]\, INP_A_c(12) => 
        \INP_A_c[12]\, INP_A_c(11) => \INP_A_c[11]\, INP_A_c(10)
         => \INP_A_c[10]\, INP_A_c(9) => \INP_A_c[9]\, INP_A_c(8)
         => \INP_A_c[8]\, INP_A_c(7) => \INP_A_c[7]\, INP_A_c(6)
         => \INP_A_c[6]\, INP_A_c(5) => \INP_A_c[5]\, INP_A_c(4)
         => \INP_A_c[4]\, INP_A_c(3) => \INP_A_c[3]\, INP_A_c(2)
         => \INP_A_c[2]\, INP_A_c(1) => \INP_A_c[1]\, INP_A_c(0)
         => \INP_A_c[0]\, INP_B_c(17) => \INP_B_c[17]\, 
        INP_B_c(16) => \INP_B_c[16]\, INP_B_c(15) => 
        \INP_B_c[15]\, INP_B_c(14) => \INP_B_c[14]\, INP_B_c(13)
         => \INP_B_c[13]\, INP_B_c(12) => \INP_B_c[12]\, 
        INP_B_c(11) => \INP_B_c[11]\, INP_B_c(10) => 
        \INP_B_c[10]\, INP_B_c(9) => \INP_B_c[9]\, INP_B_c(8) => 
        \INP_B_c[8]\, INP_B_c(7) => \INP_B_c[7]\, INP_B_c(6) => 
        \INP_B_c[6]\, INP_B_c(5) => \INP_B_c[5]\, INP_B_c(4) => 
        \INP_B_c[4]\, INP_B_c(3) => \INP_B_c[3]\, INP_B_c(2) => 
        \INP_B_c[2]\, INP_B_c(1) => \INP_B_c[1]\, INP_B_c(0) => 
        \INP_B_c[0]\, INP_88b_c(43) => \INP_88b_c[43]\, 
        INP_88b_c(42) => \INP_88b_c[42]\, INP_88b_c(41) => 
        \INP_88b_c[41]\, INP_88b_c(40) => \INP_88b_c[40]\, 
        INP_88b_c(39) => \INP_88b_c[39]\, INP_88b_c(38) => 
        \INP_88b_c[38]\, INP_88b_c(37) => \INP_88b_c[37]\, 
        INP_88b_c(36) => \INP_88b_c[36]\, INP_88b_c(35) => 
        \INP_88b_c[35]\, INP_88b_c(34) => \INP_88b_c[34]\, 
        INP_88b_c(33) => \INP_88b_c[33]\, INP_88b_c(32) => 
        \INP_88b_c[32]\, INP_88b_c(31) => \INP_88b_c[31]\, 
        INP_88b_c(30) => \INP_88b_c[30]\, INP_88b_c(29) => 
        \INP_88b_c[29]\, INP_88b_c(28) => \INP_88b_c[28]\, 
        INP_88b_c(27) => \INP_88b_c[27]\, INP_88b_c(26) => 
        \INP_88b_c[26]\, INP_88b_c(25) => \INP_88b_c[25]\, 
        INP_88b_c(24) => \INP_88b_c[24]\, INP_88b_c(23) => 
        \INP_88b_c[23]\, INP_88b_c(22) => \INP_88b_c[22]\, 
        INP_88b_c(21) => \INP_88b_c[21]\, INP_88b_c(20) => 
        \INP_88b_c[20]\, INP_88b_c(19) => \INP_88b_c[19]\, 
        INP_88b_c(18) => \INP_88b_c[18]\, INP_88b_c(17) => 
        \INP_88b_c[17]\, INP_88b_c(16) => \INP_88b_c[16]\, 
        INP_88b_c(15) => \INP_88b_c[15]\, INP_88b_c(14) => 
        \INP_88b_c[14]\, INP_88b_c(13) => \INP_88b_c[13]\, 
        INP_88b_c(12) => \INP_88b_c[12]\, INP_88b_c(11) => 
        \INP_88b_c[11]\, INP_88b_c(10) => \INP_88b_c[10]\, 
        INP_88b_c(9) => \INP_88b_c[9]\, INP_88b_c(8) => 
        \INP_88b_c[8]\, INP_88b_c(7) => \INP_88b_c[7]\, 
        INP_88b_c(6) => \INP_88b_c[6]\, INP_88b_c(5) => 
        \INP_88b_c[5]\, INP_88b_c(4) => \INP_88b_c[4]\, 
        INP_88b_c(3) => \INP_88b_c[3]\, INP_88b_c(2) => 
        \INP_88b_c[2]\, INP_88b_c(1) => \INP_88b_c[1]\, 
        INP_88b_c(0) => \INP_88b_c[0]\, CARRYIN => CARRYIN, 
        RSTN_c => RSTN_c, CLK_c => CLK_c);
    
    \E_in_r[9]\ : SLE
      port map(D => \INP_E_c[9]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[9]_net_1\);
    
    \INP_88b_ibuf[36]\ : INBUF
      port map(PAD => INP_88b(36), Y => \INP_88b_c[36]\);
    
    \RESULT_obuf[64]\ : OUTBUF
      port map(D => \RES2[20]\, PAD => RESULT(64));
    
    \INP_B_ibuf[11]\ : INBUF
      port map(PAD => INP_B(11), Y => \INP_B_c[11]\);
    
    \INP_B_ibuf[16]\ : INBUF
      port map(PAD => INP_B(16), Y => \INP_B_c[16]\);
    
    \RESULT_obuf[71]\ : OUTBUF
      port map(D => \RES2[27]\, PAD => RESULT(71));
    
    \INP_B_ibuf[10]\ : INBUF
      port map(PAD => INP_B(10), Y => \INP_B_c[10]\);
    
    \INP_88b_ibuf[11]\ : INBUF
      port map(PAD => INP_88b(11), Y => \INP_88b_c[11]\);
    
    \INP_E_ibuf[14]\ : INBUF
      port map(PAD => INP_E(14), Y => \INP_E_c[14]\);
    
    \RESULT_obuf[33]\ : OUTBUF
      port map(D => \RES1[33]\, PAD => RESULT(33));
    
    \INP_88b_ibuf[32]\ : INBUF
      port map(PAD => INP_88b(32), Y => \INP_88b_c[32]\);
    
    \F_in_r[21]\ : SLE
      port map(D => \INP_88b_c[65]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[21]_net_1\);
    
    \INP_B_ibuf[0]\ : INBUF
      port map(PAD => INP_B(0), Y => \INP_B_c[0]\);
    
    \F_in_r[9]\ : SLE
      port map(D => \INP_88b_c[53]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[9]_net_1\);
    
    \INP_E_ibuf[11]\ : INBUF
      port map(PAD => INP_E(11), Y => \INP_E_c[11]\);
    
    \D_in_r[10]\ : SLE
      port map(D => \INP_D_c[10]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[10]_net_1\);
    
    \RESULT_obuf[79]\ : OUTBUF
      port map(D => \RES2[35]\, PAD => RESULT(79));
    
    \INP_D_ibuf[17]\ : INBUF
      port map(PAD => INP_D(17), Y => \INP_D_c[17]\);
    
    \F_in_r[22]\ : SLE
      port map(D => \INP_88b_c[66]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[22]_net_1\);
    
    \RESULT_obuf[82]\ : OUTBUF
      port map(D => \RES2[38]\, PAD => RESULT(82));
    
    \INP_88b_ibuf[43]\ : INBUF
      port map(PAD => INP_88b(43), Y => \INP_88b_c[43]\);
    
    U1 : MultAdder_w_Din
      port map(RES2(43) => \RES2[43]\, RES2(42) => \RES2[42]\, 
        RES2(41) => \RES2[41]\, RES2(40) => \RES2[40]\, RES2(39)
         => \RES2[39]\, RES2(38) => \RES2[38]\, RES2(37) => 
        \RES2[37]\, RES2(36) => \RES2[36]\, RES2(35) => 
        \RES2[35]\, RES2(34) => \RES2[34]\, RES2(33) => 
        \RES2[33]\, RES2(32) => \RES2[32]\, RES2(31) => 
        \RES2[31]\, RES2(30) => \RES2[30]\, RES2(29) => 
        \RES2[29]\, RES2(28) => \RES2[28]\, RES2(27) => 
        \RES2[27]\, RES2(26) => \RES2[26]\, RES2(25) => 
        \RES2[25]\, RES2(24) => \RES2[24]\, RES2(23) => 
        \RES2[23]\, RES2(22) => \RES2[22]\, RES2(21) => 
        \RES2[21]\, RES2(20) => \RES2[20]\, RES2(19) => 
        \RES2[19]\, RES2(18) => \RES2[18]\, RES2(17) => 
        \RES2[17]\, RES2(16) => \RES2[16]\, RES2(15) => 
        \RES2[15]\, RES2(14) => \RES2[14]\, RES2(13) => 
        \RES2[13]\, RES2(12) => \RES2[12]\, RES2(11) => 
        \RES2[11]\, RES2(10) => \RES2[10]\, RES2(9) => \RES2[9]\, 
        RES2(8) => \RES2[8]\, RES2(7) => \RES2[7]\, RES2(6) => 
        \RES2[6]\, RES2(5) => \RES2[5]\, RES2(4) => \RES2[4]\, 
        RES2(3) => \RES2[3]\, RES2(2) => \RES2[2]\, RES2(1) => 
        \RES2[1]\, RES2(0) => \RES2[0]\, D_in(17) => 
        \D_in[17]_net_1\, D_in(16) => \D_in[16]_net_1\, D_in(15)
         => \D_in[15]_net_1\, D_in(14) => \D_in[14]_net_1\, 
        D_in(13) => \D_in[13]_net_1\, D_in(12) => 
        \D_in[12]_net_1\, D_in(11) => \D_in[11]_net_1\, D_in(10)
         => \D_in[10]_net_1\, D_in(9) => \D_in[9]_net_1\, D_in(8)
         => \D_in[8]_net_1\, D_in(7) => \D_in[7]_net_1\, D_in(6)
         => \D_in[6]_net_1\, D_in(5) => \D_in[5]_net_1\, D_in(4)
         => \D_in[4]_net_1\, D_in(3) => \D_in[3]_net_1\, D_in(2)
         => \D_in[2]_net_1\, D_in(1) => \D_in[1]_net_1\, D_in(0)
         => \D_in[0]_net_1\, E_in(17) => \E_in[17]_net_1\, 
        E_in(16) => \E_in[16]_net_1\, E_in(15) => 
        \E_in[15]_net_1\, E_in(14) => \E_in[14]_net_1\, E_in(13)
         => \E_in[13]_net_1\, E_in(12) => \E_in[12]_net_1\, 
        E_in(11) => \E_in[11]_net_1\, E_in(10) => 
        \E_in[10]_net_1\, E_in(9) => \E_in[9]_net_1\, E_in(8) => 
        \E_in[8]_net_1\, E_in(7) => \E_in[7]_net_1\, E_in(6) => 
        \E_in[6]_net_1\, E_in(5) => \E_in[5]_net_1\, E_in(4) => 
        \E_in[4]_net_1\, E_in(3) => \E_in[3]_net_1\, E_in(2) => 
        \E_in[2]_net_1\, E_in(1) => \E_in[1]_net_1\, E_in(0) => 
        \E_in[0]_net_1\, F_in(43) => \F_in[43]_net_1\, F_in(42)
         => \F_in[42]_net_1\, F_in(41) => \F_in[41]_net_1\, 
        F_in(40) => \F_in[40]_net_1\, F_in(39) => 
        \F_in[39]_net_1\, F_in(38) => \F_in[38]_net_1\, F_in(37)
         => \F_in[37]_net_1\, F_in(36) => \F_in[36]_net_1\, 
        F_in(35) => \F_in[35]_net_1\, F_in(34) => 
        \F_in[34]_net_1\, F_in(33) => \F_in[33]_net_1\, F_in(32)
         => \F_in[32]_net_1\, F_in(31) => \F_in[31]_net_1\, 
        F_in(30) => \F_in[30]_net_1\, F_in(29) => 
        \F_in[29]_net_1\, F_in(28) => \F_in[28]_net_1\, F_in(27)
         => \F_in[27]_net_1\, F_in(26) => \F_in[26]_net_1\, 
        F_in(25) => \F_in[25]_net_1\, F_in(24) => 
        \F_in[24]_net_1\, F_in(23) => \F_in[23]_net_1\, F_in(22)
         => \F_in[22]_net_1\, F_in(21) => \F_in[21]_net_1\, 
        F_in(20) => \F_in[20]_net_1\, F_in(19) => 
        \F_in[19]_net_1\, F_in(18) => \F_in[18]_net_1\, F_in(17)
         => \F_in[17]_net_1\, F_in(16) => \F_in[16]_net_1\, 
        F_in(15) => \F_in[15]_net_1\, F_in(14) => 
        \F_in[14]_net_1\, F_in(13) => \F_in[13]_net_1\, F_in(12)
         => \F_in[12]_net_1\, F_in(11) => \F_in[11]_net_1\, 
        F_in(10) => \F_in[10]_net_1\, F_in(9) => \F_in[9]_net_1\, 
        F_in(8) => \F_in[8]_net_1\, F_in(7) => \F_in[7]_net_1\, 
        F_in(6) => \F_in[6]_net_1\, F_in(5) => \F_in[5]_net_1\, 
        F_in(4) => \F_in[4]_net_1\, F_in(3) => \F_in[3]_net_1\, 
        F_in(2) => \F_in[2]_net_1\, F_in(1) => \F_in[1]_net_1\, 
        F_in(0) => \F_in[0]_net_1\, RSTN_c => RSTN_c, CLK_c => 
        CLK_c, CARRYIN => CARRYIN);
    
    \RESULT_obuf[51]\ : OUTBUF
      port map(D => \RES2[7]\, PAD => RESULT(51));
    
    \RESULT_obuf[76]\ : OUTBUF
      port map(D => \RES2[32]\, PAD => RESULT(76));
    
    \INP_E_ibuf[4]\ : INBUF
      port map(PAD => INP_E(4), Y => \INP_E_c[4]\);
    
    \INP_88b_ibuf[74]\ : INBUF
      port map(PAD => INP_88b(74), Y => \INP_88b_c[74]\);
    
    \INP_88b_ibuf[24]\ : INBUF
      port map(PAD => INP_88b(24), Y => \INP_88b_c[24]\);
    
    \INP_88b_ibuf[50]\ : INBUF
      port map(PAD => INP_88b(50), Y => \INP_88b_c[50]\);
    
    \D_in_r[1]\ : SLE
      port map(D => \INP_D_c[1]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[1]_net_1\);
    
    CLK_ibuf_RNIVQ04 : CLKINT
      port map(A => \CLK_ibuf\, Y => CLK_c);
    
    \RESULT_obuf[59]\ : OUTBUF
      port map(D => \RES2[15]\, PAD => RESULT(59));
    
    \F_in[15]\ : SLE
      port map(D => \F_in_r[15]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[15]_net_1\);
    
    \RESULT_obuf[4]\ : OUTBUF
      port map(D => \RES1[4]\, PAD => RESULT(4));
    
    \RESULT_obuf[13]\ : OUTBUF
      port map(D => \RES1[13]\, PAD => RESULT(13));
    
    \INP_88b_ibuf[80]\ : INBUF
      port map(PAD => INP_88b(80), Y => \INP_88b_c[80]\);
    
    \INP_88b_ibuf[5]\ : INBUF
      port map(PAD => INP_88b(5), Y => \INP_88b_c[5]\);
    
    \E_in[16]\ : SLE
      port map(D => \E_in_r[16]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[16]_net_1\);
    
    \D_in_r[6]\ : SLE
      port map(D => \INP_D_c[6]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \D_in_r[6]_net_1\);
    
    \RESULT_obuf[56]\ : OUTBUF
      port map(D => \RES2[12]\, PAD => RESULT(56));
    
    \D_in[11]\ : SLE
      port map(D => \D_in_r[11]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[11]_net_1\);
    
    \INP_88b_ibuf[13]\ : INBUF
      port map(PAD => INP_88b(13), Y => \INP_88b_c[13]\);
    
    \F_in[7]\ : SLE
      port map(D => \F_in_r[7]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[7]_net_1\);
    
    \D_in[13]\ : SLE
      port map(D => \D_in_r[13]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[13]_net_1\);
    
    \INP_88b_ibuf[7]\ : INBUF
      port map(PAD => INP_88b(7), Y => \INP_88b_c[7]\);
    
    \F_in[4]\ : SLE
      port map(D => \F_in_r[4]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[4]_net_1\);
    
    \RESULT_obuf[35]\ : OUTBUF
      port map(D => \RES1[35]\, PAD => RESULT(35));
    
    \INP_88b_ibuf[31]\ : INBUF
      port map(PAD => INP_88b(31), Y => \INP_88b_c[31]\);
    
    \D_in[1]\ : SLE
      port map(D => \D_in_r[1]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \D_in[1]_net_1\);
    
    \INP_88b_ibuf[55]\ : INBUF
      port map(PAD => INP_88b(55), Y => \INP_88b_c[55]\);
    
    \F_in_r[11]\ : SLE
      port map(D => \INP_88b_c[55]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[11]_net_1\);
    
    \E_in[12]\ : SLE
      port map(D => \E_in_r[12]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[12]_net_1\);
    
    \F_in_r[37]\ : SLE
      port map(D => \INP_88b_c[81]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[37]_net_1\);
    
    \F_in[20]\ : SLE
      port map(D => \F_in_r[20]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[20]_net_1\);
    
    \INP_88b_ibuf[64]\ : INBUF
      port map(PAD => INP_88b(64), Y => \INP_88b_c[64]\);
    
    \E_in_r[0]\ : SLE
      port map(D => \INP_E_c[0]\, CLK => CLK_c, EN => VCC_net_1, 
        ALn => RSTN_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \E_in_r[0]_net_1\);
    
    \F_in[30]\ : SLE
      port map(D => \F_in_r[30]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[30]_net_1\);
    
    \INP_88b_ibuf[85]\ : INBUF
      port map(PAD => INP_88b(85), Y => \INP_88b_c[85]\);
    
    \F_in_r[12]\ : SLE
      port map(D => \INP_88b_c[56]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[12]_net_1\);
    
    \INP_E_ibuf[15]\ : INBUF
      port map(PAD => INP_E(15), Y => \INP_E_c[15]\);
    
    \INP_B_ibuf[2]\ : INBUF
      port map(PAD => INP_B(2), Y => \INP_B_c[2]\);
    
    \F_in[11]\ : SLE
      port map(D => \F_in_r[11]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[11]_net_1\);
    
    \E_in[1]\ : SLE
      port map(D => \E_in_r[1]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \E_in[1]_net_1\);
    
    RSTN_ibuf : INBUF
      port map(PAD => RSTN, Y => \RSTN_ibuf\);
    
    \INP_D_ibuf[9]\ : INBUF
      port map(PAD => INP_D(9), Y => \INP_D_c[9]\);
    
    \RESULT_obuf[67]\ : OUTBUF
      port map(D => \RES2[23]\, PAD => RESULT(67));
    
    \INP_88b_ibuf[57]\ : INBUF
      port map(PAD => INP_88b(57), Y => \INP_88b_c[57]\);
    
    \RESULT_obuf[43]\ : OUTBUF
      port map(D => \RES1[43]\, PAD => RESULT(43));
    
    \F_in_r[0]\ : SLE
      port map(D => \INP_88b_c[44]\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in_r[0]_net_1\);
    
    \F_in[28]\ : SLE
      port map(D => \F_in_r[28]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[28]_net_1\);
    
    \INP_D_ibuf[3]\ : INBUF
      port map(PAD => INP_D(3), Y => \INP_D_c[3]\);
    
    \F_in[29]\ : SLE
      port map(D => \F_in_r[29]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[29]_net_1\);
    
    \F_in[38]\ : SLE
      port map(D => \F_in_r[38]_net_1\, CLK => CLK_c, EN => 
        VCC_net_1, ALn => RSTN_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \F_in[38]_net_1\);
    

end DEF_ARCH; 
