--------------------------------------------------------------------------------
-- Company: MICROSEMI
--
-- File: Mult32x32_multipleMACC.vhd
-- File history:
--      1.0: 27-04-13: 
--
-- Description: 
--
-- Implementation of Multiplier 32x32 with 4 MATHBLOCKS(3 MULTDADDS,1 MULT)
--
-- Targeted device: Family::SmartFusion2,
--					   Die::M2S050T 
--				   Package::896 FBGA
--
-- Author: PHANIKIRAN T
--------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity Mult32x32_multipleMACC is
	port (
    	clk 	: IN std_logic;
		reset_n : IN std_logic;
		MultA	: IN signed(31 downto 0);
		MultB	: IN signed(31 downto 0);
		Mul_result: OUT signed(63 downto 0)
	);
end	 Mult32x32_multipleMACC;

architecture Mult32x32_multipleMACC_arch of Mult32x32_multipleMACC is
   -- signal declarations
	signal inp_reg0: signed(31 downto 0); 
	signal inp_reg1: signed(31 downto 0);
	signal inp_reg2: signed(31 downto 0); 
	signal inp_reg3: signed(31 downto 0);
	
	signal reg1: signed(63 downto 0); 

	
begin

  
		process (clk,reset_n)
		begin
		  if(reset_n = '0')then
			inp_reg0	<= (others => '0');
			inp_reg1	<= (others => '0');
			inp_reg2	<= (others => '0');
			inp_reg3	<= (others => '0');		
	 	 else
		       if(rising_edge(clk))then
				inp_reg0 <= MultA;
				inp_reg1 <= inp_reg0;
			
				inp_reg2 <= MultB;
				inp_reg3 <= inp_reg2;				
	  	      end if;
		  end if;
		end process;


		process (clk,reset_n)
		begin
		  if(reset_n = '0')then
			reg1 <= (others => '0');
			Mul_result	<= (others => '0');
		  else
		       if(rising_edge(clk))then
					reg1   <= inp_reg1 * inp_reg3;
		  		Mul_result <= reg1;
	  	      end if;
		  end if;
		end process;


end Mult32x32_multipleMACC_arch;
