--------------------------------------------------------------------------------
-- Company:
--
-- File: SLL_SRL_TESTBENCH.vhd
--
-- File history:
--
-- Description	  : Provides stimuls vectors to the Shift register SLL_SRL.vhd module
--				
-- Targeted device: Family		:: SmartFusion2  
-- 					  Die		:: M2S050T
--					  Package	:: 896 FBGA
--		Author	  : PHANIKIRAN T
--------------------------------------------------------------------------------



LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY SLL_SRL_TESTBENCH IS
END SLL_SRL_TESTBENCH;

ARCHITECTURE SLL_SRL_ARCH OF SLL_SRL_TESTBENCH IS


COMPONENT SLL_SRL IS
PORT (
    CLK 		: IN STD_LOGIC;
    RSTN 		: IN STD_LOGIC;
	SHIFT_INP	: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
   	SLL_OP	 	: OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
	SRL_OP	 	: OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
);
END COMPONENT SLL_SRL;

CONSTANT clk_period : time := 10 ns;

SIGNAL clk		: STD_LOGIC:= '0';
SIGNAL reset_n	: STD_LOGIC:= '0';

SIGNAL SHIFT_INP: STD_LOGIC_VECTOR(17 downto 0);

SIGNAL SLL_OP	: STD_LOGIC_VECTOR(17 downto 0);
SIGNAL SRL_OP	: STD_LOGIC_VECTOR(17 downto 0);

SIGNAL stop 	: STD_LOGIC := '0';	


BEGIN


UUT: SLL_SRL
		port map(	
				CLK 		=> clk,
			    RSTN 		=> reset_n,
				SHIFT_INP	=> SHIFT_INP,
   				SLL_OP	 	=> SLL_OP,
				SRL_OP		=> SRL_OP	
         );

--- Clock and Reset Generation 

 clk_proc :PROCESS
   BEGIN
		IF(stop = '0')THEN
	        clk <= '0';
    	    WAIT FOR clk_period/2;
        	clk <= '1';
	        WAIT FOR clk_period/2;
		ELSE
			clk <= '0';
		END IF;
 	END PROCESS;

  stim_proc: PROCESS
   BEGIN
        reset_n <='0';
        WAIT FOR 20 ns;
        reset_n	<='1';
        WAIT;
  END PROCESS;



PROCESS
BEGIN
		WAIT UNTIL(reset_n ='1');
		WAIT UNTIL rising_edge(clk);
		SHIFT_INP	<= "011100110010101101";--3CCADh
		WAIT UNTIL rising_edge(clk);
		SHIFT_INP	<= "111001010110101111";--395AFh
		WAIT UNTIL rising_edge(clk);
		SHIFT_INP	<= "010110010110101011";--165ABh
		WAIT FOR 500 ns;
		WAIT UNTIL rising_edge(clk);
			stop <=  '1';
		
		report "TEST FINISHED!"
		severity failure;
		--wait;
END PROCESS;

end SLL_SRL_ARCH;

