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    Synopsys Generic Technology Mapper, Version mapact, Build 976R, Built May 23 2013 12:10:32
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version H-2013.03M-1

    Mapper Startup Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 57MB)

    @N:MF249 :  | Running in 32-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB)

    Start loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 58MB)

    Finished loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 60MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:01s; Memory used current: 76MB peak: 78MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 78MB)

    Finished factoring (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:01s; Memory used current: 76MB peak: 78MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:02s; Memory used current: 76MB peak: 78MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:02s; Memory used current: 76MB peak: 78MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:02s; Memory used current: 76MB peak: 78MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:02s; Memory used current: 76MB peak: 78MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:02s; Memory used current: 76MB peak: 78MB)

    Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:02s; Memory used current: 76MB peak: 78MB)

    Finished technology mapping (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:02s; Memory used current: 76MB peak: 78MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    @N:FP130 :  | Promoting Net CLK_c on CLKINT  I_1
    @N:FP130 :  | Promoting Net RSTN_c on CLKINT  I_2

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:03s; Memory used current: 76MB peak: 78MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:03s; Memory used current: 76MB peak: 78MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    1 non-gated/non-generated clock tree(s) driving 164 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId0001       CLK                 port                   164        D_in[10]
    =======================================================================================
    ===== Gated/Generated Clocks =====
    ************** None **************
    ----------------------------------
    ==================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Writing Analyst data base D:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Adder_Sub_88bit\synthesis\Adder_Sub_88bit.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:04s; Memory used current: 75MB peak: 78MB)

    Writing EDIF Netlist and constraint files
    H-2013.03M-1

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:06s; Memory used current: 76MB peak: 78MB)

    @W:MT420 :  | Found inferred clock Adder_Sub_88bit|CLK with period 1000.00ns. Please declare a user-defined clock on object "p:CLK"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Mon Oct 07 03:40:56 2013
    #

    Top view:               Adder_Sub_88bit
    Requested Frequency:    1.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: -0.146

                            Requested      Estimated      Requested     Estimated                 Clock        Clock
    Starting Clock          Frequency      Frequency      Period        Period        Slack       Type         Group
    --------------------------------------------------------------------------------------------------------------------------------
    Adder_Sub_88bit|CLK     1.0 MHz        938.4 MHz      1000.000      1.066         998.934     inferred     Autoconstr_clkgroup_0
    System                  1211.1 MHz     1029.4 MHz     0.826         0.971         -0.146      system       system_clkgroup
    ================================================================================================================================

    Clock Relationships
    *******************

    Clocks                       |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------
    Starting             Ending  |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------
    System               System  |  0.826       -0.146   |  No paths    -      |  No paths    -      |  No paths    -
    Adder_Sub_88bit|CLK  System  |  1000.000    998.934  |  No paths    -      |  No paths    -      |  No paths    -
    =====================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: Adder_Sub_88bit|CLK
    ====================================

    Starting Points with Worst Slack
    ********************************

                 Starting                                             Arrival
    Instance     Reference               Type     Pin     Net         Time        Slack
                 Clock
    -------------------------------------------------------------------------------------
    A_in[0]      Adder_Sub_88bit|CLK     SLE      Q       A_in[0]     0.094       998.934
    A_in[1]      Adder_Sub_88bit|CLK     SLE      Q       A_in[1]     0.094       998.934
    A_in[2]      Adder_Sub_88bit|CLK     SLE      Q       A_in[2]     0.094       998.934
    A_in[3]      Adder_Sub_88bit|CLK     SLE      Q       A_in[3]     0.094       998.934
    A_in[4]      Adder_Sub_88bit|CLK     SLE      Q       A_in[4]     0.094       998.934
    A_in[5]      Adder_Sub_88bit|CLK     SLE      Q       A_in[5]     0.094       998.934
    A_in[6]      Adder_Sub_88bit|CLK     SLE      Q       A_in[6]     0.094       998.934
    A_in[7]      Adder_Sub_88bit|CLK     SLE      Q       A_in[7]     0.094       998.934
    A_in[8]      Adder_Sub_88bit|CLK     SLE      Q       A_in[8]     0.094       998.934
    A_in[9]      Adder_Sub_88bit|CLK     SLE      Q       A_in[9]     0.094       998.934
    =====================================================================================

    Ending Points with Worst Slack
    ******************************

                                Starting                                              Required
    Instance                    Reference               Type     Pin      Net         Time         Slack
                                Clock
    ------------------------------------------------------------------------------------------------------
    U1.MultAdder_w_Din_0.U0     Adder_Sub_88bit|CLK     MACC     A[0]     D_in[0]     1000.000     998.934
    U0.MultAdder_0.U0           Adder_Sub_88bit|CLK     MACC     A[0]     A_in[0]     1000.000     998.934
    U1.MultAdder_w_Din_0.U0     Adder_Sub_88bit|CLK     MACC     A[0]     D_in[0]     1000.000     998.934
    U0.MultAdder_0.U0           Adder_Sub_88bit|CLK     MACC     A[0]     A_in[0]     1000.000     998.934
    U0.MultAdder_0.U0           Adder_Sub_88bit|CLK     MACC     A[1]     A_in[1]     1000.000     998.934
    U1.MultAdder_w_Din_0.U0     Adder_Sub_88bit|CLK     MACC     A[1]     D_in[1]     1000.000     998.934
    U0.MultAdder_0.U0           Adder_Sub_88bit|CLK     MACC     A[1]     A_in[1]     1000.000     998.934
    U1.MultAdder_w_Din_0.U0     Adder_Sub_88bit|CLK     MACC     A[1]     D_in[1]     1000.000     998.934
    U0.MultAdder_0.U0           Adder_Sub_88bit|CLK     MACC     A[2]     A_in[2]     1000.000     998.934
    U1.MultAdder_w_Din_0.U0     Adder_Sub_88bit|CLK     MACC     A[2]     D_in[2]     1000.000     998.934
    ======================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         1000.000

        - Propagation time:                      1.066
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 998.934

        Number of logic level(s):                0
        Starting point:                          A_in[0] / Q
        Ending point:                            U0.MultAdder_0.U0 / A[0]
        The start point is clocked by            Adder_Sub_88bit|CLK [rising] on pin CLK
        The end   point is clocked by            System [rising]

    Instance / Net                 Pin      Pin               Arrival     No. of
    Name                  Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------
    A_in[0]               SLE      Q        Out     0.094     0.094       -
    A_in[0]               Net      -        -       0.971     -           1
    U0.MultAdder_0.U0     MACC     A[0]     In      -         1.066       -
    ================================================================================
    Total path delay (propagation time + setup) of 1.066 is 0.094(8.8%) logic and 0.971(91.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                          Starting                                             Arrival
    Instance              Reference     Type     Pin               Net         Time        Slack
                          Clock
    ---------------------------------------------------------------------------------------------
    U0.MultAdder_0.U0     System        MACC     OVFL_CARRYOUT     CARRYIN     0.000       -0.146
    U0.MultAdder_0.U0     System        MACC     OVFL_CARRYOUT     CARRYIN     0.000       -0.146
    =============================================================================================

    Ending Points with Worst Slack
    ******************************

                                Starting                                       Required
    Instance                    Reference     Type     Pin         Net         Time         Slack
                                Clock
    ----------------------------------------------------------------------------------------------
    U1.MultAdder_w_Din_0.U0     System        MACC     CARRYIN     CARRYIN     0.826        -0.146
    U1.MultAdder_w_Din_0.U0     System        MACC     CARRYIN     CARRYIN     0.826        -0.146
    ==============================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -0.146

        Number of logic level(s):                0
        Starting point:                          U0.MultAdder_0.U0 / OVFL_CARRYOUT
        Ending point:                            U1.MultAdder_w_Din_0.U0 / CARRYIN
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                       Pin               Pin               Arrival     No. of
    Name                        Type     Name              Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------
    U0.MultAdder_0.U0           MACC     OVFL_CARRYOUT     Out     0.000     0.000       -
    CARRYIN                     Net      -                 -       0.971     -           1
    U1.MultAdder_w_Din_0.U0     MACC     CARRYIN           In      -         0.971       -
    ===============================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -0.146

        Number of logic level(s):                0
        Starting point:                          U0.MultAdder_0.U0 / OVFL_CARRYOUT
        Ending point:                            U1.MultAdder_w_Din_0.U0 / CARRYIN
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                       Pin               Pin               Arrival     No. of
    Name                        Type     Name              Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------
    U0.MultAdder_0.U0           MACC     OVFL_CARRYOUT     Out     0.000     0.000       -
    CARRYIN                     Net      -                 -       0.971     -           1
    U1.MultAdder_w_Din_0.U0     MACC     CARRYIN           In      -         0.971       -
    ===============================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    ---------------------------------------
    Resource Usage Report for Adder_Sub_88bit

    Mapping to part: m2s050fbga896-1
    Cell usage:
    CLKINT          2 uses

    Sequential Cells:
    SLE            160 uses
    Registers not packed on I/O Pads:      160

    DSP Blocks:    2
     MACC:         2 Mults

    I/O ports: 250
    I/O primitives: 250
    INBUF          162 uses
    OUTBUF         88 uses

    Global Clock Buffers: 2

    Total LUTs:    0

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:08s; Memory used current: 33MB peak: 78MB)

    Process took 0h:00m:19s realtime, 0h:00m:08s cputime
    # Mon Oct 07 03:40:56 2013

    ###########################################################]

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