@N|Running in 64-bit mode
@N: CD720 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ns
@N:"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\BarrelShifter\hdl\BarrelShifter_18bit.vhd":23:7:23:25|Top entity is set to BarrelShifter_18bit.
@N: CD231 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vhd2008\std1164.vhd":913:16:913:17|Using onehot encoding for type mvl9plus ('U'="1000000000")
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\BarrelShifter\hdl\BarrelShifter_18bit.vhd":23:7:23:25|Synthesizing work.barrelshifter_18bit.barrelshift_arch 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\BarrelShifter\component\work\Mult18x18_barrShift\Mult18x18_barrShift.vhd":17:7:17:25|Synthesizing work.mult18x18_barrshift.rtl 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\BarrelShifter\component\work\Mult18x18_barrShift\Mult18x18_barrShift_0\Mult18x18_barrShift_Mult18x18_barrShift_0_HARD_MULT_ADDSUB.vhd":8:7:8:64|Synthesizing work.mult18x18_barrshift_mult18x18_barrshift_0_hard_mult_addsub.def_arch 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":575:10:575:12|Synthesizing smartfusion2.vcc.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":569:10:569:12|Synthesizing smartfusion2.gnd.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":695:10:695:13|Synthesizing smartfusion2.macc.syn_black_box 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\BarrelShifter\component\work\Mult18x18\Mult18x18.vhd":17:7:17:15|Synthesizing work.mult18x18.rtl 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\BarrelShifter\component\work\Mult18x18\Mult18x18_0\Mult18x18_Mult18x18_0_HARD_MULT.vhd":8:7:8:37|Synthesizing work.mult18x18_mult18x18_0_hard_mult.def_arch 

