@W: CD638 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":194:8:194:19|Signal coef_rdaddr2 is undriven 
@W: CD638 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":197:8:197:17|Signal coef1_rden is undriven 
@W: CD638 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Signal coef_rddata2 is undriven 
@W: CD638 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":229:8:229:17|Signal portc_addr is undriven 
@W: CD638 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":230:8:230:16|Signal portc_din is undriven 
@W: CD638 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":231:8:231:21|Signal portb_coefaddr is undriven 
@W: CD638 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":232:8:232:20|Signal portb_inpaddr is undriven 
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":231:8:231:21|Bit 0 of signal PORTB_Coefaddr is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":231:8:231:21|Bit 1 of signal PORTB_Coefaddr is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":231:8:231:21|Bit 2 of signal PORTB_Coefaddr is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":231:8:231:21|Bit 3 of signal PORTB_Coefaddr is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":231:8:231:21|Bit 4 of signal PORTB_Coefaddr is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":231:8:231:21|Bit 5 of signal PORTB_Coefaddr is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":229:8:229:17|Bit 0 of signal PORTC_ADDR is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":229:8:229:17|Bit 1 of signal PORTC_ADDR is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":229:8:229:17|Bit 2 of signal PORTC_ADDR is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":229:8:229:17|Bit 3 of signal PORTC_ADDR is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":229:8:229:17|Bit 4 of signal PORTC_ADDR is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":229:8:229:17|Bit 5 of signal PORTC_ADDR is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 0 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 1 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 2 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 3 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 4 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 5 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 6 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 7 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 8 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 9 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 10 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 11 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 12 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 13 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 14 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 15 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 16 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL252 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":201:8:201:19|Bit 17 of signal Coef_rddata2 is floating -- simulation mismatch possible.
@W: CL240 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":197:8:197:17|Coef1_rden is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL169 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":683:3:683:4|Pruning register rden_2  
@W: CL271 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":615:3:615:4|Pruning bits 7 to 6 of inp_wraddr2_3(7 downto 0) -- not in use ... 
@W: CL271 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":615:3:615:4|Pruning bits 7 to 6 of inp_wraddr1_3(7 downto 0) -- not in use ... 
@W: CL271 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":516:3:516:4|Pruning bits 7 to 6 of InpB_rdaddr1_4(7 downto 0) -- not in use ... 
@W: CL271 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":500:3:500:4|Pruning bits 7 to 6 of InpA_rdaddr1_4(7 downto 0) -- not in use ... 
@W: CL271 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":409:3:409:4|Pruning bits 7 to 6 of Coef_rdaddr1_2(7 downto 0) -- not in use ... 
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 0 of input b_addr of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 1 of input b_addr of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 2 of input b_addr of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 3 of input b_addr of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 4 of input b_addr of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 5 of input b_addr of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 0 of input c_addr of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 1 of input c_addr of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 2 of input c_addr of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 3 of input c_addr of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 4 of input c_addr of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 5 of input c_addr of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 0 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 1 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 2 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 3 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 4 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 5 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 6 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 7 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 8 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 9 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 10 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 11 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 12 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 13 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 14 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 15 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 16 of input c_din of instance U1 is floating
@W: CL245 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":712:0:712:1|Bit 17 of input c_din of instance U1 is floating
@W: CL111 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\Symmetric_MAC_FIR_Filter\hdl\Symmetric_MAC_FIR.vhd":769:2:769:3|All reachable assignments to Sel_Coef2 assign '0'; register removed by optimization

