`

    #Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014
    #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1
    #OS: Windows 7 6.1
    #Hostname: W764-TADIGADAPA

    #Implementation: synthesis

    $ Start of Compile
    #Wed May 21 20:12:45 2014

    Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

    @N:CD720 : std.vhd(146) | Setting time resolution to ns
    @N: : Transpose_FIR.vhd(21) | Top entity is set to Transpose_FIR.
    File C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd changed - recompiling
    File D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Parallel FIR Filters\Transpose FIR Filter\Transpose_FIR_w_macc\component\work\multadd\multadd.vhd changed - recompiling
    File D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Parallel FIR Filters\Transpose FIR Filter\Transpose_FIR_w_macc\hdl\Transpose_FIR.vhd changed - recompiling
    File C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vhd2008\signed.vhd changed - recompiling
    VHDL syntax check successful!
    @N:CD231 : std1164.vhd(913) | Using onehot encoding for type mvl9plus ('U'="1000000000")
    @N:CD630 : Transpose_FIR.vhd(21) | Synthesizing work.transpose_fir.transpose_fir_arch
    @W:CD638 : Transpose_FIR.vhd(67) | Signal P_0 is undriven
    @W:CD638 : Transpose_FIR.vhd(70) | Signal coef is undriven
    @N:CD630 : multadd.vhd(17) | Synthesizing work.multadd.rtl
    @N:CD630 : multadd_multadd_0_HARD_MULT_ADDSUB.vhd(8) | Synthesizing work.multadd_multadd_0_hard_mult_addsub.def_arch
    @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box
    Post processing for smartfusion2.vcc.syn_black_box
    @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box
    Post processing for smartfusion2.gnd.syn_black_box
    @N:CD630 : smartfusion2.vhd(695) | Synthesizing smartfusion2.macc.syn_black_box
    Post processing for smartfusion2.macc.syn_black_box
    Post processing for work.multadd_multadd_0_hard_mult_addsub.def_arch
    Post processing for work.multadd.rtl
    Post processing for work.transpose_fir.transpose_fir_arch
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 0 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 1 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 2 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 3 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 4 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 5 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 6 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 7 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 8 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 9 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 10 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 11 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 12 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 13 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 14 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 15 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 16 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 17 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 18 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 19 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 20 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 21 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 22 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 23 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 24 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 25 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 26 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 27 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 28 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 29 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 30 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 31 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 32 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 33 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 34 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 35 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 36 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 37 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 38 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 39 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 40 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 41 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 42 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Transpose_FIR.vhd(67) | Bit 43 of signal P_0 is floating -- simulation mismatch possible.
    @END

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 20:12:45 2014

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

    Linked File: DSP
    Printing clock  summary report in "D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Parallel FIR Filters\Transpose FIR Filter\Transpose_FIR_w_macc\synthesis\Transpose_FIR_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    syn_allowed_resources : blockrams=69  set on top level netlist Transpose_FIR

    Clock Summary
    **************

    Start                 Requested     Requested     Clock        Clock
    Clock                 Frequency     Period        Type         Group
    ------------------------------------------------------------------------------------
    System                1.0 MHz       1000.000      system       system_clkgroup
    Transpose_FIR|Clk     1.0 MHz       1000.000      inferred     Autoconstr_clkgroup_0
    ====================================================================================

    @W:MT530 : multadd_multadd_0_hard_mult_addsub.vhd(108) | Found inferred clock Transpose_FIR|Clk which controls 18 sequential elements including U1\.16\.UUT_1.multadd_0.U0. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Parallel FIR Filters\Transpose FIR Filter\Transpose_FIR_w_macc\synthesis\Transpose_FIR.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 135MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 20:12:47 2014

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    @N:FP130 :  | Promoting Net Clk_c on CLKINT  I_1
    @N:FP130 :  | Promoting Net resetn_c on CLKINT  I_2

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    1 non-gated/non-generated clock tree(s) driving 50 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId0001        Clk                 port                   50         Xreg[10]
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Writing Analyst data base D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Parallel FIR Filters\Transpose FIR Filter\Transpose_FIR_w_macc\synthesis\Transpose_FIR.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    I-2013.09M-SP1

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 134MB)

    @W:MT420 :  | Found inferred clock Transpose_FIR|Clk with period 1000.00ns. Please declare a user-defined clock on object "p:Clk"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed May 21 20:12:49 2014
    #

    Top view:               Transpose_FIR
    Requested Frequency:    1.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: -0.146

                          Requested      Estimated      Requested     Estimated                 Clock        Clock
    Starting Clock        Frequency      Frequency      Period        Period        Slack       Type         Group
    ------------------------------------------------------------------------------------------------------------------------------
    Transpose_FIR|Clk     1.0 MHz        920.7 MHz      1000.000      1.086         998.914     inferred     Autoconstr_clkgroup_0
    System                1211.1 MHz     1029.4 MHz     0.826         0.971         -0.146      system       system_clkgroup
    ==============================================================================================================================

    Clock Relationships
    *******************

    Clocks                     |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -------------------------------------------------------------------------------------------------------------------
    Starting           Ending  |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
    -------------------------------------------------------------------------------------------------------------------
    System             System  |  0.826       -0.146   |  No paths    -      |  No paths    -      |  No paths    -
    Transpose_FIR|Clk  System  |  1000.000    998.914  |  No paths    -      |  No paths    -      |  No paths    -
    ===================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: Transpose_FIR|Clk
    ====================================

    Starting Points with Worst Slack
    ********************************

                 Starting                                           Arrival
    Instance     Reference             Type     Pin     Net         Time        Slack
                 Clock
    -----------------------------------------------------------------------------------
    Xreg[0]      Transpose_FIR|Clk     SLE      Q       Xreg[0]     0.094       998.914
    Xreg[1]      Transpose_FIR|Clk     SLE      Q       Xreg[1]     0.094       998.914
    Xreg[2]      Transpose_FIR|Clk     SLE      Q       Xreg[2]     0.094       998.914
    Xreg[3]      Transpose_FIR|Clk     SLE      Q       Xreg[3]     0.094       998.914
    Xreg[4]      Transpose_FIR|Clk     SLE      Q       Xreg[4]     0.094       998.914
    Xreg[5]      Transpose_FIR|Clk     SLE      Q       Xreg[5]     0.094       998.914
    Xreg[6]      Transpose_FIR|Clk     SLE      Q       Xreg[6]     0.094       998.914
    Xreg[7]      Transpose_FIR|Clk     SLE      Q       Xreg[7]     0.094       998.914
    Xreg[8]      Transpose_FIR|Clk     SLE      Q       Xreg[8]     0.094       998.914
    Xreg[9]      Transpose_FIR|Clk     SLE      Q       Xreg[9]     0.094       998.914
    ===================================================================================

    Ending Points with Worst Slack
    ******************************

                                   Starting                                            Required
    Instance                       Reference             Type     Pin      Net         Time         Slack
                                   Clock
    -------------------------------------------------------------------------------------------------------
    U1\.8\.UUT_1.multadd_0.U0      Transpose_FIR|Clk     MACC     A[0]     Xreg[0]     1000.000     998.914
    U1\.1\.UUT_1.multadd_0.U0      Transpose_FIR|Clk     MACC     A[0]     Xreg[0]     1000.000     998.914
    U1\.12\.UUT_1.multadd_0.U0     Transpose_FIR|Clk     MACC     A[0]     Xreg[0]     1000.000     998.914
    U1\.11\.UUT_1.multadd_0.U0     Transpose_FIR|Clk     MACC     A[0]     Xreg[0]     1000.000     998.914
    U1\.16\.UUT_1.multadd_0.U0     Transpose_FIR|Clk     MACC     A[0]     Xreg[0]     1000.000     998.914
    U1\.4\.UUT_1.multadd_0.U0      Transpose_FIR|Clk     MACC     A[0]     Xreg[0]     1000.000     998.914
    U1\.8\.UUT_1.multadd_0.U0      Transpose_FIR|Clk     MACC     A[0]     Xreg[0]     1000.000     998.914
    U1\.1\.UUT_1.multadd_0.U0      Transpose_FIR|Clk     MACC     A[0]     Xreg[0]     1000.000     998.914
    U1\.6\.UUT_1.multadd_0.U0      Transpose_FIR|Clk     MACC     A[0]     Xreg[0]     1000.000     998.914
    U1\.15\.UUT_1.multadd_0.U0     Transpose_FIR|Clk     MACC     A[0]     Xreg[0]     1000.000     998.914
    =======================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         1000.000

        - Propagation time:                      1.086
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 998.914

        Number of logic level(s):                0
        Starting point:                          Xreg[0] / Q
        Ending point:                            U1\.8\.UUT_1.multadd_0.U0 / A[0]
        The start point is clocked by            Transpose_FIR|Clk [rising] on pin CLK
        The end   point is clocked by            System [rising]

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                          Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    Xreg[0]                       SLE      Q        Out     0.094     0.094       -
    Xreg[0]                       Net      -        -       0.992     -           16
    U1\.8\.UUT_1.multadd_0.U0     MACC     A[0]     In      -         1.086       -
    ========================================================================================
    Total path delay (propagation time + setup) of 1.086 is 0.094(8.7%) logic and 0.992(91.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                   Starting                                           Arrival
    Instance                       Reference     Type     Pin          Net            Time        Slack
                                   Clock
    ----------------------------------------------------------------------------------------------------
    U1\.8\.UUT_1.multadd_0.U0      System        MACC     CDOUT[0]     CDIN_8[0]      0.000       -0.146
    U1\.8\.UUT_1.multadd_0.U0      System        MACC     CDOUT[0]     CDIN_8[0]      0.000       -0.146
    U1\.13\.UUT_1.multadd_0.U0     System        MACC     CDOUT[0]     CDIN_13[0]     0.000       -0.146
    U1\.5\.UUT_1.multadd_0.U0      System        MACC     CDOUT[0]     CDIN_5[0]      0.000       -0.146
    U1\.3\.UUT_1.multadd_0.U0      System        MACC     CDOUT[0]     CDIN_3[0]      0.000       -0.146
    U1\.3\.UUT_1.multadd_0.U0      System        MACC     CDOUT[0]     CDIN_3[0]      0.000       -0.146
    U1\.1\.UUT_1.multadd_0.U0      System        MACC     CDOUT[0]     CDIN_1[0]      0.000       -0.146
    U1\.7\.UUT_1.multadd_0.U0      System        MACC     CDOUT[0]     CDIN_7[0]      0.000       -0.146
    U1\.6\.UUT_1.multadd_0.U0      System        MACC     CDOUT[0]     CDIN_6[0]      0.000       -0.146
    U1\.9\.UUT_1.multadd_0.U0      System        MACC     CDOUT[0]     CDIN_9[0]      0.000       -0.146
    ====================================================================================================

    Ending Points with Worst Slack
    ******************************

                                   Starting                                          Required
    Instance                       Reference     Type     Pin         Net            Time         Slack
                                   Clock
    ----------------------------------------------------------------------------------------------------
    U1\.8\.UUT_1.multadd_0.U0      System        MACC     CDIN[0]     CDIN_7[0]      0.826        -0.146
    U1\.8\.UUT_1.multadd_0.U0      System        MACC     CDIN[0]     CDIN_7[0]      0.826        -0.146
    U1\.13\.UUT_1.multadd_0.U0     System        MACC     CDIN[0]     CDIN_12[0]     0.826        -0.146
    U1\.7\.UUT_1.multadd_0.U0      System        MACC     CDIN[0]     CDIN_6[0]      0.826        -0.146
    U1\.3\.UUT_1.multadd_0.U0      System        MACC     CDIN[0]     CDIN_2[0]      0.826        -0.146
    U1\.3\.UUT_1.multadd_0.U0      System        MACC     CDIN[0]     CDIN_2[0]      0.826        -0.146
    U1\.6\.UUT_1.multadd_0.U0      System        MACC     CDIN[0]     CDIN_5[0]      0.826        -0.146
    U1\.11\.UUT_1.multadd_0.U0     System        MACC     CDIN[0]     CDIN_10[0]     0.826        -0.146
    U1\.12\.UUT_1.multadd_0.U0     System        MACC     CDIN[0]     CDIN_11[0]     0.826        -0.146
    U1\.9\.UUT_1.multadd_0.U0      System        MACC     CDIN[0]     CDIN_8[0]      0.826        -0.146
    ====================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -0.146

        Number of logic level(s):                0
        Starting point:                          U1\.8\.UUT_1.multadd_0.U0 / CDOUT[0]
        Ending point:                            U1\.9\.UUT_1.multadd_0.U0 / CDIN[0]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                         Pin          Pin               Arrival     No. of
    Name                          Type     Name         Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------
    U1\.8\.UUT_1.multadd_0.U0     MACC     CDOUT[0]     Out     0.000     0.000       -
    CDIN_8[0]                     Net      -            -       0.971     -           1
    U1\.9\.UUT_1.multadd_0.U0     MACC     CDIN[0]      In      -         0.971       -
    ============================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -0.146

        Number of logic level(s):                0
        Starting point:                          U1\.8\.UUT_1.multadd_0.U0 / CDOUT[0]
        Ending point:                            U1\.9\.UUT_1.multadd_0.U0 / CDIN[0]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                         Pin          Pin               Arrival     No. of
    Name                          Type     Name         Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------
    U1\.8\.UUT_1.multadd_0.U0     MACC     CDOUT[0]     Out     0.000     0.000       -
    CDIN_8[0]                     Net      -            -       0.971     -           1
    U1\.9\.UUT_1.multadd_0.U0     MACC     CDIN[0]      In      -         0.971       -
    ============================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -0.146

        Number of logic level(s):                0
        Starting point:                          U1\.13\.UUT_1.multadd_0.U0 / CDOUT[0]
        Ending point:                            U1\.14\.UUT_1.multadd_0.U0 / CDIN[0]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                          Pin          Pin               Arrival     No. of
    Name                           Type     Name         Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------
    U1\.13\.UUT_1.multadd_0.U0     MACC     CDOUT[0]     Out     0.000     0.000       -
    CDIN_13[0]                     Net      -            -       0.971     -           1
    U1\.14\.UUT_1.multadd_0.U0     MACC     CDIN[0]      In      -         0.971       -
    =============================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -0.146

        Number of logic level(s):                0
        Starting point:                          U1\.5\.UUT_1.multadd_0.U0 / CDOUT[0]
        Ending point:                            U1\.6\.UUT_1.multadd_0.U0 / CDIN[0]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                         Pin          Pin               Arrival     No. of
    Name                          Type     Name         Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------
    U1\.5\.UUT_1.multadd_0.U0     MACC     CDOUT[0]     Out     0.000     0.000       -
    CDIN_5[0]                     Net      -            -       0.971     -           1
    U1\.6\.UUT_1.multadd_0.U0     MACC     CDIN[0]      In      -         0.971       -
    ============================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -0.146

        Number of logic level(s):                0
        Starting point:                          U1\.3\.UUT_1.multadd_0.U0 / CDOUT[0]
        Ending point:                            U1\.4\.UUT_1.multadd_0.U0 / CDIN[0]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                         Pin          Pin               Arrival     No. of
    Name                          Type     Name         Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------
    U1\.3\.UUT_1.multadd_0.U0     MACC     CDOUT[0]     Out     0.000     0.000       -
    CDIN_3[0]                     Net      -            -       0.971     -           1
    U1\.4\.UUT_1.multadd_0.U0     MACC     CDIN[0]      In      -         0.971       -
    ============================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    ---------------------------------------
    Resource Usage Report for Transpose_FIR

    Mapping to part: m2s050fbga896-1
    Cell usage:
    CLKINT          2 uses

    Sequential Cells:
    SLE            18 uses

    DSP Blocks:   16
     MACC:        16 Mults

    I/O ports: 64
    I/O primitives: 64
    INBUF          20 uses
    OUTBUF         44 uses

    Global Clock Buffers: 2

    Total LUTs:    0

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 48MB peak: 134MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 20:12:49 2014

    ###########################################################]

`