----------------------------------------------------------------------
-- Created by Actel SmartDesign Mon Nov 11 15:51:39 2013
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic 
-- clock and reset pins connected.  If your design has special
-- clock/reset or testbench driver requirements then you should 
-- copy this file and modify it. 
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

    constant SYSCLK_PERIOD : time := 100 ns;

    signal SYSCLK : std_logic := '0';
    signal NSYSRESET : std_logic := '0';

    component Inp_RAM
        -- ports
        port( 
            -- Inputs
            C_DIN : in std_logic_vector(17 downto 0);
            A_ADDR : in std_logic_vector(5 downto 0);
            B_ADDR : in std_logic_vector(5 downto 0);
            C_ADDR : in std_logic_vector(5 downto 0);
            C_BLK : in std_logic;
            CLK : in std_logic;
            A_BLK : in std_logic;
            B_BLK : in std_logic;

            -- Outputs
            A_DOUT : out std_logic_vector(17 downto 0);
            B_DOUT : out std_logic_vector(17 downto 0)

            -- Inouts

        );
    end component;

begin

    process
        variable vhdl_initial : BOOLEAN := TRUE;

    begin
        if ( vhdl_initial ) then
            -- Assert Reset
            NSYSRESET <= '0';
            wait for ( SYSCLK_PERIOD * 10 );
            
            NSYSRESET <= '1';
            wait;
        end if;
    end process;

    -- 10MHz Clock Driver
    SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );

    -- Instantiate Unit Under Test:  Inp_RAM
    Inp_RAM_0 : Inp_RAM
        -- port map
        port map( 
            -- Inputs
            C_DIN => (others=> '0'),
            A_ADDR => (others=> '0'),
            B_ADDR => (others=> '0'),
            C_ADDR => (others=> '0'),
            C_BLK => SYSCLK,
            CLK => SYSCLK,
            A_BLK => '0',
            B_BLK => '0',

            -- Outputs
            A_DOUT => open,
            B_DOUT => open

            -- Inouts

        );

end behavioral;

