@W: BN132 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\counter_44bit\hdl\counter_44bit.vhd":116:1:116:2|Removing sequential instance B[0],  because it is equivalent to instance A[0]
@W: MT530 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\counter_44bit\component\work\multacc\multacc_0\multacc_multacc_0_hard_mult_acc.vhd":105:4:105:5|Found inferred clock Counter_44bit|CLK which controls 47 sequential elements including UUT.MultAcc_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
