--------------------------------------------------------------------------------
-- Company:
--
-- File: Accumulator_TestBench.vhd
--
-- File history:
--
-- Description	  : Provides stimuls vectors to the Accumulator_TestBench
--				
-- Targeted device: Family		:: SmartFusion2  
-- 					  Die		:: M2S050T
--					  Package	:: 896 FBGA
--		Author	  : PHANIKIRAN T
--------------------------------------------------------------------------------


LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY Counter_44bit_Testbench IS
END Counter_44bit_Testbench;

ARCHITECTURE behavioral OF Counter_44bit_Testbench IS



COMPONENT Counter_44bit IS
PORT (
       CLK 		: IN STD_LOGIC;
    RSTN 		: IN STD_LOGIC;

-- Input
	LD			: IN STD_LOGIC;	
	UP_DN		: IN STD_LOGIC;

	CNTBY_LDINP	: IN STD_LOGIC;-- Need to assert always to perform this operation
	LOAD_INP	: IN STD_LOGIC_VECTOR(43 DOWNTO 0);


-- Output
   	CNTR_O	 	: OUT STD_LOGIC_VECTOR(43 DOWNTO 0)
	);
END COMPONENT Counter_44bit;

CONSTANT clk_period : time := 10 ns;

SIGNAL clk			: STD_LOGIC:= '0';
SIGNAL reset_n		: STD_LOGIC:= '0';



SIGNAL LD			: STD_LOGIC := '0';
SIGNAL UP_DN		: STD_LOGIC := '0';

SIGNAL CNTBY_LDINP	: STD_LOGIC := '0';-- Need to assert always to perform this operation
SIGNAL LOAD_INP		: STD_LOGIC_VECTOR(43 DOWNTO 0);
SIGNAL CNTR_O		: STD_LOGIC_VECTOR(43 DOWNTO 0);

SIGNAL stop 		: STD_LOGIC := '0';	


BEGIN


UUT: Counter_44bit
		port map(	

				CLK 	=> CLK,
				RSTN 	=> reset_n,

				LD		=> LD,
				UP_DN	=> UP_DN,

			CNTBY_LDINP	=> CNTBY_LDINP,
			LOAD_INP	=> LOAD_INP,


-- Output
   			CNTR_O	 	=> CNTR_O

         		);

--- Clock and Reset Generation 

 clk_proc : PROCESS
   			BEGIN
				IF(stop = '0')THEN
					clk <= '0';
    			    WAIT FOR clk_period/2;
					clk <= '1';
					WAIT FOR clk_period/2;
				ELSE
					clk <= '0';
				END IF;
			END PROCESS;

 stim_proc: PROCESS
			BEGIN
				reset_n <='0';
					WAIT FOR 20 ns;
				reset_n	<='1';
					WAIT;
			END PROCESS;


PROCESS
BEGIN
		WAIT UNTIL(reset_n ='1');
		WAIT UNTIL rising_edge(clk);
		LD			<= '1';
		LOAD_INP	<= X"00000000FEA";	
		WAIT UNTIL rising_edge(clk);
		WAIT FOR 100 ns;
		WAIT UNTIL rising_edge(clk);
		UP_DN		<= '1';
		WAIT FOR 500 ns;
		WAIT UNTIL rising_edge(clk);
		CNTBY_LDINP	<= '1';
		LOAD_INP	<= X"00000000123";	
		WAIT FOR 500 ns;
		WAIT UNTIL rising_edge(clk);
		stop <=  '1';
		
		report "TEST FINISHED!"
		severity failure;
		--wait;
END PROCESS;

end behavioral;

