@N|Running in 64-bit mode
@N: CD720 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Parallel FIR Filters\Transpose_Sym_FIR\hdl\Transpose_Sym_FIR.vhd":22:7:22:23|Top entity is set to Transpose_Sym_FIR.
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Parallel FIR Filters\Transpose_Sym_FIR\hdl\Transpose_Sym_FIR.vhd":22:7:22:23|Synthesizing work.transpose_sym_fir.transpose_fir_arch 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Parallel FIR Filters\Transpose_Sym_FIR\component\work\multadd\multadd.vhd":17:7:17:13|Synthesizing work.multadd.rtl 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Parallel FIR Filters\Transpose_Sym_FIR\component\work\multadd\multadd_0\multadd_multadd_0_HARD_MULT_ADDSUB.vhd":8:7:8:40|Synthesizing work.multadd_multadd_0_hard_mult_addsub.def_arch 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":575:10:575:12|Synthesizing smartfusion2.vcc.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":569:10:569:12|Synthesizing smartfusion2.gnd.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":695:10:695:13|Synthesizing smartfusion2.macc.syn_black_box 

