--------------------------------------------------------------------------------
-- Company:
--
-- File			: Adder_Sub_88bit.vhd
-- File history	: VER 1.0
--      
-- Description: 
--		This design illustrates the implementation of 88-bit addition using
--      two mathblocks.
--
--      88-bit input is fed to the two  Math blocks with 44-bit MSB to one math block and  
--		44-bit LSB to another mathblock.

-- 		Targeted device: <Family :: SmartFusion2>
--					   		<Die :: M2S050> 
--						<Package :: 896 FBGA>
-- Author	: PHANIKIRAN T
--------------------------------------------------------------------------------


LIBRARY IEEE;

USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;

ENTITY Adder_Sub_88bit IS
PORT (
    CLK 		: IN STD_LOGIC;
    RSTN 		: IN STD_LOGIC;

-- inputs
	INP_A 		: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
	INP_B 		: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
	INP_88b		: IN STD_LOGIC_VECTOR(87 DOWNTO 0);

	INP_D 		: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
	INP_E 		: IN STD_LOGIC_VECTOR(17 DOWNTO 0);

-- Output

   	RESULT	 	: OUT STD_LOGIC_VECTOR(87 DOWNTO 0)
	
	);
END Adder_Sub_88bit;


ARCHITECTURE  AdderSub88bit_Arch OF Adder_Sub_88bit IS

 -- COMPONENT DECLARATIONS

COMPONENT MultAdder IS
    -- Port list
    port(
        -- Inputs
        A0        : in  std_logic_vector(17 downto 0);
        A0_ACLR_N : in  std_logic;
        A0_EN     : in  std_logic;
        A0_SCLR_N : in  std_logic;
        B0        : in  std_logic_vector(17 downto 0);
        B0_ACLR_N : in  std_logic;
        B0_EN     : in  std_logic;
        B0_SCLR_N : in  std_logic;
        C         : in  std_logic_vector(43 downto 0);
        CLK       : in  std_logic;
        C_ACLR_N  : in  std_logic;
        C_EN      : in  std_logic;
        C_SCLR_N  : in  std_logic;
        P_ACLR_N  : in  std_logic;
        P_EN      : in  std_logic;
        P_SCLR_N  : in  std_logic;
        -- Outputs
        CARRYOUT  : out std_logic;
        CDOUT     : out std_logic_vector(43 downto 0);
        P         : out std_logic_vector(43 downto 0)
        );
END COMPONENT MultAdder;
  
COMPONENT MultAdder_w_Din is
    -- Port list
    port(
        -- Inputs
        A0        : in  std_logic_vector(17 downto 0);
        A0_ACLR_N : in  std_logic;
        A0_EN     : in  std_logic;
        A0_SCLR_N : in  std_logic;
        B0        : in  std_logic_vector(17 downto 0);
        B0_ACLR_N : in  std_logic;
        B0_EN     : in  std_logic;
        B0_SCLR_N : in  std_logic;
        C         : in  std_logic_vector(43 downto 0);
		CARRYIN   : in  std_logic;
        CLK       : in  std_logic;
        C_ACLR_N  : in  std_logic;
        C_EN      : in  std_logic;
        C_SCLR_N  : in  std_logic;
        P_ACLR_N  : in  std_logic;
        P_EN      : in  std_logic;
        P_SCLR_N  : in  std_logic;
        -- Outputs
        CDOUT     : out std_logic_vector(43 downto 0);
        P         : out std_logic_vector(43 downto 0)
        );
END COMPONENT MultAdder_w_Din;

 -- SIGNAL DECLARATIONS

SIGNAL A_in		: STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL B_in		: STD_LOGIC_VECTOR(17 DOWNTO 0);

SIGNAL D_in		: STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL E_in		: STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL C_in		: STD_LOGIC_VECTOR(87 DOWNTO 0);

SIGNAL RES1		: STD_LOGIC_VECTOR(43 DOWNTO 0);
SIGNAL RES2		: STD_LOGIC_VECTOR(43 DOWNTO 0);
SIGNAL CARRYIN	: STD_LOGIC;




BEGIN

PROCESS(CLK,RSTN)
BEGIN
IF(RSTN ='0')THEN
		A_in <= (OTHERS =>'0');
		B_in <= (OTHERS =>'0');
		C_in <= (OTHERS =>'0');
		D_in <= (OTHERS =>'0'); 
		E_in <= (OTHERS =>'0');	
ELSE
	IF(rising_edge(CLK))THEN
		A_in <= INP_A;
		B_in <= INP_B;
		C_in <= INP_88b;
		D_in <= INP_D; 
		E_in <= INP_E;	
	END IF;
END IF;

END PROCESS;



-- Port list
 U0 : MultAdder
		port map
		(
        A0        => A_in,
        A0_ACLR_N => RSTN,
        A0_EN     => '1',
        A0_SCLR_N => '1',
        B0        => B_in,
        B0_ACLR_N => RSTN,
        B0_EN     => '1',
        B0_SCLR_N => '1',
        C         => C_in(43 DOWNTO 0),
        CLK       => CLK,
        C_ACLR_N  => RSTN,
        C_EN      => '1',
        C_SCLR_N  => '1',
        P_ACLR_N  => RSTN,
        P_EN      => '1',
        P_SCLR_N  => '1',
        -- Outputs
        CARRYOUT  => CARRYIN,
        CDOUT     => OPEN,
        P         => RES1
        );



U1:MultAdder_w_Din
	port map(
        -- Inputs
    	A0        => D_in,
        A0_ACLR_N => RSTN,
        A0_EN     => '1',
        A0_SCLR_N => '1',
        B0        => E_in,
        B0_ACLR_N => RSTN,
        B0_EN     => '1',
        B0_SCLR_N => '1',
        C         => C_in(87 DOWNTO 44),
		CARRYIN	  => CARRYIN,
        CLK       => CLK,
        C_ACLR_N  => RSTN, 
        C_EN      => '1',
        C_SCLR_N  => '1',
        P_ACLR_N  => RSTN,
        P_EN      => '1',
        P_SCLR_N  => '1',
        -- Outputs
        CDOUT     => OPEN,
        P         => RES2
        );


RESULT <= RES2 & RES1;

END AdderSub88bit_Arch;
