--------------------------------------------------------------------------------
-- Company: MICROSEMI
--
-- File: Extended_adder_2_input.vhd
--
-- File history:
--      v1.0: 14-06-13: 
--
-- Description		: Implementation of 2-input extended addition
--
-- Targeted device	: Family	:: SmartFusion2  
-- 					  Die		:: M2S050T
--					  Package	:: 896 FBGA	
--			Author	: PHANIKIRAN T
--------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity Extended_adder_2_input is
port(	clk			: in std_logic;
		reset_n		: in std_logic;

		INPUTA		: in std_logic_vector(17 downto 0);
		INPUTB		: in std_logic_vector(17 downto 0);
		INPUTC		: in std_logic_vector(51 downto 0);

		AddOutput	: out std_logic_vector(51 downto 0)
		
         );
end Extended_adder_2_input;


architecture Extended_adder_2_input_arch of Extended_adder_2_input is


component dotp_multadd is
    -- Port list
    port(
        -- Inputs
        A0        : in  std_logic_vector(17 downto 0);
        A0_ACLR_N : in  std_logic;
        A0_EN     : in  std_logic;
        A0_SCLR_N : in  std_logic;
        B0        : in  std_logic_vector(17 downto 0);
        B0_ACLR_N : in  std_logic;
        B0_EN     : in  std_logic;
        B0_SCLR_N : in  std_logic;
        C         : in  std_logic_vector(43 downto 0);
        CLK       : in  std_logic;
        C_ACLR_N  : in  std_logic;
        C_EN      : in  std_logic;
        C_SCLR_N  : in  std_logic;
        P_ACLR_N  : in  std_logic;
        P_EN      : in  std_logic;
        P_SCLR_N  : in  std_logic;
        -- Outputs
     	CARRYOUT  : out std_logic;
        CDOUT     : out std_logic_vector(43 downto 0);
        P         : out std_logic_vector(43 downto 0)
        );
end component dotp_multadd;

  
signal S			: std_logic; 
signal U			: std_logic_vector(8 downto 0); 
signal CARRYOUT		: std_logic; 
signal P			: std_logic_vector(43 downto 0);
signal Result_Upper	: std_logic_vector(7 downto 0); 
signal C			: std_logic_vector(43 downto 0); 
signal B0			: std_logic_vector(17 downto 0); 
signal A0			: std_logic_vector(17 downto 0); 

begin



U0:dotp_multadd 
    -- Port list
    port map(
        -- Inputs
        A0        => INPUTA,
        A0_ACLR_N => '1',
        A0_EN     => '1',
        A0_SCLR_N => '1',
        B0        => INPUTB,
        B0_ACLR_N => '1',
        B0_EN     => '1',
        B0_SCLR_N => '1',
        C         =>  INPUTC(43 downto 0),
        CLK       => clk,
        C_ACLR_N  => '1',
        C_EN      => '1',
        C_SCLR_N  => '1',
        P_ACLR_N  => '1',
        P_EN      => '1',
        P_SCLR_N  => '1',
        -- Outputs
        CARRYOUT  => CARRYOUT,
		CDOUT     => OPEN,
        P         => P 
        );
 		

 		
	process(clk, reset_n)
	begin
		if (reset_n = '0') then
			AddOutput	<= (others => '0');  
		else
			if(rising_edge(clk))then
					AddOutput(51 downto 44)	<= Result_Upper + INPUTC(51 downto 44);
					AddOutput(43 downto 0)  <= P;
			 end if;	
		end if;
	end process;	

S <= P(43) AND CARRYOUT;


Result_Upper(7 downto 1) <= (OTHERS => S);
Result_Upper(0)<= CARRYOUT;



end Extended_adder_2_input_arch;
