Project Settings
Project Name | BarrelShifter_18bit_syn | Implementation Name | synthesis
Top Module | work.BarrelShifter_18bit | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
Compile Input | Complete | 12 | 1 | 0 | - | 0m:00s | - | 5/21/2014 4:57:02 PM
Pre-mapping | Complete | 3 | 1 | 0 | 0m:00s | 0m:00s | 133MB | 5/21/2014 4:57:03 PM
Map & Optimize | Complete | 11 | 1 | 0 | 0m:00s | 0m:01s | 133MB | 5/21/2014 4:57:05 PM
Area Summary
Sequential Cells | 18 | DSP Blocks (MACC) (dsp_used) | 2
I/O Cells | 38 | Global Clock Buffers | 2
LUTs (total_luts) | 0 |  |
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
BarrelShifter_18bit|CLK | 1.0 MHz | 938.4 MHz | 998.934
System | 1211.1 MHz | 1029.4 MHz | -0.146
Optimizations Summary
Combined Clock Conversion | 1 / 0 |  |