--------------------------------------------------------------------------------
-- Company: 
--
-- File: ASLL_ASRL.vhd
-- File history: 
--      Ver1.0: 
--
-- Description: 
--
-- This design illustrates implemenataion of Arithmetic Shift left logic/Shift right logic 
-- using Single Mathblock
--		
-- Targeted device:  Family	:: SmartFusion2
--						Die	:: M2S050 
--					 Package:: 896 FBGA
--
--------------------------------------------------------------------------------

LIBRARY IEEE;

USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_signed.all;
USE IEEE.std_logic_arith.all;

ENTITY ASLL_ASRL IS
PORT (
    CLK 		: IN STD_LOGIC;
    RSTN 		: IN STD_LOGIC;
	SHIFT_INP	: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
   	ASLL_OP	 	: OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
	ASRL_OP	 	: OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
	);
END ASLL_ASRL;


ARCHITECTURE ASLL_ASHL_ARCH OF ASLL_ASRL IS

-- COMPONENT DECLARATIONS;

	COMPONENT Mult18x18 IS
    	-- Port list
    PORT(
        -- Inputs
        B0        : IN  STD_LOGIC_VECTOR(17 DOWNTO 0);
        B0_ACLR_N : IN  STD_LOGIC;
        B0_EN     : IN  STD_LOGIC;
        B0_SCLR_N : IN  STD_LOGIC;
        CLK       : IN  STD_LOGIC;
        P_ACLR_N  : IN  STD_LOGIC;
        P_EN      : IN  STD_LOGIC;
        P_SCLR_N  : IN  STD_LOGIC;
        -- Outputs
        CDOUT     : OUT std_logic_vector(43 DOWNTO 0);
        P         : OUT STD_LOGIC_VECTOR(35 DOWNTO 0)
        );
	END COMPONENT Mult18x18;


-- SIGNAL DECLARATIONS;

SIGNAL SHIFT_VAL	: STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL SHIFT_OP		: STD_LOGIC_VECTOR(35 DOWNTO 0);



BEGIN




U0 : Mult18x18
PORT MAP(
        -- Inputs
        B0        => SHIFT_VAL,
        B0_ACLR_N => RSTN,
        B0_EN     => '1',
        B0_SCLR_N => '1',
        CLK       => CLK,
        P_ACLR_N  => RSTN,
        P_EN      => '1',
        P_SCLR_N  => '1',
        -- Outputs
        CDOUT     => OPEN,
        P         => SHIFT_OP
		);


PROCESS(CLK,RSTN)
BEGIN
	IF(RSTN ='0')THEN
		SHIFT_VAL <= (OTHERS => '0');
	ELSE
		IF(rising_edge(CLK))THEN
			SHIFT_VAL <= (SHIFT_INP(16) & SHIFT_INP(16 DOWNTO 0));
		END IF;
	END IF;
END PROCESS;

ASLL_OP <= SHIFT_OP(17 DOWNTO 0);
ASRL_OP <= SHIFT_OP(35 DOWNTO 18);

END ASLL_ASHL_ARCH;
