@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: MT206 |Auto Constrain mode is enabled
@N: FF150 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\wide multiplier\mult32x32_multipliemacc\hdl\mult32x32_multiplemacc.vhd":72:15:72:33|Multiplier reg1_2[63:0] implemented with multiple MACC blocks using cascade/shift feature.
@N: FX271 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\wide multiplier\mult32x32_multipliemacc\hdl\mult32x32_multiplemacc.vhd":72:15:72:33|Instance "inp_reg0[31]" with 5 loads replicated 1 times to improve timing 
@N: FP130 |Promoting Net clk_c on CLKINT  I_1 
@N: FP130 |Promoting Net reset_n_c on CLKINT  I_2 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
