`

    #Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014
    #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1
    #OS: Windows 7 6.1
    #Hostname: W764-TADIGADAPA

    #Implementation: synthesis

    $ Start of Compile
    #Wed May 21 18:23:19 2014

    Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

    @N:CD720 : std.vhd(146) | Setting time resolution to ns
    @N: : Extended_adder_2_input.vhd(23) | Top entity is set to Extended_adder_2_input.
    VHDL syntax check successful!
    @N:CD231 : std1164.vhd(913) | Using onehot encoding for type mvl9plus ('U'="1000000000")
    @N:CD630 : Extended_adder_2_input.vhd(23) | Synthesizing work.extended_adder_2_input.extended_adder_2_input_arch
    @W:CD638 : Extended_adder_2_input.vhd(69) | Signal u is undriven
    @W:CD638 : Extended_adder_2_input.vhd(73) | Signal c is undriven
    @W:CD638 : Extended_adder_2_input.vhd(74) | Signal b0 is undriven
    @W:CD638 : Extended_adder_2_input.vhd(75) | Signal a0 is undriven
    @N:CD630 : dotp_multadd.vhd(17) | Synthesizing work.dotp_multadd.rtl
    @N:CD630 : dotp_multadd_dotp_multadd_0_HARD_MULT_ADDSUB.vhd(8) | Synthesizing work.dotp_multadd_dotp_multadd_0_hard_mult_addsub.def_arch
    @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box
    Post processing for smartfusion2.vcc.syn_black_box
    @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box
    Post processing for smartfusion2.gnd.syn_black_box
    @N:CD630 : smartfusion2.vhd(695) | Synthesizing smartfusion2.macc.syn_black_box
    Post processing for smartfusion2.macc.syn_black_box
    Post processing for work.dotp_multadd_dotp_multadd_0_hard_mult_addsub.def_arch
    Post processing for work.dotp_multadd.rtl
    Post processing for work.extended_adder_2_input.extended_adder_2_input_arch
    @END

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 18:23:20 2014

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Linked File: DSP
    Printing clock  summary report in "D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_2_input\synthesis\Extended_adder_2_input_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    syn_allowed_resources : blockrams=69  set on top level netlist Extended_adder_2_input

    Clock Summary
    **************

    Start                          Requested     Requested     Clock        Clock
    Clock                          Frequency     Period        Type         Group
    -------------------------------------------------------------------------------------------
    Extended_adder_2_input|clk     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
    System                         1.0 MHz       1000.000      system       system_clkgroup
    ===========================================================================================

    @W:MT530 : dotp_multadd_dotp_multadd_0_hard_mult_addsub.vhd(113) | Found inferred clock Extended_adder_2_input|clk which controls 52 sequential elements including U0.dotp_multadd_0.U0. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_2_input\synthesis\Extended_adder_2_input.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 133MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 18:23:21 2014

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Available hyper_sources - for debug and ip models
    	None Found

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		    -0.96ns		   9 /        52
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		    -0.96ns		   9 /        52
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		    -0.96ns		   9 /        52
    ------------------------------------------------------------

    @N:FP130 :  | Promoting Net reset_n_c on CLKINT  I_3
    @N:FP130 :  | Promoting Net clk_c on CLKINT  I_4

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    1 non-gated/non-generated clock tree(s) driving 54 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId0001        clk                 port                   54         AddOutput[0]
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Writing Analyst data base D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_2_input\synthesis\Extended_adder_2_input.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    I-2013.09M-SP1

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    @W:MT420 :  | Found inferred clock Extended_adder_2_input|clk with period 10.00ns. Please declare a user-defined clock on object "p:clk"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed May 21 18:23:23 2014
    #

    Top view:               Extended_adder_2_input
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: 6.865

                                   Requested     Estimated     Requested     Estimated               Clock        Clock
    Starting Clock                 Frequency     Frequency     Period        Period        Slack     Type         Group
    ---------------------------------------------------------------------------------------------------------------------------------
    Extended_adder_2_input|clk     100.0 MHz     NA            10.000        NA            NA        inferred     Inferred_clkgroup_0
    System                         100.0 MHz     319.0 MHz     10.000        3.135         6.865     system       system_clkgroup
    =================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ----------------------------------------------------------------------------------------------------------------------------
    Starting  Ending                      |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    ----------------------------------------------------------------------------------------------------------------------------
    System    Extended_adder_2_input|clk  |  10.000      6.865  |  No paths    -      |  No paths    -      |  No paths    -
    ============================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                             Starting                                              Arrival
    Instance                 Reference     Type     Pin               Net          Time        Slack
                             Clock
    ------------------------------------------------------------------------------------------------
    U0.dotp_multadd_0.U0     System        MACC     P[43]             P[43]        0.000       6.865
    U0.dotp_multadd_0.U0     System        MACC     P[43]             P[43]        0.000       6.865
    U0.dotp_multadd_0.U0     System        MACC     OVFL_CARRYOUT     CARRYOUT     0.000       7.138
    U0.dotp_multadd_0.U0     System        MACC     OVFL_CARRYOUT     CARRYOUT     0.000       7.138
    U0.dotp_multadd_0.U0     System        MACC     P[0]              P[0]         0.000       8.628
    U0.dotp_multadd_0.U0     System        MACC     P[0]              P[0]         0.000       8.628
    U0.dotp_multadd_0.U0     System        MACC     P[1]              P[1]         0.000       8.628
    U0.dotp_multadd_0.U0     System        MACC     P[1]              P[1]         0.000       8.628
    U0.dotp_multadd_0.U0     System        MACC     P[2]              P[2]         0.000       8.628
    U0.dotp_multadd_0.U0     System        MACC     P[2]              P[2]         0.000       8.628
    ================================================================================================

    Ending Points with Worst Slack
    ******************************

                      Starting                                                   Required
    Instance          Reference     Type     Pin     Net                         Time         Slack
                      Clock
    -----------------------------------------------------------------------------------------------
    AddOutput[51]     System        SLE      D       un6_addoutput_s_7_S         9.745        6.865
    AddOutput[50]     System        SLE      D       un6_addoutput_cry_6_0_S     9.745        7.111
    AddOutput[45]     System        SLE      D       un6_addoutput_cry_1_0_S     9.745        7.124
    AddOutput[46]     System        SLE      D       un6_addoutput_cry_2_0_S     9.745        7.124
    AddOutput[47]     System        SLE      D       un6_addoutput_cry_3_0_S     9.745        7.124
    AddOutput[48]     System        SLE      D       un6_addoutput_cry_4_0_S     9.745        7.124
    AddOutput[49]     System        SLE      D       un6_addoutput_cry_5_0_S     9.745        7.124
    AddOutput[44]     System        SLE      D       un6_addoutput_cry_0_Y       9.745        7.390
    AddOutput[43]     System        SLE      D       P[43]                       9.745        8.610
    AddOutput[0]      System        SLE      D       P[0]                        9.745        8.628
    ===============================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.255
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.745

        - Propagation time:                      2.879
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     6.865

        Number of logic level(s):                1
        Starting point:                          U0.dotp_multadd_0.U0 / P[43]
        Ending point:                            AddOutput[51] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Extended_adder_2_input|clk [rising] on pin CLK

    Instance / Net                    Pin       Pin               Arrival     No. of
    Name                     Type     Name      Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------
    U0.dotp_multadd_0.U0     MACC     P[43]     Out     0.000     0.000       -
    P[43]                    Net      -         -       1.135     -           8
    un6_addoutput_s_7        ARI1     D         In      -         1.135       -
    un6_addoutput_s_7        ARI1     S         Out     0.627     1.762       -
    un6_addoutput_s_7_S      Net      -         -       1.117     -           1
    AddOutput[51]            SLE      D         In      -         2.879       -
    ====================================================================================
    Total path delay (propagation time + setup) of 3.135 is 0.883(28.2%) logic and 2.252(71.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    ---------------------------------------
    Resource Usage Report for Extended_adder_2_input

    Mapping to part: m2s050tfbga896std
    Cell usage:
    CLKINT          2 uses

    Carry primitives used for arithmetic functions:
    ARI1           8 uses

    Sequential Cells:
    SLE            52 uses

    DSP Blocks:    1
     MACC:         1 Mult

    I/O ports: 142
    I/O primitives: 142
    INBUF          90 uses
    OUTBUF         52 uses

    Global Clock Buffers: 2

    Total LUTs:    8

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 133MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 18:23:23 2014

    ###########################################################]

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