----------------------------------------------------------------------
-- Created by SmartDesign Thu Apr 18 14:55:39 2013
-- Version: v11.0 11.0.0.23
----------------------------------------------------------------------

----------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

library SmartFusion2;
use SmartFusion2.all;
----------------------------------------------------------------------
-- top entity declaration
----------------------------------------------------------------------
entity top is
    -- Port list
    port(
        -- Inputs
        A             : in  std_logic_vector(17 downto 0);
        ARSHFT17      : in  std_logic;
        A_ARST_N      : in  std_logic_vector(1 downto 0);
        B             : in  std_logic_vector(17 downto 0);
        B_ARST_N      : in  std_logic_vector(1 downto 0);
        C             : in  std_logic_vector(43 downto 0);
        CDIN          : in  std_logic_vector(43 downto 0);
        CDSEL         : in  std_logic;
        CLK           : in  std_logic_vector(1 downto 0);
        C_ARST_N      : in  std_logic_vector(1 downto 0);
        C_EN          : in  std_logic_vector(1 downto 0);
        FDBKSEL       : in  std_logic;
        P_ARST_N      : in  std_logic_vector(1 downto 0);
        -- Outputs
        OVFL_CARRYOUT : out std_logic;
        P             : out std_logic_vector(43 downto 0)
        );
end top;
----------------------------------------------------------------------
-- top architecture body
----------------------------------------------------------------------
architecture RTL of top is
----------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------
-- MACC
component MACC
    -- Port list
    port(
        -- Inputs
        A                 : in  std_logic_vector(17 downto 0);
        ARSHFT17          : in  std_logic;
        ARSHFT17_AD       : in  std_logic;
        ARSHFT17_AL_N     : in  std_logic;
        ARSHFT17_BYPASS   : in  std_logic;
        ARSHFT17_EN       : in  std_logic;
        ARSHFT17_SD_N     : in  std_logic;
        ARSHFT17_SL_N     : in  std_logic;
        A_ARST_N          : in  std_logic_vector(1 downto 0);
        A_BYPASS          : in  std_logic_vector(1 downto 0);
        A_EN              : in  std_logic_vector(1 downto 0);
        A_SRST_N          : in  std_logic_vector(1 downto 0);
        B                 : in  std_logic_vector(17 downto 0);
        B_ARST_N          : in  std_logic_vector(1 downto 0);
        B_BYPASS          : in  std_logic_vector(1 downto 0);
        B_EN              : in  std_logic_vector(1 downto 0);
        B_SRST_N          : in  std_logic_vector(1 downto 0);
        C                 : in  std_logic_vector(43 downto 0);
        CARRYIN           : in  std_logic;
        CDIN              : in  std_logic_vector(43 downto 0);
        CDSEL             : in  std_logic;
        CDSEL_AD          : in  std_logic;
        CDSEL_AL_N        : in  std_logic;
        CDSEL_BYPASS      : in  std_logic;
        CDSEL_EN          : in  std_logic;
        CDSEL_SD_N        : in  std_logic;
        CDSEL_SL_N        : in  std_logic;
        CLK               : in  std_logic_vector(1 downto 0);
        C_ARST_N          : in  std_logic_vector(1 downto 0);
        C_BYPASS          : in  std_logic_vector(1 downto 0);
        C_EN              : in  std_logic_vector(1 downto 0);
        C_SRST_N          : in  std_logic_vector(1 downto 0);
        DOTP              : in  std_logic;
        FDBKSEL           : in  std_logic;
        FDBKSEL_AD        : in  std_logic;
        FDBKSEL_AL_N      : in  std_logic;
        FDBKSEL_BYPASS    : in  std_logic;
        FDBKSEL_EN        : in  std_logic;
        FDBKSEL_SD_N      : in  std_logic;
        FDBKSEL_SL_N      : in  std_logic;
        OVFL_CARRYOUT_SEL : in  std_logic;
        P_ARST_N          : in  std_logic_vector(1 downto 0);
        P_BYPASS          : in  std_logic_vector(1 downto 0);
        P_EN              : in  std_logic_vector(1 downto 0);
        P_SRST_N          : in  std_logic_vector(1 downto 0);
        SIMD              : in  std_logic;
        SUB               : in  std_logic;
        SUB_AD            : in  std_logic;
        SUB_AL_N          : in  std_logic;
        SUB_BYPASS        : in  std_logic;
        SUB_EN            : in  std_logic;
        SUB_SD_N          : in  std_logic;
        SUB_SL_N          : in  std_logic;
        -- Outputs
        CDOUT             : out std_logic_vector(43 downto 0);
        OVFL_CARRYOUT     : out std_logic;
        P                 : out std_logic_vector(43 downto 0)
        );
end component;
----------------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------------
signal OVFL_CARRYOUT_net_0 : std_logic;
signal P_net_0             : std_logic_vector(43 downto 0);
signal OVFL_CARRYOUT_net_1 : std_logic;
signal P_net_1             : std_logic_vector(43 downto 0);
----------------------------------------------------------------------
-- TiedOff Signals
----------------------------------------------------------------------
signal VCC_net             : std_logic;
signal GND_net             : std_logic;
signal A_EN_const_net_0    : std_logic_vector(1 downto 0);
signal A_SRST_N_const_net_0: std_logic_vector(1 downto 0);
signal B_EN_const_net_0    : std_logic_vector(1 downto 0);
signal B_SRST_N_const_net_0: std_logic_vector(1 downto 0);
signal C_SRST_N_const_net_0: std_logic_vector(1 downto 0);
signal P_EN_const_net_0    : std_logic_vector(1 downto 0);
signal P_SRST_N_const_net_0: std_logic_vector(1 downto 0);
signal A_BYPASS_const_net_0: std_logic_vector(1 downto 0);
signal B_BYPASS_const_net_0: std_logic_vector(1 downto 0);
signal C_BYPASS_const_net_0: std_logic_vector(1 downto 0);
signal P_BYPASS_const_net_0: std_logic_vector(1 downto 0);

begin
----------------------------------------------------------------------
-- Constant assignments
----------------------------------------------------------------------
 VCC_net              <= '1';
 GND_net              <= '0';
 A_EN_const_net_0     <= B"11";
 A_SRST_N_const_net_0 <= B"11";
 B_EN_const_net_0     <= B"11";
 B_SRST_N_const_net_0 <= B"11";
 C_SRST_N_const_net_0 <= B"11";
 P_EN_const_net_0     <= B"11";
 P_SRST_N_const_net_0 <= B"11";
 A_BYPASS_const_net_0 <= B"00";
 B_BYPASS_const_net_0 <= B"00";
 C_BYPASS_const_net_0 <= B"00";
 P_BYPASS_const_net_0 <= B"00";
----------------------------------------------------------------------
-- Top level output port assignments
----------------------------------------------------------------------
 OVFL_CARRYOUT_net_1 <= OVFL_CARRYOUT_net_0;
 OVFL_CARRYOUT       <= OVFL_CARRYOUT_net_1;
 P_net_1             <= P_net_0;
 P(43 downto 0)      <= P_net_1;
----------------------------------------------------------------------
-- Component instances
----------------------------------------------------------------------
-- MACC_0
MACC_0 : MACC
    port map( 
        -- Inputs
        FDBKSEL           => FDBKSEL,
        FDBKSEL_EN        => VCC_net,
        FDBKSEL_AL_N      => VCC_net,
        FDBKSEL_SL_N      => VCC_net,
        CDSEL             => CDSEL,
        CDSEL_EN          => VCC_net,
        CDSEL_AL_N        => VCC_net,
        CDSEL_SL_N        => VCC_net,
        ARSHFT17          => ARSHFT17,
        ARSHFT17_EN       => VCC_net,
        ARSHFT17_AL_N     => VCC_net,
        ARSHFT17_SL_N     => VCC_net,
        SUB               => GND_net,
        SUB_EN            => VCC_net,
        SUB_AL_N          => VCC_net,
        SUB_SL_N          => VCC_net,
        CARRYIN           => GND_net,
        SIMD              => GND_net,
        DOTP              => GND_net,
        OVFL_CARRYOUT_SEL => GND_net,
        FDBKSEL_BYPASS    => GND_net,
        FDBKSEL_AD        => GND_net,
        FDBKSEL_SD_N      => VCC_net,
        CDSEL_BYPASS      => GND_net,
        CDSEL_AD          => GND_net,
        CDSEL_SD_N        => GND_net,
        ARSHFT17_BYPASS   => GND_net,
        ARSHFT17_AD       => GND_net,
        ARSHFT17_SD_N     => VCC_net,
        SUB_BYPASS        => GND_net,
        SUB_AD            => GND_net,
        SUB_SD_N          => VCC_net,
        CLK               => CLK,
        A                 => A,
        A_EN              => A_EN_const_net_0,
        A_ARST_N          => A_ARST_N,
        A_SRST_N          => A_SRST_N_const_net_0,
        B                 => B,
        B_EN              => B_EN_const_net_0,
        B_ARST_N          => B_ARST_N,
        B_SRST_N          => B_SRST_N_const_net_0,
        C                 => C,
        C_EN              => C_EN,
        C_ARST_N          => C_ARST_N,
        C_SRST_N          => C_SRST_N_const_net_0,
        P_EN              => P_EN_const_net_0,
        P_ARST_N          => P_ARST_N,
        P_SRST_N          => P_SRST_N_const_net_0,
        A_BYPASS          => A_BYPASS_const_net_0,
        B_BYPASS          => B_BYPASS_const_net_0,
        C_BYPASS          => C_BYPASS_const_net_0,
        P_BYPASS          => P_BYPASS_const_net_0,
        CDIN              => CDIN,
        -- Outputs
        OVFL_CARRYOUT     => OVFL_CARRYOUT_net_0,
        CDOUT             => OPEN,
        P                 => P_net_0 
        );

end RTL;
