-- Version: v11.1 SP3 11.1.3.1

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Inp_RAM1_Inp_RAM1_0_URAM is

    port( un1_inpA_rddata2_10                     : out   std_logic_vector(16 downto 1);
          inpA_rddata2                            : inout std_logic_vector(17 downto 0) := (others => 'Z');
          inpB_rddata2                            : inout std_logic_vector(17 downto 0) := (others => 'Z');
          InpA_rdaddr1                            : in    std_logic_vector(5 downto 0);
          InpB_rdaddr1                            : in    std_logic_vector(5 downto 0);
          inp_wraddr2                             : in    std_logic_vector(5 downto 0);
          inp_wrdata_dly0                         : in    std_logic_vector(17 downto 0);
          Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS_Y : out   std_logic;
          un1_inpA_rddata2_cry_16                 : out   std_logic;
          clk_c                                   : in    std_logic;
          InpA_rden1                              : in    std_logic;
          InpB_rden1                              : in    std_logic;
          InpCoef1_wren                           : in    std_logic
        );

end Inp_RAM1_Inp_RAM1_0_URAM;

architecture DEF_ARCH of Inp_RAM1_Inp_RAM1_0_URAM is 

  component ARI1
    generic (INIT:std_logic_vector := x"0");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component RAM64x18
    generic (MEMORYFILE:string := "");

    port( A_DOUT        : out   std_logic_vector(17 downto 0);
          B_DOUT        : out   std_logic_vector(17 downto 0);
          BUSY          : out   std_logic;
          A_ADDR_CLK    : in    std_logic := 'U';
          A_DOUT_CLK    : in    std_logic := 'U';
          A_ADDR_SRST_N : in    std_logic := 'U';
          A_DOUT_SRST_N : in    std_logic := 'U';
          A_ADDR_ARST_N : in    std_logic := 'U';
          A_DOUT_ARST_N : in    std_logic := 'U';
          A_ADDR_EN     : in    std_logic := 'U';
          A_DOUT_EN     : in    std_logic := 'U';
          A_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          B_ADDR_CLK    : in    std_logic := 'U';
          B_DOUT_CLK    : in    std_logic := 'U';
          B_ADDR_SRST_N : in    std_logic := 'U';
          B_DOUT_SRST_N : in    std_logic := 'U';
          B_ADDR_ARST_N : in    std_logic := 'U';
          B_DOUT_ARST_N : in    std_logic := 'U';
          B_ADDR_EN     : in    std_logic := 'U';
          B_DOUT_EN     : in    std_logic := 'U';
          B_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          C_CLK         : in    std_logic := 'U';
          C_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          C_DIN         : in    std_logic_vector(17 downto 0) := (others => 'U');
          C_WEN         : in    std_logic := 'U';
          C_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_EN          : in    std_logic := 'U';
          A_ADDR_LAT    : in    std_logic := 'U';
          A_DOUT_LAT    : in    std_logic := 'U';
          A_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          B_EN          : in    std_logic := 'U';
          B_ADDR_LAT    : in    std_logic := 'U';
          B_DOUT_LAT    : in    std_logic := 'U';
          B_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          C_EN          : in    std_logic := 'U';
          C_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          SII_LOCK      : in    std_logic := 'U'
        );
  end component;

    signal un1_inpA_rddata2_cry_0, GND_net_1, 
        un1_inpA_rddata2_cry_1, un1_inpA_rddata2_cry_2, 
        un1_inpA_rddata2_cry_3, un1_inpA_rddata2_cry_4, 
        un1_inpA_rddata2_cry_5, un1_inpA_rddata2_cry_6, 
        un1_inpA_rddata2_cry_7, un1_inpA_rddata2_cry_8, 
        un1_inpA_rddata2_cry_9, un1_inpA_rddata2_cry_10, 
        un1_inpA_rddata2_cry_11, un1_inpA_rddata2_cry_12, 
        un1_inpA_rddata2_cry_13, un1_inpA_rddata2_cry_14, 
        un1_inpA_rddata2_cry_15, VCC_net_1 : std_logic;

begin 


    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI0T1CE : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(15), B => inpB_rddata2(15), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_cry_14, S => un1_inpA_rddata2_10(15), Y
         => OPEN, FCO => un1_inpA_rddata2_cry_15);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIK7GP1 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(1), B => inpB_rddata2(1), C => 
        GND_net_1, D => GND_net_1, FCI => un1_inpA_rddata2_cry_0, 
        S => un1_inpA_rddata2_10(1), Y => OPEN, FCO => 
        un1_inpA_rddata2_cry_1);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIEB8M2 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(2), B => inpB_rddata2(2), C => 
        GND_net_1, D => GND_net_1, FCI => un1_inpA_rddata2_cry_1, 
        S => un1_inpA_rddata2_10(2), Y => OPEN, FCO => 
        un1_inpA_rddata2_cry_2);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIIHPLB : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(12), B => inpB_rddata2(12), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_cry_11, S => un1_inpA_rddata2_10(12), Y
         => OPEN, FCO => un1_inpA_rddata2_cry_12);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI2JOF4 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(4), B => inpB_rddata2(4), C => 
        GND_net_1, D => GND_net_1, FCI => un1_inpA_rddata2_cry_3, 
        S => un1_inpA_rddata2_10(4), Y => OPEN, FCO => 
        un1_inpA_rddata2_cry_4);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIA2P28 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(8), B => inpB_rddata2(8), C => 
        GND_net_1, D => GND_net_1, FCI => un1_inpA_rddata2_cry_7, 
        S => un1_inpA_rddata2_10(8), Y => OPEN, FCO => 
        un1_inpA_rddata2_cry_8);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ0Q8F : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(16), B => inpB_rddata2(16), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_cry_15, S => un1_inpA_rddata2_10(16), Y
         => OPEN, FCO => un1_inpA_rddata2_cry_16);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNISMGC5 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(5), B => inpB_rddata2(5), C => 
        GND_net_1, D => GND_net_1, FCI => un1_inpA_rddata2_cry_4, 
        S => un1_inpA_rddata2_10(5), Y => OPEN, FCO => 
        un1_inpA_rddata2_cry_5);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI8F0J3 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(3), B => inpB_rddata2(3), C => 
        GND_net_1, D => GND_net_1, FCI => un1_inpA_rddata2_cry_2, 
        S => un1_inpA_rddata2_10(3), Y => OPEN, FCO => 
        un1_inpA_rddata2_cry_3);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI46HV8 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(9), B => inpB_rddata2(9), C => 
        GND_net_1, D => GND_net_1, FCI => un1_inpA_rddata2_cry_8, 
        S => un1_inpA_rddata2_10(9), Y => OPEN, FCO => 
        un1_inpA_rddata2_cry_9);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIU99S9 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(10), B => inpB_rddata2(10), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_cry_9, S => un1_inpA_rddata2_10(10), Y
         => OPEN, FCO => un1_inpA_rddata2_cry_10);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIOD1PA : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(11), B => inpB_rddata2(11), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_cry_10, S => un1_inpA_rddata2_10(11), Y
         => OPEN, FCO => un1_inpA_rddata2_cry_11);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNI6P9FD : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(14), B => inpB_rddata2(14), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_cry_13, S => un1_inpA_rddata2_10(14), Y
         => OPEN, FCO => un1_inpA_rddata2_cry_14);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIMQ896 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(6), B => inpB_rddata2(6), C => 
        GND_net_1, D => GND_net_1, FCI => un1_inpA_rddata2_cry_5, 
        S => un1_inpA_rddata2_10(6), Y => OPEN, FCO => 
        un1_inpA_rddata2_cry_6);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0 : RAM64x18

              generic map(MEMORYFILE => "Inp_RAM1_Inp_RAM1_0_URAM_R0C0.mem"
        )

      port map(A_DOUT(17) => inpA_rddata2(17), A_DOUT(16) => 
        inpA_rddata2(16), A_DOUT(15) => inpA_rddata2(15), 
        A_DOUT(14) => inpA_rddata2(14), A_DOUT(13) => 
        inpA_rddata2(13), A_DOUT(12) => inpA_rddata2(12), 
        A_DOUT(11) => inpA_rddata2(11), A_DOUT(10) => 
        inpA_rddata2(10), A_DOUT(9) => inpA_rddata2(9), A_DOUT(8)
         => inpA_rddata2(8), A_DOUT(7) => inpA_rddata2(7), 
        A_DOUT(6) => inpA_rddata2(6), A_DOUT(5) => 
        inpA_rddata2(5), A_DOUT(4) => inpA_rddata2(4), A_DOUT(3)
         => inpA_rddata2(3), A_DOUT(2) => inpA_rddata2(2), 
        A_DOUT(1) => inpA_rddata2(1), A_DOUT(0) => 
        inpA_rddata2(0), B_DOUT(17) => inpB_rddata2(17), 
        B_DOUT(16) => inpB_rddata2(16), B_DOUT(15) => 
        inpB_rddata2(15), B_DOUT(14) => inpB_rddata2(14), 
        B_DOUT(13) => inpB_rddata2(13), B_DOUT(12) => 
        inpB_rddata2(12), B_DOUT(11) => inpB_rddata2(11), 
        B_DOUT(10) => inpB_rddata2(10), B_DOUT(9) => 
        inpB_rddata2(9), B_DOUT(8) => inpB_rddata2(8), B_DOUT(7)
         => inpB_rddata2(7), B_DOUT(6) => inpB_rddata2(6), 
        B_DOUT(5) => inpB_rddata2(5), B_DOUT(4) => 
        inpB_rddata2(4), B_DOUT(3) => inpB_rddata2(3), B_DOUT(2)
         => inpB_rddata2(2), B_DOUT(1) => inpB_rddata2(1), 
        B_DOUT(0) => inpB_rddata2(0), BUSY => OPEN, A_ADDR_CLK
         => VCC_net_1, A_DOUT_CLK => clk_c, A_ADDR_SRST_N => 
        VCC_net_1, A_DOUT_SRST_N => VCC_net_1, A_ADDR_ARST_N => 
        VCC_net_1, A_DOUT_ARST_N => VCC_net_1, A_ADDR_EN => 
        VCC_net_1, A_DOUT_EN => VCC_net_1, A_BLK(1) => InpA_rden1, 
        A_BLK(0) => VCC_net_1, A_ADDR(9) => InpA_rdaddr1(5), 
        A_ADDR(8) => InpA_rdaddr1(4), A_ADDR(7) => 
        InpA_rdaddr1(3), A_ADDR(6) => InpA_rdaddr1(2), A_ADDR(5)
         => InpA_rdaddr1(1), A_ADDR(4) => InpA_rdaddr1(0), 
        A_ADDR(3) => GND_net_1, A_ADDR(2) => GND_net_1, A_ADDR(1)
         => GND_net_1, A_ADDR(0) => GND_net_1, B_ADDR_CLK => 
        VCC_net_1, B_DOUT_CLK => clk_c, B_ADDR_SRST_N => 
        VCC_net_1, B_DOUT_SRST_N => VCC_net_1, B_ADDR_ARST_N => 
        VCC_net_1, B_DOUT_ARST_N => VCC_net_1, B_ADDR_EN => 
        VCC_net_1, B_DOUT_EN => VCC_net_1, B_BLK(1) => InpB_rden1, 
        B_BLK(0) => VCC_net_1, B_ADDR(9) => InpB_rdaddr1(5), 
        B_ADDR(8) => InpB_rdaddr1(4), B_ADDR(7) => 
        InpB_rdaddr1(3), B_ADDR(6) => InpB_rdaddr1(2), B_ADDR(5)
         => InpB_rdaddr1(1), B_ADDR(4) => InpB_rdaddr1(0), 
        B_ADDR(3) => GND_net_1, B_ADDR(2) => GND_net_1, B_ADDR(1)
         => GND_net_1, B_ADDR(0) => GND_net_1, C_CLK => clk_c, 
        C_ADDR(9) => inp_wraddr2(5), C_ADDR(8) => inp_wraddr2(4), 
        C_ADDR(7) => inp_wraddr2(3), C_ADDR(6) => inp_wraddr2(2), 
        C_ADDR(5) => inp_wraddr2(1), C_ADDR(4) => inp_wraddr2(0), 
        C_ADDR(3) => GND_net_1, C_ADDR(2) => GND_net_1, C_ADDR(1)
         => GND_net_1, C_ADDR(0) => GND_net_1, C_DIN(17) => 
        inp_wrdata_dly0(17), C_DIN(16) => inp_wrdata_dly0(16), 
        C_DIN(15) => inp_wrdata_dly0(15), C_DIN(14) => 
        inp_wrdata_dly0(14), C_DIN(13) => inp_wrdata_dly0(13), 
        C_DIN(12) => inp_wrdata_dly0(12), C_DIN(11) => 
        inp_wrdata_dly0(11), C_DIN(10) => inp_wrdata_dly0(10), 
        C_DIN(9) => inp_wrdata_dly0(9), C_DIN(8) => 
        inp_wrdata_dly0(8), C_DIN(7) => inp_wrdata_dly0(7), 
        C_DIN(6) => inp_wrdata_dly0(6), C_DIN(5) => 
        inp_wrdata_dly0(5), C_DIN(4) => inp_wrdata_dly0(4), 
        C_DIN(3) => inp_wrdata_dly0(3), C_DIN(2) => 
        inp_wrdata_dly0(2), C_DIN(1) => inp_wrdata_dly0(1), 
        C_DIN(0) => inp_wrdata_dly0(0), C_WEN => VCC_net_1, 
        C_BLK(1) => InpCoef1_wren, C_BLK(0) => VCC_net_1, A_EN
         => VCC_net_1, A_ADDR_LAT => VCC_net_1, A_DOUT_LAT => 
        GND_net_1, A_WIDTH(2) => VCC_net_1, A_WIDTH(1) => 
        GND_net_1, A_WIDTH(0) => GND_net_1, B_EN => VCC_net_1, 
        B_ADDR_LAT => VCC_net_1, B_DOUT_LAT => GND_net_1, 
        B_WIDTH(2) => VCC_net_1, B_WIDTH(1) => GND_net_1, 
        B_WIDTH(0) => GND_net_1, C_EN => VCC_net_1, C_WIDTH(2)
         => VCC_net_1, C_WIDTH(1) => GND_net_1, C_WIDTH(0) => 
        GND_net_1, SII_LOCK => GND_net_1);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIGU067 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(7), B => inpB_rddata2(7), C => 
        GND_net_1, D => GND_net_1, FCI => un1_inpA_rddata2_cry_6, 
        S => un1_inpA_rddata2_10(7), Y => OPEN, FCO => 
        un1_inpA_rddata2_cry_7);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(0), B => inpB_rddata2(0), C => 
        GND_net_1, D => GND_net_1, FCI => GND_net_1, S => OPEN, Y
         => Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS_Y, FCO => 
        un1_inpA_rddata2_cry_0);
    
    Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNICLHIC : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(13), B => inpB_rddata2(13), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_cry_12, S => un1_inpA_rddata2_10(13), Y
         => OPEN, FCO => un1_inpA_rddata2_cry_13);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Inp_RAM1 is

    port( un1_inpA_rddata2_10                     : out   std_logic_vector(16 downto 1);
          inpA_rddata2                            : inout std_logic_vector(17 downto 0) := (others => 'Z');
          inpB_rddata2                            : inout std_logic_vector(17 downto 0) := (others => 'Z');
          InpA_rdaddr1                            : in    std_logic_vector(5 downto 0);
          InpB_rdaddr1                            : in    std_logic_vector(5 downto 0);
          inp_wraddr2                             : in    std_logic_vector(5 downto 0);
          inp_wrdata_dly0                         : in    std_logic_vector(17 downto 0);
          Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS_Y : out   std_logic;
          un1_inpA_rddata2_cry_16                 : out   std_logic;
          clk_c                                   : in    std_logic;
          InpA_rden1                              : in    std_logic;
          InpB_rden1                              : in    std_logic;
          InpCoef1_wren                           : in    std_logic
        );

end Inp_RAM1;

architecture DEF_ARCH of Inp_RAM1 is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component Inp_RAM1_Inp_RAM1_0_URAM
    port( un1_inpA_rddata2_10                     : out   std_logic_vector(16 downto 1);
          inpA_rddata2                            : inout   std_logic_vector(17 downto 0);
          inpB_rddata2                            : inout   std_logic_vector(17 downto 0);
          InpA_rdaddr1                            : in    std_logic_vector(5 downto 0) := (others => 'U');
          InpB_rdaddr1                            : in    std_logic_vector(5 downto 0) := (others => 'U');
          inp_wraddr2                             : in    std_logic_vector(5 downto 0) := (others => 'U');
          inp_wrdata_dly0                         : in    std_logic_vector(17 downto 0) := (others => 'U');
          Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS_Y : out   std_logic;
          un1_inpA_rddata2_cry_16                 : out   std_logic;
          clk_c                                   : in    std_logic := 'U';
          InpA_rden1                              : in    std_logic := 'U';
          InpB_rden1                              : in    std_logic := 'U';
          InpCoef1_wren                           : in    std_logic := 'U'
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

    for all : Inp_RAM1_Inp_RAM1_0_URAM
	Use entity work.Inp_RAM1_Inp_RAM1_0_URAM(DEF_ARCH);
begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    Inp_RAM1_0 : Inp_RAM1_Inp_RAM1_0_URAM
      port map(un1_inpA_rddata2_10(16) => un1_inpA_rddata2_10(16), 
        un1_inpA_rddata2_10(15) => un1_inpA_rddata2_10(15), 
        un1_inpA_rddata2_10(14) => un1_inpA_rddata2_10(14), 
        un1_inpA_rddata2_10(13) => un1_inpA_rddata2_10(13), 
        un1_inpA_rddata2_10(12) => un1_inpA_rddata2_10(12), 
        un1_inpA_rddata2_10(11) => un1_inpA_rddata2_10(11), 
        un1_inpA_rddata2_10(10) => un1_inpA_rddata2_10(10), 
        un1_inpA_rddata2_10(9) => un1_inpA_rddata2_10(9), 
        un1_inpA_rddata2_10(8) => un1_inpA_rddata2_10(8), 
        un1_inpA_rddata2_10(7) => un1_inpA_rddata2_10(7), 
        un1_inpA_rddata2_10(6) => un1_inpA_rddata2_10(6), 
        un1_inpA_rddata2_10(5) => un1_inpA_rddata2_10(5), 
        un1_inpA_rddata2_10(4) => un1_inpA_rddata2_10(4), 
        un1_inpA_rddata2_10(3) => un1_inpA_rddata2_10(3), 
        un1_inpA_rddata2_10(2) => un1_inpA_rddata2_10(2), 
        un1_inpA_rddata2_10(1) => un1_inpA_rddata2_10(1), 
        inpA_rddata2(17) => inpA_rddata2(17), inpA_rddata2(16)
         => inpA_rddata2(16), inpA_rddata2(15) => 
        inpA_rddata2(15), inpA_rddata2(14) => inpA_rddata2(14), 
        inpA_rddata2(13) => inpA_rddata2(13), inpA_rddata2(12)
         => inpA_rddata2(12), inpA_rddata2(11) => 
        inpA_rddata2(11), inpA_rddata2(10) => inpA_rddata2(10), 
        inpA_rddata2(9) => inpA_rddata2(9), inpA_rddata2(8) => 
        inpA_rddata2(8), inpA_rddata2(7) => inpA_rddata2(7), 
        inpA_rddata2(6) => inpA_rddata2(6), inpA_rddata2(5) => 
        inpA_rddata2(5), inpA_rddata2(4) => inpA_rddata2(4), 
        inpA_rddata2(3) => inpA_rddata2(3), inpA_rddata2(2) => 
        inpA_rddata2(2), inpA_rddata2(1) => inpA_rddata2(1), 
        inpA_rddata2(0) => inpA_rddata2(0), inpB_rddata2(17) => 
        inpB_rddata2(17), inpB_rddata2(16) => inpB_rddata2(16), 
        inpB_rddata2(15) => inpB_rddata2(15), inpB_rddata2(14)
         => inpB_rddata2(14), inpB_rddata2(13) => 
        inpB_rddata2(13), inpB_rddata2(12) => inpB_rddata2(12), 
        inpB_rddata2(11) => inpB_rddata2(11), inpB_rddata2(10)
         => inpB_rddata2(10), inpB_rddata2(9) => inpB_rddata2(9), 
        inpB_rddata2(8) => inpB_rddata2(8), inpB_rddata2(7) => 
        inpB_rddata2(7), inpB_rddata2(6) => inpB_rddata2(6), 
        inpB_rddata2(5) => inpB_rddata2(5), inpB_rddata2(4) => 
        inpB_rddata2(4), inpB_rddata2(3) => inpB_rddata2(3), 
        inpB_rddata2(2) => inpB_rddata2(2), inpB_rddata2(1) => 
        inpB_rddata2(1), inpB_rddata2(0) => inpB_rddata2(0), 
        InpA_rdaddr1(5) => InpA_rdaddr1(5), InpA_rdaddr1(4) => 
        InpA_rdaddr1(4), InpA_rdaddr1(3) => InpA_rdaddr1(3), 
        InpA_rdaddr1(2) => InpA_rdaddr1(2), InpA_rdaddr1(1) => 
        InpA_rdaddr1(1), InpA_rdaddr1(0) => InpA_rdaddr1(0), 
        InpB_rdaddr1(5) => InpB_rdaddr1(5), InpB_rdaddr1(4) => 
        InpB_rdaddr1(4), InpB_rdaddr1(3) => InpB_rdaddr1(3), 
        InpB_rdaddr1(2) => InpB_rdaddr1(2), InpB_rdaddr1(1) => 
        InpB_rdaddr1(1), InpB_rdaddr1(0) => InpB_rdaddr1(0), 
        inp_wraddr2(5) => inp_wraddr2(5), inp_wraddr2(4) => 
        inp_wraddr2(4), inp_wraddr2(3) => inp_wraddr2(3), 
        inp_wraddr2(2) => inp_wraddr2(2), inp_wraddr2(1) => 
        inp_wraddr2(1), inp_wraddr2(0) => inp_wraddr2(0), 
        inp_wrdata_dly0(17) => inp_wrdata_dly0(17), 
        inp_wrdata_dly0(16) => inp_wrdata_dly0(16), 
        inp_wrdata_dly0(15) => inp_wrdata_dly0(15), 
        inp_wrdata_dly0(14) => inp_wrdata_dly0(14), 
        inp_wrdata_dly0(13) => inp_wrdata_dly0(13), 
        inp_wrdata_dly0(12) => inp_wrdata_dly0(12), 
        inp_wrdata_dly0(11) => inp_wrdata_dly0(11), 
        inp_wrdata_dly0(10) => inp_wrdata_dly0(10), 
        inp_wrdata_dly0(9) => inp_wrdata_dly0(9), 
        inp_wrdata_dly0(8) => inp_wrdata_dly0(8), 
        inp_wrdata_dly0(7) => inp_wrdata_dly0(7), 
        inp_wrdata_dly0(6) => inp_wrdata_dly0(6), 
        inp_wrdata_dly0(5) => inp_wrdata_dly0(5), 
        inp_wrdata_dly0(4) => inp_wrdata_dly0(4), 
        inp_wrdata_dly0(3) => inp_wrdata_dly0(3), 
        inp_wrdata_dly0(2) => inp_wrdata_dly0(2), 
        inp_wrdata_dly0(1) => inp_wrdata_dly0(1), 
        inp_wrdata_dly0(0) => inp_wrdata_dly0(0), 
        Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS_Y => 
        Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS_Y, 
        un1_inpA_rddata2_cry_16 => un1_inpA_rddata2_cry_16, clk_c
         => clk_c, InpA_rden1 => InpA_rden1, InpB_rden1 => 
        InpB_rden1, InpCoef1_wren => InpCoef1_wren);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Inp_RAM_Inp_RAM_0_URAM is

    port( un1_inpA_rddata2_12                     : out   std_logic_vector(16 downto 1);
          inpA_rddata2                            : in    std_logic_vector(16 downto 0);
          un1_inpA_rddata2_11                     : out   std_logic_vector(16 downto 1);
          inpB_rddata2                            : in    std_logic_vector(16 downto 0);
          un1_inpA_rddata2_13                     : out   std_logic_vector(16 downto 1);
          InpA_rdaddr1                            : in    std_logic_vector(5 downto 0);
          InpB_rdaddr1                            : in    std_logic_vector(5 downto 0);
          inp_wraddr1                             : in    std_logic_vector(5 downto 0);
          inp_wrdata_dly0                         : in    std_logic_vector(17 downto 0);
          inpA_rddata1_17                         : out   std_logic;
          inpB_rddata1_17                         : out   std_logic;
          Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_0_Y : out   std_logic;
          un1_inpA_rddata2_2_cry_16               : out   std_logic;
          Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_Y   : out   std_logic;
          un1_inpA_rddata2_0_cry_16               : out   std_logic;
          Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIKTA7_Y   : out   std_logic;
          un1_inpA_rddata2_3_cry_16               : out   std_logic;
          clk_c                                   : in    std_logic;
          InpA_rden0                              : in    std_logic;
          InpB_rden0                              : in    std_logic;
          InpCoef0_wren                           : in    std_logic
        );

end Inp_RAM_Inp_RAM_0_URAM;

architecture DEF_ARCH of Inp_RAM_Inp_RAM_0_URAM is 

  component ARI1
    generic (INIT:std_logic_vector := x"0");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component RAM64x18
    generic (MEMORYFILE:string := "");

    port( A_DOUT        : out   std_logic_vector(17 downto 0);
          B_DOUT        : out   std_logic_vector(17 downto 0);
          BUSY          : out   std_logic;
          A_ADDR_CLK    : in    std_logic := 'U';
          A_DOUT_CLK    : in    std_logic := 'U';
          A_ADDR_SRST_N : in    std_logic := 'U';
          A_DOUT_SRST_N : in    std_logic := 'U';
          A_ADDR_ARST_N : in    std_logic := 'U';
          A_DOUT_ARST_N : in    std_logic := 'U';
          A_ADDR_EN     : in    std_logic := 'U';
          A_DOUT_EN     : in    std_logic := 'U';
          A_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          B_ADDR_CLK    : in    std_logic := 'U';
          B_DOUT_CLK    : in    std_logic := 'U';
          B_ADDR_SRST_N : in    std_logic := 'U';
          B_DOUT_SRST_N : in    std_logic := 'U';
          B_ADDR_ARST_N : in    std_logic := 'U';
          B_DOUT_ARST_N : in    std_logic := 'U';
          B_ADDR_EN     : in    std_logic := 'U';
          B_DOUT_EN     : in    std_logic := 'U';
          B_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          C_CLK         : in    std_logic := 'U';
          C_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          C_DIN         : in    std_logic_vector(17 downto 0) := (others => 'U');
          C_WEN         : in    std_logic := 'U';
          C_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_EN          : in    std_logic := 'U';
          A_ADDR_LAT    : in    std_logic := 'U';
          A_DOUT_LAT    : in    std_logic := 'U';
          A_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          B_EN          : in    std_logic := 'U';
          B_ADDR_LAT    : in    std_logic := 'U';
          B_DOUT_LAT    : in    std_logic := 'U';
          B_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          C_EN          : in    std_logic := 'U';
          C_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          SII_LOCK      : in    std_logic := 'U'
        );
  end component;

    signal un1_inpA_rddata2_2_cry_0, \inpB_rddata1[0]\, 
        GND_net_1, un1_inpA_rddata2_2_cry_1, \inpB_rddata1[1]\, 
        un1_inpA_rddata2_2_cry_2, \inpB_rddata1[2]\, 
        un1_inpA_rddata2_2_cry_3, \inpB_rddata1[3]\, 
        un1_inpA_rddata2_2_cry_4, \inpB_rddata1[4]\, 
        un1_inpA_rddata2_2_cry_5, \inpB_rddata1[5]\, 
        un1_inpA_rddata2_2_cry_6, \inpB_rddata1[6]\, 
        un1_inpA_rddata2_2_cry_7, \inpB_rddata1[7]\, 
        un1_inpA_rddata2_2_cry_8, \inpB_rddata1[8]\, 
        un1_inpA_rddata2_2_cry_9, \inpB_rddata1[9]\, 
        un1_inpA_rddata2_2_cry_10, \inpB_rddata1[10]\, 
        un1_inpA_rddata2_2_cry_11, \inpB_rddata1[11]\, 
        un1_inpA_rddata2_2_cry_12, \inpB_rddata1[12]\, 
        un1_inpA_rddata2_2_cry_13, \inpB_rddata1[13]\, 
        un1_inpA_rddata2_2_cry_14, \inpB_rddata1[14]\, 
        un1_inpA_rddata2_2_cry_15, \inpB_rddata1[15]\, 
        \inpB_rddata1[16]\, un1_inpA_rddata2_0_cry_0, 
        \inpA_rddata1[0]\, un1_inpA_rddata2_0_cry_1, 
        \inpA_rddata1[1]\, un1_inpA_rddata2_0_cry_2, 
        \inpA_rddata1[2]\, un1_inpA_rddata2_0_cry_3, 
        \inpA_rddata1[3]\, un1_inpA_rddata2_0_cry_4, 
        \inpA_rddata1[4]\, un1_inpA_rddata2_0_cry_5, 
        \inpA_rddata1[5]\, un1_inpA_rddata2_0_cry_6, 
        \inpA_rddata1[6]\, un1_inpA_rddata2_0_cry_7, 
        \inpA_rddata1[7]\, un1_inpA_rddata2_0_cry_8, 
        \inpA_rddata1[8]\, un1_inpA_rddata2_0_cry_9, 
        \inpA_rddata1[9]\, un1_inpA_rddata2_0_cry_10, 
        \inpA_rddata1[10]\, un1_inpA_rddata2_0_cry_11, 
        \inpA_rddata1[11]\, un1_inpA_rddata2_0_cry_12, 
        \inpA_rddata1[12]\, un1_inpA_rddata2_0_cry_13, 
        \inpA_rddata1[13]\, un1_inpA_rddata2_0_cry_14, 
        \inpA_rddata1[14]\, un1_inpA_rddata2_0_cry_15, 
        \inpA_rddata1[15]\, \inpA_rddata1[16]\, 
        un1_inpA_rddata2_3_cry_0, un1_inpA_rddata2_3_cry_1, 
        un1_inpA_rddata2_3_cry_2, un1_inpA_rddata2_3_cry_3, 
        un1_inpA_rddata2_3_cry_4, un1_inpA_rddata2_3_cry_5, 
        un1_inpA_rddata2_3_cry_6, un1_inpA_rddata2_3_cry_7, 
        un1_inpA_rddata2_3_cry_8, un1_inpA_rddata2_3_cry_9, 
        un1_inpA_rddata2_3_cry_10, un1_inpA_rddata2_3_cry_11, 
        un1_inpA_rddata2_3_cry_12, un1_inpA_rddata2_3_cry_13, 
        un1_inpA_rddata2_3_cry_14, un1_inpA_rddata2_3_cry_15, 
        VCC_net_1 : std_logic;

begin 


    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIGBO09_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(15), B => \inpB_rddata1[15]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_14, S => un1_inpA_rddata2_12(15), 
        Y => OPEN, FCO => un1_inpA_rddata2_2_cry_15);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIK8IO6 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[11]\, B => inpB_rddata2(11), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_10, S => un1_inpA_rddata2_11(11), 
        Y => OPEN, FCO => un1_inpA_rddata2_0_cry_11);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIFMD25_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(8), B => \inpB_rddata1[8]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_7, S => un1_inpA_rddata2_12(8), Y
         => OPEN, FCO => un1_inpA_rddata2_2_cry_8);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIBPJA7 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[12]\, B => inpB_rddata2(12), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_11, S => un1_inpA_rddata2_11(12), 
        Y => OPEN, FCO => un1_inpA_rddata2_0_cry_12);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI67FK5_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(9), B => \inpB_rddata1[9]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_8, S => un1_inpA_rddata2_12(9), Y
         => OPEN, FCO => un1_inpA_rddata2_2_cry_9);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI1LAU3_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(6), B => \inpB_rddata1[6]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_5, S => un1_inpA_rddata2_12(6), Y
         => OPEN, FCO => un1_inpA_rddata2_2_cry_6);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIK8IO6_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(11), B => \inpB_rddata1[11]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_10, S => un1_inpA_rddata2_12(11), 
        Y => OPEN, FCO => un1_inpA_rddata2_2_cry_11);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI7SPI9 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[16]\, B => inpB_rddata2(16), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_15, S => un1_inpA_rddata2_11(16), 
        Y => OPEN, FCO => un1_inpA_rddata2_0_cry_16);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIGBO09 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[15]\, B => inpB_rddata2(15), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_14, S => un1_inpA_rddata2_11(15), 
        Y => OPEN, FCO => un1_inpA_rddata2_0_cry_15);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIA49C3_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(5), B => \inpB_rddata1[5]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_4, S => un1_inpA_rddata2_12(5), Y
         => OPEN, FCO => un1_inpA_rddata2_2_cry_5);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIBPJA7_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(12), B => \inpB_rddata1[12]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_11, S => un1_inpA_rddata2_12(12), 
        Y => OPEN, FCO => un1_inpA_rddata2_2_cry_12);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIS5OG2 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[10]\, B => \inpB_rddata1[10]\, 
        C => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_9, S => un1_inpA_rddata2_13(10), Y
         => OPEN, FCO => un1_inpA_rddata2_3_cry_10);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNITNG66_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(10), B => \inpB_rddata1[10]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_9, S => un1_inpA_rddata2_12(10), Y
         => OPEN, FCO => un1_inpA_rddata2_2_cry_10);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIKNPS3 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[16]\, B => \inpB_rddata1[16]\, 
        C => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_15, S => un1_inpA_rddata2_13(16), 
        Y => OPEN, FCO => un1_inpA_rddata2_3_cry_16);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIJJ7Q2 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[4]\, B => inpB_rddata2(4), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_3, S => un1_inpA_rddata2_11(4), Y
         => OPEN, FCO => un1_inpA_rddata2_0_cry_4);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[0]\, B => inpB_rddata2(0), C
         => GND_net_1, D => GND_net_1, FCI => GND_net_1, S => 
        OPEN, Y => Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_Y, FCO => 
        un1_inpA_rddata2_0_cry_0);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNICS3E3 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[14]\, B => \inpB_rddata1[14]\, 
        C => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_13, S => un1_inpA_rddata2_13(14), 
        Y => OPEN, FCO => un1_inpA_rddata2_3_cry_14);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI1LAU3 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[6]\, B => inpB_rddata2(6), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_5, S => un1_inpA_rddata2_11(6), Y
         => OPEN, FCO => un1_inpA_rddata2_0_cry_6);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNISO0M : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[2]\, B => \inpB_rddata1[2]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_1, S => un1_inpA_rddata2_13(2), Y
         => OPEN, FCO => un1_inpA_rddata2_3_cry_2);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIE1341 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[1]\, B => inpB_rddata2(1), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_0, S => un1_inpA_rddata2_11(1), Y
         => OPEN, FCO => un1_inpA_rddata2_0_cry_1);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIS2682_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(3), B => \inpB_rddata1[3]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_2, S => un1_inpA_rddata2_12(3), Y
         => OPEN, FCO => un1_inpA_rddata2_2_cry_3);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI4KM41 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[4]\, B => \inpB_rddata1[4]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_3, S => un1_inpA_rddata2_13(4), Y
         => OPEN, FCO => un1_inpA_rddata2_3_cry_4);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIKA222 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[8]\, B => \inpB_rddata1[8]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_7, S => un1_inpA_rddata2_13(8), Y
         => OPEN, FCO => un1_inpA_rddata2_3_cry_8);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIJJ7Q2_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(4), B => \inpB_rddata1[4]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_3, S => un1_inpA_rddata2_12(4), Y
         => OPEN, FCO => un1_inpA_rddata2_2_cry_4);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNITNG66 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[10]\, B => inpB_rddata2(10), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_9, S => un1_inpA_rddata2_11(10), Y
         => OPEN, FCO => un1_inpA_rddata2_0_cry_10);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIO5CG4 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[7]\, B => inpB_rddata2(7), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_6, S => un1_inpA_rddata2_11(7), Y
         => OPEN, FCO => un1_inpA_rddata2_0_cry_7);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI0DNQ1 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[7]\, B => \inpB_rddata1[7]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_6, S => un1_inpA_rddata2_13(7), Y
         => OPEN, FCO => un1_inpA_rddata2_3_cry_7);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI2ALS7 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[13]\, B => inpB_rddata2(13), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_12, S => un1_inpA_rddata2_11(13), 
        Y => OPEN, FCO => un1_inpA_rddata2_0_cry_13);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI5I4M1_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(2), B => \inpB_rddata1[2]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_1, S => un1_inpA_rddata2_12(2), Y
         => OPEN, FCO => un1_inpA_rddata2_2_cry_2);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI7SPI9_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(16), B => \inpB_rddata1[16]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_15, S => un1_inpA_rddata2_12(16), 
        Y => OPEN, FCO => un1_inpA_rddata2_2_cry_16);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIFMD25 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[8]\, B => inpB_rddata2(8), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_7, S => un1_inpA_rddata2_11(8), Y
         => OPEN, FCO => un1_inpA_rddata2_0_cry_8);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIPQME8 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[14]\, B => inpB_rddata2(14), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_13, S => un1_inpA_rddata2_11(14), 
        Y => OPEN, FCO => un1_inpA_rddata2_0_cry_14);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIOH1C1 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[5]\, B => \inpB_rddata1[5]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_4, S => un1_inpA_rddata2_13(5), Y
         => OPEN, FCO => un1_inpA_rddata2_3_cry_5);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(0), B => \inpB_rddata1[0]\, C
         => GND_net_1, D => GND_net_1, FCI => GND_net_1, S => 
        OPEN, Y => Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_0_Y, FCO
         => un1_inpA_rddata2_2_cry_0);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIPQME8_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(14), B => \inpB_rddata1[14]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_13, S => un1_inpA_rddata2_12(14), 
        Y => OPEN, FCO => un1_inpA_rddata2_2_cry_14);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIOUO63 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[13]\, B => \inpB_rddata1[13]\, 
        C => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_12, S => un1_inpA_rddata2_13(13), 
        Y => OPEN, FCO => un1_inpA_rddata2_3_cry_13);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIA49C3 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[5]\, B => inpB_rddata2(5), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_4, S => un1_inpA_rddata2_11(5), Y
         => OPEN, FCO => un1_inpA_rddata2_0_cry_5);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIS2682 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[3]\, B => inpB_rddata2(3), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_2, S => un1_inpA_rddata2_11(3), Y
         => OPEN, FCO => un1_inpA_rddata2_0_cry_3);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIE1341_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(1), B => \inpB_rddata1[1]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_0, S => un1_inpA_rddata2_12(1), Y
         => OPEN, FCO => un1_inpA_rddata2_2_cry_1);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI0QEL3 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[15]\, B => \inpB_rddata1[15]\, 
        C => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_14, S => un1_inpA_rddata2_13(15), 
        Y => OPEN, FCO => un1_inpA_rddata2_3_cry_15);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIKTA7 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[0]\, B => \inpB_rddata1[0]\, C
         => GND_net_1, D => GND_net_1, FCI => GND_net_1, S => 
        OPEN, Y => Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIKTA7_Y, FCO => 
        un1_inpA_rddata2_3_cry_0);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI88D92 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[9]\, B => \inpB_rddata1[9]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_8, S => un1_inpA_rddata2_13(9), Y
         => OPEN, FCO => un1_inpA_rddata2_3_cry_9);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI2ALS7_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(13), B => \inpB_rddata1[13]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_12, S => un1_inpA_rddata2_12(13), 
        Y => OPEN, FCO => un1_inpA_rddata2_2_cry_13);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0 : RAM64x18
      generic map(MEMORYFILE => "Inp_RAM_Inp_RAM_0_URAM_R0C0.mem"
        )

      port map(A_DOUT(17) => inpA_rddata1_17, A_DOUT(16) => 
        \inpA_rddata1[16]\, A_DOUT(15) => \inpA_rddata1[15]\, 
        A_DOUT(14) => \inpA_rddata1[14]\, A_DOUT(13) => 
        \inpA_rddata1[13]\, A_DOUT(12) => \inpA_rddata1[12]\, 
        A_DOUT(11) => \inpA_rddata1[11]\, A_DOUT(10) => 
        \inpA_rddata1[10]\, A_DOUT(9) => \inpA_rddata1[9]\, 
        A_DOUT(8) => \inpA_rddata1[8]\, A_DOUT(7) => 
        \inpA_rddata1[7]\, A_DOUT(6) => \inpA_rddata1[6]\, 
        A_DOUT(5) => \inpA_rddata1[5]\, A_DOUT(4) => 
        \inpA_rddata1[4]\, A_DOUT(3) => \inpA_rddata1[3]\, 
        A_DOUT(2) => \inpA_rddata1[2]\, A_DOUT(1) => 
        \inpA_rddata1[1]\, A_DOUT(0) => \inpA_rddata1[0]\, 
        B_DOUT(17) => inpB_rddata1_17, B_DOUT(16) => 
        \inpB_rddata1[16]\, B_DOUT(15) => \inpB_rddata1[15]\, 
        B_DOUT(14) => \inpB_rddata1[14]\, B_DOUT(13) => 
        \inpB_rddata1[13]\, B_DOUT(12) => \inpB_rddata1[12]\, 
        B_DOUT(11) => \inpB_rddata1[11]\, B_DOUT(10) => 
        \inpB_rddata1[10]\, B_DOUT(9) => \inpB_rddata1[9]\, 
        B_DOUT(8) => \inpB_rddata1[8]\, B_DOUT(7) => 
        \inpB_rddata1[7]\, B_DOUT(6) => \inpB_rddata1[6]\, 
        B_DOUT(5) => \inpB_rddata1[5]\, B_DOUT(4) => 
        \inpB_rddata1[4]\, B_DOUT(3) => \inpB_rddata1[3]\, 
        B_DOUT(2) => \inpB_rddata1[2]\, B_DOUT(1) => 
        \inpB_rddata1[1]\, B_DOUT(0) => \inpB_rddata1[0]\, BUSY
         => OPEN, A_ADDR_CLK => VCC_net_1, A_DOUT_CLK => clk_c, 
        A_ADDR_SRST_N => VCC_net_1, A_DOUT_SRST_N => VCC_net_1, 
        A_ADDR_ARST_N => VCC_net_1, A_DOUT_ARST_N => VCC_net_1, 
        A_ADDR_EN => VCC_net_1, A_DOUT_EN => VCC_net_1, A_BLK(1)
         => InpA_rden0, A_BLK(0) => VCC_net_1, A_ADDR(9) => 
        InpA_rdaddr1(5), A_ADDR(8) => InpA_rdaddr1(4), A_ADDR(7)
         => InpA_rdaddr1(3), A_ADDR(6) => InpA_rdaddr1(2), 
        A_ADDR(5) => InpA_rdaddr1(1), A_ADDR(4) => 
        InpA_rdaddr1(0), A_ADDR(3) => GND_net_1, A_ADDR(2) => 
        GND_net_1, A_ADDR(1) => GND_net_1, A_ADDR(0) => GND_net_1, 
        B_ADDR_CLK => VCC_net_1, B_DOUT_CLK => clk_c, 
        B_ADDR_SRST_N => VCC_net_1, B_DOUT_SRST_N => VCC_net_1, 
        B_ADDR_ARST_N => VCC_net_1, B_DOUT_ARST_N => VCC_net_1, 
        B_ADDR_EN => VCC_net_1, B_DOUT_EN => VCC_net_1, B_BLK(1)
         => InpB_rden0, B_BLK(0) => VCC_net_1, B_ADDR(9) => 
        InpB_rdaddr1(5), B_ADDR(8) => InpB_rdaddr1(4), B_ADDR(7)
         => InpB_rdaddr1(3), B_ADDR(6) => InpB_rdaddr1(2), 
        B_ADDR(5) => InpB_rdaddr1(1), B_ADDR(4) => 
        InpB_rdaddr1(0), B_ADDR(3) => GND_net_1, B_ADDR(2) => 
        GND_net_1, B_ADDR(1) => GND_net_1, B_ADDR(0) => GND_net_1, 
        C_CLK => clk_c, C_ADDR(9) => inp_wraddr1(5), C_ADDR(8)
         => inp_wraddr1(4), C_ADDR(7) => inp_wraddr1(3), 
        C_ADDR(6) => inp_wraddr1(2), C_ADDR(5) => inp_wraddr1(1), 
        C_ADDR(4) => inp_wraddr1(0), C_ADDR(3) => GND_net_1, 
        C_ADDR(2) => GND_net_1, C_ADDR(1) => GND_net_1, C_ADDR(0)
         => GND_net_1, C_DIN(17) => inp_wrdata_dly0(17), 
        C_DIN(16) => inp_wrdata_dly0(16), C_DIN(15) => 
        inp_wrdata_dly0(15), C_DIN(14) => inp_wrdata_dly0(14), 
        C_DIN(13) => inp_wrdata_dly0(13), C_DIN(12) => 
        inp_wrdata_dly0(12), C_DIN(11) => inp_wrdata_dly0(11), 
        C_DIN(10) => inp_wrdata_dly0(10), C_DIN(9) => 
        inp_wrdata_dly0(9), C_DIN(8) => inp_wrdata_dly0(8), 
        C_DIN(7) => inp_wrdata_dly0(7), C_DIN(6) => 
        inp_wrdata_dly0(6), C_DIN(5) => inp_wrdata_dly0(5), 
        C_DIN(4) => inp_wrdata_dly0(4), C_DIN(3) => 
        inp_wrdata_dly0(3), C_DIN(2) => inp_wrdata_dly0(2), 
        C_DIN(1) => inp_wrdata_dly0(1), C_DIN(0) => 
        inp_wrdata_dly0(0), C_WEN => VCC_net_1, C_BLK(1) => 
        InpCoef0_wren, C_BLK(0) => VCC_net_1, A_EN => VCC_net_1, 
        A_ADDR_LAT => VCC_net_1, A_DOUT_LAT => GND_net_1, 
        A_WIDTH(2) => VCC_net_1, A_WIDTH(1) => GND_net_1, 
        A_WIDTH(0) => GND_net_1, B_EN => VCC_net_1, B_ADDR_LAT
         => VCC_net_1, B_DOUT_LAT => GND_net_1, B_WIDTH(2) => 
        VCC_net_1, B_WIDTH(1) => GND_net_1, B_WIDTH(0) => 
        GND_net_1, C_EN => VCC_net_1, C_WIDTH(2) => VCC_net_1, 
        C_WIDTH(1) => GND_net_1, C_WIDTH(0) => GND_net_1, 
        SII_LOCK => GND_net_1);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNICFCJ1 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[6]\, B => \inpB_rddata1[6]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_5, S => un1_inpA_rddata2_13(6), Y
         => OPEN, FCO => un1_inpA_rddata2_3_cry_6);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI67FK5 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[9]\, B => inpB_rddata2(9), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_8, S => un1_inpA_rddata2_11(9), Y
         => OPEN, FCO => un1_inpA_rddata2_0_cry_9);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI41EV2 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[12]\, B => \inpB_rddata1[12]\, 
        C => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_11, S => un1_inpA_rddata2_13(12), 
        Y => OPEN, FCO => un1_inpA_rddata2_3_cry_12);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIGMBT : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[3]\, B => \inpB_rddata1[3]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_2, S => un1_inpA_rddata2_13(3), Y
         => OPEN, FCO => un1_inpA_rddata2_3_cry_3);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIO5CG4_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => inpA_rddata2(7), B => \inpB_rddata1[7]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_6, S => un1_inpA_rddata2_12(7), Y
         => OPEN, FCO => un1_inpA_rddata2_2_cry_7);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI5I4M1 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[2]\, B => inpB_rddata2(2), C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_1, S => un1_inpA_rddata2_11(2), Y
         => OPEN, FCO => un1_inpA_rddata2_0_cry_2);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIG33O2 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[11]\, B => \inpB_rddata1[11]\, 
        C => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_10, S => un1_inpA_rddata2_13(11), 
        Y => OPEN, FCO => un1_inpA_rddata2_3_cry_11);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0_RNI8RLE : ARI1
      generic map(INIT => x"555AA")

      port map(A => \inpA_rddata1[1]\, B => \inpB_rddata1[1]\, C
         => GND_net_1, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_0, S => un1_inpA_rddata2_13(1), Y
         => OPEN, FCO => un1_inpA_rddata2_3_cry_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Inp_RAM is

    port( un1_inpA_rddata2_12                     : out   std_logic_vector(16 downto 1);
          inpA_rddata2                            : in    std_logic_vector(16 downto 0);
          un1_inpA_rddata2_11                     : out   std_logic_vector(16 downto 1);
          inpB_rddata2                            : in    std_logic_vector(16 downto 0);
          un1_inpA_rddata2_13                     : out   std_logic_vector(16 downto 1);
          InpA_rdaddr1                            : in    std_logic_vector(5 downto 0);
          InpB_rdaddr1                            : in    std_logic_vector(5 downto 0);
          inp_wraddr1                             : in    std_logic_vector(5 downto 0);
          inp_wrdata_dly0                         : in    std_logic_vector(17 downto 0);
          \inpA_rddata1[17]\                      : out   std_logic;
          \inpB_rddata1[17]\                      : out   std_logic;
          Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_0_Y : out   std_logic;
          un1_inpA_rddata2_2_cry_16               : out   std_logic;
          Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_Y   : out   std_logic;
          un1_inpA_rddata2_0_cry_16               : out   std_logic;
          Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIKTA7_Y   : out   std_logic;
          un1_inpA_rddata2_3_cry_16               : out   std_logic;
          clk_c                                   : in    std_logic;
          InpA_rden0                              : in    std_logic;
          InpB_rden0                              : in    std_logic;
          InpCoef0_wren                           : in    std_logic
        );

end Inp_RAM;

architecture DEF_ARCH of Inp_RAM is 

  component Inp_RAM_Inp_RAM_0_URAM
    port( un1_inpA_rddata2_12                     : out   std_logic_vector(16 downto 1);
          inpA_rddata2                            : in    std_logic_vector(16 downto 0) := (others => 'U');
          un1_inpA_rddata2_11                     : out   std_logic_vector(16 downto 1);
          inpB_rddata2                            : in    std_logic_vector(16 downto 0) := (others => 'U');
          un1_inpA_rddata2_13                     : out   std_logic_vector(16 downto 1);
          InpA_rdaddr1                            : in    std_logic_vector(5 downto 0) := (others => 'U');
          InpB_rdaddr1                            : in    std_logic_vector(5 downto 0) := (others => 'U');
          inp_wraddr1                             : in    std_logic_vector(5 downto 0) := (others => 'U');
          inp_wrdata_dly0                         : in    std_logic_vector(17 downto 0) := (others => 'U');
          inpA_rddata1_17                         : out   std_logic;
          inpB_rddata1_17                         : out   std_logic;
          Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_0_Y : out   std_logic;
          un1_inpA_rddata2_2_cry_16               : out   std_logic;
          Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_Y   : out   std_logic;
          un1_inpA_rddata2_0_cry_16               : out   std_logic;
          Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIKTA7_Y   : out   std_logic;
          un1_inpA_rddata2_3_cry_16               : out   std_logic;
          clk_c                                   : in    std_logic := 'U';
          InpA_rden0                              : in    std_logic := 'U';
          InpB_rden0                              : in    std_logic := 'U';
          InpCoef0_wren                           : in    std_logic := 'U'
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

    for all : Inp_RAM_Inp_RAM_0_URAM
	Use entity work.Inp_RAM_Inp_RAM_0_URAM(DEF_ARCH);
begin 


    Inp_RAM_0 : Inp_RAM_Inp_RAM_0_URAM
      port map(un1_inpA_rddata2_12(16) => un1_inpA_rddata2_12(16), 
        un1_inpA_rddata2_12(15) => un1_inpA_rddata2_12(15), 
        un1_inpA_rddata2_12(14) => un1_inpA_rddata2_12(14), 
        un1_inpA_rddata2_12(13) => un1_inpA_rddata2_12(13), 
        un1_inpA_rddata2_12(12) => un1_inpA_rddata2_12(12), 
        un1_inpA_rddata2_12(11) => un1_inpA_rddata2_12(11), 
        un1_inpA_rddata2_12(10) => un1_inpA_rddata2_12(10), 
        un1_inpA_rddata2_12(9) => un1_inpA_rddata2_12(9), 
        un1_inpA_rddata2_12(8) => un1_inpA_rddata2_12(8), 
        un1_inpA_rddata2_12(7) => un1_inpA_rddata2_12(7), 
        un1_inpA_rddata2_12(6) => un1_inpA_rddata2_12(6), 
        un1_inpA_rddata2_12(5) => un1_inpA_rddata2_12(5), 
        un1_inpA_rddata2_12(4) => un1_inpA_rddata2_12(4), 
        un1_inpA_rddata2_12(3) => un1_inpA_rddata2_12(3), 
        un1_inpA_rddata2_12(2) => un1_inpA_rddata2_12(2), 
        un1_inpA_rddata2_12(1) => un1_inpA_rddata2_12(1), 
        inpA_rddata2(16) => inpA_rddata2(16), inpA_rddata2(15)
         => inpA_rddata2(15), inpA_rddata2(14) => 
        inpA_rddata2(14), inpA_rddata2(13) => inpA_rddata2(13), 
        inpA_rddata2(12) => inpA_rddata2(12), inpA_rddata2(11)
         => inpA_rddata2(11), inpA_rddata2(10) => 
        inpA_rddata2(10), inpA_rddata2(9) => inpA_rddata2(9), 
        inpA_rddata2(8) => inpA_rddata2(8), inpA_rddata2(7) => 
        inpA_rddata2(7), inpA_rddata2(6) => inpA_rddata2(6), 
        inpA_rddata2(5) => inpA_rddata2(5), inpA_rddata2(4) => 
        inpA_rddata2(4), inpA_rddata2(3) => inpA_rddata2(3), 
        inpA_rddata2(2) => inpA_rddata2(2), inpA_rddata2(1) => 
        inpA_rddata2(1), inpA_rddata2(0) => inpA_rddata2(0), 
        un1_inpA_rddata2_11(16) => un1_inpA_rddata2_11(16), 
        un1_inpA_rddata2_11(15) => un1_inpA_rddata2_11(15), 
        un1_inpA_rddata2_11(14) => un1_inpA_rddata2_11(14), 
        un1_inpA_rddata2_11(13) => un1_inpA_rddata2_11(13), 
        un1_inpA_rddata2_11(12) => un1_inpA_rddata2_11(12), 
        un1_inpA_rddata2_11(11) => un1_inpA_rddata2_11(11), 
        un1_inpA_rddata2_11(10) => un1_inpA_rddata2_11(10), 
        un1_inpA_rddata2_11(9) => un1_inpA_rddata2_11(9), 
        un1_inpA_rddata2_11(8) => un1_inpA_rddata2_11(8), 
        un1_inpA_rddata2_11(7) => un1_inpA_rddata2_11(7), 
        un1_inpA_rddata2_11(6) => un1_inpA_rddata2_11(6), 
        un1_inpA_rddata2_11(5) => un1_inpA_rddata2_11(5), 
        un1_inpA_rddata2_11(4) => un1_inpA_rddata2_11(4), 
        un1_inpA_rddata2_11(3) => un1_inpA_rddata2_11(3), 
        un1_inpA_rddata2_11(2) => un1_inpA_rddata2_11(2), 
        un1_inpA_rddata2_11(1) => un1_inpA_rddata2_11(1), 
        inpB_rddata2(16) => inpB_rddata2(16), inpB_rddata2(15)
         => inpB_rddata2(15), inpB_rddata2(14) => 
        inpB_rddata2(14), inpB_rddata2(13) => inpB_rddata2(13), 
        inpB_rddata2(12) => inpB_rddata2(12), inpB_rddata2(11)
         => inpB_rddata2(11), inpB_rddata2(10) => 
        inpB_rddata2(10), inpB_rddata2(9) => inpB_rddata2(9), 
        inpB_rddata2(8) => inpB_rddata2(8), inpB_rddata2(7) => 
        inpB_rddata2(7), inpB_rddata2(6) => inpB_rddata2(6), 
        inpB_rddata2(5) => inpB_rddata2(5), inpB_rddata2(4) => 
        inpB_rddata2(4), inpB_rddata2(3) => inpB_rddata2(3), 
        inpB_rddata2(2) => inpB_rddata2(2), inpB_rddata2(1) => 
        inpB_rddata2(1), inpB_rddata2(0) => inpB_rddata2(0), 
        un1_inpA_rddata2_13(16) => un1_inpA_rddata2_13(16), 
        un1_inpA_rddata2_13(15) => un1_inpA_rddata2_13(15), 
        un1_inpA_rddata2_13(14) => un1_inpA_rddata2_13(14), 
        un1_inpA_rddata2_13(13) => un1_inpA_rddata2_13(13), 
        un1_inpA_rddata2_13(12) => un1_inpA_rddata2_13(12), 
        un1_inpA_rddata2_13(11) => un1_inpA_rddata2_13(11), 
        un1_inpA_rddata2_13(10) => un1_inpA_rddata2_13(10), 
        un1_inpA_rddata2_13(9) => un1_inpA_rddata2_13(9), 
        un1_inpA_rddata2_13(8) => un1_inpA_rddata2_13(8), 
        un1_inpA_rddata2_13(7) => un1_inpA_rddata2_13(7), 
        un1_inpA_rddata2_13(6) => un1_inpA_rddata2_13(6), 
        un1_inpA_rddata2_13(5) => un1_inpA_rddata2_13(5), 
        un1_inpA_rddata2_13(4) => un1_inpA_rddata2_13(4), 
        un1_inpA_rddata2_13(3) => un1_inpA_rddata2_13(3), 
        un1_inpA_rddata2_13(2) => un1_inpA_rddata2_13(2), 
        un1_inpA_rddata2_13(1) => un1_inpA_rddata2_13(1), 
        InpA_rdaddr1(5) => InpA_rdaddr1(5), InpA_rdaddr1(4) => 
        InpA_rdaddr1(4), InpA_rdaddr1(3) => InpA_rdaddr1(3), 
        InpA_rdaddr1(2) => InpA_rdaddr1(2), InpA_rdaddr1(1) => 
        InpA_rdaddr1(1), InpA_rdaddr1(0) => InpA_rdaddr1(0), 
        InpB_rdaddr1(5) => InpB_rdaddr1(5), InpB_rdaddr1(4) => 
        InpB_rdaddr1(4), InpB_rdaddr1(3) => InpB_rdaddr1(3), 
        InpB_rdaddr1(2) => InpB_rdaddr1(2), InpB_rdaddr1(1) => 
        InpB_rdaddr1(1), InpB_rdaddr1(0) => InpB_rdaddr1(0), 
        inp_wraddr1(5) => inp_wraddr1(5), inp_wraddr1(4) => 
        inp_wraddr1(4), inp_wraddr1(3) => inp_wraddr1(3), 
        inp_wraddr1(2) => inp_wraddr1(2), inp_wraddr1(1) => 
        inp_wraddr1(1), inp_wraddr1(0) => inp_wraddr1(0), 
        inp_wrdata_dly0(17) => inp_wrdata_dly0(17), 
        inp_wrdata_dly0(16) => inp_wrdata_dly0(16), 
        inp_wrdata_dly0(15) => inp_wrdata_dly0(15), 
        inp_wrdata_dly0(14) => inp_wrdata_dly0(14), 
        inp_wrdata_dly0(13) => inp_wrdata_dly0(13), 
        inp_wrdata_dly0(12) => inp_wrdata_dly0(12), 
        inp_wrdata_dly0(11) => inp_wrdata_dly0(11), 
        inp_wrdata_dly0(10) => inp_wrdata_dly0(10), 
        inp_wrdata_dly0(9) => inp_wrdata_dly0(9), 
        inp_wrdata_dly0(8) => inp_wrdata_dly0(8), 
        inp_wrdata_dly0(7) => inp_wrdata_dly0(7), 
        inp_wrdata_dly0(6) => inp_wrdata_dly0(6), 
        inp_wrdata_dly0(5) => inp_wrdata_dly0(5), 
        inp_wrdata_dly0(4) => inp_wrdata_dly0(4), 
        inp_wrdata_dly0(3) => inp_wrdata_dly0(3), 
        inp_wrdata_dly0(2) => inp_wrdata_dly0(2), 
        inp_wrdata_dly0(1) => inp_wrdata_dly0(1), 
        inp_wrdata_dly0(0) => inp_wrdata_dly0(0), inpA_rddata1_17
         => \inpA_rddata1[17]\, inpB_rddata1_17 => 
        \inpB_rddata1[17]\, 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_0_Y => 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_0_Y, 
        un1_inpA_rddata2_2_cry_16 => un1_inpA_rddata2_2_cry_16, 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_Y => 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_Y, 
        un1_inpA_rddata2_0_cry_16 => un1_inpA_rddata2_0_cry_16, 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIKTA7_Y => 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIKTA7_Y, 
        un1_inpA_rddata2_3_cry_16 => un1_inpA_rddata2_3_cry_16, 
        clk_c => clk_c, InpA_rden0 => InpA_rden0, InpB_rden0 => 
        InpB_rden0, InpCoef0_wren => InpCoef0_wren);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC is

    port( Yn_out      : out   std_logic_vector(43 downto 0);
          inp_rddata  : in    std_logic_vector(17 downto 0);
          Coef_rddata : in    std_logic_vector(17 downto 0);
          reset_n_c   : in    std_logic;
          clr_i_0     : in    std_logic;
          clk_c       : in    std_logic
        );

end mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC;

architecture DEF_ARCH of 
        mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;
    signal nc34, nc9, nc13, nc23, nc33, nc16, nc26, nc27, nc17, 
        nc36, nc37, nc5, nc4, nc42, nc41, nc25, nc15, nc35, nc28, 
        nc18, nc38, nc1, nc2, nc22, nc12, nc21, nc11, nc3, nc32, 
        nc40, nc31, nc44, nc7, nc6, nc19, nc29, nc39, nc8, nc43, 
        nc20, nc10, nc24, nc14, nc30 : std_logic;

begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    U0 : MACC
      port map(CLK(1) => clk_c, CLK(0) => clk_c, A(17) => 
        inp_rddata(17), A(16) => inp_rddata(16), A(15) => 
        inp_rddata(15), A(14) => inp_rddata(14), A(13) => 
        inp_rddata(13), A(12) => inp_rddata(12), A(11) => 
        inp_rddata(11), A(10) => inp_rddata(10), A(9) => 
        inp_rddata(9), A(8) => inp_rddata(8), A(7) => 
        inp_rddata(7), A(6) => inp_rddata(6), A(5) => 
        inp_rddata(5), A(4) => inp_rddata(4), A(3) => 
        inp_rddata(3), A(2) => inp_rddata(2), A(1) => 
        inp_rddata(1), A(0) => inp_rddata(0), A_EN(1) => 
        VCC_net_1, A_EN(0) => VCC_net_1, A_ARST_N(1) => reset_n_c, 
        A_ARST_N(0) => reset_n_c, A_SRST_N(1) => VCC_net_1, 
        A_SRST_N(0) => VCC_net_1, B(17) => Coef_rddata(17), B(16)
         => Coef_rddata(16), B(15) => Coef_rddata(15), B(14) => 
        Coef_rddata(14), B(13) => Coef_rddata(13), B(12) => 
        Coef_rddata(12), B(11) => Coef_rddata(11), B(10) => 
        Coef_rddata(10), B(9) => Coef_rddata(9), B(8) => 
        Coef_rddata(8), B(7) => Coef_rddata(7), B(6) => 
        Coef_rddata(6), B(5) => Coef_rddata(5), B(4) => 
        Coef_rddata(4), B(3) => Coef_rddata(3), B(2) => 
        Coef_rddata(2), B(1) => Coef_rddata(1), B(0) => 
        Coef_rddata(0), B_EN(1) => VCC_net_1, B_EN(0) => 
        VCC_net_1, B_ARST_N(1) => reset_n_c, B_ARST_N(0) => 
        reset_n_c, B_SRST_N(1) => VCC_net_1, B_SRST_N(0) => 
        VCC_net_1, C(43) => GND_net_1, C(42) => GND_net_1, C(41)
         => GND_net_1, C(40) => GND_net_1, C(39) => GND_net_1, 
        C(38) => GND_net_1, C(37) => GND_net_1, C(36) => 
        GND_net_1, C(35) => GND_net_1, C(34) => GND_net_1, C(33)
         => GND_net_1, C(32) => GND_net_1, C(31) => GND_net_1, 
        C(30) => GND_net_1, C(29) => GND_net_1, C(28) => 
        GND_net_1, C(27) => GND_net_1, C(26) => GND_net_1, C(25)
         => GND_net_1, C(24) => GND_net_1, C(23) => GND_net_1, 
        C(22) => GND_net_1, C(21) => GND_net_1, C(20) => 
        GND_net_1, C(19) => GND_net_1, C(18) => GND_net_1, C(17)
         => GND_net_1, C(16) => GND_net_1, C(15) => GND_net_1, 
        C(14) => GND_net_1, C(13) => GND_net_1, C(12) => 
        GND_net_1, C(11) => GND_net_1, C(10) => GND_net_1, C(9)
         => GND_net_1, C(8) => GND_net_1, C(7) => GND_net_1, C(6)
         => GND_net_1, C(5) => GND_net_1, C(4) => GND_net_1, C(3)
         => GND_net_1, C(2) => GND_net_1, C(1) => GND_net_1, C(0)
         => GND_net_1, C_EN(1) => VCC_net_1, C_EN(0) => VCC_net_1, 
        C_ARST_N(1) => VCC_net_1, C_ARST_N(0) => VCC_net_1, 
        C_SRST_N(1) => VCC_net_1, C_SRST_N(0) => VCC_net_1, 
        P_EN(1) => VCC_net_1, P_EN(0) => VCC_net_1, P_ARST_N(1)
         => reset_n_c, P_ARST_N(0) => reset_n_c, P_SRST_N(1) => 
        clr_i_0, P_SRST_N(0) => clr_i_0, FDBKSEL => VCC_net_1, 
        FDBKSEL_EN => VCC_net_1, FDBKSEL_AL_N => VCC_net_1, 
        FDBKSEL_SL_N => VCC_net_1, CDSEL => GND_net_1, CDSEL_EN
         => VCC_net_1, CDSEL_AL_N => VCC_net_1, CDSEL_SL_N => 
        VCC_net_1, ARSHFT17 => GND_net_1, ARSHFT17_EN => 
        VCC_net_1, ARSHFT17_AL_N => VCC_net_1, ARSHFT17_SL_N => 
        VCC_net_1, SUB => GND_net_1, SUB_EN => VCC_net_1, 
        SUB_AL_N => VCC_net_1, SUB_SL_N => VCC_net_1, CARRYIN => 
        GND_net_1, SIMD => GND_net_1, DOTP => GND_net_1, 
        OVFL_CARRYOUT_SEL => GND_net_1, A_BYPASS(1) => GND_net_1, 
        A_BYPASS(0) => GND_net_1, B_BYPASS(1) => GND_net_1, 
        B_BYPASS(0) => GND_net_1, C_BYPASS(1) => VCC_net_1, 
        C_BYPASS(0) => VCC_net_1, P_BYPASS(1) => GND_net_1, 
        P_BYPASS(0) => GND_net_1, FDBKSEL_BYPASS => VCC_net_1, 
        FDBKSEL_AD => GND_net_1, FDBKSEL_SD_N => VCC_net_1, 
        CDSEL_BYPASS => VCC_net_1, CDSEL_AD => GND_net_1, 
        CDSEL_SD_N => VCC_net_1, ARSHFT17_BYPASS => VCC_net_1, 
        ARSHFT17_AD => GND_net_1, ARSHFT17_SD_N => VCC_net_1, 
        SUB_BYPASS => VCC_net_1, SUB_AD => GND_net_1, SUB_SD_N
         => VCC_net_1, CDIN(43) => GND_net_1, CDIN(42) => 
        GND_net_1, CDIN(41) => GND_net_1, CDIN(40) => GND_net_1, 
        CDIN(39) => GND_net_1, CDIN(38) => GND_net_1, CDIN(37)
         => GND_net_1, CDIN(36) => GND_net_1, CDIN(35) => 
        GND_net_1, CDIN(34) => GND_net_1, CDIN(33) => GND_net_1, 
        CDIN(32) => GND_net_1, CDIN(31) => GND_net_1, CDIN(30)
         => GND_net_1, CDIN(29) => GND_net_1, CDIN(28) => 
        GND_net_1, CDIN(27) => GND_net_1, CDIN(26) => GND_net_1, 
        CDIN(25) => GND_net_1, CDIN(24) => GND_net_1, CDIN(23)
         => GND_net_1, CDIN(22) => GND_net_1, CDIN(21) => 
        GND_net_1, CDIN(20) => GND_net_1, CDIN(19) => GND_net_1, 
        CDIN(18) => GND_net_1, CDIN(17) => GND_net_1, CDIN(16)
         => GND_net_1, CDIN(15) => GND_net_1, CDIN(14) => 
        GND_net_1, CDIN(13) => GND_net_1, CDIN(12) => GND_net_1, 
        CDIN(11) => GND_net_1, CDIN(10) => GND_net_1, CDIN(9) => 
        GND_net_1, CDIN(8) => GND_net_1, CDIN(7) => GND_net_1, 
        CDIN(6) => GND_net_1, CDIN(5) => GND_net_1, CDIN(4) => 
        GND_net_1, CDIN(3) => GND_net_1, CDIN(2) => GND_net_1, 
        CDIN(1) => GND_net_1, CDIN(0) => GND_net_1, CDOUT(43) => 
        nc34, CDOUT(42) => nc9, CDOUT(41) => nc13, CDOUT(40) => 
        nc23, CDOUT(39) => nc33, CDOUT(38) => nc16, CDOUT(37) => 
        nc26, CDOUT(36) => nc27, CDOUT(35) => nc17, CDOUT(34) => 
        nc36, CDOUT(33) => nc37, CDOUT(32) => nc5, CDOUT(31) => 
        nc4, CDOUT(30) => nc42, CDOUT(29) => nc41, CDOUT(28) => 
        nc25, CDOUT(27) => nc15, CDOUT(26) => nc35, CDOUT(25) => 
        nc28, CDOUT(24) => nc18, CDOUT(23) => nc38, CDOUT(22) => 
        nc1, CDOUT(21) => nc2, CDOUT(20) => nc22, CDOUT(19) => 
        nc12, CDOUT(18) => nc21, CDOUT(17) => nc11, CDOUT(16) => 
        nc3, CDOUT(15) => nc32, CDOUT(14) => nc40, CDOUT(13) => 
        nc31, CDOUT(12) => nc44, CDOUT(11) => nc7, CDOUT(10) => 
        nc6, CDOUT(9) => nc19, CDOUT(8) => nc29, CDOUT(7) => nc39, 
        CDOUT(6) => nc8, CDOUT(5) => nc43, CDOUT(4) => nc20, 
        CDOUT(3) => nc10, CDOUT(2) => nc24, CDOUT(1) => nc14, 
        CDOUT(0) => nc30, P(43) => Yn_out(43), P(42) => 
        Yn_out(42), P(41) => Yn_out(41), P(40) => Yn_out(40), 
        P(39) => Yn_out(39), P(38) => Yn_out(38), P(37) => 
        Yn_out(37), P(36) => Yn_out(36), P(35) => Yn_out(35), 
        P(34) => Yn_out(34), P(33) => Yn_out(33), P(32) => 
        Yn_out(32), P(31) => Yn_out(31), P(30) => Yn_out(30), 
        P(29) => Yn_out(29), P(28) => Yn_out(28), P(27) => 
        Yn_out(27), P(26) => Yn_out(26), P(25) => Yn_out(25), 
        P(24) => Yn_out(24), P(23) => Yn_out(23), P(22) => 
        Yn_out(22), P(21) => Yn_out(21), P(20) => Yn_out(20), 
        P(19) => Yn_out(19), P(18) => Yn_out(18), P(17) => 
        Yn_out(17), P(16) => Yn_out(16), P(15) => Yn_out(15), 
        P(14) => Yn_out(14), P(13) => Yn_out(13), P(12) => 
        Yn_out(12), P(11) => Yn_out(11), P(10) => Yn_out(10), 
        P(9) => Yn_out(9), P(8) => Yn_out(8), P(7) => Yn_out(7), 
        P(6) => Yn_out(6), P(5) => Yn_out(5), P(4) => Yn_out(4), 
        P(3) => Yn_out(3), P(2) => Yn_out(2), P(1) => Yn_out(1), 
        P(0) => Yn_out(0), OVFL_CARRYOUT => OPEN);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity mulacc_18x18 is

    port( Yn_out      : out   std_logic_vector(43 downto 0);
          inp_rddata  : in    std_logic_vector(17 downto 0);
          Coef_rddata : in    std_logic_vector(17 downto 0);
          reset_n_c   : in    std_logic;
          clr_i_0     : in    std_logic;
          clk_c       : in    std_logic
        );

end mulacc_18x18;

architecture DEF_ARCH of mulacc_18x18 is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC
    port( Yn_out      : out   std_logic_vector(43 downto 0);
          inp_rddata  : in    std_logic_vector(17 downto 0) := (others => 'U');
          Coef_rddata : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_n_c   : in    std_logic := 'U';
          clr_i_0     : in    std_logic := 'U';
          clk_c       : in    std_logic := 'U'
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

    for all : mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC
	Use entity work.
        mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC(DEF_ARCH);
begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    mulacc_18x18_0 : mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC
      port map(Yn_out(43) => Yn_out(43), Yn_out(42) => Yn_out(42), 
        Yn_out(41) => Yn_out(41), Yn_out(40) => Yn_out(40), 
        Yn_out(39) => Yn_out(39), Yn_out(38) => Yn_out(38), 
        Yn_out(37) => Yn_out(37), Yn_out(36) => Yn_out(36), 
        Yn_out(35) => Yn_out(35), Yn_out(34) => Yn_out(34), 
        Yn_out(33) => Yn_out(33), Yn_out(32) => Yn_out(32), 
        Yn_out(31) => Yn_out(31), Yn_out(30) => Yn_out(30), 
        Yn_out(29) => Yn_out(29), Yn_out(28) => Yn_out(28), 
        Yn_out(27) => Yn_out(27), Yn_out(26) => Yn_out(26), 
        Yn_out(25) => Yn_out(25), Yn_out(24) => Yn_out(24), 
        Yn_out(23) => Yn_out(23), Yn_out(22) => Yn_out(22), 
        Yn_out(21) => Yn_out(21), Yn_out(20) => Yn_out(20), 
        Yn_out(19) => Yn_out(19), Yn_out(18) => Yn_out(18), 
        Yn_out(17) => Yn_out(17), Yn_out(16) => Yn_out(16), 
        Yn_out(15) => Yn_out(15), Yn_out(14) => Yn_out(14), 
        Yn_out(13) => Yn_out(13), Yn_out(12) => Yn_out(12), 
        Yn_out(11) => Yn_out(11), Yn_out(10) => Yn_out(10), 
        Yn_out(9) => Yn_out(9), Yn_out(8) => Yn_out(8), Yn_out(7)
         => Yn_out(7), Yn_out(6) => Yn_out(6), Yn_out(5) => 
        Yn_out(5), Yn_out(4) => Yn_out(4), Yn_out(3) => Yn_out(3), 
        Yn_out(2) => Yn_out(2), Yn_out(1) => Yn_out(1), Yn_out(0)
         => Yn_out(0), inp_rddata(17) => inp_rddata(17), 
        inp_rddata(16) => inp_rddata(16), inp_rddata(15) => 
        inp_rddata(15), inp_rddata(14) => inp_rddata(14), 
        inp_rddata(13) => inp_rddata(13), inp_rddata(12) => 
        inp_rddata(12), inp_rddata(11) => inp_rddata(11), 
        inp_rddata(10) => inp_rddata(10), inp_rddata(9) => 
        inp_rddata(9), inp_rddata(8) => inp_rddata(8), 
        inp_rddata(7) => inp_rddata(7), inp_rddata(6) => 
        inp_rddata(6), inp_rddata(5) => inp_rddata(5), 
        inp_rddata(4) => inp_rddata(4), inp_rddata(3) => 
        inp_rddata(3), inp_rddata(2) => inp_rddata(2), 
        inp_rddata(1) => inp_rddata(1), inp_rddata(0) => 
        inp_rddata(0), Coef_rddata(17) => Coef_rddata(17), 
        Coef_rddata(16) => Coef_rddata(16), Coef_rddata(15) => 
        Coef_rddata(15), Coef_rddata(14) => Coef_rddata(14), 
        Coef_rddata(13) => Coef_rddata(13), Coef_rddata(12) => 
        Coef_rddata(12), Coef_rddata(11) => Coef_rddata(11), 
        Coef_rddata(10) => Coef_rddata(10), Coef_rddata(9) => 
        Coef_rddata(9), Coef_rddata(8) => Coef_rddata(8), 
        Coef_rddata(7) => Coef_rddata(7), Coef_rddata(6) => 
        Coef_rddata(6), Coef_rddata(5) => Coef_rddata(5), 
        Coef_rddata(4) => Coef_rddata(4), Coef_rddata(3) => 
        Coef_rddata(3), Coef_rddata(2) => Coef_rddata(2), 
        Coef_rddata(1) => Coef_rddata(1), Coef_rddata(0) => 
        Coef_rddata(0), reset_n_c => reset_n_c, clr_i_0 => 
        clr_i_0, clk_c => clk_c);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Coef_RAM_Coef_RAM_0_URAM is

    port( Coef_rddata1 : out   std_logic_vector(17 downto 0);
          Coef_rdaddr1 : in    std_logic_vector(5 downto 0);
          clk_c        : in    std_logic;
          Coef0_rden   : in    std_logic
        );

end Coef_RAM_Coef_RAM_0_URAM;

architecture DEF_ARCH of Coef_RAM_Coef_RAM_0_URAM is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component RAM64x18
    generic (MEMORYFILE:string := "");

    port( A_DOUT        : out   std_logic_vector(17 downto 0);
          B_DOUT        : out   std_logic_vector(17 downto 0);
          BUSY          : out   std_logic;
          A_ADDR_CLK    : in    std_logic := 'U';
          A_DOUT_CLK    : in    std_logic := 'U';
          A_ADDR_SRST_N : in    std_logic := 'U';
          A_DOUT_SRST_N : in    std_logic := 'U';
          A_ADDR_ARST_N : in    std_logic := 'U';
          A_DOUT_ARST_N : in    std_logic := 'U';
          A_ADDR_EN     : in    std_logic := 'U';
          A_DOUT_EN     : in    std_logic := 'U';
          A_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          B_ADDR_CLK    : in    std_logic := 'U';
          B_DOUT_CLK    : in    std_logic := 'U';
          B_ADDR_SRST_N : in    std_logic := 'U';
          B_DOUT_SRST_N : in    std_logic := 'U';
          B_ADDR_ARST_N : in    std_logic := 'U';
          B_DOUT_ARST_N : in    std_logic := 'U';
          B_ADDR_EN     : in    std_logic := 'U';
          B_DOUT_EN     : in    std_logic := 'U';
          B_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          C_CLK         : in    std_logic := 'U';
          C_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          C_DIN         : in    std_logic_vector(17 downto 0) := (others => 'U');
          C_WEN         : in    std_logic := 'U';
          C_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_EN          : in    std_logic := 'U';
          A_ADDR_LAT    : in    std_logic := 'U';
          A_DOUT_LAT    : in    std_logic := 'U';
          A_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          B_EN          : in    std_logic := 'U';
          B_ADDR_LAT    : in    std_logic := 'U';
          B_DOUT_LAT    : in    std_logic := 'U';
          B_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          C_EN          : in    std_logic := 'U';
          C_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          SII_LOCK      : in    std_logic := 'U'
        );
  end component;

    signal VCC_net_1, GND_net_1 : std_logic;
    signal nc1, nc8, nc13, nc16, nc9, nc14, nc5, nc15, nc3, nc10, 
        nc7, nc17, nc4, nc12, nc2, nc18, nc6, nc11 : std_logic;

begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    Coef_RAM_Coef_RAM_0_URAM_R0C0 : RAM64x18

              generic map(MEMORYFILE => "Coef_RAM_Coef_RAM_0_URAM_R0C0.mem"
        )

      port map(A_DOUT(17) => Coef_rddata1(17), A_DOUT(16) => 
        Coef_rddata1(16), A_DOUT(15) => Coef_rddata1(15), 
        A_DOUT(14) => Coef_rddata1(14), A_DOUT(13) => 
        Coef_rddata1(13), A_DOUT(12) => Coef_rddata1(12), 
        A_DOUT(11) => Coef_rddata1(11), A_DOUT(10) => 
        Coef_rddata1(10), A_DOUT(9) => Coef_rddata1(9), A_DOUT(8)
         => Coef_rddata1(8), A_DOUT(7) => Coef_rddata1(7), 
        A_DOUT(6) => Coef_rddata1(6), A_DOUT(5) => 
        Coef_rddata1(5), A_DOUT(4) => Coef_rddata1(4), A_DOUT(3)
         => Coef_rddata1(3), A_DOUT(2) => Coef_rddata1(2), 
        A_DOUT(1) => Coef_rddata1(1), A_DOUT(0) => 
        Coef_rddata1(0), B_DOUT(17) => nc1, B_DOUT(16) => nc8, 
        B_DOUT(15) => nc13, B_DOUT(14) => nc16, B_DOUT(13) => nc9, 
        B_DOUT(12) => nc14, B_DOUT(11) => nc5, B_DOUT(10) => nc15, 
        B_DOUT(9) => nc3, B_DOUT(8) => nc10, B_DOUT(7) => nc7, 
        B_DOUT(6) => nc17, B_DOUT(5) => nc4, B_DOUT(4) => nc12, 
        B_DOUT(3) => nc2, B_DOUT(2) => nc18, B_DOUT(1) => nc6, 
        B_DOUT(0) => nc11, BUSY => OPEN, A_ADDR_CLK => VCC_net_1, 
        A_DOUT_CLK => clk_c, A_ADDR_SRST_N => VCC_net_1, 
        A_DOUT_SRST_N => VCC_net_1, A_ADDR_ARST_N => VCC_net_1, 
        A_DOUT_ARST_N => VCC_net_1, A_ADDR_EN => VCC_net_1, 
        A_DOUT_EN => VCC_net_1, A_BLK(1) => Coef0_rden, A_BLK(0)
         => VCC_net_1, A_ADDR(9) => Coef_rdaddr1(5), A_ADDR(8)
         => Coef_rdaddr1(4), A_ADDR(7) => Coef_rdaddr1(3), 
        A_ADDR(6) => Coef_rdaddr1(2), A_ADDR(5) => 
        Coef_rdaddr1(1), A_ADDR(4) => Coef_rdaddr1(0), A_ADDR(3)
         => GND_net_1, A_ADDR(2) => GND_net_1, A_ADDR(1) => 
        GND_net_1, A_ADDR(0) => GND_net_1, B_ADDR_CLK => 
        VCC_net_1, B_DOUT_CLK => clk_c, B_ADDR_SRST_N => 
        VCC_net_1, B_DOUT_SRST_N => VCC_net_1, B_ADDR_ARST_N => 
        VCC_net_1, B_DOUT_ARST_N => VCC_net_1, B_ADDR_EN => 
        VCC_net_1, B_DOUT_EN => VCC_net_1, B_BLK(1) => GND_net_1, 
        B_BLK(0) => VCC_net_1, B_ADDR(9) => GND_net_1, B_ADDR(8)
         => GND_net_1, B_ADDR(7) => GND_net_1, B_ADDR(6) => 
        GND_net_1, B_ADDR(5) => GND_net_1, B_ADDR(4) => GND_net_1, 
        B_ADDR(3) => GND_net_1, B_ADDR(2) => GND_net_1, B_ADDR(1)
         => GND_net_1, B_ADDR(0) => GND_net_1, C_CLK => clk_c, 
        C_ADDR(9) => GND_net_1, C_ADDR(8) => GND_net_1, C_ADDR(7)
         => GND_net_1, C_ADDR(6) => GND_net_1, C_ADDR(5) => 
        GND_net_1, C_ADDR(4) => GND_net_1, C_ADDR(3) => GND_net_1, 
        C_ADDR(2) => GND_net_1, C_ADDR(1) => GND_net_1, C_ADDR(0)
         => GND_net_1, C_DIN(17) => GND_net_1, C_DIN(16) => 
        GND_net_1, C_DIN(15) => GND_net_1, C_DIN(14) => GND_net_1, 
        C_DIN(13) => GND_net_1, C_DIN(12) => GND_net_1, C_DIN(11)
         => GND_net_1, C_DIN(10) => GND_net_1, C_DIN(9) => 
        GND_net_1, C_DIN(8) => GND_net_1, C_DIN(7) => GND_net_1, 
        C_DIN(6) => GND_net_1, C_DIN(5) => GND_net_1, C_DIN(4)
         => GND_net_1, C_DIN(3) => GND_net_1, C_DIN(2) => 
        GND_net_1, C_DIN(1) => GND_net_1, C_DIN(0) => GND_net_1, 
        C_WEN => VCC_net_1, C_BLK(1) => GND_net_1, C_BLK(0) => 
        VCC_net_1, A_EN => VCC_net_1, A_ADDR_LAT => VCC_net_1, 
        A_DOUT_LAT => GND_net_1, A_WIDTH(2) => VCC_net_1, 
        A_WIDTH(1) => GND_net_1, A_WIDTH(0) => GND_net_1, B_EN
         => VCC_net_1, B_ADDR_LAT => VCC_net_1, B_DOUT_LAT => 
        GND_net_1, B_WIDTH(2) => VCC_net_1, B_WIDTH(1) => 
        GND_net_1, B_WIDTH(0) => GND_net_1, C_EN => VCC_net_1, 
        C_WIDTH(2) => VCC_net_1, C_WIDTH(1) => GND_net_1, 
        C_WIDTH(0) => GND_net_1, SII_LOCK => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Coef_RAM is

    port( Coef_rddata1 : out   std_logic_vector(17 downto 0);
          Coef_rdaddr1 : in    std_logic_vector(5 downto 0);
          clk_c        : in    std_logic;
          Coef0_rden   : in    std_logic
        );

end Coef_RAM;

architecture DEF_ARCH of Coef_RAM is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component Coef_RAM_Coef_RAM_0_URAM
    port( Coef_rddata1 : out   std_logic_vector(17 downto 0);
          Coef_rdaddr1 : in    std_logic_vector(5 downto 0) := (others => 'U');
          clk_c        : in    std_logic := 'U';
          Coef0_rden   : in    std_logic := 'U'
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

    for all : Coef_RAM_Coef_RAM_0_URAM
	Use entity work.Coef_RAM_Coef_RAM_0_URAM(DEF_ARCH);
begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    Coef_RAM_0 : Coef_RAM_Coef_RAM_0_URAM
      port map(Coef_rddata1(17) => Coef_rddata1(17), 
        Coef_rddata1(16) => Coef_rddata1(16), Coef_rddata1(15)
         => Coef_rddata1(15), Coef_rddata1(14) => 
        Coef_rddata1(14), Coef_rddata1(13) => Coef_rddata1(13), 
        Coef_rddata1(12) => Coef_rddata1(12), Coef_rddata1(11)
         => Coef_rddata1(11), Coef_rddata1(10) => 
        Coef_rddata1(10), Coef_rddata1(9) => Coef_rddata1(9), 
        Coef_rddata1(8) => Coef_rddata1(8), Coef_rddata1(7) => 
        Coef_rddata1(7), Coef_rddata1(6) => Coef_rddata1(6), 
        Coef_rddata1(5) => Coef_rddata1(5), Coef_rddata1(4) => 
        Coef_rddata1(4), Coef_rddata1(3) => Coef_rddata1(3), 
        Coef_rddata1(2) => Coef_rddata1(2), Coef_rddata1(1) => 
        Coef_rddata1(1), Coef_rddata1(0) => Coef_rddata1(0), 
        Coef_rdaddr1(5) => Coef_rdaddr1(5), Coef_rdaddr1(4) => 
        Coef_rdaddr1(4), Coef_rdaddr1(3) => Coef_rdaddr1(3), 
        Coef_rdaddr1(2) => Coef_rdaddr1(2), Coef_rdaddr1(1) => 
        Coef_rdaddr1(1), Coef_rdaddr1(0) => Coef_rdaddr1(0), 
        clk_c => clk_c, Coef0_rden => Coef0_rden);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Symmetric_MAC_FIR is

    port( Xn_in      : in    std_logic_vector(17 downto 0);
          Mac_out    : out   std_logic_vector(43 downto 0);
          clk        : in    std_logic;
          reset_n    : in    std_logic;
          Filter_En  : in    std_logic;
          Data_Valid : in    std_logic;
          rdy        : out   std_logic
        );

end Symmetric_MAC_FIR;

architecture DEF_ARCH of Symmetric_MAC_FIR is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector := x"0");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component INBUF
    generic (IOSTD:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector := x"0");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OUTBUF
    generic (IOSTD:string := "");

    port( D   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CLKINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component Inp_RAM1
    port( un1_inpA_rddata2_10                     : out   std_logic_vector(16 downto 1);
          inpA_rddata2                            : inout   std_logic_vector(17 downto 0);
          inpB_rddata2                            : inout   std_logic_vector(17 downto 0);
          InpA_rdaddr1                            : in    std_logic_vector(5 downto 0) := (others => 'U');
          InpB_rdaddr1                            : in    std_logic_vector(5 downto 0) := (others => 'U');
          inp_wraddr2                             : in    std_logic_vector(5 downto 0) := (others => 'U');
          inp_wrdata_dly0                         : in    std_logic_vector(17 downto 0) := (others => 'U');
          Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS_Y : out   std_logic;
          un1_inpA_rddata2_cry_16                 : out   std_logic;
          clk_c                                   : in    std_logic := 'U';
          InpA_rden1                              : in    std_logic := 'U';
          InpB_rden1                              : in    std_logic := 'U';
          InpCoef1_wren                           : in    std_logic := 'U'
        );
  end component;

  component Inp_RAM
    port( un1_inpA_rddata2_12                     : out   std_logic_vector(16 downto 1);
          inpA_rddata2                            : in    std_logic_vector(16 downto 0) := (others => 'U');
          un1_inpA_rddata2_11                     : out   std_logic_vector(16 downto 1);
          inpB_rddata2                            : in    std_logic_vector(16 downto 0) := (others => 'U');
          un1_inpA_rddata2_13                     : out   std_logic_vector(16 downto 1);
          InpA_rdaddr1                            : in    std_logic_vector(5 downto 0) := (others => 'U');
          InpB_rdaddr1                            : in    std_logic_vector(5 downto 0) := (others => 'U');
          inp_wraddr1                             : in    std_logic_vector(5 downto 0) := (others => 'U');
          inp_wrdata_dly0                         : in    std_logic_vector(17 downto 0) := (others => 'U');
          \inpA_rddata1[17]\                      : out   std_logic;
          \inpB_rddata1[17]\                      : out   std_logic;
          Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_0_Y : out   std_logic;
          un1_inpA_rddata2_2_cry_16               : out   std_logic;
          Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_Y   : out   std_logic;
          un1_inpA_rddata2_0_cry_16               : out   std_logic;
          Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIKTA7_Y   : out   std_logic;
          un1_inpA_rddata2_3_cry_16               : out   std_logic;
          clk_c                                   : in    std_logic := 'U';
          InpA_rden0                              : in    std_logic := 'U';
          InpB_rden0                              : in    std_logic := 'U';
          InpCoef0_wren                           : in    std_logic := 'U'
        );
  end component;

  component mulacc_18x18
    port( Yn_out      : out   std_logic_vector(43 downto 0);
          inp_rddata  : in    std_logic_vector(17 downto 0) := (others => 'U');
          Coef_rddata : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_n_c   : in    std_logic := 'U';
          clr_i_0     : in    std_logic := 'U';
          clk_c       : in    std_logic := 'U'
        );
  end component;

  component Coef_RAM
    port( Coef_rddata1 : out   std_logic_vector(17 downto 0);
          Coef_rdaddr1 : in    std_logic_vector(5 downto 0) := (others => 'U');
          clk_c        : in    std_logic := 'U';
          Coef0_rden   : in    std_logic := 'U'
        );
  end component;

    signal \rdy_sig\, \inp_rddata[0]_net_1\, 
        \inp_rddata[1]_net_1\, \inp_rddata[2]_net_1\, 
        \inp_rddata[3]_net_1\, \inp_rddata[4]_net_1\, 
        \inp_rddata[5]_net_1\, \inp_rddata[6]_net_1\, 
        \inp_rddata[7]_net_1\, \inp_rddata[8]_net_1\, 
        \inp_rddata[9]_net_1\, \inp_rddata[10]_net_1\, 
        \inp_rddata[11]_net_1\, \inp_rddata[12]_net_1\, 
        \inp_rddata[13]_net_1\, \inp_rddata[14]_net_1\, 
        \inp_rddata[15]_net_1\, \inp_rddata[16]_net_1\, 
        \inp_rddata[17]_net_1\, VCC_net_1, \Coef_rddata[0]_net_1\, 
        \Coef_rddata[1]_net_1\, \Coef_rddata[2]_net_1\, 
        \Coef_rddata[3]_net_1\, \Coef_rddata[4]_net_1\, 
        \Coef_rddata[5]_net_1\, \Coef_rddata[6]_net_1\, 
        \Coef_rddata[7]_net_1\, \Coef_rddata[8]_net_1\, 
        \Coef_rddata[9]_net_1\, \Coef_rddata[10]_net_1\, 
        \Coef_rddata[11]_net_1\, \Coef_rddata[12]_net_1\, 
        \Coef_rddata[13]_net_1\, \Coef_rddata[14]_net_1\, 
        \Coef_rddata[15]_net_1\, \Coef_rddata[16]_net_1\, 
        \Coef_rddata[17]_net_1\, \Yn_out[0]\, \Yn_out[1]\, 
        \Yn_out[2]\, \Yn_out[3]\, \Yn_out[4]\, \Yn_out[5]\, 
        \Yn_out[6]\, \Yn_out[7]\, \Yn_out[8]\, \Yn_out[9]\, 
        \Yn_out[10]\, \Yn_out[11]\, \Yn_out[12]\, \Yn_out[13]\, 
        \Yn_out[14]\, \Yn_out[15]\, \Yn_out[16]\, \Yn_out[17]\, 
        \Yn_out[18]\, \Yn_out[19]\, \Yn_out[20]\, \Yn_out[21]\, 
        \Yn_out[22]\, \Yn_out[23]\, \Yn_out[24]\, \Yn_out[25]\, 
        \Yn_out[26]\, \Yn_out[27]\, \Yn_out[28]\, \Yn_out[29]\, 
        \Yn_out[30]\, \Yn_out[31]\, \Yn_out[32]\, \Yn_out[33]\, 
        \Yn_out[34]\, \Yn_out[35]\, \Yn_out[36]\, \Yn_out[37]\, 
        \Yn_out[38]\, \Yn_out[39]\, \Yn_out[40]\, \Yn_out[41]\, 
        \Yn_out[42]\, \Yn_out[43]\, \Coef_rdaddr1[0]_net_1\, 
        \Coef_rdaddr1[1]_net_1\, \Coef_rdaddr1[2]_net_1\, 
        \Coef_rdaddr1[3]_net_1\, \Coef_rdaddr1[4]_net_1\, 
        \Coef_rdaddr1[5]_net_1\, \Coef0_rden\, GND_net_1, 
        \Coef_rddata1[0]\, \Coef_rddata1[1]\, \Coef_rddata1[2]\, 
        \Coef_rddata1[3]\, \Coef_rddata1[4]\, \Coef_rddata1[5]\, 
        \Coef_rddata1[6]\, \Coef_rddata1[7]\, \Coef_rddata1[8]\, 
        \Coef_rddata1[9]\, \Coef_rddata1[10]\, \Coef_rddata1[11]\, 
        \Coef_rddata1[12]\, \Coef_rddata1[13]\, 
        \Coef_rddata1[14]\, \Coef_rddata1[15]\, 
        \Coef_rddata1[16]\, \Coef_rddata1[17]\, 
        \InpA_rdaddr1[0]_net_1\, \InpA_rdaddr1[1]_net_1\, 
        \InpA_rdaddr1[2]_net_1\, \InpA_rdaddr1[3]_net_1\, 
        \InpA_rdaddr1[4]_net_1\, \InpA_rdaddr1[5]_net_1\, 
        \InpA_rden0\, \InpB_rdaddr1[0]_net_1\, 
        \InpB_rdaddr1[1]_net_1\, \InpB_rdaddr1[2]_net_1\, 
        \InpB_rdaddr1[3]_net_1\, \InpB_rdaddr1[4]_net_1\, 
        \InpB_rdaddr1[5]_net_1\, \InpB_rden0\, 
        \inp_wraddr1[0]_net_1\, \inp_wraddr1[1]_net_1\, 
        \inp_wraddr1[2]_net_1\, \inp_wraddr1[3]_net_1\, 
        \inp_wraddr1[4]_net_1\, \inp_wraddr1[5]_net_1\, 
        \InpCoef0_wren\, \inp_wrdata_dly0[0]_net_1\, 
        \inp_wrdata_dly0[1]_net_1\, \inp_wrdata_dly0[2]_net_1\, 
        \inp_wrdata_dly0[3]_net_1\, \inp_wrdata_dly0[4]_net_1\, 
        \inp_wrdata_dly0[5]_net_1\, \inp_wrdata_dly0[6]_net_1\, 
        \inp_wrdata_dly0[7]_net_1\, \inp_wrdata_dly0[8]_net_1\, 
        \inp_wrdata_dly0[9]_net_1\, \inp_wrdata_dly0[10]_net_1\, 
        \inp_wrdata_dly0[11]_net_1\, \inp_wrdata_dly0[12]_net_1\, 
        \inp_wrdata_dly0[13]_net_1\, \inp_wrdata_dly0[14]_net_1\, 
        \inp_wrdata_dly0[15]_net_1\, \inp_wrdata_dly0[16]_net_1\, 
        \inp_wrdata_dly0[17]_net_1\, \inpA_rddata1[17]\, 
        \inpB_rddata1[17]\, \InpA_rden1\, \InpB_rden1\, 
        \inp_wraddr2[0]_net_1\, \inp_wraddr2[1]_net_1\, 
        \inp_wraddr2[2]_net_1\, \inp_wraddr2[3]_net_1\, 
        \inp_wraddr2[4]_net_1\, \inp_wraddr2[5]_net_1\, 
        \InpCoef1_wren\, \inpA_rddata2[0]\, \inpA_rddata2[1]\, 
        \inpA_rddata2[2]\, \inpA_rddata2[3]\, \inpA_rddata2[4]\, 
        \inpA_rddata2[5]\, \inpA_rddata2[6]\, \inpA_rddata2[7]\, 
        \inpA_rddata2[8]\, \inpA_rddata2[9]\, \inpA_rddata2[10]\, 
        \inpA_rddata2[11]\, \inpA_rddata2[12]\, 
        \inpA_rddata2[13]\, \inpA_rddata2[14]\, 
        \inpA_rddata2[15]\, \inpA_rddata2[16]\, 
        \inpA_rddata2[17]\, \inpB_rddata2[0]\, \inpB_rddata2[1]\, 
        \inpB_rddata2[2]\, \inpB_rddata2[3]\, \inpB_rddata2[4]\, 
        \inpB_rddata2[5]\, \inpB_rddata2[6]\, \inpB_rddata2[7]\, 
        \inpB_rddata2[8]\, \inpB_rddata2[9]\, \inpB_rddata2[10]\, 
        \inpB_rddata2[11]\, \inpB_rddata2[12]\, 
        \inpB_rddata2[13]\, \inpB_rddata2[14]\, 
        \inpB_rddata2[15]\, \inpB_rddata2[16]\, 
        \inpB_rddata2[17]\, \mac_state[1]_net_1\, 
        \mac_state[4]_net_1\, \Transferdone\, \rdy_cnt[0]_net_1\, 
        \rdy_cnt[2]_net_1\, \rdy_cnt[3]_net_1\, 
        \rdy_cnt[4]_net_1\, \rdy_cnt[7]_net_1\, 
        \A_rdaddr[2]_net_1\, \A_rdaddr[3]_net_1\, 
        \A_rdaddr[4]_net_1\, \A_rdaddr[7]_net_1\, 
        \inpB_rdaddr[0]_net_1\, \inpB_rdaddr[1]_net_1\, 
        \inpB_rdaddr[2]_net_1\, \inpB_rdaddr[3]_net_1\, 
        \inpB_rdaddr[4]_net_1\, \inpB_rdaddr[5]_net_1\, 
        \inpB_rdaddr[6]_net_1\, \inpB_rdaddr[7]_net_1\, 
        \Coef_rdaddr[1]_net_1\, \Coef_rdaddr[2]_net_1\, 
        \Coef_rdaddr[3]_net_1\, \Coef_rdaddr[4]_net_1\, 
        \Coef_rdaddr[6]_net_1\, \Coef_rdaddr[7]_net_1\, 
        \inp_wraddr[0]_net_1\, \inp_wraddr[1]_net_1\, 
        \inp_wraddr[3]_net_1\, \inp_wraddr[4]_net_1\, 
        \inp_wraddr[7]_net_1\, \Coef_rdaddr[0]_net_1\, 
        \Coef_rdaddr[5]_net_1\, \clr\, \inp_wrdata[0]_net_1\, 
        \inp_wrdata[1]_net_1\, \inp_wrdata[2]_net_1\, 
        \inp_wrdata[3]_net_1\, \inp_wrdata[4]_net_1\, 
        \inp_wrdata[5]_net_1\, \inp_wrdata[6]_net_1\, 
        \inp_wrdata[7]_net_1\, \inp_wrdata[8]_net_1\, 
        \inp_wrdata[9]_net_1\, \inp_wrdata[10]_net_1\, 
        \inp_wrdata[11]_net_1\, \inp_wrdata[12]_net_1\, 
        \inp_wrdata[13]_net_1\, \inp_wrdata[14]_net_1\, 
        \inp_wrdata[15]_net_1\, \inp_wrdata[16]_net_1\, 
        \inp_wrdata[17]_net_1\, \Data_Valid_dly\, \Sel_Coef1\, 
        \Sel_InpA0\, \Sel_InpA1\, \Sel_InpB0\, \Sel_InpB1\, 
        \clrsig_1\, \clrsig_0\, \clrsig\, \FiltOp_done\, 
        \mac_state[0]_net_1\, \mac_state[2]_net_1\, 
        \un13_rdy_sig_0_a2_0_a2\, transferdone5, 
        \rdy_cnt[1]_net_1\, \rdy_cnt[5]_net_1\, 
        \rdy_cnt[6]_net_1\, \mac_state[3]_net_1\, 
        \op_eq.filtop_done3\, \inp_wraddr[2]_net_1\, 
        \inp_wraddr[5]_net_1\, \inp_wraddr[6]_net_1\, 
        \op_eq.new_data2\, \A_rdaddr[0]_net_1\, 
        \A_rdaddr[1]_net_1\, \A_rdaddr[5]_net_1\, 
        \A_rdaddr[6]_net_1\, \B_rdaddr[0]_net_1\, \New_data\, 
        \mac_state[5]_net_1\, 
        \un1_inp_wraddr_0_a2_0_a2_0[0]_net_1\, InpCoef0_wren_2, 
        InpCoef1_wren_1, \rdy_cnt_3[0]\, \rdy_cnt_3[1]\, 
        \rdy_cnt_3[5]\, InpA_rden0_1, InpB_rden0_1, 
        \un1_inpA_rddata2_10[1]\, \un1_inpA_rddata2_10[2]\, 
        \un1_inpA_rddata2_10[3]\, \un1_inpA_rddata2_10[4]\, 
        \un1_inpA_rddata2_10[5]\, \un1_inpA_rddata2_10[6]\, 
        \un1_inpA_rddata2_10[7]\, \un1_inpA_rddata2_10[8]\, 
        \un1_inpA_rddata2_10[9]\, \un1_inpA_rddata2_10[10]\, 
        \un1_inpA_rddata2_10[11]\, \un1_inpA_rddata2_10[12]\, 
        \un1_inpA_rddata2_10[13]\, \un1_inpA_rddata2_10[14]\, 
        \un1_inpA_rddata2_10[15]\, \un1_inpA_rddata2_10[16]\, 
        \un1_inpA_rddata2_10[17]\, \un1_inpA_rddata2_11[1]\, 
        \un1_inpA_rddata2_11[2]\, \un1_inpA_rddata2_11[3]\, 
        \un1_inpA_rddata2_11[4]\, \un1_inpA_rddata2_11[5]\, 
        \un1_inpA_rddata2_11[6]\, \un1_inpA_rddata2_11[7]\, 
        \un1_inpA_rddata2_11[8]\, \un1_inpA_rddata2_11[9]\, 
        \un1_inpA_rddata2_11[10]\, \un1_inpA_rddata2_11[11]\, 
        \un1_inpA_rddata2_11[12]\, \un1_inpA_rddata2_11[13]\, 
        \un1_inpA_rddata2_11[14]\, \un1_inpA_rddata2_11[15]\, 
        \un1_inpA_rddata2_11[16]\, \un1_inpA_rddata2_11[17]\, 
        \un1_inpA_rddata2_12[1]\, \un1_inpA_rddata2_12[2]\, 
        \un1_inpA_rddata2_12[3]\, \un1_inpA_rddata2_12[4]\, 
        \un1_inpA_rddata2_12[5]\, \un1_inpA_rddata2_12[6]\, 
        \un1_inpA_rddata2_12[7]\, \un1_inpA_rddata2_12[8]\, 
        \un1_inpA_rddata2_12[9]\, \un1_inpA_rddata2_12[10]\, 
        \un1_inpA_rddata2_12[11]\, \un1_inpA_rddata2_12[12]\, 
        \un1_inpA_rddata2_12[13]\, \un1_inpA_rddata2_12[14]\, 
        \un1_inpA_rddata2_12[15]\, \un1_inpA_rddata2_12[16]\, 
        \un1_inpA_rddata2_12[17]\, \un1_inpA_rddata2_13[1]\, 
        \un1_inpA_rddata2_13[2]\, \un1_inpA_rddata2_13[3]\, 
        \un1_inpA_rddata2_13[4]\, \un1_inpA_rddata2_13[5]\, 
        \un1_inpA_rddata2_13[6]\, \un1_inpA_rddata2_13[7]\, 
        \un1_inpA_rddata2_13[8]\, \un1_inpA_rddata2_13[9]\, 
        \un1_inpA_rddata2_13[10]\, \un1_inpA_rddata2_13[11]\, 
        \un1_inpA_rddata2_13[12]\, \un1_inpA_rddata2_13[13]\, 
        \un1_inpA_rddata2_13[14]\, \un1_inpA_rddata2_13[15]\, 
        \un1_inpA_rddata2_13[16]\, \un1_inpA_rddata2_13[17]\, 
        \mac_state_ns[1]\, \mac_state_ns[2]\, \mac_state_ns[3]\, 
        \mac_state_ns[4]\, \mac_state_ns[0]\, \inpB_rdaddr_4[0]\, 
        \inpB_rdaddr_4[1]\, \inpB_rdaddr_4[5]\, 
        \inpB_rdaddr_4[6]\, N_5, N_24, N_66, N_68, N_120, N_122, 
        N_123, N_124, N_125, N_127, N_128, N_129, N_131, N_146, 
        N_152, N_153, N_154, N_155, N_157, N_158, N_168, N_171, 
        N_174, N_177, N_180, N_183, N_186, N_189, 
        \inp_rddata_RNO[15]_net_1\, \inp_rddata_RNO[14]_net_1\, 
        N_198, N_201, N_204, N_207, N_210, N_213, N_216, N_219, 
        N_69, clk_c, reset_n_c, Filter_En_c, \Xn_in_c[0]\, 
        \Xn_in_c[1]\, \Xn_in_c[2]\, \Xn_in_c[3]\, \Xn_in_c[4]\, 
        \Xn_in_c[5]\, \Xn_in_c[6]\, \Xn_in_c[7]\, \Xn_in_c[8]\, 
        \Xn_in_c[9]\, \Xn_in_c[10]\, \Xn_in_c[11]\, \Xn_in_c[12]\, 
        \Xn_in_c[13]\, \Xn_in_c[14]\, \Xn_in_c[15]\, 
        \Xn_in_c[16]\, \Xn_in_c[17]\, Data_Valid_c, 
        \Mac_out_c[0]\, \Mac_out_c[1]\, \Mac_out_c[2]\, 
        \Mac_out_c[3]\, \Mac_out_c[4]\, \Mac_out_c[5]\, 
        \Mac_out_c[6]\, \Mac_out_c[7]\, \Mac_out_c[8]\, 
        \Mac_out_c[9]\, \Mac_out_c[10]\, \Mac_out_c[11]\, 
        \Mac_out_c[12]\, \Mac_out_c[13]\, \Mac_out_c[14]\, 
        \Mac_out_c[15]\, \Mac_out_c[16]\, \Mac_out_c[17]\, 
        \Mac_out_c[18]\, \Mac_out_c[19]\, \Mac_out_c[20]\, 
        \Mac_out_c[21]\, \Mac_out_c[22]\, \Mac_out_c[23]\, 
        \Mac_out_c[24]\, \Mac_out_c[25]\, \Mac_out_c[26]\, 
        \Mac_out_c[27]\, \Mac_out_c[28]\, \Mac_out_c[29]\, 
        \Mac_out_c[30]\, \Mac_out_c[31]\, \Mac_out_c[32]\, 
        \Mac_out_c[33]\, \Mac_out_c[34]\, \Mac_out_c[35]\, 
        \Mac_out_c[36]\, \Mac_out_c[37]\, \Mac_out_c[38]\, 
        \Mac_out_c[39]\, \Mac_out_c[40]\, \Mac_out_c[41]\, 
        \Mac_out_c[42]\, \Mac_out_c[43]\, N_1157, N_584, N_576, 
        N_568, N_560, N_552, N_543, N_20_1, N_14, N_19, 
        un1_inpA_rddata2_3_cry_16, \un1_coef_rdaddr_1_axbxc1\, 
        \un1_coef_rdaddr_1_axbxc2\, \un1_coef_rdaddr_1_axbxc3\, 
        \un1_coef_rdaddr_1_axbxc6\, \un1_coef_rdaddr_1_axbxc7\, 
        un1_coef_rdaddr_1_c2, un1_coef_rdaddr_1_c4, 
        un1_coef_rdaddr_1_c5, un1_coef_rdaddr_1_c6, 
        \un1_a_rdaddr_axbxc1\, \un1_a_rdaddr_axbxc3\, 
        \un1_a_rdaddr_axbxc4\, \un1_a_rdaddr_axbxc7\, 
        un1_a_rdaddr_c3, \un1_rdy_cnt_1_axbxc2\, 
        \un1_rdy_cnt_1_axbxc3\, un1_rdy_cnt_1_c1, 
        \un1_inp_wraddr_1_axbxc0\, \un1_inp_wraddr_1_axbxc1\, 
        \un1_inp_wraddr_1_axbxc3\, \un1_inp_wraddr_1_axbxc4\, 
        \un1_inp_wraddr_1_axbxc7\, un1_inpA_rddata2_cry_16, 
        un1_inpA_rddata2_0_cry_16, un1_inpA_rddata2_2_cry_16, 
        un1_inp_wraddr_1_ac0_3tt_N_7_mux, 
        \inp_wraddr_2_i_0_2_m5_e\, \un1_a_rdaddr_ac0_7_0\, 
        \un1_a_rdaddr_ac0_11_0\, \inpA_rdaddr[0]_net_1\, 
        \inpA_rdaddr_lm[0]\, \inpA_rdaddr[1]_net_1\, 
        \inpA_rdaddr_cry[1]_net_1\, \inpA_rdaddr_s[1]\, 
        \inpA_rdaddr_lm[1]\, \inpA_rdaddr[2]_net_1\, 
        \inpA_rdaddr_cry[2]_net_1\, \inpA_rdaddr_s[2]\, 
        \inpA_rdaddr_lm[2]\, \inpA_rdaddr[3]_net_1\, 
        \inpA_rdaddr_cry[3]_net_1\, \inpA_rdaddr_s[3]\, 
        \inpA_rdaddr_lm[3]\, \inpA_rdaddr[4]_net_1\, 
        \inpA_rdaddr_cry[4]_net_1\, \inpA_rdaddr_s[4]\, 
        \inpA_rdaddr_lm[4]\, \inpA_rdaddr[5]_net_1\, 
        \inpA_rdaddr_cry[5]_net_1\, \inpA_rdaddr_s[5]\, 
        \inpA_rdaddr_lm[5]\, \inpA_rdaddr[6]_net_1\, 
        \inpA_rdaddr_cry[6]_net_1\, \inpA_rdaddr_s[6]\, 
        \inpA_rdaddr_lm[6]\, \inpA_rdaddr[7]_net_1\, 
        \inpA_rdaddr_s[7]_net_1\, \inpA_rdaddr_lm[7]\, 
        \B_rdaddr_lm[0]\, \B_rdaddr[1]_net_1\, 
        \B_rdaddr_cry[1]_net_1\, \B_rdaddr_s[1]\, 
        \B_rdaddr_lm[1]\, \B_rdaddr[2]_net_1\, 
        \B_rdaddr_cry[2]_net_1\, \B_rdaddr_s[2]\, 
        \B_rdaddr_lm[2]\, \B_rdaddr[3]_net_1\, 
        \B_rdaddr_cry[3]_net_1\, \B_rdaddr_s[3]\, 
        \B_rdaddr_lm[3]\, \B_rdaddr[4]_net_1\, 
        \B_rdaddr_cry[4]_net_1\, \B_rdaddr_s[4]\, 
        \B_rdaddr_lm[4]\, \B_rdaddr[5]_net_1\, 
        \B_rdaddr_cry[5]_net_1\, \B_rdaddr_s[5]\, 
        \B_rdaddr_lm[5]\, \B_rdaddr[6]_net_1\, 
        \B_rdaddr_cry[6]_net_1\, \B_rdaddr_s[6]\, 
        \B_rdaddr_lm[6]\, \B_rdaddr[7]_net_1\, 
        \B_rdaddr_s[7]_net_1\, \B_rdaddr_lm[7]\, 
        inpB_rdaddr_4_1_0_m2_cry_0, inpB_rdaddr_4_1_0_m2_cry_1, 
        inpB_rdaddr_4_1_0_m2_cry_2, inpB_rdaddr_4_1_0_m2_cry_3, 
        inpB_rdaddr_4_1_0_m2_cry_4, inpB_rdaddr_4_1_0_m2_cry_5, 
        inpB_rdaddr_4_1_0_m2_cry_6, 
        un1_b_rdaddr10_i_0_627_0_0_a2_4, 
        un1_b_rdaddr10_i_0_627_0_0_a2_5, 
        \un1_rdy_cnt_1_axbxc4_m3_i_o2_1\, 
        \op_eq.filtop_done3_0_o3_0_net_1\, 
        \mac_state_ns_0_0_0[4]_net_1\, 
        \transferdone5_0_a2_0_a2_4\, \transferdone5_0_a2_0_a2_5\, 
        \mac_state_ns_a2_0_a2_0_a2_1[0]_net_1\, 
        \rdy_cnt_3_0_a2_0_a2_6_m3_i_o2_1\, 
        \rdy_cnt_3_0_a2_0_a2_6_m3_i_o2_2\, 
        \un1_rdy_cnt_1_axbxc7_m5_i_o2_3\, 
        \un1_rdy_cnt_1_axbxc7_m5_i_o2_4\, \un1_a_rdaddr_ac0_9_0\, 
        \A_rdaddr_2_i_0_a2_3[2]_net_1\, 
        \op_eq.new_data2_0_a2_2_net_1\, 
        \Coef_rdaddr_2_i_a2_0[1]_net_1\, 
        \Coef_rdaddr_2_i_a2_1[1]_net_1\, 
        \inpA_rdaddr_1_sqmuxa_i_0_0_a2_1\, 
        \un2_data_valid_dly_i_0_a2_3\, 
        \un2_data_valid_dly_i_0_a2_4\, 
        \un1_inp_wraddr_1_axbxc5_m2_i_o2_0\, 
        \un1_inp_wraddr_1_ac0_9_m1_0_a2_1\, 
        un1_rdy_cnt_1_ac0_7_0_0, 
        \inpB_rdaddr_4_i_0_a2_2[2]_net_1\, 
        \inpB_rdaddr_4_i_0_a2_3[2]_net_1\, 
        \un1_inp_wraddr_1_ac0_m1_0_a2_0\, un16_inp_wraddr_2_i_0, 
        \mac_state_i_0[0]\, N_108_i_0, N_107_i_0, 
        \A_rdaddr_i_0[0]\, N_141_i_0, N_51_i_0, N_49_i_0, 
        N_47_i_0, N_45_i_0, un1_sel_inpa0_4_i_0, N_7_i_0, N_8_i_0, 
        N_6_i_0, N_4_i_0, \Coef_rdaddr_i_0[0]\, N_36_i_0, 
        N_34_i_0, N_11_i_0, N_9_i_0, N_1068_i_0, 
        un1_rdy_cnt_1_axbxc7_N_13_i_i_0, 
        rdy_cnt_3_0_a2_0_a2_6_N_6_i_0, 
        un1_rdy_cnt_1_axbxc4_N_9_i_i_0, rdy_sig_4_iv_i_0, 
        N_156_i_0, N_526_i_0, N_518_i_0, N_510_i_0, N_502_i_0, 
        N_493_i_0, N_10_i_0, InpA_rden1_1_iv_i_0, 
        InpB_rden1_1_iv_i_0, N_163_i_0, N_161_i_0, clr_i_0, 
        un1_inpA_rddata2_1_m_3_11_339_i_m2_i_m2_ns_1, 
        un1_inpA_rddata2_1_m_3_603_i_m2_i_m2_1_2, 
        un1_inpA_rddata2_1_m_3_0_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_1_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_2_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_3_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_4_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_5_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_6_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_7_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_8_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_9_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_10_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_12_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_13_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_14_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_15_i_m2_i_m2_1_1, 
        un1_inpA_rddata2_1_m_3_16_i_m2_i_m2_1_1, 
        \un1_inp_wraddr_0_a2_0_a2_0_1[0]_net_1\, g1_0, g1_4, 
        B_rdaddr_s_705_FCO, inpA_rdaddr_s_706_FCO, 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIKTA7_Y, 
        Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS_Y, 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_Y, 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_0_Y, 
        \inpB_rdaddr_RNIE1OF_Y[0]\, \clk_ibuf\, \reset_n_ibuf\
         : std_logic;

    for all : Inp_RAM1
	Use entity work.Inp_RAM1(DEF_ARCH);
    for all : Inp_RAM
	Use entity work.Inp_RAM(DEF_ARCH);
    for all : mulacc_18x18
	Use entity work.mulacc_18x18(DEF_ARCH);
    for all : Coef_RAM
	Use entity work.Coef_RAM(DEF_ARCH);
begin 


    \rdy_cnt[5]\ : SLE
      port map(D => \rdy_cnt_3[5]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \rdy_cnt[5]_net_1\);
    
    \inpA_rdaddr_s[7]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \inpA_rdaddr[7]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => 
        \inpA_rdaddr_cry[6]_net_1\, S => \inpA_rdaddr_s[7]_net_1\, 
        Y => OPEN, FCO => OPEN);
    
    \Coef_rddata[10]\ : SLE
      port map(D => \Coef_rddata1[10]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[10]_net_1\);
    
    \Mac_out[23]\ : SLE
      port map(D => \Yn_out[23]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[23]\);
    
    \Xn_in_ibuf[12]\ : INBUF
      port map(PAD => Xn_in(12), Y => \Xn_in_c[12]\);
    
    \inp_wraddr2_RNO[3]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \inp_wraddr[6]_net_1\, B => 
        \inp_wraddr[3]_net_1\, Y => N_518_i_0);
    
    \inp_rddata[10]\ : SLE
      port map(D => N_207, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[10]_net_1\);
    
    \inpB_rdaddr[5]\ : SLE
      port map(D => \inpB_rdaddr_4[5]\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => GND_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inpB_rdaddr[5]_net_1\);
    
    \Mac_out[19]\ : SLE
      port map(D => \Yn_out[19]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[19]\);
    
    \inp_wraddr2[3]\ : SLE
      port map(D => N_518_i_0, CLK => clk_c, EN => 
        \un1_inp_wraddr_0_a2_0_a2_0[0]_net_1\, ALn => reset_n_c, 
        ADn => VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT
         => GND_net_1, Q => \inp_wraddr2[3]_net_1\);
    
    \Mac_out[43]\ : SLE
      port map(D => \Yn_out[43]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[43]\);
    
    rdy_cnt_3_0_a2_0_a2_6_N_6_i : CFG4
      generic map(INIT => x"4441")

      port map(A => \Transferdone\, B => \rdy_cnt[6]_net_1\, C
         => \rdy_cnt_3_0_a2_0_a2_6_m3_i_o2_2\, D => 
        \rdy_cnt_3_0_a2_0_a2_6_m3_i_o2_1\, Y => 
        rdy_cnt_3_0_a2_0_a2_6_N_6_i_0);
    
    un13_rdy_sig_0_a2_0_a2 : CFG2
      generic map(INIT => x"2")

      port map(A => \rdy_sig\, B => \Transferdone\, Y => 
        \un13_rdy_sig_0_a2_0_a2\);
    
    InpCoef0_wren : SLE
      port map(D => InpCoef0_wren_2, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \InpCoef0_wren\);
    
    \inpA_rdaddr_cry[1]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \inpA_rdaddr[1]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => inpA_rdaddr_s_706_FCO, 
        S => \inpA_rdaddr_s[1]\, Y => OPEN, FCO => 
        \inpA_rdaddr_cry[1]_net_1\);
    
    \inp_wrdata[7]\ : SLE
      port map(D => \Xn_in_c[7]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[7]_net_1\);
    
    \B_rdaddr_lm_0[1]\ : CFG4
      generic map(INIT => x"DCFC")

      port map(A => un1_b_rdaddr10_i_0_627_0_0_a2_5, B => 
        \Transferdone\, C => \B_rdaddr_s[1]\, D => 
        un1_b_rdaddr10_i_0_627_0_0_a2_4, Y => \B_rdaddr_lm[1]\);
    
    un1_a_rdaddr_axbxc4 : CFG3
      generic map(INIT => x"78")

      port map(A => \A_rdaddr[3]_net_1\, B => un1_a_rdaddr_c3, C
         => \A_rdaddr[4]_net_1\, Y => \un1_a_rdaddr_axbxc4\);
    
    \inp_wraddr1_RNO[0]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \inp_wraddr[6]_net_1\, B => 
        \inp_wraddr[0]_net_1\, Y => N_543);
    
    \Coef_rdaddr[2]\ : SLE
      port map(D => \un1_coef_rdaddr_1_axbxc2\, CLK => clk_c, EN
         => \mac_state[1]_net_1\, ALn => reset_n_c, ADn => 
        VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT => 
        GND_net_1, Q => \Coef_rdaddr[2]_net_1\);
    
    \B_rdaddr[7]\ : SLE
      port map(D => \B_rdaddr_lm[7]\, CLK => clk_c, EN => 
        N_108_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \B_rdaddr[7]_net_1\);
    
    \Xn_in_ibuf[16]\ : INBUF
      port map(PAD => Xn_in(16), Y => \Xn_in_c[16]\);
    
    \Coef_rddata[12]\ : SLE
      port map(D => \Coef_rddata1[12]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[12]_net_1\);
    
    \A_rdaddr_RNO[0]\ : CFG1
      generic map(INIT => x"1")

      port map(A => \A_rdaddr[0]_net_1\, Y => \A_rdaddr_i_0[0]\);
    
    \B_rdaddr_cry[1]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \B_rdaddr[1]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => B_rdaddr_s_705_FCO, S
         => \B_rdaddr_s[1]\, Y => OPEN, FCO => 
        \B_rdaddr_cry[1]_net_1\);
    
    \Xn_in_ibuf[6]\ : INBUF
      port map(PAD => Xn_in(6), Y => \Xn_in_c[6]\);
    
    \InpA_rdaddr1[2]\ : SLE
      port map(D => \inpA_rdaddr[2]_net_1\, CLK => clk_c, EN => 
        N_161_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \InpA_rdaddr1[2]_net_1\);
    
    \inp_wraddr[5]\ : SLE
      port map(D => N_9_i_0, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \inp_wraddr[5]_net_1\);
    
    \inpA_rdaddr_cry[2]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \inpA_rdaddr[2]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => 
        \inpA_rdaddr_cry[1]_net_1\, S => \inpA_rdaddr_s[2]\, Y
         => OPEN, FCO => \inpA_rdaddr_cry[2]_net_1\);
    
    \Coef_rdaddr_RNO[4]\ : CFG4
      generic map(INIT => x"134C")

      port map(A => \Coef_rdaddr_2_i_a2_0[1]_net_1\, B => 
        \Coef_rdaddr[4]_net_1\, C => 
        \Coef_rdaddr_2_i_a2_1[1]_net_1\, D => 
        un1_coef_rdaddr_1_c4, Y => N_6_i_0);
    
    \inp_rddata_RNO_0[1]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[1]\, D => \un1_inpA_rddata2_10[1]\, 
        Y => un1_inpA_rddata2_1_m_3_12_i_m2_i_m2_1_1);
    
    \B_rdaddr[0]\ : SLE
      port map(D => \B_rdaddr_lm[0]\, CLK => clk_c, EN => 
        N_108_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \B_rdaddr[0]_net_1\);
    
    \inp_rddata_RNO_1[17]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[17]\, D => \un1_inpA_rddata2_10[17]\, 
        Y => un1_inpA_rddata2_1_m_3_10_i_m2_i_m2_1_1);
    
    \A_rdaddr[2]\ : SLE
      port map(D => N_7_i_0, CLK => clk_c, EN => \FiltOp_done\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \A_rdaddr[2]_net_1\);
    
    \mac_state_ns_0_0[2]\ : CFG4
      generic map(INIT => x"F222")

      port map(A => \mac_state[3]_net_1\, B => \Transferdone\, C
         => Data_Valid_c, D => \mac_state[4]_net_1\, Y => 
        \mac_state_ns[2]\);
    
    \inp_wrdata_dly0[4]\ : SLE
      port map(D => \inp_wrdata[4]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[4]_net_1\);
    
    \inp_rddata[8]\ : SLE
      port map(D => N_213, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[8]_net_1\);
    
    \inp_rddata[11]\ : SLE
      port map(D => N_204, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[11]_net_1\);
    
    \inpA_rdaddr_lm_0[0]\ : CFG4
      generic map(INIT => x"C505")

      port map(A => \inpA_rdaddr[0]_net_1\, B => 
        \A_rdaddr[0]_net_1\, C => N_5, D => \mac_state[0]_net_1\, 
        Y => \inpA_rdaddr_lm[0]\);
    
    \inp_wrdata_dly0[12]\ : SLE
      port map(D => \inp_wrdata[12]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[12]_net_1\);
    
    \Mac_out[30]\ : SLE
      port map(D => \Yn_out[30]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[30]\);
    
    \inp_wrdata_dly0[15]\ : SLE
      port map(D => \inp_wrdata[15]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[15]_net_1\);
    
    \inp_wraddr2_RNO[2]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \inp_wraddr[6]_net_1\, B => 
        \inp_wraddr[2]_net_1\, Y => N_510_i_0);
    
    \inp_wraddr1[0]\ : SLE
      port map(D => N_543, CLK => clk_c, EN => 
        \un1_inp_wraddr_0_a2_0_a2_0[0]_net_1\, ALn => reset_n_c, 
        ADn => VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT
         => GND_net_1, Q => \inp_wraddr1[0]_net_1\);
    
    \inp_rddata_RNO_4[17]\ : ARI1
      generic map(INIT => x"46600")

      port map(A => VCC_net_1, B => \inpA_rddata2[17]\, C => 
        \inpB_rddata2[17]\, D => GND_net_1, FCI => 
        un1_inpA_rddata2_cry_16, S => \un1_inpA_rddata2_10[17]\, 
        Y => OPEN, FCO => OPEN);
    
    \InpB_rdaddr1[4]\ : SLE
      port map(D => \inpB_rdaddr[4]_net_1\, CLK => clk_c, EN => 
        N_163_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \InpB_rdaddr1[4]_net_1\);
    
    un1_inp_wraddr_1_axbxc0 : CFG4
      generic map(INIT => x"C666")

      port map(A => \Data_Valid_dly\, B => \inp_wraddr[0]_net_1\, 
        C => \un2_data_valid_dly_i_0_a2_4\, D => 
        \un2_data_valid_dly_i_0_a2_3\, Y => 
        \un1_inp_wraddr_1_axbxc0\);
    
    \mac_state[4]\ : SLE
      port map(D => \mac_state_ns[1]\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \mac_state[4]_net_1\);
    
    \inpB_rdaddr_RNO_1[7]\ : ARI1
      generic map(INIT => x"43CAA")

      port map(A => \mac_state_i_0[0]\, B => \B_rdaddr[7]_net_1\, 
        C => \inpB_rdaddr[7]_net_1\, D => \mac_state[1]_net_1\, 
        FCI => inpB_rdaddr_4_1_0_m2_cry_6, S => N_125, Y => OPEN, 
        FCO => OPEN);
    
    \inpB_rdaddr_4_1_0[1]\ : CFG4
      generic map(INIT => x"CECC")

      port map(A => \inpB_rdaddr_4_i_0_a2_2[2]_net_1\, B => N_127, 
        C => N_66, D => \inpB_rdaddr_4_i_0_a2_3[2]_net_1\, Y => 
        \inpB_rdaddr_4[1]\);
    
    un1_inp_wraddr_1_ac0_3tt_m3_e : CFG4
      generic map(INIT => x"8000")

      port map(A => \inp_wraddr[2]_net_1\, B => 
        \inp_wraddr[1]_net_1\, C => \Data_Valid_dly\, D => 
        \inp_wraddr[0]_net_1\, Y => 
        un1_inp_wraddr_1_ac0_3tt_N_7_mux);
    
    \inp_wraddr[0]\ : SLE
      port map(D => \un1_inp_wraddr_1_axbxc0\, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wraddr[0]_net_1\);
    
    \inpA_rdaddr_lm_0[7]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => \inpA_rdaddr_s[7]_net_1\, B => N_5, C => 
        N_158, Y => \inpA_rdaddr_lm[7]\);
    
    InpA_rden0_1_iv_0_o3 : CFG3
      generic map(INIT => x"FE")

      port map(A => \inpA_rdaddr[4]_net_1\, B => 
        \inpA_rdaddr[3]_net_1\, C => \inpA_rdaddr[2]_net_1\, Y
         => N_68);
    
    \Mac_out_obuf[42]\ : OUTBUF
      port map(D => \Mac_out_c[42]\, PAD => Mac_out(42));
    
    \inp_rddata_RNO[3]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[3]\, B => 
        un1_inpA_rddata2_1_m_3_14_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[3]\, Y => N_174);
    
    \Mac_out_obuf[32]\ : OUTBUF
      port map(D => \Mac_out_c[32]\, PAD => Mac_out(32));
    
    un1_coef_rdaddr_1_axbxc2 : CFG2
      generic map(INIT => x"6")

      port map(A => un1_coef_rdaddr_1_c2, B => 
        \Coef_rdaddr[2]_net_1\, Y => \un1_coef_rdaddr_1_axbxc2\);
    
    un1_coef_rdaddr_1_ac0_7 : CFG4
      generic map(INIT => x"8000")

      port map(A => \Coef_rdaddr[2]_net_1\, B => 
        un1_coef_rdaddr_1_c2, C => \Coef_rdaddr[4]_net_1\, D => 
        \Coef_rdaddr[3]_net_1\, Y => un1_coef_rdaddr_1_c5);
    
    \Mac_out_obuf[15]\ : OUTBUF
      port map(D => \Mac_out_c[15]\, PAD => Mac_out(15));
    
    Data_Valid_dly : SLE
      port map(D => Data_Valid_c, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Data_Valid_dly\);
    
    \inp_wraddr_RNO[6]\ : CFG4
      generic map(INIT => x"060C")

      port map(A => \un1_inp_wraddr_1_ac0_9_m1_0_a2_1\, B => 
        \inp_wraddr[6]_net_1\, C => N_1157, D => 
        un1_inp_wraddr_1_ac0_3tt_N_7_mux, Y => N_11_i_0);
    
    \inp_wraddr2[0]\ : SLE
      port map(D => N_493_i_0, CLK => clk_c, EN => 
        \un1_inp_wraddr_0_a2_0_a2_0[0]_net_1\, ALn => reset_n_c, 
        ADn => VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT
         => GND_net_1, Q => \inp_wraddr2[0]_net_1\);
    
    \A_rdaddr_RNO[5]\ : CFG4
      generic map(INIT => x"060C")

      port map(A => \un1_a_rdaddr_ac0_7_0\, B => 
        \A_rdaddr[5]_net_1\, C => N_146, D => un1_a_rdaddr_c3, Y
         => N_34_i_0);
    
    un1_rdy_cnt_1_axbxc2 : CFG4
      generic map(INIT => x"78F0")

      port map(A => \rdy_cnt[0]_net_1\, B => 
        \un13_rdy_sig_0_a2_0_a2\, C => \rdy_cnt[2]_net_1\, D => 
        \rdy_cnt[1]_net_1\, Y => \un1_rdy_cnt_1_axbxc2\);
    
    \InpB_rdaddr1[5]\ : SLE
      port map(D => \inpB_rdaddr[5]_net_1\, CLK => clk_c, EN => 
        N_163_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \InpB_rdaddr1[5]_net_1\);
    
    \Mac_out_obuf[36]\ : OUTBUF
      port map(D => \Mac_out_c[36]\, PAD => Mac_out(36));
    
    \Mac_out_obuf[22]\ : OUTBUF
      port map(D => \Mac_out_c[22]\, PAD => Mac_out(22));
    
    \inp_wrdata[5]\ : SLE
      port map(D => \Xn_in_c[5]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[5]_net_1\);
    
    \B_rdaddr[2]\ : SLE
      port map(D => \B_rdaddr_lm[2]\, CLK => clk_c, EN => 
        N_108_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \B_rdaddr[2]_net_1\);
    
    \mac_state[2]\ : SLE
      port map(D => \mac_state_ns[3]\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \mac_state[2]_net_1\);
    
    \inpB_rdaddr_RNO_2[7]\ : CFG2
      generic map(INIT => x"E")

      port map(A => \inpB_rdaddr[6]_net_1\, B => 
        \inpB_rdaddr[7]_net_1\, Y => g1_0);
    
    \inpB_rdaddr_RNIQROE2[4]\ : ARI1
      generic map(INIT => x"58DD8")

      port map(A => \mac_state[1]_net_1\, B => 
        \mac_state[0]_net_1\, C => \B_rdaddr[4]_net_1\, D => 
        \inpB_rdaddr[4]_net_1\, FCI => inpB_rdaddr_4_1_0_m2_cry_3, 
        S => N_124, Y => OPEN, FCO => inpB_rdaddr_4_1_0_m2_cry_4);
    
    \inpA_rdaddr_lm_0[5]\ : CFG3
      generic map(INIT => x"2E")

      port map(A => \inpA_rdaddr_s[5]\, B => N_5, C => N_24, Y
         => \inpA_rdaddr_lm[5]\);
    
    \inpA_rdaddr_lm_0[3]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => \inpA_rdaddr_s[3]\, B => N_5, C => N_155, Y
         => \inpA_rdaddr_lm[3]\);
    
    Transferdone : SLE
      port map(D => transferdone5, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Transferdone\);
    
    \inp_rddata_RNO_0[13]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[13]\, D => \un1_inpA_rddata2_10[13]\, 
        Y => un1_inpA_rddata2_1_m_3_6_i_m2_i_m2_1_1);
    
    \inpB_rdaddr[6]\ : SLE
      port map(D => \inpB_rdaddr_4[6]\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => GND_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inpB_rdaddr[6]_net_1\);
    
    \Mac_out_obuf[41]\ : OUTBUF
      port map(D => \Mac_out_c[41]\, PAD => Mac_out(41));
    
    \Mac_out[8]\ : SLE
      port map(D => \Yn_out[8]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[8]\);
    
    \inpA_rdaddr_cry[5]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \inpA_rdaddr[5]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => 
        \inpA_rdaddr_cry[4]_net_1\, S => \inpA_rdaddr_s[5]\, Y
         => OPEN, FCO => \inpA_rdaddr_cry[5]_net_1\);
    
    \inpA_rdaddr_4_i_i_a2[7]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \mac_state[0]_net_1\, B => 
        \A_rdaddr[7]_net_1\, Y => N_158);
    
    un1_coef_rdaddr_1_ac0_1 : CFG2
      generic map(INIT => x"8")

      port map(A => \Coef_rdaddr[0]_net_1\, B => 
        \Coef_rdaddr[1]_net_1\, Y => un1_coef_rdaddr_1_c2);
    
    \mac_state[5]\ : SLE
      port map(D => \mac_state_ns[0]\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => GND_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \mac_state[5]_net_1\);
    
    \Mac_out[31]\ : SLE
      port map(D => \Yn_out[31]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[31]\);
    
    \inpB_rdaddr_RNO[4]\ : CFG4
      generic map(INIT => x"C4CC")

      port map(A => \inpB_rdaddr_4_i_0_a2_2[2]_net_1\, B => N_124, 
        C => N_66, D => \inpB_rdaddr_4_i_0_a2_3[2]_net_1\, Y => 
        N_49_i_0);
    
    un2_data_valid_dly_i_0_a2_4 : CFG4
      generic map(INIT => x"0040")

      port map(A => \inp_wraddr[3]_net_1\, B => 
        \inp_wraddr[6]_net_1\, C => \inp_wraddr[5]_net_1\, D => 
        \inp_wraddr[4]_net_1\, Y => \un2_data_valid_dly_i_0_a2_4\);
    
    \Mac_out_obuf[31]\ : OUTBUF
      port map(D => \Mac_out_c[31]\, PAD => Mac_out(31));
    
    \B_rdaddr_lm_0[2]\ : CFG4
      generic map(INIT => x"1030")

      port map(A => un1_b_rdaddr10_i_0_627_0_0_a2_5, B => 
        \Transferdone\, C => \B_rdaddr_s[2]\, D => 
        un1_b_rdaddr10_i_0_627_0_0_a2_4, Y => \B_rdaddr_lm[2]\);
    
    \Mac_out_obuf[26]\ : OUTBUF
      port map(D => \Mac_out_c[26]\, PAD => Mac_out(26));
    
    \inp_rddata_RNO_3[17]\ : ARI1
      generic map(INIT => x"46600")

      port map(A => VCC_net_1, B => \inpA_rddata2[17]\, C => 
        \inpB_rddata1[17]\, D => GND_net_1, FCI => 
        un1_inpA_rddata2_2_cry_16, S => \un1_inpA_rddata2_12[17]\, 
        Y => OPEN, FCO => OPEN);
    
    \op_eq.new_data2_0_a2_2\ : CFG3
      generic map(INIT => x"80")

      port map(A => \Coef_rdaddr[5]_net_1\, B => 
        \Coef_rdaddr[2]_net_1\, C => \Coef_rdaddr[0]_net_1\, Y
         => \op_eq.new_data2_0_a2_2_net_1\);
    
    \inpB_rdaddr_RNI4I0V1[3]\ : ARI1
      generic map(INIT => x"58DD8")

      port map(A => \mac_state[1]_net_1\, B => 
        \mac_state[0]_net_1\, C => \B_rdaddr[3]_net_1\, D => 
        \inpB_rdaddr[3]_net_1\, FCI => inpB_rdaddr_4_1_0_m2_cry_2, 
        S => N_123, Y => OPEN, FCO => inpB_rdaddr_4_1_0_m2_cry_3);
    
    \B_rdaddr_cry[5]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \B_rdaddr[5]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => \B_rdaddr_cry[4]_net_1\, 
        S => \B_rdaddr_s[5]\, Y => OPEN, FCO => 
        \B_rdaddr_cry[5]_net_1\);
    
    \rdy_cnt_3_0_a2_0_a2[5]\ : CFG4
      generic map(INIT => x"1444")

      port map(A => \Transferdone\, B => \rdy_cnt[5]_net_1\, C
         => un1_rdy_cnt_1_c1, D => un1_rdy_cnt_1_ac0_7_0_0, Y => 
        \rdy_cnt_3[5]\);
    
    \inp_rddata[16]\ : SLE
      port map(D => N_189, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[16]_net_1\);
    
    \Coef_rddata[17]\ : SLE
      port map(D => \Coef_rddata1[17]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[17]_net_1\);
    
    \op_eq.filtop_done3_0_a2\ : CFG3
      generic map(INIT => x"10")

      port map(A => \op_eq.filtop_done3_0_o3_0_net_1\, B => N_14, 
        C => N_20_1, Y => \op_eq.filtop_done3\);
    
    \Xn_in_ibuf[17]\ : INBUF
      port map(PAD => Xn_in(17), Y => \Xn_in_c[17]\);
    
    \Mac_out[28]\ : SLE
      port map(D => \Yn_out[28]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[28]\);
    
    \inpB_rdaddr_4_i_0_a2_2[2]\ : CFG2
      generic map(INIT => x"2")

      port map(A => \mac_state[1]_net_1\, B => 
        \inpB_rdaddr[5]_net_1\, Y => 
        \inpB_rdaddr_4_i_0_a2_2[2]_net_1\);
    
    \InpB_rdaddr1[3]\ : SLE
      port map(D => \inpB_rdaddr[3]_net_1\, CLK => clk_c, EN => 
        N_163_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \InpB_rdaddr1[3]_net_1\);
    
    \Coef_rdaddr_2_i_a2_0[1]\ : CFG3
      generic map(INIT => x"10")

      port map(A => \Coef_rdaddr[3]_net_1\, B => 
        \Coef_rdaddr[2]_net_1\, C => \Coef_rdaddr[0]_net_1\, Y
         => \Coef_rdaddr_2_i_a2_0[1]_net_1\);
    
    \A_rdaddr[4]\ : SLE
      port map(D => \un1_a_rdaddr_axbxc4\, CLK => clk_c, EN => 
        \FiltOp_done\, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \A_rdaddr[4]_net_1\);
    
    \inpB_rdaddr_4_1_0[5]\ : CFG4
      generic map(INIT => x"CECC")

      port map(A => \inpB_rdaddr_4_i_0_a2_2[2]_net_1\, B => N_128, 
        C => N_66, D => \inpB_rdaddr_4_i_0_a2_3[2]_net_1\, Y => 
        \inpB_rdaddr_4[5]\);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    un1_coef_rdaddr_1_axbxc1 : CFG2
      generic map(INIT => x"6")

      port map(A => \Coef_rdaddr[0]_net_1\, B => 
        \Coef_rdaddr[1]_net_1\, Y => \un1_coef_rdaddr_1_axbxc1\);
    
    un1_a_rdaddr_ac0_3 : CFG3
      generic map(INIT => x"80")

      port map(A => \A_rdaddr[2]_net_1\, B => \A_rdaddr[1]_net_1\, 
        C => \A_rdaddr[0]_net_1\, Y => un1_a_rdaddr_c3);
    
    rdy_cnt_3_0_a2_0_a2_6_m3_i_o2_1 : CFG3
      generic map(INIT => x"7F")

      port map(A => \rdy_cnt[0]_net_1\, B => \rdy_sig\, C => 
        \rdy_cnt[5]_net_1\, Y => 
        \rdy_cnt_3_0_a2_0_a2_6_m3_i_o2_1\);
    
    \Mac_out_obuf[40]\ : OUTBUF
      port map(D => \Mac_out_c[40]\, PAD => Mac_out(40));
    
    \Mac_out_obuf[21]\ : OUTBUF
      port map(D => \Mac_out_c[21]\, PAD => Mac_out(21));
    
    InpB_rden1_1_iv_0_0_o2_RNIKH9O : CFG3
      generic map(INIT => x"DF")

      port map(A => \inpB_rdaddr[5]_net_1\, B => N_131, C => N_66, 
        Y => N_163_i_0);
    
    \Xn_in_ibuf[8]\ : INBUF
      port map(PAD => Xn_in(8), Y => \Xn_in_c[8]\);
    
    \Mac_out_obuf[30]\ : OUTBUF
      port map(D => \Mac_out_c[30]\, PAD => Mac_out(30));
    
    \inp_rddata_RNO_2[17]\ : ARI1
      generic map(INIT => x"46600")

      port map(A => VCC_net_1, B => \inpA_rddata1[17]\, C => 
        \inpB_rddata1[17]\, D => GND_net_1, FCI => 
        un1_inpA_rddata2_3_cry_16, S => \un1_inpA_rddata2_13[17]\, 
        Y => OPEN, FCO => OPEN);
    
    \inp_wraddr1_RNO[1]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \inp_wraddr[6]_net_1\, B => 
        \inp_wraddr[1]_net_1\, Y => N_552);
    
    \B_rdaddr_lm_0[0]\ : CFG4
      generic map(INIT => x"ABBB")

      port map(A => \Transferdone\, B => \B_rdaddr[0]_net_1\, C
         => un1_b_rdaddr10_i_0_627_0_0_a2_4, D => 
        un1_b_rdaddr10_i_0_627_0_0_a2_5, Y => \B_rdaddr_lm[0]\);
    
    Sel_InpA1 : SLE
      port map(D => \InpA_rden1\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Sel_InpA1\);
    
    \Mac_out_obuf[1]\ : OUTBUF
      port map(D => \Mac_out_c[1]\, PAD => Mac_out(1));
    
    un1_inp_wraddr_1_ac0_m1_0_a2_0 : CFG2
      generic map(INIT => x"8")

      port map(A => \Data_Valid_dly\, B => \inp_wraddr[0]_net_1\, 
        Y => \un1_inp_wraddr_1_ac0_m1_0_a2_0\);
    
    \inp_wrdata[8]\ : SLE
      port map(D => \Xn_in_c[8]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[8]_net_1\);
    
    \Xn_in_ibuf[10]\ : INBUF
      port map(PAD => Xn_in(10), Y => \Xn_in_c[10]\);
    
    reset_n_ibuf : INBUF
      port map(PAD => reset_n, Y => \reset_n_ibuf\);
    
    \inp_wraddr2[1]\ : SLE
      port map(D => N_502_i_0, CLK => clk_c, EN => 
        \un1_inp_wraddr_0_a2_0_a2_0[0]_net_1\, ALn => reset_n_c, 
        ADn => VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT
         => GND_net_1, Q => \inp_wraddr2[1]_net_1\);
    
    \inpB_rdaddr_4_i_0_a2_3[2]\ : CFG4
      generic map(INIT => x"0001")

      port map(A => \inpB_rdaddr[7]_net_1\, B => 
        \inpB_rdaddr[6]_net_1\, C => \inpB_rdaddr[1]_net_1\, D
         => \inpB_rdaddr[0]_net_1\, Y => 
        \inpB_rdaddr_4_i_0_a2_3[2]_net_1\);
    
    Sel_InpA0 : SLE
      port map(D => \InpA_rden0\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Sel_InpA0\);
    
    \rdy_cnt_RNO[7]\ : CFG4
      generic map(INIT => x"C9CC")

      port map(A => \un1_rdy_cnt_1_axbxc7_m5_i_o2_3\, B => 
        \rdy_cnt[7]_net_1\, C => \un1_rdy_cnt_1_axbxc7_m5_i_o2_4\, 
        D => \un13_rdy_sig_0_a2_0_a2\, Y => 
        un1_rdy_cnt_1_axbxc7_N_13_i_i_0);
    
    \inp_wrdata[2]\ : SLE
      port map(D => \Xn_in_c[2]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[2]_net_1\);
    
    \Mac_out[13]\ : SLE
      port map(D => \Yn_out[13]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[13]\);
    
    \Mac_out[32]\ : SLE
      port map(D => \Yn_out[32]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[32]\);
    
    \inp_wraddr1[1]\ : SLE
      port map(D => N_552, CLK => clk_c, EN => 
        \un1_inp_wraddr_0_a2_0_a2_0[0]_net_1\, ALn => reset_n_c, 
        ADn => VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT
         => GND_net_1, Q => \inp_wraddr1[1]_net_1\);
    
    \Coef_rdaddr1[2]\ : SLE
      port map(D => \Coef_rdaddr[2]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rdaddr1[2]_net_1\);
    
    \Mac_out_obuf[20]\ : OUTBUF
      port map(D => \Mac_out_c[20]\, PAD => Mac_out(20));
    
    \inp_rddata_RNO[14]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[14]\, B => 
        un1_inpA_rddata2_1_m_3_7_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[14]\, Y => 
        \inp_rddata_RNO[14]_net_1\);
    
    un1_inp_wraddr_1_axbxc3 : CFG2
      generic map(INIT => x"6")

      port map(A => un1_inp_wraddr_1_ac0_3tt_N_7_mux, B => 
        \inp_wraddr[3]_net_1\, Y => \un1_inp_wraddr_1_axbxc3\);
    
    \inpB_rdaddr[2]\ : SLE
      port map(D => N_45_i_0, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \inpB_rdaddr[2]_net_1\);
    
    un1_inp_wraddr_1_ac0_9_m1_0_a2_1 : CFG3
      generic map(INIT => x"80")

      port map(A => \inp_wraddr[5]_net_1\, B => 
        \inp_wraddr[4]_net_1\, C => \inp_wraddr[3]_net_1\, Y => 
        \un1_inp_wraddr_1_ac0_9_m1_0_a2_1\);
    
    \rdy_cnt[6]\ : SLE
      port map(D => rdy_cnt_3_0_a2_0_a2_6_N_6_i_0, CLK => clk_c, 
        EN => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \rdy_cnt[6]_net_1\);
    
    \mac_state_RNIJG98[0]\ : CFG2
      generic map(INIT => x"E")

      port map(A => \mac_state[1]_net_1\, B => 
        \mac_state[0]_net_1\, Y => N_107_i_0);
    
    inp_wraddr_2_i_0_2_m5_e : CFG3
      generic map(INIT => x"80")

      port map(A => \inp_wraddr[1]_net_1\, B => 
        \inp_wraddr[0]_net_1\, C => \Data_Valid_dly\, Y => 
        \inp_wraddr_2_i_0_2_m5_e\);
    
    \inpA_rdaddr[0]\ : SLE
      port map(D => \inpA_rdaddr_lm[0]\, CLK => clk_c, EN => 
        N_107_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inpA_rdaddr[0]_net_1\);
    
    \A_rdaddr[1]\ : SLE
      port map(D => \un1_a_rdaddr_axbxc1\, CLK => clk_c, EN => 
        \FiltOp_done\, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \A_rdaddr[1]_net_1\);
    
    transferdone5_0_a2_0_a2 : CFG4
      generic map(INIT => x"2000")

      port map(A => \rdy_cnt[1]_net_1\, B => \rdy_cnt[3]_net_1\, 
        C => \transferdone5_0_a2_0_a2_5\, D => 
        \transferdone5_0_a2_0_a2_4\, Y => transferdone5);
    
    \inp_rddata[14]\ : SLE
      port map(D => \inp_rddata_RNO[14]_net_1\, CLK => clk_c, EN
         => un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => 
        VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT => 
        GND_net_1, Q => \inp_rddata[14]_net_1\);
    
    clr_RNI1SC3 : CFG1
      generic map(INIT => x"1")

      port map(A => \clr\, Y => clr_i_0);
    
    \B_rdaddr[4]\ : SLE
      port map(D => \B_rdaddr_lm[4]\, CLK => clk_c, EN => 
        N_108_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \B_rdaddr[4]_net_1\);
    
    \A_rdaddr_2_i_0_a2_3[2]\ : CFG4
      generic map(INIT => x"0100")

      port map(A => \A_rdaddr[7]_net_1\, B => \A_rdaddr[4]_net_1\, 
        C => \A_rdaddr[2]_net_1\, D => \A_rdaddr[1]_net_1\, Y => 
        \A_rdaddr_2_i_0_a2_3[2]_net_1\);
    
    \inp_rddata[2]\ : SLE
      port map(D => N_177, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[2]_net_1\);
    
    \Mac_out_obuf[18]\ : OUTBUF
      port map(D => \Mac_out_c[18]\, PAD => Mac_out(18));
    
    \inpA_rdaddr[3]\ : SLE
      port map(D => \inpA_rdaddr_lm[3]\, CLK => clk_c, EN => 
        N_107_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inpA_rdaddr[3]_net_1\);
    
    rdy_sig_RNO : CFG3
      generic map(INIT => x"FE")

      port map(A => \mac_state[1]_net_1\, B => 
        \mac_state[4]_net_1\, C => \Transferdone\, Y => N_156_i_0);
    
    rdy_obuf : OUTBUF
      port map(D => \rdy_sig\, PAD => rdy);
    
    \inp_rddata_RNO_0[8]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[8]\, D => \un1_inpA_rddata2_10[8]\, 
        Y => un1_inpA_rddata2_1_m_3_1_i_m2_i_m2_1_1);
    
    \Mac_out_obuf[8]\ : OUTBUF
      port map(D => \Mac_out_c[8]\, PAD => Mac_out(8));
    
    \A_rdaddr[6]\ : SLE
      port map(D => N_36_i_0, CLK => clk_c, EN => \FiltOp_done\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \A_rdaddr[6]_net_1\);
    
    un1_coef_rdaddr_1_ac0_9 : CFG4
      generic map(INIT => x"8000")

      port map(A => \Coef_rdaddr[2]_net_1\, B => 
        \Coef_rdaddr[3]_net_1\, C => un1_coef_rdaddr_1_c2, D => 
        N_20_1, Y => un1_coef_rdaddr_1_c6);
    
    \inpA_rdaddr[1]\ : SLE
      port map(D => \inpA_rdaddr_lm[1]\, CLK => clk_c, EN => 
        N_107_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inpA_rdaddr[1]_net_1\);
    
    InpCoef1_wren_1_0_a2_0_a2 : CFG4
      generic map(INIT => x"0800")

      port map(A => \inp_wraddr[6]_net_1\, B => N_120, C => 
        \inp_wraddr[7]_net_1\, D => \Data_Valid_dly\, Y => 
        InpCoef1_wren_1);
    
    \inpB_rdaddr_RNO[2]\ : CFG4
      generic map(INIT => x"C4CC")

      port map(A => \inpB_rdaddr_4_i_0_a2_2[2]_net_1\, B => N_122, 
        C => N_66, D => \inpB_rdaddr_4_i_0_a2_3[2]_net_1\, Y => 
        N_45_i_0);
    
    InpA_rden0_1_iv_0_o2 : CFG2
      generic map(INIT => x"D")

      port map(A => \inpA_rdaddr[6]_net_1\, B => 
        \inpA_rdaddr[7]_net_1\, Y => N_69);
    
    \Mac_out_obuf[14]\ : OUTBUF
      port map(D => \Mac_out_c[14]\, PAD => Mac_out(14));
    
    un1_a_rdaddr_ac0_7_0 : CFG2
      generic map(INIT => x"8")

      port map(A => \A_rdaddr[3]_net_1\, B => \A_rdaddr[4]_net_1\, 
        Y => \un1_a_rdaddr_ac0_7_0\);
    
    \Mac_out[7]\ : SLE
      port map(D => \Yn_out[7]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[7]\);
    
    \Coef_rdaddr_2_i_a2_1_0[1]\ : CFG4
      generic map(INIT => x"0004")

      port map(A => \Coef_rdaddr[1]_net_1\, B => N_20_1, C => 
        \Coef_rdaddr[7]_net_1\, D => \Coef_rdaddr[6]_net_1\, Y
         => \Coef_rdaddr_2_i_a2_1[1]_net_1\);
    
    InpA_rden1 : SLE
      port map(D => InpA_rden1_1_iv_i_0, CLK => clk_c, EN => 
        \mac_state[1]_net_1\, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \InpA_rden1\);
    
    InpA_rden0 : SLE
      port map(D => InpA_rden0_1, CLK => clk_c, EN => 
        \mac_state[1]_net_1\, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \InpA_rden0\);
    
    \inp_rddata_RNO[12]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[12]\, B => 
        un1_inpA_rddata2_1_m_3_5_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[12]\, Y => N_201);
    
    \B_rdaddr_RNIKVJK[1]\ : CFG4
      generic map(INIT => x"8000")

      port map(A => \B_rdaddr[6]_net_1\, B => \B_rdaddr[5]_net_1\, 
        C => \B_rdaddr[1]_net_1\, D => \B_rdaddr[0]_net_1\, Y => 
        un1_b_rdaddr10_i_0_627_0_0_a2_4);
    
    \inp_wrdata[13]\ : SLE
      port map(D => \Xn_in_c[13]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[13]_net_1\);
    
    \Xn_in_ibuf[3]\ : INBUF
      port map(PAD => Xn_in(3), Y => \Xn_in_c[3]\);
    
    \inpA_rdaddr_cry[4]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \inpA_rdaddr[4]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => 
        \inpA_rdaddr_cry[3]_net_1\, S => \inpA_rdaddr_s[4]\, Y
         => OPEN, FCO => \inpA_rdaddr_cry[4]_net_1\);
    
    \Mac_out_obuf[0]\ : OUTBUF
      port map(D => \Mac_out_c[0]\, PAD => Mac_out(0));
    
    \B_rdaddr_lm_0[3]\ : CFG4
      generic map(INIT => x"1030")

      port map(A => un1_b_rdaddr10_i_0_627_0_0_a2_5, B => 
        \Transferdone\, C => \B_rdaddr_s[3]\, D => 
        un1_b_rdaddr10_i_0_627_0_0_a2_4, Y => \B_rdaddr_lm[3]\);
    
    \inp_wraddr[2]\ : SLE
      port map(D => N_1068_i_0, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wraddr[2]_net_1\);
    
    \Xn_in_ibuf[5]\ : INBUF
      port map(PAD => Xn_in(5), Y => \Xn_in_c[5]\);
    
    \Mac_out[37]\ : SLE
      port map(D => \Yn_out[37]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[37]\);
    
    clrsig : SLE
      port map(D => N_141_i_0, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \clrsig\);
    
    \inp_wrdata[17]\ : SLE
      port map(D => \Xn_in_c[17]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[17]_net_1\);
    
    \inp_rddata[9]\ : SLE
      port map(D => N_210, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[9]_net_1\);
    
    \inp_wraddr1_RNO[5]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \inp_wraddr[6]_net_1\, B => 
        \inp_wraddr[5]_net_1\, Y => N_584);
    
    \Mac_out[5]\ : SLE
      port map(D => \Yn_out[5]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[5]\);
    
    \B_rdaddr[1]\ : SLE
      port map(D => \B_rdaddr_lm[1]\, CLK => clk_c, EN => 
        N_108_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \B_rdaddr[1]_net_1\);
    
    \inp_rddata_RNO[10]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[10]\, B => 
        un1_inpA_rddata2_1_m_3_3_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[10]\, Y => N_207);
    
    \inpB_rdaddr_RNO[3]\ : CFG4
      generic map(INIT => x"C4CC")

      port map(A => \inpB_rdaddr_4_i_0_a2_2[2]_net_1\, B => N_123, 
        C => N_66, D => \inpB_rdaddr_4_i_0_a2_3[2]_net_1\, Y => 
        N_47_i_0);
    
    FiltOp_done_RNIUBVJ : CFG2
      generic map(INIT => x"E")

      port map(A => \FiltOp_done\, B => \Transferdone\, Y => 
        N_108_i_0);
    
    \Mac_out[20]\ : SLE
      port map(D => \Yn_out[20]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[20]\);
    
    \inp_wrdata_dly0[17]\ : SLE
      port map(D => \inp_wrdata[17]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[17]_net_1\);
    
    un1_inp_wraddr_1_axbxc1 : CFG4
      generic map(INIT => x"A666")

      port map(A => \inp_wraddr[1]_net_1\, B => 
        \un1_inp_wraddr_1_ac0_m1_0_a2_0\, C => 
        \un2_data_valid_dly_i_0_a2_3\, D => 
        \un2_data_valid_dly_i_0_a2_4\, Y => 
        \un1_inp_wraddr_1_axbxc1\);
    
    clrsig_1 : SLE
      port map(D => \clrsig_0\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \clrsig_1\);
    
    \inpB_rdaddr_RNIGA8F1[2]\ : ARI1
      generic map(INIT => x"58DD8")

      port map(A => \mac_state[1]_net_1\, B => 
        \mac_state[0]_net_1\, C => \B_rdaddr[2]_net_1\, D => 
        \inpB_rdaddr[2]_net_1\, FCI => inpB_rdaddr_4_1_0_m2_cry_1, 
        S => N_122, Y => OPEN, FCO => inpB_rdaddr_4_1_0_m2_cry_2);
    
    \Coef_rddata[2]\ : SLE
      port map(D => \Coef_rddata1[2]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[2]_net_1\);
    
    \B_rdaddr_RNII7HU2[5]\ : ARI1
      generic map(INIT => x"58DD8")

      port map(A => \mac_state[1]_net_1\, B => 
        \mac_state[0]_net_1\, C => \B_rdaddr[5]_net_1\, D => 
        \inpB_rdaddr[5]_net_1\, FCI => inpB_rdaddr_4_1_0_m2_cry_4, 
        S => N_128, Y => OPEN, FCO => inpB_rdaddr_4_1_0_m2_cry_5);
    
    Sel_InpB1 : SLE
      port map(D => \InpB_rden1\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Sel_InpB1\);
    
    \inp_wrdata[1]\ : SLE
      port map(D => \Xn_in_c[1]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[1]_net_1\);
    
    \Mac_out_obuf[7]\ : OUTBUF
      port map(D => \Mac_out_c[7]\, PAD => Mac_out(7));
    
    \inp_wrdata_dly0[3]\ : SLE
      port map(D => \inp_wrdata[3]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[3]_net_1\);
    
    \Mac_out[40]\ : SLE
      port map(D => \Yn_out[40]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[40]\);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    Sel_InpB0 : SLE
      port map(D => \InpB_rden0\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Sel_InpB0\);
    
    \B_rdaddr[6]\ : SLE
      port map(D => \B_rdaddr_lm[6]\, CLK => clk_c, EN => 
        N_108_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \B_rdaddr[6]_net_1\);
    
    \inp_rddata[6]\ : SLE
      port map(D => N_219, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[6]_net_1\);
    
    \inp_wrdata[15]\ : SLE
      port map(D => \Xn_in_c[15]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[15]_net_1\);
    
    \inp_rddata_RNO_0[7]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[7]\, D => \un1_inpA_rddata2_10[7]\, 
        Y => un1_inpA_rddata2_1_m_3_0_i_m2_i_m2_1_1);
    
    \inp_wrdata[16]\ : SLE
      port map(D => \Xn_in_c[16]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[16]_net_1\);
    
    InpA_rden1_1_iv_i : CFG4
      generic map(INIT => x"5515")

      port map(A => N_69, B => N_68, C => \inpA_rdaddr[5]_net_1\, 
        D => \InpA_rden1\, Y => InpA_rden1_1_iv_i_0);
    
    \Mac_out_obuf[37]\ : OUTBUF
      port map(D => \Mac_out_c[37]\, PAD => Mac_out(37));
    
    transferdone5_0_a2_0_a2_5 : CFG4
      generic map(INIT => x"1000")

      port map(A => \rdy_cnt[4]_net_1\, B => \rdy_cnt[2]_net_1\, 
        C => \rdy_cnt[6]_net_1\, D => \mac_state[3]_net_1\, Y => 
        \transferdone5_0_a2_0_a2_5\);
    
    Sel_Coef1 : SLE
      port map(D => \Coef0_rden\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Sel_Coef1\);
    
    \Mac_out[36]\ : SLE
      port map(D => \Yn_out[36]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[36]\);
    
    FiltOp_done : SLE
      port map(D => \op_eq.filtop_done3\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \FiltOp_done\);
    
    \inpA_rdaddr_4_i_i_a2[4]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \mac_state[0]_net_1\, B => 
        \A_rdaddr[4]_net_1\, Y => N_157);
    
    \inp_rddata_RNO_0[6]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[6]\, D => \un1_inpA_rddata2_10[6]\, 
        Y => un1_inpA_rddata2_1_m_3_603_i_m2_i_m2_1_2);
    
    \Mac_out_obuf[39]\ : OUTBUF
      port map(D => \Mac_out_c[39]\, PAD => Mac_out(39));
    
    \inp_wraddr[6]\ : SLE
      port map(D => N_11_i_0, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \inp_wraddr[6]_net_1\);
    
    \inpA_rdaddr_cry[6]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \inpA_rdaddr[6]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => 
        \inpA_rdaddr_cry[5]_net_1\, S => \inpA_rdaddr_s[6]\, Y
         => OPEN, FCO => \inpA_rdaddr_cry[6]_net_1\);
    
    \rdy_cnt_RNO[4]\ : CFG3
      generic map(INIT => x"9C")

      port map(A => \un1_rdy_cnt_1_axbxc4_m3_i_o2_1\, B => 
        \rdy_cnt[4]_net_1\, C => \un13_rdy_sig_0_a2_0_a2\, Y => 
        un1_rdy_cnt_1_axbxc4_N_9_i_i_0);
    
    \Mac_out_obuf[27]\ : OUTBUF
      port map(D => \Mac_out_c[27]\, PAD => Mac_out(27));
    
    un1_coef_rdaddr_1_axbxc7 : CFG3
      generic map(INIT => x"78")

      port map(A => \Coef_rdaddr[6]_net_1\, B => 
        un1_coef_rdaddr_1_c6, C => \Coef_rdaddr[7]_net_1\, Y => 
        \un1_coef_rdaddr_1_axbxc7\);
    
    \inp_wraddr2_RNO[1]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \inp_wraddr[6]_net_1\, B => 
        \inp_wraddr[1]_net_1\, Y => N_502_i_0);
    
    \inp_rddata[1]\ : SLE
      port map(D => N_180, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[1]_net_1\);
    
    \inpA_rdaddr[4]\ : SLE
      port map(D => \inpA_rdaddr_lm[4]\, CLK => clk_c, EN => 
        N_107_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inpA_rdaddr[4]_net_1\);
    
    InpB_rden1_1_iv_0_o3 : CFG3
      generic map(INIT => x"FE")

      port map(A => \inpB_rdaddr[4]_net_1\, B => 
        \inpB_rdaddr[3]_net_1\, C => \inpB_rdaddr[2]_net_1\, Y
         => N_66);
    
    \Mac_out[18]\ : SLE
      port map(D => \Yn_out[18]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[18]\);
    
    \inpB_rdaddr_RNO_0[7]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => \inpB_rdaddr[5]_net_1\, B => g1_0, C => 
        \inpB_rdaddr[1]_net_1\, D => \inpB_rdaddr[0]_net_1\, Y
         => g1_4);
    
    \InpA_rdaddr1[3]\ : SLE
      port map(D => \inpA_rdaddr[3]_net_1\, CLK => clk_c, EN => 
        N_161_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \InpA_rdaddr1[3]_net_1\);
    
    reset_n_ibuf_RNILECB : CLKINT
      port map(A => \reset_n_ibuf\, Y => reset_n_c);
    
    \Mac_out[21]\ : SLE
      port map(D => \Yn_out[21]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[21]\);
    
    \A_rdaddr_2_i_0_a2[2]\ : CFG4
      generic map(INIT => x"4000")

      port map(A => \A_rdaddr[3]_net_1\, B => \A_rdaddr[0]_net_1\, 
        C => \un1_a_rdaddr_ac0_11_0\, D => 
        \A_rdaddr_2_i_0_a2_3[2]_net_1\, Y => N_146);
    
    \Mac_out[6]\ : SLE
      port map(D => \Yn_out[6]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[6]\);
    
    \inp_rddata_RNO[6]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[6]\, B => 
        un1_inpA_rddata2_1_m_3_603_i_m2_i_m2_1_2, C => 
        \Sel_InpA0\, D => \un1_inpA_rddata2_13[6]\, Y => N_219);
    
    Coef0_rden_1_f0_i_o2 : CFG4
      generic map(INIT => x"FFFE")

      port map(A => \Coef_rdaddr[5]_net_1\, B => 
        \Coef_rdaddr[4]_net_1\, C => 
        \op_eq.filtop_done3_0_o3_0_net_1\, D => N_14, Y => N_19);
    
    \Mac_out_obuf[43]\ : OUTBUF
      port map(D => \Mac_out_c[43]\, PAD => Mac_out(43));
    
    \Mac_out_obuf[29]\ : OUTBUF
      port map(D => \Mac_out_c[29]\, PAD => Mac_out(29));
    
    \inp_wrdata_dly0[10]\ : SLE
      port map(D => \inp_wrdata[10]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[10]_net_1\);
    
    un1_inp_wraddr_1_axbxc5_m2_i_o2_0 : CFG2
      generic map(INIT => x"7")

      port map(A => \inp_wraddr[3]_net_1\, B => 
        \inp_wraddr[4]_net_1\, Y => 
        \un1_inp_wraddr_1_axbxc5_m2_i_o2_0\);
    
    \Mac_out_obuf[33]\ : OUTBUF
      port map(D => \Mac_out_c[33]\, PAD => Mac_out(33));
    
    \B_rdaddr_lm_0[4]\ : CFG4
      generic map(INIT => x"1030")

      port map(A => un1_b_rdaddr10_i_0_627_0_0_a2_5, B => 
        \Transferdone\, C => \B_rdaddr_s[4]\, D => 
        un1_b_rdaddr10_i_0_627_0_0_a2_4, Y => \B_rdaddr_lm[4]\);
    
    \Xn_in_ibuf[11]\ : INBUF
      port map(PAD => Xn_in(11), Y => \Xn_in_c[11]\);
    
    \Mac_out[41]\ : SLE
      port map(D => \Yn_out[41]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[41]\);
    
    \inp_wrdata[4]\ : SLE
      port map(D => \Xn_in_c[4]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[4]_net_1\);
    
    \Coef_rddata[3]\ : SLE
      port map(D => \Coef_rddata1[3]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[3]_net_1\);
    
    \B_rdaddr_cry[3]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \B_rdaddr[3]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => \B_rdaddr_cry[2]_net_1\, 
        S => \B_rdaddr_s[3]\, Y => OPEN, FCO => 
        \B_rdaddr_cry[3]_net_1\);
    
    \inpB_rdaddr_RNIE1OF[0]\ : ARI1
      generic map(INIT => x"58DD8")

      port map(A => \mac_state[1]_net_1\, B => 
        \mac_state[0]_net_1\, C => \B_rdaddr[0]_net_1\, D => 
        \inpB_rdaddr[0]_net_1\, FCI => GND_net_1, S => OPEN, Y
         => \inpB_rdaddr_RNIE1OF_Y[0]\, FCO => 
        inpB_rdaddr_4_1_0_m2_cry_0);
    
    \inp_wraddr1_RNO[3]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \inp_wraddr[6]_net_1\, B => 
        \inp_wraddr[3]_net_1\, Y => N_568);
    
    inpA_rdaddr_1_sqmuxa_i_0_0_a2_1 : CFG3
      generic map(INIT => x"80")

      port map(A => \inpA_rdaddr[0]_net_1\, B => 
        \inpA_rdaddr[5]_net_1\, C => \inpA_rdaddr[1]_net_1\, Y
         => \inpA_rdaddr_1_sqmuxa_i_0_0_a2_1\);
    
    \inp_wrdata_dly0[1]\ : SLE
      port map(D => \inp_wrdata[1]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[1]_net_1\);
    
    \Mac_out_obuf[23]\ : OUTBUF
      port map(D => \Mac_out_c[23]\, PAD => Mac_out(23));
    
    \Mac_out_obuf[2]\ : OUTBUF
      port map(D => \Mac_out_c[2]\, PAD => Mac_out(2));
    
    \inp_wrdata[9]\ : SLE
      port map(D => \Xn_in_c[9]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[9]_net_1\);
    
    \inp_rddata[13]\ : SLE
      port map(D => N_198, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[13]_net_1\);
    
    \Coef_rddata[7]\ : SLE
      port map(D => \Coef_rddata1[7]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[7]_net_1\);
    
    \inp_wrdata_dly0[6]\ : SLE
      port map(D => \inp_wrdata[6]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[6]_net_1\);
    
    \inpA_rdaddr_lm_0[6]\ : CFG4
      generic map(INIT => x"E222")

      port map(A => \inpA_rdaddr_s[6]\, B => N_5, C => 
        \A_rdaddr[6]_net_1\, D => \mac_state[0]_net_1\, Y => 
        \inpA_rdaddr_lm[6]\);
    
    clk_ibuf : INBUF
      port map(PAD => clk, Y => \clk_ibuf\);
    
    transferdone5_0_a2_0_a2_4 : CFG3
      generic map(INIT => x"04")

      port map(A => \rdy_cnt[7]_net_1\, B => \rdy_cnt[5]_net_1\, 
        C => \rdy_cnt[0]_net_1\, Y => \transferdone5_0_a2_0_a2_4\);
    
    \Mac_out[35]\ : SLE
      port map(D => \Yn_out[35]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[35]\);
    
    \inpA_rdaddr[7]\ : SLE
      port map(D => \inpA_rdaddr_lm[7]\, CLK => clk_c, EN => 
        N_107_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inpA_rdaddr[7]_net_1\);
    
    \inp_rddata[4]\ : SLE
      port map(D => N_171, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[4]_net_1\);
    
    \inp_rddata[3]\ : SLE
      port map(D => N_174, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[3]_net_1\);
    
    \Mac_out_obuf[12]\ : OUTBUF
      port map(D => \Mac_out_c[12]\, PAD => Mac_out(12));
    
    \inp_wrdata[11]\ : SLE
      port map(D => \Xn_in_c[11]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[11]_net_1\);
    
    \Mac_out[22]\ : SLE
      port map(D => \Yn_out[22]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[22]\);
    
    \inp_rddata[5]\ : SLE
      port map(D => N_168, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[5]_net_1\);
    
    \inp_rddata[15]\ : SLE
      port map(D => \inp_rddata_RNO[15]_net_1\, CLK => clk_c, EN
         => un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => 
        VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT => 
        GND_net_1, Q => \inp_rddata[15]_net_1\);
    
    InpB_rden1 : SLE
      port map(D => InpB_rden1_1_iv_i_0, CLK => clk_c, EN => 
        \mac_state[1]_net_1\, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \InpB_rden1\);
    
    \Coef_rdaddr[3]\ : SLE
      port map(D => \un1_coef_rdaddr_1_axbxc3\, CLK => clk_c, EN
         => \mac_state[1]_net_1\, ALn => reset_n_c, ADn => 
        VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT => 
        GND_net_1, Q => \Coef_rdaddr[3]_net_1\);
    
    \Mac_out[2]\ : SLE
      port map(D => \Yn_out[2]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[2]\);
    
    \Coef_rdaddr1[4]\ : SLE
      port map(D => \Coef_rdaddr[4]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rdaddr1[4]_net_1\);
    
    un1_a_rdaddr_axbxc7 : CFG4
      generic map(INIT => x"6AAA")

      port map(A => \A_rdaddr[7]_net_1\, B => 
        \un1_a_rdaddr_ac0_11_0\, C => \un1_a_rdaddr_ac0_7_0\, D
         => un1_a_rdaddr_c3, Y => \un1_a_rdaddr_axbxc7\);
    
    \inp_wraddr[7]\ : SLE
      port map(D => \un1_inp_wraddr_1_axbxc7\, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wraddr[7]_net_1\);
    
    clr : SLE
      port map(D => \clrsig_1\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \clr\);
    
    \Coef_rdaddr[5]\ : SLE
      port map(D => N_8_i_0, CLK => clk_c, EN => 
        \mac_state[1]_net_1\, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \Coef_rdaddr[5]_net_1\);
    
    \rdy_cnt_3_0_a2_0_a2[0]\ : CFG3
      generic map(INIT => x"14")

      port map(A => \Transferdone\, B => \rdy_sig\, C => 
        \rdy_cnt[0]_net_1\, Y => \rdy_cnt_3[0]\);
    
    \inp_rddata_RNO[17]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[17]\, B => 
        un1_inpA_rddata2_1_m_3_10_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[17]\, Y => N_186);
    
    InpB_rden1_1_iv_0_0_o2 : CFG2
      generic map(INIT => x"D")

      port map(A => \inpB_rdaddr[6]_net_1\, B => 
        \inpB_rdaddr[7]_net_1\, Y => N_131);
    
    \Mac_out[42]\ : SLE
      port map(D => \Yn_out[42]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[42]\);
    
    \Mac_out[34]\ : SLE
      port map(D => \Yn_out[34]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[34]\);
    
    \B_rdaddr_RNICL9E3[6]\ : ARI1
      generic map(INIT => x"58DD8")

      port map(A => \mac_state[1]_net_1\, B => 
        \mac_state[0]_net_1\, C => \B_rdaddr[6]_net_1\, D => 
        \inpB_rdaddr[6]_net_1\, FCI => inpB_rdaddr_4_1_0_m2_cry_5, 
        S => N_129, Y => OPEN, FCO => inpB_rdaddr_4_1_0_m2_cry_6);
    
    \Mac_out_obuf[16]\ : OUTBUF
      port map(D => \Mac_out_c[16]\, PAD => Mac_out(16));
    
    \inpB_rdaddr[0]\ : SLE
      port map(D => \inpB_rdaddr_4[0]\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => GND_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inpB_rdaddr[0]_net_1\);
    
    \inp_rddata_RNO_0[10]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[10]\, D => \un1_inpA_rddata2_10[10]\, 
        Y => un1_inpA_rddata2_1_m_3_3_i_m2_i_m2_1_1);
    
    \InpA_rdaddr1[4]\ : SLE
      port map(D => \inpA_rdaddr[4]_net_1\, CLK => clk_c, EN => 
        N_161_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \InpA_rdaddr1[4]_net_1\);
    
    \Xn_in_ibuf[15]\ : INBUF
      port map(PAD => Xn_in(15), Y => \Xn_in_c[15]\);
    
    un1_a_rdaddr_ac0_11_0 : CFG2
      generic map(INIT => x"8")

      port map(A => \A_rdaddr[5]_net_1\, B => \A_rdaddr[6]_net_1\, 
        Y => \un1_a_rdaddr_ac0_11_0\);
    
    \inp_rddata_RNO_0[9]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[9]\, D => \un1_inpA_rddata2_10[9]\, 
        Y => un1_inpA_rddata2_1_m_3_2_i_m2_i_m2_1_1);
    
    \Coef_rddata[14]\ : SLE
      port map(D => \Coef_rddata1[14]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[14]_net_1\);
    
    \Mac_out_obuf[4]\ : OUTBUF
      port map(D => \Mac_out_c[4]\, PAD => Mac_out(4));
    
    \inp_wraddr2[4]\ : SLE
      port map(D => N_526_i_0, CLK => clk_c, EN => 
        \un1_inp_wraddr_0_a2_0_a2_0[0]_net_1\, ALn => reset_n_c, 
        ADn => VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT
         => GND_net_1, Q => \inp_wraddr2[4]_net_1\);
    
    \inp_rddata_RNO[5]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[5]\, B => 
        un1_inpA_rddata2_1_m_3_16_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[5]\, Y => N_168);
    
    \Coef_rddata[9]\ : SLE
      port map(D => \Coef_rddata1[9]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[9]_net_1\);
    
    \Mac_out_obuf[11]\ : OUTBUF
      port map(D => \Mac_out_c[11]\, PAD => Mac_out(11));
    
    \inp_wraddr2_RNO[4]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \inp_wraddr[6]_net_1\, B => 
        \inp_wraddr[4]_net_1\, Y => N_526_i_0);
    
    \rdy_cnt[7]\ : SLE
      port map(D => un1_rdy_cnt_1_axbxc7_N_13_i_i_0, CLK => clk_c, 
        EN => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \rdy_cnt[7]_net_1\);
    
    \inp_rddata_RNO_0[5]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[5]\, D => \un1_inpA_rddata2_10[5]\, 
        Y => un1_inpA_rddata2_1_m_3_16_i_m2_i_m2_1_1);
    
    \inpB_rdaddr[3]\ : SLE
      port map(D => N_47_i_0, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \inpB_rdaddr[3]_net_1\);
    
    \Coef_rdaddr[7]\ : SLE
      port map(D => \un1_coef_rdaddr_1_axbxc7\, CLK => clk_c, EN
         => \mac_state[1]_net_1\, ALn => reset_n_c, ADn => 
        VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT => 
        GND_net_1, Q => \Coef_rdaddr[7]_net_1\);
    
    rdy_sig_4_iv_i : CFG3
      generic map(INIT => x"23")

      port map(A => \New_data\, B => \Transferdone\, C => 
        \mac_state[1]_net_1\, Y => rdy_sig_4_iv_i_0);
    
    un1_a_rdaddr_axbxc1 : CFG2
      generic map(INIT => x"6")

      port map(A => \A_rdaddr[0]_net_1\, B => \A_rdaddr[1]_net_1\, 
        Y => \un1_a_rdaddr_axbxc1\);
    
    \inp_wrdata[10]\ : SLE
      port map(D => \Xn_in_c[10]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[10]_net_1\);
    
    \op_eq.filtop_done3_0_o3_0\ : CFG3
      generic map(INIT => x"FE")

      port map(A => \Coef_rdaddr[3]_net_1\, B => 
        \Coef_rdaddr[2]_net_1\, C => \Coef_rdaddr[0]_net_1\, Y
         => \op_eq.filtop_done3_0_o3_0_net_1\);
    
    \inp_rddata_RNO_0[15]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[15]\, D => \un1_inpA_rddata2_10[15]\, 
        Y => un1_inpA_rddata2_1_m_3_8_i_m2_i_m2_1_1);
    
    \rdy_cnt[3]\ : SLE
      port map(D => \un1_rdy_cnt_1_axbxc3\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \rdy_cnt[3]_net_1\);
    
    \inpB_rdaddr[1]\ : SLE
      port map(D => \inpB_rdaddr_4[1]\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => GND_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inpB_rdaddr[1]_net_1\);
    
    \Xn_in_ibuf[7]\ : INBUF
      port map(PAD => Xn_in(7), Y => \Xn_in_c[7]\);
    
    \inpB_rdaddr_RNO[7]\ : CFG4
      generic map(INIT => x"CC8C")

      port map(A => g1_4, B => N_125, C => \mac_state[1]_net_1\, 
        D => N_66, Y => N_51_i_0);
    
    \mac_state_ns_a2_0_a2_0_a2_1[0]\ : CFG2
      generic map(INIT => x"1")

      port map(A => \mac_state[2]_net_1\, B => 
        \mac_state[4]_net_1\, Y => 
        \mac_state_ns_a2_0_a2_0_a2_1[0]_net_1\);
    
    \Mac_out[39]\ : SLE
      port map(D => \Yn_out[39]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[39]\);
    
    \Mac_out[10]\ : SLE
      port map(D => \Yn_out[10]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[10]\);
    
    \Mac_out_obuf[10]\ : OUTBUF
      port map(D => \Mac_out_c[10]\, PAD => Mac_out(10));
    
    \inp_wrdata_dly0[11]\ : SLE
      port map(D => \inp_wrdata[11]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[11]_net_1\);
    
    \inpA_rdaddr_lm_0[1]\ : CFG4
      generic map(INIT => x"E222")

      port map(A => \inpA_rdaddr_s[1]\, B => N_5, C => 
        \A_rdaddr[1]_net_1\, D => \mac_state[0]_net_1\, Y => 
        \inpA_rdaddr_lm[1]\);
    
    \inp_wraddr[3]\ : SLE
      port map(D => \un1_inp_wraddr_1_axbxc3\, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wraddr[3]_net_1\);
    
    \inp_rddata_RNO_0[11]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[11]\, D => \un1_inpA_rddata2_10[11]\, 
        Y => un1_inpA_rddata2_1_m_3_4_i_m2_i_m2_1_1);
    
    \Mac_out[27]\ : SLE
      port map(D => \Yn_out[27]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[27]\);
    
    \Mac_out[1]\ : SLE
      port map(D => \Yn_out[1]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[1]\);
    
    \Coef_rdaddr_RNO[5]\ : CFG4
      generic map(INIT => x"134C")

      port map(A => \Coef_rdaddr_2_i_a2_0[1]_net_1\, B => 
        \Coef_rdaddr[5]_net_1\, C => 
        \Coef_rdaddr_2_i_a2_1[1]_net_1\, D => 
        un1_coef_rdaddr_1_c5, Y => N_8_i_0);
    
    \B_rdaddr_cry[2]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \B_rdaddr[2]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => \B_rdaddr_cry[1]_net_1\, 
        S => \B_rdaddr_s[2]\, Y => OPEN, FCO => 
        \B_rdaddr_cry[2]_net_1\);
    
    un1_rdy_cnt_1_axbxc7_m5_i_o2_3 : CFG3
      generic map(INIT => x"7F")

      port map(A => \rdy_cnt[6]_net_1\, B => \rdy_cnt[2]_net_1\, 
        C => \rdy_cnt[0]_net_1\, Y => 
        \un1_rdy_cnt_1_axbxc7_m5_i_o2_3\);
    
    \inp_wraddr1_RNO[4]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \inp_wraddr[6]_net_1\, B => 
        \inp_wraddr[4]_net_1\, Y => N_576);
    
    \InpA_rdaddr1[1]\ : SLE
      port map(D => \inpA_rdaddr[1]_net_1\, CLK => clk_c, EN => 
        N_161_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \InpA_rdaddr1[1]_net_1\);
    
    B_rdaddr_s_705 : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \B_rdaddr[0]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => VCC_net_1, S => OPEN, Y
         => OPEN, FCO => B_rdaddr_s_705_FCO);
    
    \Coef_rdaddr1[1]\ : SLE
      port map(D => \Coef_rdaddr[1]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rdaddr1[1]_net_1\);
    
    un1_rdy_cnt_1_axbxc7_m5_i_o2_4 : CFG4
      generic map(INIT => x"7FFF")

      port map(A => \rdy_cnt[5]_net_1\, B => \rdy_cnt[4]_net_1\, 
        C => \rdy_cnt[3]_net_1\, D => \rdy_cnt[1]_net_1\, Y => 
        \un1_rdy_cnt_1_axbxc7_m5_i_o2_4\);
    
    \inp_wraddr2_RNO[5]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \inp_wraddr[6]_net_1\, B => 
        \inp_wraddr[5]_net_1\, Y => un16_inp_wraddr_2_i_0);
    
    \inpB_rdaddr_4_1_0[0]\ : CFG4
      generic map(INIT => x"CECC")

      port map(A => \inpB_rdaddr_4_i_0_a2_2[2]_net_1\, B => 
        \inpB_rdaddr_RNIE1OF_Y[0]\, C => N_66, D => 
        \inpB_rdaddr_4_i_0_a2_3[2]_net_1\, Y => 
        \inpB_rdaddr_4[0]\);
    
    \inp_wrdata_dly0[9]\ : SLE
      port map(D => \inp_wrdata[9]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[9]_net_1\);
    
    \B_rdaddr_RNIU4GV[1]\ : ARI1
      generic map(INIT => x"58DD8")

      port map(A => \mac_state[1]_net_1\, B => 
        \mac_state[0]_net_1\, C => \B_rdaddr[1]_net_1\, D => 
        \inpB_rdaddr[1]_net_1\, FCI => inpB_rdaddr_4_1_0_m2_cry_0, 
        S => N_127, Y => OPEN, FCO => inpB_rdaddr_4_1_0_m2_cry_1);
    
    \rdy_cnt_3_0_a2_0_a2[1]\ : CFG4
      generic map(INIT => x"1450")

      port map(A => \Transferdone\, B => \rdy_sig\, C => 
        \rdy_cnt[1]_net_1\, D => \rdy_cnt[0]_net_1\, Y => 
        \rdy_cnt_3[1]\);
    
    \inp_rddata_RNO[9]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[9]\, B => 
        un1_inpA_rddata2_1_m_3_2_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[9]\, Y => N_210);
    
    \inp_rddata[7]\ : SLE
      port map(D => N_216, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[7]_net_1\);
    
    \Mac_out_obuf[5]\ : OUTBUF
      port map(D => \Mac_out_c[5]\, PAD => Mac_out(5));
    
    \inp_wrdata_dly0[0]\ : SLE
      port map(D => \inp_wrdata[0]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[0]_net_1\);
    
    un1_coef_rdaddr_1_axbxc3 : CFG4
      generic map(INIT => x"6AAA")

      port map(A => \Coef_rdaddr[3]_net_1\, B => 
        \Coef_rdaddr[1]_net_1\, C => \Coef_rdaddr[0]_net_1\, D
         => \Coef_rdaddr[2]_net_1\, Y => 
        \un1_coef_rdaddr_1_axbxc3\);
    
    inpA_rdaddr_s_706 : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \inpA_rdaddr[0]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => VCC_net_1, S => OPEN, Y
         => OPEN, FCO => inpA_rdaddr_s_706_FCO);
    
    Sel_InpA1_RNIGP841 : CFG4
      generic map(INIT => x"FAC8")

      port map(A => \Sel_InpB1\, B => \Sel_InpA1\, C => 
        \Sel_InpB0\, D => \Sel_InpA0\, Y => un1_sel_inpa0_4_i_0);
    
    \mac_state[3]\ : SLE
      port map(D => \mac_state_ns[2]\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \mac_state[3]_net_1\);
    
    \inp_wrdata_dly0[5]\ : SLE
      port map(D => \inp_wrdata[5]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[5]_net_1\);
    
    \inp_wraddr1_RNO[2]\ : CFG2
      generic map(INIT => x"4")

      port map(A => \inp_wraddr[6]_net_1\, B => 
        \inp_wraddr[2]_net_1\, Y => N_560);
    
    \inp_wrdata[6]\ : SLE
      port map(D => \Xn_in_c[6]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[6]_net_1\);
    
    un1_a_rdaddr_axbxc3 : CFG4
      generic map(INIT => x"6AAA")

      port map(A => \A_rdaddr[3]_net_1\, B => \A_rdaddr[2]_net_1\, 
        C => \A_rdaddr[0]_net_1\, D => \A_rdaddr[1]_net_1\, Y => 
        \un1_a_rdaddr_axbxc3\);
    
    \Mac_out[3]\ : SLE
      port map(D => \Yn_out[3]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[3]\);
    
    \inp_wraddr[4]\ : SLE
      port map(D => \un1_inp_wraddr_1_axbxc4\, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wraddr[4]_net_1\);
    
    \inp_rddata_RNO_0[0]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_0_Y, D => 
        Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS_Y, Y => 
        un1_inpA_rddata2_1_m_3_11_339_i_m2_i_m2_ns_1);
    
    \rdy_cnt[2]\ : SLE
      port map(D => \un1_rdy_cnt_1_axbxc2\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \rdy_cnt[2]_net_1\);
    
    \Coef_rddata[6]\ : SLE
      port map(D => \Coef_rddata1[6]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[6]_net_1\);
    
    \Mac_out[26]\ : SLE
      port map(D => \Yn_out[26]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[26]\);
    
    clk_ibuf_RNIVTI2 : CLKINT
      port map(A => \clk_ibuf\, Y => clk_c);
    
    \mac_state_ns_0_0[4]\ : CFG4
      generic map(INIT => x"FF40")

      port map(A => Data_Valid_c, B => \mac_state[2]_net_1\, C
         => \Data_Valid_dly\, D => \mac_state_ns_0_0_0[4]_net_1\, 
        Y => \mac_state_ns[4]\);
    
    \Mac_out[11]\ : SLE
      port map(D => \Yn_out[11]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[11]\);
    
    \inpA_rdaddr_4_i_0[5]\ : CFG2
      generic map(INIT => x"7")

      port map(A => \mac_state[0]_net_1\, B => 
        \A_rdaddr[5]_net_1\, Y => N_24);
    
    \Coef_rdaddr1[0]\ : SLE
      port map(D => \Coef_rdaddr[0]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rdaddr1[0]_net_1\);
    
    \inp_rddata_RNO_0[14]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[14]\, D => \un1_inpA_rddata2_10[14]\, 
        Y => un1_inpA_rddata2_1_m_3_7_i_m2_i_m2_1_1);
    
    un1_rdy_cnt_1_axbxc4_m3_i_o2_1 : CFG4
      generic map(INIT => x"7FFF")

      port map(A => \rdy_cnt[3]_net_1\, B => \rdy_cnt[2]_net_1\, 
        C => \rdy_cnt[1]_net_1\, D => \rdy_cnt[0]_net_1\, Y => 
        \un1_rdy_cnt_1_axbxc4_m3_i_o2_1\);
    
    \Coef_rddata[0]\ : SLE
      port map(D => \Coef_rddata1[0]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[0]_net_1\);
    
    Coef0_rden : SLE
      port map(D => N_10_i_0, CLK => clk_c, EN => 
        \mac_state[1]_net_1\, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \Coef0_rden\);
    
    \inp_wrdata[3]\ : SLE
      port map(D => \Xn_in_c[3]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[3]_net_1\);
    
    \inp_wrdata[0]\ : SLE
      port map(D => \Xn_in_c[0]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[0]_net_1\);
    
    \Coef_rddata[11]\ : SLE
      port map(D => \Coef_rddata1[11]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[11]_net_1\);
    
    \inp_rddata_RNO_0[12]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[12]\, D => \un1_inpA_rddata2_10[12]\, 
        Y => un1_inpA_rddata2_1_m_3_5_i_m2_i_m2_1_1);
    
    \inp_wrdata_dly0[7]\ : SLE
      port map(D => \inp_wrdata[7]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[7]_net_1\);
    
    un1_rdy_cnt_1_ac0_7_0 : CFG4
      generic map(INIT => x"8000")

      port map(A => \rdy_cnt[4]_net_1\, B => \rdy_cnt[3]_net_1\, 
        C => \rdy_cnt[2]_net_1\, D => \rdy_cnt[1]_net_1\, Y => 
        un1_rdy_cnt_1_ac0_7_0_0);
    
    \inp_rddata_RNO_0[2]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[2]\, D => \un1_inpA_rddata2_10[2]\, 
        Y => un1_inpA_rddata2_1_m_3_13_i_m2_i_m2_1_1);
    
    \inpB_rdaddr[4]\ : SLE
      port map(D => N_49_i_0, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \inpB_rdaddr[4]_net_1\);
    
    \inp_rddata_RNO[7]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[7]\, B => 
        un1_inpA_rddata2_1_m_3_0_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[7]\, Y => N_216);
    
    inpA_rdaddr_1_sqmuxa_i_0_0 : CFG4
      generic map(INIT => x"5755")

      port map(A => \mac_state[1]_net_1\, B => N_69, C => N_68, D
         => \inpA_rdaddr_1_sqmuxa_i_0_0_a2_1\, Y => N_5);
    
    \A_rdaddr_RNO[2]\ : CFG4
      generic map(INIT => x"1230")

      port map(A => \A_rdaddr[0]_net_1\, B => N_146, C => 
        \A_rdaddr[2]_net_1\, D => \A_rdaddr[1]_net_1\, Y => 
        N_7_i_0);
    
    \Xn_in_ibuf[13]\ : INBUF
      port map(PAD => Xn_in(13), Y => \Xn_in_c[13]\);
    
    InpA_rden0_1_iv_0_o2_RNI05NC : CFG3
      generic map(INIT => x"DF")

      port map(A => \inpA_rdaddr[5]_net_1\, B => N_69, C => N_68, 
        Y => N_161_i_0);
    
    \inpA_rdaddr_cry[3]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \inpA_rdaddr[3]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => 
        \inpA_rdaddr_cry[2]_net_1\, S => \inpA_rdaddr_s[3]\, Y
         => OPEN, FCO => \inpA_rdaddr_cry[3]_net_1\);
    
    \un1_inp_wraddr_0_a2_0_a2_0_1[0]\ : CFG3
      generic map(INIT => x"01")

      port map(A => \inp_wraddr[3]_net_1\, B => 
        \inp_wraddr[2]_net_1\, C => \inp_wraddr[4]_net_1\, Y => 
        \un1_inp_wraddr_0_a2_0_a2_0_1[0]_net_1\);
    
    \inp_wraddr2[2]\ : SLE
      port map(D => N_510_i_0, CLK => clk_c, EN => 
        \un1_inp_wraddr_0_a2_0_a2_0[0]_net_1\, ALn => reset_n_c, 
        ADn => VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT
         => GND_net_1, Q => \inp_wraddr2[2]_net_1\);
    
    \mac_state_ns_0_0[1]\ : CFG4
      generic map(INIT => x"B3A0")

      port map(A => Filter_En_c, B => Data_Valid_c, C => 
        \mac_state[5]_net_1\, D => \mac_state[4]_net_1\, Y => 
        \mac_state_ns[1]\);
    
    clrsig_RNO : CFG2
      generic map(INIT => x"E")

      port map(A => \mac_state[0]_net_1\, B => 
        \mac_state[2]_net_1\, Y => N_141_i_0);
    
    InpCoef0_wren_2_0_a2_0_a2 : CFG3
      generic map(INIT => x"10")

      port map(A => \inp_wraddr[6]_net_1\, B => 
        \inp_wraddr[7]_net_1\, C => \Data_Valid_dly\, Y => 
        InpCoef0_wren_2);
    
    \Mac_out[12]\ : SLE
      port map(D => \Yn_out[12]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[12]\);
    
    \Mac_out[4]\ : SLE
      port map(D => \Yn_out[4]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[4]\);
    
    \inp_wraddr1[5]\ : SLE
      port map(D => N_584, CLK => clk_c, EN => 
        \un1_inp_wraddr_0_a2_0_a2_0[0]_net_1\, ALn => reset_n_c, 
        ADn => VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT
         => GND_net_1, Q => \inp_wraddr1[5]_net_1\);
    
    \inp_wraddr1[2]\ : SLE
      port map(D => N_560, CLK => clk_c, EN => 
        \un1_inp_wraddr_0_a2_0_a2_0[0]_net_1\, ALn => reset_n_c, 
        ADn => VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT
         => GND_net_1, Q => \inp_wraddr1[2]_net_1\);
    
    \inp_rddata_RNO[4]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[4]\, B => 
        un1_inpA_rddata2_1_m_3_15_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[4]\, Y => N_171);
    
    \inp_rddata_RNO[0]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_Y, B => 
        un1_inpA_rddata2_1_m_3_11_339_i_m2_i_m2_ns_1, C => 
        \Sel_InpA0\, D => Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIKTA7_Y, 
        Y => N_183);
    
    \Xn_in_ibuf[9]\ : INBUF
      port map(PAD => Xn_in(9), Y => \Xn_in_c[9]\);
    
    \inp_wrdata[12]\ : SLE
      port map(D => \Xn_in_c[12]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[12]_net_1\);
    
    \mac_state_ns_0_0_a2_0[3]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \Transferdone\, B => \mac_state[3]_net_1\, Y
         => N_152);
    
    \inp_rddata_RNO_0[3]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[3]\, D => \un1_inpA_rddata2_10[3]\, 
        Y => un1_inpA_rddata2_1_m_3_14_i_m2_i_m2_1_1);
    
    InpB_rden1_1_iv_i : CFG4
      generic map(INIT => x"5515")

      port map(A => N_131, B => N_66, C => \inpB_rdaddr[5]_net_1\, 
        D => \InpB_rden1\, Y => InpB_rden1_1_iv_i_0);
    
    \Mac_out[25]\ : SLE
      port map(D => \Yn_out[25]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[25]\);
    
    \inp_wraddr_RNO[5]\ : CFG4
      generic map(INIT => x"090C")

      port map(A => \un1_inp_wraddr_1_axbxc5_m2_i_o2_0\, B => 
        \inp_wraddr[5]_net_1\, C => N_1157, D => 
        un1_inp_wraddr_1_ac0_3tt_N_7_mux, Y => N_9_i_0);
    
    \Xn_in_ibuf[4]\ : INBUF
      port map(PAD => Xn_in(4), Y => \Xn_in_c[4]\);
    
    \inp_wrdata_dly0[8]\ : SLE
      port map(D => \inp_wrdata[8]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[8]_net_1\);
    
    U2_1 : Inp_RAM1
      port map(un1_inpA_rddata2_10(16) => 
        \un1_inpA_rddata2_10[16]\, un1_inpA_rddata2_10(15) => 
        \un1_inpA_rddata2_10[15]\, un1_inpA_rddata2_10(14) => 
        \un1_inpA_rddata2_10[14]\, un1_inpA_rddata2_10(13) => 
        \un1_inpA_rddata2_10[13]\, un1_inpA_rddata2_10(12) => 
        \un1_inpA_rddata2_10[12]\, un1_inpA_rddata2_10(11) => 
        \un1_inpA_rddata2_10[11]\, un1_inpA_rddata2_10(10) => 
        \un1_inpA_rddata2_10[10]\, un1_inpA_rddata2_10(9) => 
        \un1_inpA_rddata2_10[9]\, un1_inpA_rddata2_10(8) => 
        \un1_inpA_rddata2_10[8]\, un1_inpA_rddata2_10(7) => 
        \un1_inpA_rddata2_10[7]\, un1_inpA_rddata2_10(6) => 
        \un1_inpA_rddata2_10[6]\, un1_inpA_rddata2_10(5) => 
        \un1_inpA_rddata2_10[5]\, un1_inpA_rddata2_10(4) => 
        \un1_inpA_rddata2_10[4]\, un1_inpA_rddata2_10(3) => 
        \un1_inpA_rddata2_10[3]\, un1_inpA_rddata2_10(2) => 
        \un1_inpA_rddata2_10[2]\, un1_inpA_rddata2_10(1) => 
        \un1_inpA_rddata2_10[1]\, inpA_rddata2(17) => 
        \inpA_rddata2[17]\, inpA_rddata2(16) => 
        \inpA_rddata2[16]\, inpA_rddata2(15) => 
        \inpA_rddata2[15]\, inpA_rddata2(14) => 
        \inpA_rddata2[14]\, inpA_rddata2(13) => 
        \inpA_rddata2[13]\, inpA_rddata2(12) => 
        \inpA_rddata2[12]\, inpA_rddata2(11) => 
        \inpA_rddata2[11]\, inpA_rddata2(10) => 
        \inpA_rddata2[10]\, inpA_rddata2(9) => \inpA_rddata2[9]\, 
        inpA_rddata2(8) => \inpA_rddata2[8]\, inpA_rddata2(7) => 
        \inpA_rddata2[7]\, inpA_rddata2(6) => \inpA_rddata2[6]\, 
        inpA_rddata2(5) => \inpA_rddata2[5]\, inpA_rddata2(4) => 
        \inpA_rddata2[4]\, inpA_rddata2(3) => \inpA_rddata2[3]\, 
        inpA_rddata2(2) => \inpA_rddata2[2]\, inpA_rddata2(1) => 
        \inpA_rddata2[1]\, inpA_rddata2(0) => \inpA_rddata2[0]\, 
        inpB_rddata2(17) => \inpB_rddata2[17]\, inpB_rddata2(16)
         => \inpB_rddata2[16]\, inpB_rddata2(15) => 
        \inpB_rddata2[15]\, inpB_rddata2(14) => 
        \inpB_rddata2[14]\, inpB_rddata2(13) => 
        \inpB_rddata2[13]\, inpB_rddata2(12) => 
        \inpB_rddata2[12]\, inpB_rddata2(11) => 
        \inpB_rddata2[11]\, inpB_rddata2(10) => 
        \inpB_rddata2[10]\, inpB_rddata2(9) => \inpB_rddata2[9]\, 
        inpB_rddata2(8) => \inpB_rddata2[8]\, inpB_rddata2(7) => 
        \inpB_rddata2[7]\, inpB_rddata2(6) => \inpB_rddata2[6]\, 
        inpB_rddata2(5) => \inpB_rddata2[5]\, inpB_rddata2(4) => 
        \inpB_rddata2[4]\, inpB_rddata2(3) => \inpB_rddata2[3]\, 
        inpB_rddata2(2) => \inpB_rddata2[2]\, inpB_rddata2(1) => 
        \inpB_rddata2[1]\, inpB_rddata2(0) => \inpB_rddata2[0]\, 
        InpA_rdaddr1(5) => \InpA_rdaddr1[5]_net_1\, 
        InpA_rdaddr1(4) => \InpA_rdaddr1[4]_net_1\, 
        InpA_rdaddr1(3) => \InpA_rdaddr1[3]_net_1\, 
        InpA_rdaddr1(2) => \InpA_rdaddr1[2]_net_1\, 
        InpA_rdaddr1(1) => \InpA_rdaddr1[1]_net_1\, 
        InpA_rdaddr1(0) => \InpA_rdaddr1[0]_net_1\, 
        InpB_rdaddr1(5) => \InpB_rdaddr1[5]_net_1\, 
        InpB_rdaddr1(4) => \InpB_rdaddr1[4]_net_1\, 
        InpB_rdaddr1(3) => \InpB_rdaddr1[3]_net_1\, 
        InpB_rdaddr1(2) => \InpB_rdaddr1[2]_net_1\, 
        InpB_rdaddr1(1) => \InpB_rdaddr1[1]_net_1\, 
        InpB_rdaddr1(0) => \InpB_rdaddr1[0]_net_1\, 
        inp_wraddr2(5) => \inp_wraddr2[5]_net_1\, inp_wraddr2(4)
         => \inp_wraddr2[4]_net_1\, inp_wraddr2(3) => 
        \inp_wraddr2[3]_net_1\, inp_wraddr2(2) => 
        \inp_wraddr2[2]_net_1\, inp_wraddr2(1) => 
        \inp_wraddr2[1]_net_1\, inp_wraddr2(0) => 
        \inp_wraddr2[0]_net_1\, inp_wrdata_dly0(17) => 
        \inp_wrdata_dly0[17]_net_1\, inp_wrdata_dly0(16) => 
        \inp_wrdata_dly0[16]_net_1\, inp_wrdata_dly0(15) => 
        \inp_wrdata_dly0[15]_net_1\, inp_wrdata_dly0(14) => 
        \inp_wrdata_dly0[14]_net_1\, inp_wrdata_dly0(13) => 
        \inp_wrdata_dly0[13]_net_1\, inp_wrdata_dly0(12) => 
        \inp_wrdata_dly0[12]_net_1\, inp_wrdata_dly0(11) => 
        \inp_wrdata_dly0[11]_net_1\, inp_wrdata_dly0(10) => 
        \inp_wrdata_dly0[10]_net_1\, inp_wrdata_dly0(9) => 
        \inp_wrdata_dly0[9]_net_1\, inp_wrdata_dly0(8) => 
        \inp_wrdata_dly0[8]_net_1\, inp_wrdata_dly0(7) => 
        \inp_wrdata_dly0[7]_net_1\, inp_wrdata_dly0(6) => 
        \inp_wrdata_dly0[6]_net_1\, inp_wrdata_dly0(5) => 
        \inp_wrdata_dly0[5]_net_1\, inp_wrdata_dly0(4) => 
        \inp_wrdata_dly0[4]_net_1\, inp_wrdata_dly0(3) => 
        \inp_wrdata_dly0[3]_net_1\, inp_wrdata_dly0(2) => 
        \inp_wrdata_dly0[2]_net_1\, inp_wrdata_dly0(1) => 
        \inp_wrdata_dly0[1]_net_1\, inp_wrdata_dly0(0) => 
        \inp_wrdata_dly0[0]_net_1\, 
        Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS_Y => 
        Inp_RAM1_Inp_RAM1_0_URAM_R0C0_RNIQ3OS_Y, 
        un1_inpA_rddata2_cry_16 => un1_inpA_rddata2_cry_16, clk_c
         => clk_c, InpA_rden1 => \InpA_rden1\, InpB_rden1 => 
        \InpB_rden1\, InpCoef1_wren => \InpCoef1_wren\);
    
    \rdy_cnt[4]\ : SLE
      port map(D => un1_rdy_cnt_1_axbxc4_N_9_i_i_0, CLK => clk_c, 
        EN => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \rdy_cnt[4]_net_1\);
    
    \Mac_out_obuf[17]\ : OUTBUF
      port map(D => \Mac_out_c[17]\, PAD => Mac_out(17));
    
    \Coef_rddata[8]\ : SLE
      port map(D => \Coef_rddata1[8]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[8]_net_1\);
    
    \inpB_rdaddr[7]\ : SLE
      port map(D => N_51_i_0, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \inpB_rdaddr[7]_net_1\);
    
    \Coef_rddata[13]\ : SLE
      port map(D => \Coef_rddata1[13]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[13]_net_1\);
    
    \inp_rddata_RNO_0[4]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[4]\, D => \un1_inpA_rddata2_10[4]\, 
        Y => un1_inpA_rddata2_1_m_3_15_i_m2_i_m2_1_1);
    
    \Mac_out[24]\ : SLE
      port map(D => \Yn_out[24]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[24]\);
    
    \A_rdaddr[5]\ : SLE
      port map(D => N_34_i_0, CLK => clk_c, EN => \FiltOp_done\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \A_rdaddr[5]_net_1\);
    
    \un1_inp_wraddr_0_a2_0_a2_0[0]\ : CFG4
      generic map(INIT => x"3133")

      port map(A => \inp_wraddr[5]_net_1\, B => 
        \inp_wraddr[7]_net_1\, C => 
        \un1_inp_wraddr_0_a2_0_a2_0_1[0]_net_1\, D => 
        \inp_wraddr[6]_net_1\, Y => 
        \un1_inp_wraddr_0_a2_0_a2_0[0]_net_1\);
    
    \Mac_out_obuf[19]\ : OUTBUF
      port map(D => \Mac_out_c[19]\, PAD => Mac_out(19));
    
    \Xn_in_ibuf[0]\ : INBUF
      port map(PAD => Xn_in(0), Y => \Xn_in_c[0]\);
    
    un2_data_valid_dly_i_0_a2 : CFG2
      generic map(INIT => x"8")

      port map(A => \un2_data_valid_dly_i_0_a2_4\, B => 
        \un2_data_valid_dly_i_0_a2_3\, Y => N_1157);
    
    \inp_rddata[17]\ : SLE
      port map(D => N_186, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[17]_net_1\);
    
    un2_data_valid_dly_i_0_a2_3 : CFG4
      generic map(INIT => x"0010")

      port map(A => \inp_wraddr[7]_net_1\, B => 
        \inp_wraddr[1]_net_1\, C => \inp_wraddr[2]_net_1\, D => 
        \inp_wraddr[0]_net_1\, Y => \un2_data_valid_dly_i_0_a2_3\);
    
    \op_eq.new_data2_0_a2\ : CFG4
      generic map(INIT => x"0040")

      port map(A => \Coef_rdaddr[4]_net_1\, B => 
        \Coef_rdaddr[3]_net_1\, C => 
        \op_eq.new_data2_0_a2_2_net_1\, D => N_14, Y => 
        \op_eq.new_data2\);
    
    \inpA_rdaddr[5]\ : SLE
      port map(D => \inpA_rdaddr_lm[5]\, CLK => clk_c, EN => 
        N_107_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inpA_rdaddr[5]_net_1\);
    
    \mac_state_ns_0_0[3]\ : CFG4
      generic map(INIT => x"FDCC")

      port map(A => \Data_Valid_dly\, B => N_152, C => 
        Data_Valid_c, D => \mac_state[2]_net_1\, Y => 
        \mac_state_ns[3]\);
    
    \Mac_out[33]\ : SLE
      port map(D => \Yn_out[33]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[33]\);
    
    \op_eq.new_data2_0_o3\ : CFG3
      generic map(INIT => x"FE")

      port map(A => \Coef_rdaddr[7]_net_1\, B => 
        \Coef_rdaddr[6]_net_1\, C => \Coef_rdaddr[1]_net_1\, Y
         => N_14);
    
    \inp_rddata_RNO[15]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[15]\, B => 
        un1_inpA_rddata2_1_m_3_8_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[15]\, Y => 
        \inp_rddata_RNO[15]_net_1\);
    
    \Mac_out_obuf[35]\ : OUTBUF
      port map(D => \Mac_out_c[35]\, PAD => Mac_out(35));
    
    \Mac_out[9]\ : SLE
      port map(D => \Yn_out[9]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[9]\);
    
    \inp_wrdata[14]\ : SLE
      port map(D => \Xn_in_c[14]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[14]_net_1\);
    
    \Mac_out_obuf[13]\ : OUTBUF
      port map(D => \Mac_out_c[13]\, PAD => Mac_out(13));
    
    U2 : Inp_RAM
      port map(un1_inpA_rddata2_12(16) => 
        \un1_inpA_rddata2_12[16]\, un1_inpA_rddata2_12(15) => 
        \un1_inpA_rddata2_12[15]\, un1_inpA_rddata2_12(14) => 
        \un1_inpA_rddata2_12[14]\, un1_inpA_rddata2_12(13) => 
        \un1_inpA_rddata2_12[13]\, un1_inpA_rddata2_12(12) => 
        \un1_inpA_rddata2_12[12]\, un1_inpA_rddata2_12(11) => 
        \un1_inpA_rddata2_12[11]\, un1_inpA_rddata2_12(10) => 
        \un1_inpA_rddata2_12[10]\, un1_inpA_rddata2_12(9) => 
        \un1_inpA_rddata2_12[9]\, un1_inpA_rddata2_12(8) => 
        \un1_inpA_rddata2_12[8]\, un1_inpA_rddata2_12(7) => 
        \un1_inpA_rddata2_12[7]\, un1_inpA_rddata2_12(6) => 
        \un1_inpA_rddata2_12[6]\, un1_inpA_rddata2_12(5) => 
        \un1_inpA_rddata2_12[5]\, un1_inpA_rddata2_12(4) => 
        \un1_inpA_rddata2_12[4]\, un1_inpA_rddata2_12(3) => 
        \un1_inpA_rddata2_12[3]\, un1_inpA_rddata2_12(2) => 
        \un1_inpA_rddata2_12[2]\, un1_inpA_rddata2_12(1) => 
        \un1_inpA_rddata2_12[1]\, inpA_rddata2(16) => 
        \inpA_rddata2[16]\, inpA_rddata2(15) => 
        \inpA_rddata2[15]\, inpA_rddata2(14) => 
        \inpA_rddata2[14]\, inpA_rddata2(13) => 
        \inpA_rddata2[13]\, inpA_rddata2(12) => 
        \inpA_rddata2[12]\, inpA_rddata2(11) => 
        \inpA_rddata2[11]\, inpA_rddata2(10) => 
        \inpA_rddata2[10]\, inpA_rddata2(9) => \inpA_rddata2[9]\, 
        inpA_rddata2(8) => \inpA_rddata2[8]\, inpA_rddata2(7) => 
        \inpA_rddata2[7]\, inpA_rddata2(6) => \inpA_rddata2[6]\, 
        inpA_rddata2(5) => \inpA_rddata2[5]\, inpA_rddata2(4) => 
        \inpA_rddata2[4]\, inpA_rddata2(3) => \inpA_rddata2[3]\, 
        inpA_rddata2(2) => \inpA_rddata2[2]\, inpA_rddata2(1) => 
        \inpA_rddata2[1]\, inpA_rddata2(0) => \inpA_rddata2[0]\, 
        un1_inpA_rddata2_11(16) => \un1_inpA_rddata2_11[16]\, 
        un1_inpA_rddata2_11(15) => \un1_inpA_rddata2_11[15]\, 
        un1_inpA_rddata2_11(14) => \un1_inpA_rddata2_11[14]\, 
        un1_inpA_rddata2_11(13) => \un1_inpA_rddata2_11[13]\, 
        un1_inpA_rddata2_11(12) => \un1_inpA_rddata2_11[12]\, 
        un1_inpA_rddata2_11(11) => \un1_inpA_rddata2_11[11]\, 
        un1_inpA_rddata2_11(10) => \un1_inpA_rddata2_11[10]\, 
        un1_inpA_rddata2_11(9) => \un1_inpA_rddata2_11[9]\, 
        un1_inpA_rddata2_11(8) => \un1_inpA_rddata2_11[8]\, 
        un1_inpA_rddata2_11(7) => \un1_inpA_rddata2_11[7]\, 
        un1_inpA_rddata2_11(6) => \un1_inpA_rddata2_11[6]\, 
        un1_inpA_rddata2_11(5) => \un1_inpA_rddata2_11[5]\, 
        un1_inpA_rddata2_11(4) => \un1_inpA_rddata2_11[4]\, 
        un1_inpA_rddata2_11(3) => \un1_inpA_rddata2_11[3]\, 
        un1_inpA_rddata2_11(2) => \un1_inpA_rddata2_11[2]\, 
        un1_inpA_rddata2_11(1) => \un1_inpA_rddata2_11[1]\, 
        inpB_rddata2(16) => \inpB_rddata2[16]\, inpB_rddata2(15)
         => \inpB_rddata2[15]\, inpB_rddata2(14) => 
        \inpB_rddata2[14]\, inpB_rddata2(13) => 
        \inpB_rddata2[13]\, inpB_rddata2(12) => 
        \inpB_rddata2[12]\, inpB_rddata2(11) => 
        \inpB_rddata2[11]\, inpB_rddata2(10) => 
        \inpB_rddata2[10]\, inpB_rddata2(9) => \inpB_rddata2[9]\, 
        inpB_rddata2(8) => \inpB_rddata2[8]\, inpB_rddata2(7) => 
        \inpB_rddata2[7]\, inpB_rddata2(6) => \inpB_rddata2[6]\, 
        inpB_rddata2(5) => \inpB_rddata2[5]\, inpB_rddata2(4) => 
        \inpB_rddata2[4]\, inpB_rddata2(3) => \inpB_rddata2[3]\, 
        inpB_rddata2(2) => \inpB_rddata2[2]\, inpB_rddata2(1) => 
        \inpB_rddata2[1]\, inpB_rddata2(0) => \inpB_rddata2[0]\, 
        un1_inpA_rddata2_13(16) => \un1_inpA_rddata2_13[16]\, 
        un1_inpA_rddata2_13(15) => \un1_inpA_rddata2_13[15]\, 
        un1_inpA_rddata2_13(14) => \un1_inpA_rddata2_13[14]\, 
        un1_inpA_rddata2_13(13) => \un1_inpA_rddata2_13[13]\, 
        un1_inpA_rddata2_13(12) => \un1_inpA_rddata2_13[12]\, 
        un1_inpA_rddata2_13(11) => \un1_inpA_rddata2_13[11]\, 
        un1_inpA_rddata2_13(10) => \un1_inpA_rddata2_13[10]\, 
        un1_inpA_rddata2_13(9) => \un1_inpA_rddata2_13[9]\, 
        un1_inpA_rddata2_13(8) => \un1_inpA_rddata2_13[8]\, 
        un1_inpA_rddata2_13(7) => \un1_inpA_rddata2_13[7]\, 
        un1_inpA_rddata2_13(6) => \un1_inpA_rddata2_13[6]\, 
        un1_inpA_rddata2_13(5) => \un1_inpA_rddata2_13[5]\, 
        un1_inpA_rddata2_13(4) => \un1_inpA_rddata2_13[4]\, 
        un1_inpA_rddata2_13(3) => \un1_inpA_rddata2_13[3]\, 
        un1_inpA_rddata2_13(2) => \un1_inpA_rddata2_13[2]\, 
        un1_inpA_rddata2_13(1) => \un1_inpA_rddata2_13[1]\, 
        InpA_rdaddr1(5) => \InpA_rdaddr1[5]_net_1\, 
        InpA_rdaddr1(4) => \InpA_rdaddr1[4]_net_1\, 
        InpA_rdaddr1(3) => \InpA_rdaddr1[3]_net_1\, 
        InpA_rdaddr1(2) => \InpA_rdaddr1[2]_net_1\, 
        InpA_rdaddr1(1) => \InpA_rdaddr1[1]_net_1\, 
        InpA_rdaddr1(0) => \InpA_rdaddr1[0]_net_1\, 
        InpB_rdaddr1(5) => \InpB_rdaddr1[5]_net_1\, 
        InpB_rdaddr1(4) => \InpB_rdaddr1[4]_net_1\, 
        InpB_rdaddr1(3) => \InpB_rdaddr1[3]_net_1\, 
        InpB_rdaddr1(2) => \InpB_rdaddr1[2]_net_1\, 
        InpB_rdaddr1(1) => \InpB_rdaddr1[1]_net_1\, 
        InpB_rdaddr1(0) => \InpB_rdaddr1[0]_net_1\, 
        inp_wraddr1(5) => \inp_wraddr1[5]_net_1\, inp_wraddr1(4)
         => \inp_wraddr1[4]_net_1\, inp_wraddr1(3) => 
        \inp_wraddr1[3]_net_1\, inp_wraddr1(2) => 
        \inp_wraddr1[2]_net_1\, inp_wraddr1(1) => 
        \inp_wraddr1[1]_net_1\, inp_wraddr1(0) => 
        \inp_wraddr1[0]_net_1\, inp_wrdata_dly0(17) => 
        \inp_wrdata_dly0[17]_net_1\, inp_wrdata_dly0(16) => 
        \inp_wrdata_dly0[16]_net_1\, inp_wrdata_dly0(15) => 
        \inp_wrdata_dly0[15]_net_1\, inp_wrdata_dly0(14) => 
        \inp_wrdata_dly0[14]_net_1\, inp_wrdata_dly0(13) => 
        \inp_wrdata_dly0[13]_net_1\, inp_wrdata_dly0(12) => 
        \inp_wrdata_dly0[12]_net_1\, inp_wrdata_dly0(11) => 
        \inp_wrdata_dly0[11]_net_1\, inp_wrdata_dly0(10) => 
        \inp_wrdata_dly0[10]_net_1\, inp_wrdata_dly0(9) => 
        \inp_wrdata_dly0[9]_net_1\, inp_wrdata_dly0(8) => 
        \inp_wrdata_dly0[8]_net_1\, inp_wrdata_dly0(7) => 
        \inp_wrdata_dly0[7]_net_1\, inp_wrdata_dly0(6) => 
        \inp_wrdata_dly0[6]_net_1\, inp_wrdata_dly0(5) => 
        \inp_wrdata_dly0[5]_net_1\, inp_wrdata_dly0(4) => 
        \inp_wrdata_dly0[4]_net_1\, inp_wrdata_dly0(3) => 
        \inp_wrdata_dly0[3]_net_1\, inp_wrdata_dly0(2) => 
        \inp_wrdata_dly0[2]_net_1\, inp_wrdata_dly0(1) => 
        \inp_wrdata_dly0[1]_net_1\, inp_wrdata_dly0(0) => 
        \inp_wrdata_dly0[0]_net_1\, \inpA_rddata1[17]\ => 
        \inpA_rddata1[17]\, \inpB_rddata1[17]\ => 
        \inpB_rddata1[17]\, 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_0_Y => 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_0_Y, 
        un1_inpA_rddata2_2_cry_16 => un1_inpA_rddata2_2_cry_16, 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_Y => 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNING1I_Y, 
        un1_inpA_rddata2_0_cry_16 => un1_inpA_rddata2_0_cry_16, 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIKTA7_Y => 
        Inp_RAM_Inp_RAM_0_URAM_R0C0_RNIKTA7_Y, 
        un1_inpA_rddata2_3_cry_16 => un1_inpA_rddata2_3_cry_16, 
        clk_c => clk_c, InpA_rden0 => \InpA_rden0\, InpB_rden0
         => \InpB_rden0\, InpCoef0_wren => \InpCoef0_wren\);
    
    \inp_wraddr[1]\ : SLE
      port map(D => \un1_inp_wraddr_1_axbxc1\, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wraddr[1]_net_1\);
    
    \Mac_out[17]\ : SLE
      port map(D => \Yn_out[17]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[17]\);
    
    clrsig_0 : SLE
      port map(D => \clrsig\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \clrsig_0\);
    
    \inp_rddata_RNO[2]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[2]\, B => 
        un1_inpA_rddata2_1_m_3_13_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[2]\, Y => N_177);
    
    InpA_rden0_1_iv_0_0_0 : CFG4
      generic map(INIT => x"EAAA")

      port map(A => N_69, B => N_68, C => \inpA_rdaddr[5]_net_1\, 
        D => \InpA_rden0\, Y => InpA_rden0_1);
    
    \Coef_rddata[1]\ : SLE
      port map(D => \Coef_rddata1[1]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[1]_net_1\);
    
    un1_a_rdaddr_ac0_9_0 : CFG3
      generic map(INIT => x"80")

      port map(A => \A_rdaddr[5]_net_1\, B => \A_rdaddr[4]_net_1\, 
        C => \A_rdaddr[3]_net_1\, Y => \un1_a_rdaddr_ac0_9_0\);
    
    \Mac_out_obuf[25]\ : OUTBUF
      port map(D => \Mac_out_c[25]\, PAD => Mac_out(25));
    
    \Mac_out[29]\ : SLE
      port map(D => \Yn_out[29]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[29]\);
    
    \Coef_rddata[4]\ : SLE
      port map(D => \Coef_rddata1[4]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[4]_net_1\);
    
    \Coef_rdaddr[6]\ : SLE
      port map(D => \un1_coef_rdaddr_1_axbxc6\, CLK => clk_c, EN
         => \mac_state[1]_net_1\, ALn => reset_n_c, ADn => 
        VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT => 
        GND_net_1, Q => \Coef_rdaddr[6]_net_1\);
    
    \inp_wraddr1[4]\ : SLE
      port map(D => N_576, CLK => clk_c, EN => 
        \un1_inp_wraddr_0_a2_0_a2_0[0]_net_1\, ALn => reset_n_c, 
        ADn => VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT
         => GND_net_1, Q => \inp_wraddr1[4]_net_1\);
    
    \B_rdaddr_lm_0[5]\ : CFG4
      generic map(INIT => x"DCFC")

      port map(A => un1_b_rdaddr10_i_0_627_0_0_a2_5, B => 
        \Transferdone\, C => \B_rdaddr_s[5]\, D => 
        un1_b_rdaddr10_i_0_627_0_0_a2_4, Y => \B_rdaddr_lm[5]\);
    
    Coef0_rden_RNO : CFG4
      generic map(INIT => x"2A3F")

      port map(A => \Coef0_rden\, B => 
        \Coef_rdaddr_2_i_a2_0[1]_net_1\, C => 
        \Coef_rdaddr_2_i_a2_1[1]_net_1\, D => N_19, Y => N_10_i_0);
    
    \mac_state_ns_0_0_0[4]\ : CFG4
      generic map(INIT => x"F444")

      port map(A => \FiltOp_done\, B => \mac_state[1]_net_1\, C
         => Filter_En_c, D => \mac_state[0]_net_1\, Y => 
        \mac_state_ns_0_0_0[4]_net_1\);
    
    \inpB_rdaddr_RNO_3[7]\ : CFG1
      generic map(INIT => x"1")

      port map(A => \mac_state[0]_net_1\, Y => \mac_state_i_0[0]\);
    
    \B_rdaddr[5]\ : SLE
      port map(D => \B_rdaddr_lm[5]\, CLK => clk_c, EN => 
        N_108_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \B_rdaddr[5]_net_1\);
    
    un1_inp_wraddr_1_axbxc4 : CFG3
      generic map(INIT => x"78")

      port map(A => \inp_wraddr[3]_net_1\, B => 
        un1_inp_wraddr_1_ac0_3tt_N_7_mux, C => 
        \inp_wraddr[4]_net_1\, Y => \un1_inp_wraddr_1_axbxc4\);
    
    U0 : mulacc_18x18
      port map(Yn_out(43) => \Yn_out[43]\, Yn_out(42) => 
        \Yn_out[42]\, Yn_out(41) => \Yn_out[41]\, Yn_out(40) => 
        \Yn_out[40]\, Yn_out(39) => \Yn_out[39]\, Yn_out(38) => 
        \Yn_out[38]\, Yn_out(37) => \Yn_out[37]\, Yn_out(36) => 
        \Yn_out[36]\, Yn_out(35) => \Yn_out[35]\, Yn_out(34) => 
        \Yn_out[34]\, Yn_out(33) => \Yn_out[33]\, Yn_out(32) => 
        \Yn_out[32]\, Yn_out(31) => \Yn_out[31]\, Yn_out(30) => 
        \Yn_out[30]\, Yn_out(29) => \Yn_out[29]\, Yn_out(28) => 
        \Yn_out[28]\, Yn_out(27) => \Yn_out[27]\, Yn_out(26) => 
        \Yn_out[26]\, Yn_out(25) => \Yn_out[25]\, Yn_out(24) => 
        \Yn_out[24]\, Yn_out(23) => \Yn_out[23]\, Yn_out(22) => 
        \Yn_out[22]\, Yn_out(21) => \Yn_out[21]\, Yn_out(20) => 
        \Yn_out[20]\, Yn_out(19) => \Yn_out[19]\, Yn_out(18) => 
        \Yn_out[18]\, Yn_out(17) => \Yn_out[17]\, Yn_out(16) => 
        \Yn_out[16]\, Yn_out(15) => \Yn_out[15]\, Yn_out(14) => 
        \Yn_out[14]\, Yn_out(13) => \Yn_out[13]\, Yn_out(12) => 
        \Yn_out[12]\, Yn_out(11) => \Yn_out[11]\, Yn_out(10) => 
        \Yn_out[10]\, Yn_out(9) => \Yn_out[9]\, Yn_out(8) => 
        \Yn_out[8]\, Yn_out(7) => \Yn_out[7]\, Yn_out(6) => 
        \Yn_out[6]\, Yn_out(5) => \Yn_out[5]\, Yn_out(4) => 
        \Yn_out[4]\, Yn_out(3) => \Yn_out[3]\, Yn_out(2) => 
        \Yn_out[2]\, Yn_out(1) => \Yn_out[1]\, Yn_out(0) => 
        \Yn_out[0]\, inp_rddata(17) => \inp_rddata[17]_net_1\, 
        inp_rddata(16) => \inp_rddata[16]_net_1\, inp_rddata(15)
         => \inp_rddata[15]_net_1\, inp_rddata(14) => 
        \inp_rddata[14]_net_1\, inp_rddata(13) => 
        \inp_rddata[13]_net_1\, inp_rddata(12) => 
        \inp_rddata[12]_net_1\, inp_rddata(11) => 
        \inp_rddata[11]_net_1\, inp_rddata(10) => 
        \inp_rddata[10]_net_1\, inp_rddata(9) => 
        \inp_rddata[9]_net_1\, inp_rddata(8) => 
        \inp_rddata[8]_net_1\, inp_rddata(7) => 
        \inp_rddata[7]_net_1\, inp_rddata(6) => 
        \inp_rddata[6]_net_1\, inp_rddata(5) => 
        \inp_rddata[5]_net_1\, inp_rddata(4) => 
        \inp_rddata[4]_net_1\, inp_rddata(3) => 
        \inp_rddata[3]_net_1\, inp_rddata(2) => 
        \inp_rddata[2]_net_1\, inp_rddata(1) => 
        \inp_rddata[1]_net_1\, inp_rddata(0) => 
        \inp_rddata[0]_net_1\, Coef_rddata(17) => 
        \Coef_rddata[17]_net_1\, Coef_rddata(16) => 
        \Coef_rddata[16]_net_1\, Coef_rddata(15) => 
        \Coef_rddata[15]_net_1\, Coef_rddata(14) => 
        \Coef_rddata[14]_net_1\, Coef_rddata(13) => 
        \Coef_rddata[13]_net_1\, Coef_rddata(12) => 
        \Coef_rddata[12]_net_1\, Coef_rddata(11) => 
        \Coef_rddata[11]_net_1\, Coef_rddata(10) => 
        \Coef_rddata[10]_net_1\, Coef_rddata(9) => 
        \Coef_rddata[9]_net_1\, Coef_rddata(8) => 
        \Coef_rddata[8]_net_1\, Coef_rddata(7) => 
        \Coef_rddata[7]_net_1\, Coef_rddata(6) => 
        \Coef_rddata[6]_net_1\, Coef_rddata(5) => 
        \Coef_rddata[5]_net_1\, Coef_rddata(4) => 
        \Coef_rddata[4]_net_1\, Coef_rddata(3) => 
        \Coef_rddata[3]_net_1\, Coef_rddata(2) => 
        \Coef_rddata[2]_net_1\, Coef_rddata(1) => 
        \Coef_rddata[1]_net_1\, Coef_rddata(0) => 
        \Coef_rddata[0]_net_1\, reset_n_c => reset_n_c, clr_i_0
         => clr_i_0, clk_c => clk_c);
    
    \Mac_out_obuf[6]\ : OUTBUF
      port map(D => \Mac_out_c[6]\, PAD => Mac_out(6));
    
    \inp_wraddr2[5]\ : SLE
      port map(D => un16_inp_wraddr_2_i_0, CLK => clk_c, EN => 
        \un1_inp_wraddr_0_a2_0_a2_0[0]_net_1\, ALn => reset_n_c, 
        ADn => VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT
         => GND_net_1, Q => \inp_wraddr2[5]_net_1\);
    
    \A_rdaddr[3]\ : SLE
      port map(D => \un1_a_rdaddr_axbxc3\, CLK => clk_c, EN => 
        \FiltOp_done\, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \A_rdaddr[3]_net_1\);
    
    \Xn_in_ibuf[1]\ : INBUF
      port map(PAD => Xn_in(1), Y => \Xn_in_c[1]\);
    
    rdy_cnt_3_0_a2_0_a2_6_m3_i_o2_2 : CFG4
      generic map(INIT => x"7FFF")

      port map(A => \rdy_cnt[4]_net_1\, B => \rdy_cnt[3]_net_1\, 
        C => \rdy_cnt[2]_net_1\, D => \rdy_cnt[1]_net_1\, Y => 
        \rdy_cnt_3_0_a2_0_a2_6_m3_i_o2_2\);
    
    New_data : SLE
      port map(D => \op_eq.new_data2\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \New_data\);
    
    \inpA_rdaddr_4_i_i_a2[3]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \mac_state[0]_net_1\, B => 
        \A_rdaddr[3]_net_1\, Y => N_155);
    
    \inpA_rdaddr_4_i_i_a2[2]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \mac_state[0]_net_1\, B => 
        \A_rdaddr[2]_net_1\, Y => N_154);
    
    \Mac_out_obuf[3]\ : OUTBUF
      port map(D => \Mac_out_c[3]\, PAD => Mac_out(3));
    
    \inp_wrdata_dly0[14]\ : SLE
      port map(D => \inp_wrdata[14]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[14]_net_1\);
    
    \Mac_out[16]\ : SLE
      port map(D => \Yn_out[16]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[16]\);
    
    \inp_rddata_RNO_0[17]\ : ARI1
      generic map(INIT => x"46600")

      port map(A => VCC_net_1, B => \inpA_rddata1[17]\, C => 
        \inpB_rddata2[17]\, D => GND_net_1, FCI => 
        un1_inpA_rddata2_0_cry_16, S => \un1_inpA_rddata2_11[17]\, 
        Y => OPEN, FCO => OPEN);
    
    \Coef_rddata[15]\ : SLE
      port map(D => \Coef_rddata1[15]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[15]_net_1\);
    
    \Coef_rdaddr_RNO[0]\ : CFG1
      generic map(INIT => x"1")

      port map(A => \Coef_rdaddr[0]_net_1\, Y => 
        \Coef_rdaddr_i_0[0]\);
    
    \Xn_in_ibuf[2]\ : INBUF
      port map(PAD => Xn_in(2), Y => \Xn_in_c[2]\);
    
    \mac_state_ns_i_0_i_a2[5]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \mac_state[1]_net_1\, B => \FiltOp_done\, Y
         => N_153);
    
    \Mac_out_obuf[9]\ : OUTBUF
      port map(D => \Mac_out_c[9]\, PAD => Mac_out(9));
    
    \inp_rddata[0]\ : SLE
      port map(D => N_183, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[0]_net_1\);
    
    un1_rdy_cnt_1_axbxc3 : CFG4
      generic map(INIT => x"78F0")

      port map(A => \rdy_cnt[1]_net_1\, B => un1_rdy_cnt_1_c1, C
         => \rdy_cnt[3]_net_1\, D => \rdy_cnt[2]_net_1\, Y => 
        \un1_rdy_cnt_1_axbxc3\);
    
    InpCoef1_wren_1_0_a2_0_o3 : CFG4
      generic map(INIT => x"0F1F")

      port map(A => \inp_wraddr[4]_net_1\, B => 
        \inp_wraddr[3]_net_1\, C => \inp_wraddr[5]_net_1\, D => 
        \inp_wraddr[2]_net_1\, Y => N_120);
    
    \InpB_rdaddr1[1]\ : SLE
      port map(D => \inpB_rdaddr[1]_net_1\, CLK => clk_c, EN => 
        N_163_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \InpB_rdaddr1[1]_net_1\);
    
    un1_rdy_cnt_1_ac0 : CFG3
      generic map(INIT => x"40")

      port map(A => \Transferdone\, B => \rdy_sig\, C => 
        \rdy_cnt[0]_net_1\, Y => un1_rdy_cnt_1_c1);
    
    U1 : Coef_RAM
      port map(Coef_rddata1(17) => \Coef_rddata1[17]\, 
        Coef_rddata1(16) => \Coef_rddata1[16]\, Coef_rddata1(15)
         => \Coef_rddata1[15]\, Coef_rddata1(14) => 
        \Coef_rddata1[14]\, Coef_rddata1(13) => 
        \Coef_rddata1[13]\, Coef_rddata1(12) => 
        \Coef_rddata1[12]\, Coef_rddata1(11) => 
        \Coef_rddata1[11]\, Coef_rddata1(10) => 
        \Coef_rddata1[10]\, Coef_rddata1(9) => \Coef_rddata1[9]\, 
        Coef_rddata1(8) => \Coef_rddata1[8]\, Coef_rddata1(7) => 
        \Coef_rddata1[7]\, Coef_rddata1(6) => \Coef_rddata1[6]\, 
        Coef_rddata1(5) => \Coef_rddata1[5]\, Coef_rddata1(4) => 
        \Coef_rddata1[4]\, Coef_rddata1(3) => \Coef_rddata1[3]\, 
        Coef_rddata1(2) => \Coef_rddata1[2]\, Coef_rddata1(1) => 
        \Coef_rddata1[1]\, Coef_rddata1(0) => \Coef_rddata1[0]\, 
        Coef_rdaddr1(5) => \Coef_rdaddr1[5]_net_1\, 
        Coef_rdaddr1(4) => \Coef_rdaddr1[4]_net_1\, 
        Coef_rdaddr1(3) => \Coef_rdaddr1[3]_net_1\, 
        Coef_rdaddr1(2) => \Coef_rdaddr1[2]_net_1\, 
        Coef_rdaddr1(1) => \Coef_rdaddr1[1]_net_1\, 
        Coef_rdaddr1(0) => \Coef_rdaddr1[0]_net_1\, clk_c => 
        clk_c, Coef0_rden => \Coef0_rden\);
    
    \inp_wraddr_RNO[2]\ : CFG4
      generic map(INIT => x"0666")

      port map(A => \inp_wraddr[2]_net_1\, B => 
        \inp_wraddr_2_i_0_2_m5_e\, C => 
        \un2_data_valid_dly_i_0_a2_3\, D => 
        \un2_data_valid_dly_i_0_a2_4\, Y => N_1068_i_0);
    
    \rdy_cnt[1]\ : SLE
      port map(D => \rdy_cnt_3[1]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \rdy_cnt[1]_net_1\);
    
    un1_coef_rdaddr_1_axbxc6 : CFG2
      generic map(INIT => x"6")

      port map(A => un1_coef_rdaddr_1_c6, B => 
        \Coef_rdaddr[6]_net_1\, Y => \un1_coef_rdaddr_1_axbxc6\);
    
    \inpA_rdaddr_lm_0[2]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => \inpA_rdaddr_s[2]\, B => N_5, C => N_154, Y
         => \inpA_rdaddr_lm[2]\);
    
    \inp_rddata_RNO[11]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[11]\, B => 
        un1_inpA_rddata2_1_m_3_4_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[11]\, Y => N_204);
    
    InpCoef1_wren : SLE
      port map(D => InpCoef1_wren_1, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => GND_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \InpCoef1_wren\);
    
    InpB_rden0 : SLE
      port map(D => InpB_rden0_1, CLK => clk_c, EN => 
        \mac_state[1]_net_1\, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \InpB_rden0\);
    
    \inpB_rdaddr_4_1_0[6]\ : CFG4
      generic map(INIT => x"CECC")

      port map(A => \inpB_rdaddr_4_i_0_a2_2[2]_net_1\, B => N_129, 
        C => N_66, D => \inpB_rdaddr_4_i_0_a2_3[2]_net_1\, Y => 
        \inpB_rdaddr_4[6]\);
    
    \Coef_rddata[5]\ : SLE
      port map(D => \Coef_rddata1[5]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[5]_net_1\);
    
    \InpA_rdaddr1[5]\ : SLE
      port map(D => \inpA_rdaddr[5]_net_1\, CLK => clk_c, EN => 
        N_161_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \InpA_rdaddr1[5]_net_1\);
    
    \B_rdaddr_s[7]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \B_rdaddr[7]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => \B_rdaddr_cry[6]_net_1\, 
        S => \B_rdaddr_s[7]_net_1\, Y => OPEN, FCO => OPEN);
    
    \inp_rddata_RNO[1]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[1]\, B => 
        un1_inpA_rddata2_1_m_3_12_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[1]\, Y => N_180);
    
    \B_rdaddr[3]\ : SLE
      port map(D => \B_rdaddr_lm[3]\, CLK => clk_c, EN => 
        N_108_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \B_rdaddr[3]_net_1\);
    
    \inpA_rdaddr[6]\ : SLE
      port map(D => \inpA_rdaddr_lm[6]\, CLK => clk_c, EN => 
        N_107_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inpA_rdaddr[6]_net_1\);
    
    \Coef_rdaddr1[3]\ : SLE
      port map(D => \Coef_rdaddr[3]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rdaddr1[3]_net_1\);
    
    \B_rdaddr_cry[4]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \B_rdaddr[4]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => \B_rdaddr_cry[3]_net_1\, 
        S => \B_rdaddr_s[4]\, Y => OPEN, FCO => 
        \B_rdaddr_cry[4]_net_1\);
    
    \B_rdaddr_RNIO3KK[2]\ : CFG4
      generic map(INIT => x"0001")

      port map(A => \B_rdaddr[7]_net_1\, B => \B_rdaddr[4]_net_1\, 
        C => \B_rdaddr[3]_net_1\, D => \B_rdaddr[2]_net_1\, Y => 
        un1_b_rdaddr10_i_0_627_0_0_a2_5);
    
    \inp_wraddr1[3]\ : SLE
      port map(D => N_568, CLK => clk_c, EN => 
        \un1_inp_wraddr_0_a2_0_a2_0[0]_net_1\, ALn => reset_n_c, 
        ADn => VCC_net_1, SLn => VCC_net_1, SD => GND_net_1, LAT
         => GND_net_1, Q => \inp_wraddr1[3]_net_1\);
    
    \Mac_out_obuf[38]\ : OUTBUF
      port map(D => \Mac_out_c[38]\, PAD => Mac_out(38));
    
    \Mac_out[0]\ : SLE
      port map(D => \Yn_out[0]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[0]\);
    
    \inp_wrdata_dly0[13]\ : SLE
      port map(D => \inp_wrdata[13]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[13]_net_1\);
    
    \B_rdaddr_lm_0[6]\ : CFG4
      generic map(INIT => x"DCFC")

      port map(A => un1_b_rdaddr10_i_0_627_0_0_a2_5, B => 
        \Transferdone\, C => \B_rdaddr_s[6]\, D => 
        un1_b_rdaddr10_i_0_627_0_0_a2_4, Y => \B_rdaddr_lm[6]\);
    
    \B_rdaddr_cry[6]\ : ARI1
      generic map(INIT => x"4AA00")

      port map(A => VCC_net_1, B => \B_rdaddr[6]_net_1\, C => 
        GND_net_1, D => GND_net_1, FCI => \B_rdaddr_cry[5]_net_1\, 
        S => \B_rdaddr_s[6]\, Y => OPEN, FCO => 
        \B_rdaddr_cry[6]_net_1\);
    
    \Coef_rddata[16]\ : SLE
      port map(D => \Coef_rddata1[16]\, CLK => clk_c, EN => 
        \Sel_Coef1\, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rddata[16]_net_1\);
    
    \Coef_rdaddr_RNO[1]\ : CFG4
      generic map(INIT => x"A2AA")

      port map(A => \un1_coef_rdaddr_1_axbxc1\, B => N_20_1, C
         => N_14, D => \Coef_rdaddr_2_i_a2_0[1]_net_1\, Y => 
        N_4_i_0);
    
    \Mac_out[15]\ : SLE
      port map(D => \Yn_out[15]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[15]\);
    
    un1_coef_rdaddr_1_ac0_5 : CFG4
      generic map(INIT => x"8000")

      port map(A => \Coef_rdaddr[3]_net_1\, B => 
        \Coef_rdaddr[1]_net_1\, C => \Coef_rdaddr[0]_net_1\, D
         => \Coef_rdaddr[2]_net_1\, Y => un1_coef_rdaddr_1_c4);
    
    Filter_En_ibuf : INBUF
      port map(PAD => Filter_En, Y => Filter_En_c);
    
    rdy_sig : SLE
      port map(D => rdy_sig_4_iv_i_0, CLK => clk_c, EN => 
        N_156_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \rdy_sig\);
    
    \Mac_out_obuf[34]\ : OUTBUF
      port map(D => \Mac_out_c[34]\, PAD => Mac_out(34));
    
    \mac_state_ns_a2_0_a2_0_a2[0]\ : CFG4
      generic map(INIT => x"0100")

      port map(A => \mac_state[3]_net_1\, B => Filter_En_c, C => 
        \mac_state[1]_net_1\, D => 
        \mac_state_ns_a2_0_a2_0_a2_1[0]_net_1\, Y => 
        \mac_state_ns[0]\);
    
    \Mac_out[38]\ : SLE
      port map(D => \Yn_out[38]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[38]\);
    
    \mac_state[0]\ : SLE
      port map(D => N_153, CLK => clk_c, EN => VCC_net_1, ALn => 
        reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \mac_state[0]_net_1\);
    
    \Mac_out_obuf[28]\ : OUTBUF
      port map(D => \Mac_out_c[28]\, PAD => Mac_out(28));
    
    \InpB_rdaddr1[0]\ : SLE
      port map(D => \inpB_rdaddr[0]_net_1\, CLK => clk_c, EN => 
        N_163_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \InpB_rdaddr1[0]_net_1\);
    
    \inp_rddata_RNO[16]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[16]\, B => 
        un1_inpA_rddata2_1_m_3_9_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[16]\, Y => N_189);
    
    \mac_state[1]\ : SLE
      port map(D => \mac_state_ns[4]\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \mac_state[1]_net_1\);
    
    \inp_wrdata_dly0[16]\ : SLE
      port map(D => \inp_wrdata[16]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[16]_net_1\);
    
    Data_Valid_ibuf : INBUF
      port map(PAD => Data_Valid, Y => Data_Valid_c);
    
    \A_rdaddr_RNO[6]\ : CFG4
      generic map(INIT => x"060C")

      port map(A => \un1_a_rdaddr_ac0_9_0\, B => 
        \A_rdaddr[6]_net_1\, C => N_146, D => un1_a_rdaddr_c3, Y
         => N_36_i_0);
    
    \Xn_in_ibuf[14]\ : INBUF
      port map(PAD => Xn_in(14), Y => \Xn_in_c[14]\);
    
    \Mac_out[14]\ : SLE
      port map(D => \Yn_out[14]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[14]\);
    
    \Coef_rdaddr[4]\ : SLE
      port map(D => N_6_i_0, CLK => clk_c, EN => 
        \mac_state[1]_net_1\, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \Coef_rdaddr[4]_net_1\);
    
    \rdy_cnt[0]\ : SLE
      port map(D => \rdy_cnt_3[0]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \rdy_cnt[0]_net_1\);
    
    \inp_wrdata_dly0[2]\ : SLE
      port map(D => \inp_wrdata[2]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly0[2]_net_1\);
    
    \inp_rddata_RNO[8]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[8]\, B => 
        un1_inpA_rddata2_1_m_3_1_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[8]\, Y => N_213);
    
    \Coef_rdaddr1[5]\ : SLE
      port map(D => \Coef_rdaddr[5]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rdaddr1[5]_net_1\);
    
    \B_rdaddr_lm_0[7]\ : CFG4
      generic map(INIT => x"1030")

      port map(A => un1_b_rdaddr10_i_0_627_0_0_a2_5, B => 
        \Transferdone\, C => \B_rdaddr_s[7]_net_1\, D => 
        un1_b_rdaddr10_i_0_627_0_0_a2_4, Y => \B_rdaddr_lm[7]\);
    
    un1_inp_wraddr_1_axbxc7 : CFG4
      generic map(INIT => x"6AAA")

      port map(A => \inp_wraddr[7]_net_1\, B => 
        \inp_wraddr[6]_net_1\, C => 
        \un1_inp_wraddr_1_ac0_9_m1_0_a2_1\, D => 
        un1_inp_wraddr_1_ac0_3tt_N_7_mux, Y => 
        \un1_inp_wraddr_1_axbxc7\);
    
    \Mac_out_obuf[24]\ : OUTBUF
      port map(D => \Mac_out_c[24]\, PAD => Mac_out(24));
    
    \inp_rddata[12]\ : SLE
      port map(D => N_201, CLK => clk_c, EN => 
        un1_sel_inpa0_4_i_0, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \inp_rddata[12]_net_1\);
    
    \A_rdaddr[7]\ : SLE
      port map(D => \un1_a_rdaddr_axbxc7\, CLK => clk_c, EN => 
        \FiltOp_done\, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \A_rdaddr[7]_net_1\);
    
    \Coef_rdaddr[0]\ : SLE
      port map(D => \Coef_rdaddr_i_0[0]\, CLK => clk_c, EN => 
        \mac_state[1]_net_1\, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \Coef_rdaddr[0]_net_1\);
    
    \InpA_rdaddr1[0]\ : SLE
      port map(D => \inpA_rdaddr[0]_net_1\, CLK => clk_c, EN => 
        N_161_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \InpA_rdaddr1[0]_net_1\);
    
    \Coef_rdaddr_2_i_a2_1[1]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \Coef_rdaddr[4]_net_1\, B => 
        \Coef_rdaddr[5]_net_1\, Y => N_20_1);
    
    \inpA_rdaddr[2]\ : SLE
      port map(D => \inpA_rdaddr_lm[2]\, CLK => clk_c, EN => 
        N_107_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inpA_rdaddr[2]_net_1\);
    
    InpB_rden0_1_iv_0_0_0 : CFG4
      generic map(INIT => x"EAAA")

      port map(A => N_131, B => N_66, C => \inpB_rdaddr[5]_net_1\, 
        D => \InpB_rden0\, Y => InpB_rden0_1);
    
    \InpB_rdaddr1[2]\ : SLE
      port map(D => \inpB_rdaddr[2]_net_1\, CLK => clk_c, EN => 
        N_163_i_0, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \InpB_rdaddr1[2]_net_1\);
    
    \inp_rddata_RNO_0[16]\ : CFG4
      generic map(INIT => x"4657")

      port map(A => \Sel_InpB0\, B => \Sel_InpA0\, C => 
        \un1_inpA_rddata2_12[16]\, D => \un1_inpA_rddata2_10[16]\, 
        Y => un1_inpA_rddata2_1_m_3_9_i_m2_i_m2_1_1);
    
    \Coef_rdaddr[1]\ : SLE
      port map(D => N_4_i_0, CLK => clk_c, EN => 
        \mac_state[1]_net_1\, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \Coef_rdaddr[1]_net_1\);
    
    \A_rdaddr[0]\ : SLE
      port map(D => \A_rdaddr_i_0[0]\, CLK => clk_c, EN => 
        \FiltOp_done\, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \A_rdaddr[0]_net_1\);
    
    \inp_wraddr2_RNO[0]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \inp_wraddr[6]_net_1\, B => 
        \inp_wraddr[0]_net_1\, Y => N_493_i_0);
    
    \inp_rddata_RNO[13]\ : CFG4
      generic map(INIT => x"B383")

      port map(A => \un1_inpA_rddata2_11[13]\, B => 
        un1_inpA_rddata2_1_m_3_6_i_m2_i_m2_1_1, C => \Sel_InpA0\, 
        D => \un1_inpA_rddata2_13[13]\, Y => N_198);
    
    \inpA_rdaddr_lm_0[4]\ : CFG3
      generic map(INIT => x"E2")

      port map(A => \inpA_rdaddr_s[4]\, B => N_5, C => N_157, Y
         => \inpA_rdaddr_lm[4]\);
    

end DEF_ARCH; 
