@W: CD638 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Parallel FIR Filters\Systolic FIR Filter\Systolic_FIR_Filter\hdl\Systolic_FIR_Filter.vhd":96:7:96:10|Signal coef is undriven 
@W: CD275 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Parallel FIR Filters\Systolic FIR Filter\Systolic_FIR_Filter\component\work\multadd\multadd_0\multadd_multadd_0_HARD_MULT_ADDSUB.vhd":31:12:31:15|Component declarations with different initial values are not supported.  Port cdin of component macc may have been given a different initial value in two different component declarations

