-- Version: v11.1 SP2 11.1.2.19

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Mult18x18_Mult18x18_0_HARD_MULT is

    port( SLL_OP_c    : out   std_logic_vector(17 downto 0);
          SRL_OP_c    : out   std_logic_vector(17 downto 0);
          SHIFT_INP_c : in    std_logic_vector(16 downto 0);
          RSTN_c      : in    std_logic;
          CLK_c       : in    std_logic
        );

end Mult18x18_Mult18x18_0_HARD_MULT;

architecture DEF_ARCH of Mult18x18_Mult18x18_0_HARD_MULT is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;
    signal nc47, nc34, nc9, nc13, nc23, nc33, nc16, nc26, nc45, 
        nc27, nc17, nc36, nc48, nc37, nc5, nc52, nc51, nc4, nc42, 
        nc41, nc25, nc15, nc35, nc49, nc28, nc18, nc38, nc1, nc2, 
        nc50, nc22, nc12, nc21, nc11, nc3, nc32, nc40, nc31, nc44, 
        nc7, nc6, nc19, nc29, nc39, nc8, nc43, nc20, nc10, nc24, 
        nc14, nc46, nc30 : std_logic;

begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    U0 : MACC
      port map(CLK(1) => CLK_c, CLK(0) => CLK_c, A(17) => 
        GND_net_1, A(16) => GND_net_1, A(15) => GND_net_1, A(14)
         => GND_net_1, A(13) => GND_net_1, A(12) => GND_net_1, 
        A(11) => GND_net_1, A(10) => GND_net_1, A(9) => GND_net_1, 
        A(8) => GND_net_1, A(7) => GND_net_1, A(6) => GND_net_1, 
        A(5) => VCC_net_1, A(4) => GND_net_1, A(3) => GND_net_1, 
        A(2) => GND_net_1, A(1) => GND_net_1, A(0) => GND_net_1, 
        A_EN(1) => VCC_net_1, A_EN(0) => VCC_net_1, A_ARST_N(1)
         => VCC_net_1, A_ARST_N(0) => VCC_net_1, A_SRST_N(1) => 
        VCC_net_1, A_SRST_N(0) => VCC_net_1, B(17) => GND_net_1, 
        B(16) => SHIFT_INP_c(16), B(15) => SHIFT_INP_c(15), B(14)
         => SHIFT_INP_c(14), B(13) => SHIFT_INP_c(13), B(12) => 
        SHIFT_INP_c(12), B(11) => SHIFT_INP_c(11), B(10) => 
        SHIFT_INP_c(10), B(9) => SHIFT_INP_c(9), B(8) => 
        SHIFT_INP_c(8), B(7) => SHIFT_INP_c(7), B(6) => 
        SHIFT_INP_c(6), B(5) => SHIFT_INP_c(5), B(4) => 
        SHIFT_INP_c(4), B(3) => SHIFT_INP_c(3), B(2) => 
        SHIFT_INP_c(2), B(1) => SHIFT_INP_c(1), B(0) => 
        SHIFT_INP_c(0), B_EN(1) => VCC_net_1, B_EN(0) => 
        VCC_net_1, B_ARST_N(1) => RSTN_c, B_ARST_N(0) => RSTN_c, 
        B_SRST_N(1) => VCC_net_1, B_SRST_N(0) => VCC_net_1, C(43)
         => GND_net_1, C(42) => GND_net_1, C(41) => GND_net_1, 
        C(40) => GND_net_1, C(39) => GND_net_1, C(38) => 
        GND_net_1, C(37) => GND_net_1, C(36) => GND_net_1, C(35)
         => GND_net_1, C(34) => GND_net_1, C(33) => GND_net_1, 
        C(32) => GND_net_1, C(31) => GND_net_1, C(30) => 
        GND_net_1, C(29) => GND_net_1, C(28) => GND_net_1, C(27)
         => GND_net_1, C(26) => GND_net_1, C(25) => GND_net_1, 
        C(24) => GND_net_1, C(23) => GND_net_1, C(22) => 
        GND_net_1, C(21) => GND_net_1, C(20) => GND_net_1, C(19)
         => GND_net_1, C(18) => GND_net_1, C(17) => GND_net_1, 
        C(16) => GND_net_1, C(15) => GND_net_1, C(14) => 
        GND_net_1, C(13) => GND_net_1, C(12) => GND_net_1, C(11)
         => GND_net_1, C(10) => GND_net_1, C(9) => GND_net_1, 
        C(8) => GND_net_1, C(7) => GND_net_1, C(6) => GND_net_1, 
        C(5) => GND_net_1, C(4) => GND_net_1, C(3) => GND_net_1, 
        C(2) => GND_net_1, C(1) => GND_net_1, C(0) => GND_net_1, 
        C_EN(1) => VCC_net_1, C_EN(0) => VCC_net_1, C_ARST_N(1)
         => VCC_net_1, C_ARST_N(0) => VCC_net_1, C_SRST_N(1) => 
        VCC_net_1, C_SRST_N(0) => VCC_net_1, P_EN(1) => VCC_net_1, 
        P_EN(0) => VCC_net_1, P_ARST_N(1) => RSTN_c, P_ARST_N(0)
         => RSTN_c, P_SRST_N(1) => VCC_net_1, P_SRST_N(0) => 
        VCC_net_1, FDBKSEL => GND_net_1, FDBKSEL_EN => VCC_net_1, 
        FDBKSEL_AL_N => VCC_net_1, FDBKSEL_SL_N => VCC_net_1, 
        CDSEL => GND_net_1, CDSEL_EN => VCC_net_1, CDSEL_AL_N => 
        VCC_net_1, CDSEL_SL_N => VCC_net_1, ARSHFT17 => GND_net_1, 
        ARSHFT17_EN => VCC_net_1, ARSHFT17_AL_N => VCC_net_1, 
        ARSHFT17_SL_N => VCC_net_1, SUB => GND_net_1, SUB_EN => 
        VCC_net_1, SUB_AL_N => VCC_net_1, SUB_SL_N => VCC_net_1, 
        CARRYIN => GND_net_1, SIMD => GND_net_1, DOTP => 
        GND_net_1, OVFL_CARRYOUT_SEL => GND_net_1, A_BYPASS(1)
         => VCC_net_1, A_BYPASS(0) => VCC_net_1, B_BYPASS(1) => 
        GND_net_1, B_BYPASS(0) => GND_net_1, C_BYPASS(1) => 
        VCC_net_1, C_BYPASS(0) => VCC_net_1, P_BYPASS(1) => 
        GND_net_1, P_BYPASS(0) => GND_net_1, FDBKSEL_BYPASS => 
        VCC_net_1, FDBKSEL_AD => GND_net_1, FDBKSEL_SD_N => 
        VCC_net_1, CDSEL_BYPASS => VCC_net_1, CDSEL_AD => 
        GND_net_1, CDSEL_SD_N => VCC_net_1, ARSHFT17_BYPASS => 
        VCC_net_1, ARSHFT17_AD => GND_net_1, ARSHFT17_SD_N => 
        VCC_net_1, SUB_BYPASS => VCC_net_1, SUB_AD => GND_net_1, 
        SUB_SD_N => VCC_net_1, CDIN(43) => GND_net_1, CDIN(42)
         => GND_net_1, CDIN(41) => GND_net_1, CDIN(40) => 
        GND_net_1, CDIN(39) => GND_net_1, CDIN(38) => GND_net_1, 
        CDIN(37) => GND_net_1, CDIN(36) => GND_net_1, CDIN(35)
         => GND_net_1, CDIN(34) => GND_net_1, CDIN(33) => 
        GND_net_1, CDIN(32) => GND_net_1, CDIN(31) => GND_net_1, 
        CDIN(30) => GND_net_1, CDIN(29) => GND_net_1, CDIN(28)
         => GND_net_1, CDIN(27) => GND_net_1, CDIN(26) => 
        GND_net_1, CDIN(25) => GND_net_1, CDIN(24) => GND_net_1, 
        CDIN(23) => GND_net_1, CDIN(22) => GND_net_1, CDIN(21)
         => GND_net_1, CDIN(20) => GND_net_1, CDIN(19) => 
        GND_net_1, CDIN(18) => GND_net_1, CDIN(17) => GND_net_1, 
        CDIN(16) => GND_net_1, CDIN(15) => GND_net_1, CDIN(14)
         => GND_net_1, CDIN(13) => GND_net_1, CDIN(12) => 
        GND_net_1, CDIN(11) => GND_net_1, CDIN(10) => GND_net_1, 
        CDIN(9) => GND_net_1, CDIN(8) => GND_net_1, CDIN(7) => 
        GND_net_1, CDIN(6) => GND_net_1, CDIN(5) => GND_net_1, 
        CDIN(4) => GND_net_1, CDIN(3) => GND_net_1, CDIN(2) => 
        GND_net_1, CDIN(1) => GND_net_1, CDIN(0) => GND_net_1, 
        CDOUT(43) => nc47, CDOUT(42) => nc34, CDOUT(41) => nc9, 
        CDOUT(40) => nc13, CDOUT(39) => nc23, CDOUT(38) => nc33, 
        CDOUT(37) => nc16, CDOUT(36) => nc26, CDOUT(35) => nc45, 
        CDOUT(34) => nc27, CDOUT(33) => nc17, CDOUT(32) => nc36, 
        CDOUT(31) => nc48, CDOUT(30) => nc37, CDOUT(29) => nc5, 
        CDOUT(28) => nc52, CDOUT(27) => nc51, CDOUT(26) => nc4, 
        CDOUT(25) => nc42, CDOUT(24) => nc41, CDOUT(23) => nc25, 
        CDOUT(22) => nc15, CDOUT(21) => nc35, CDOUT(20) => nc49, 
        CDOUT(19) => nc28, CDOUT(18) => nc18, CDOUT(17) => nc38, 
        CDOUT(16) => nc1, CDOUT(15) => nc2, CDOUT(14) => nc50, 
        CDOUT(13) => nc22, CDOUT(12) => nc12, CDOUT(11) => nc21, 
        CDOUT(10) => nc11, CDOUT(9) => nc3, CDOUT(8) => nc32, 
        CDOUT(7) => nc40, CDOUT(6) => nc31, CDOUT(5) => nc44, 
        CDOUT(4) => nc7, CDOUT(3) => nc6, CDOUT(2) => nc19, 
        CDOUT(1) => nc29, CDOUT(0) => nc39, P(43) => nc8, P(42)
         => nc43, P(41) => nc20, P(40) => nc10, P(39) => nc24, 
        P(38) => nc14, P(37) => nc46, P(36) => nc30, P(35) => 
        SRL_OP_c(17), P(34) => SRL_OP_c(16), P(33) => 
        SRL_OP_c(15), P(32) => SRL_OP_c(14), P(31) => 
        SRL_OP_c(13), P(30) => SRL_OP_c(12), P(29) => 
        SRL_OP_c(11), P(28) => SRL_OP_c(10), P(27) => SRL_OP_c(9), 
        P(26) => SRL_OP_c(8), P(25) => SRL_OP_c(7), P(24) => 
        SRL_OP_c(6), P(23) => SRL_OP_c(5), P(22) => SRL_OP_c(4), 
        P(21) => SRL_OP_c(3), P(20) => SRL_OP_c(2), P(19) => 
        SRL_OP_c(1), P(18) => SRL_OP_c(0), P(17) => SLL_OP_c(17), 
        P(16) => SLL_OP_c(16), P(15) => SLL_OP_c(15), P(14) => 
        SLL_OP_c(14), P(13) => SLL_OP_c(13), P(12) => 
        SLL_OP_c(12), P(11) => SLL_OP_c(11), P(10) => 
        SLL_OP_c(10), P(9) => SLL_OP_c(9), P(8) => SLL_OP_c(8), 
        P(7) => SLL_OP_c(7), P(6) => SLL_OP_c(6), P(5) => 
        SLL_OP_c(5), P(4) => SLL_OP_c(4), P(3) => SLL_OP_c(3), 
        P(2) => SLL_OP_c(2), P(1) => SLL_OP_c(1), P(0) => 
        SLL_OP_c(0), OVFL_CARRYOUT => OPEN);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Mult18x18 is

    port( SLL_OP_c    : out   std_logic_vector(17 downto 0);
          SRL_OP_c    : out   std_logic_vector(17 downto 0);
          SHIFT_INP_c : in    std_logic_vector(16 downto 0);
          RSTN_c      : in    std_logic;
          CLK_c       : in    std_logic
        );

end Mult18x18;

architecture DEF_ARCH of Mult18x18 is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component Mult18x18_Mult18x18_0_HARD_MULT
    port( SLL_OP_c    : out   std_logic_vector(17 downto 0);
          SRL_OP_c    : out   std_logic_vector(17 downto 0);
          SHIFT_INP_c : in    std_logic_vector(16 downto 0) := (others => 'U');
          RSTN_c      : in    std_logic := 'U';
          CLK_c       : in    std_logic := 'U'
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

    for all : Mult18x18_Mult18x18_0_HARD_MULT
	Use entity work.Mult18x18_Mult18x18_0_HARD_MULT(DEF_ARCH);
begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    Mult18x18_0 : Mult18x18_Mult18x18_0_HARD_MULT
      port map(SLL_OP_c(17) => SLL_OP_c(17), SLL_OP_c(16) => 
        SLL_OP_c(16), SLL_OP_c(15) => SLL_OP_c(15), SLL_OP_c(14)
         => SLL_OP_c(14), SLL_OP_c(13) => SLL_OP_c(13), 
        SLL_OP_c(12) => SLL_OP_c(12), SLL_OP_c(11) => 
        SLL_OP_c(11), SLL_OP_c(10) => SLL_OP_c(10), SLL_OP_c(9)
         => SLL_OP_c(9), SLL_OP_c(8) => SLL_OP_c(8), SLL_OP_c(7)
         => SLL_OP_c(7), SLL_OP_c(6) => SLL_OP_c(6), SLL_OP_c(5)
         => SLL_OP_c(5), SLL_OP_c(4) => SLL_OP_c(4), SLL_OP_c(3)
         => SLL_OP_c(3), SLL_OP_c(2) => SLL_OP_c(2), SLL_OP_c(1)
         => SLL_OP_c(1), SLL_OP_c(0) => SLL_OP_c(0), SRL_OP_c(17)
         => SRL_OP_c(17), SRL_OP_c(16) => SRL_OP_c(16), 
        SRL_OP_c(15) => SRL_OP_c(15), SRL_OP_c(14) => 
        SRL_OP_c(14), SRL_OP_c(13) => SRL_OP_c(13), SRL_OP_c(12)
         => SRL_OP_c(12), SRL_OP_c(11) => SRL_OP_c(11), 
        SRL_OP_c(10) => SRL_OP_c(10), SRL_OP_c(9) => SRL_OP_c(9), 
        SRL_OP_c(8) => SRL_OP_c(8), SRL_OP_c(7) => SRL_OP_c(7), 
        SRL_OP_c(6) => SRL_OP_c(6), SRL_OP_c(5) => SRL_OP_c(5), 
        SRL_OP_c(4) => SRL_OP_c(4), SRL_OP_c(3) => SRL_OP_c(3), 
        SRL_OP_c(2) => SRL_OP_c(2), SRL_OP_c(1) => SRL_OP_c(1), 
        SRL_OP_c(0) => SRL_OP_c(0), SHIFT_INP_c(16) => 
        SHIFT_INP_c(16), SHIFT_INP_c(15) => SHIFT_INP_c(15), 
        SHIFT_INP_c(14) => SHIFT_INP_c(14), SHIFT_INP_c(13) => 
        SHIFT_INP_c(13), SHIFT_INP_c(12) => SHIFT_INP_c(12), 
        SHIFT_INP_c(11) => SHIFT_INP_c(11), SHIFT_INP_c(10) => 
        SHIFT_INP_c(10), SHIFT_INP_c(9) => SHIFT_INP_c(9), 
        SHIFT_INP_c(8) => SHIFT_INP_c(8), SHIFT_INP_c(7) => 
        SHIFT_INP_c(7), SHIFT_INP_c(6) => SHIFT_INP_c(6), 
        SHIFT_INP_c(5) => SHIFT_INP_c(5), SHIFT_INP_c(4) => 
        SHIFT_INP_c(4), SHIFT_INP_c(3) => SHIFT_INP_c(3), 
        SHIFT_INP_c(2) => SHIFT_INP_c(2), SHIFT_INP_c(1) => 
        SHIFT_INP_c(1), SHIFT_INP_c(0) => SHIFT_INP_c(0), RSTN_c
         => RSTN_c, CLK_c => CLK_c);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity SLL_SRL is

    port( SHIFT_INP : in    std_logic_vector(17 downto 0);
          SLL_OP    : out   std_logic_vector(17 downto 0);
          SRL_OP    : out   std_logic_vector(17 downto 0);
          CLK       : in    std_logic;
          RSTN      : in    std_logic
        );

end SLL_SRL;

architecture DEF_ARCH of SLL_SRL is 

  component Mult18x18
    port( SLL_OP_c    : out   std_logic_vector(17 downto 0);
          SRL_OP_c    : out   std_logic_vector(17 downto 0);
          SHIFT_INP_c : in    std_logic_vector(16 downto 0) := (others => 'U');
          RSTN_c      : in    std_logic := 'U';
          CLK_c       : in    std_logic := 'U'
        );
  end component;

  component OUTBUF
    generic (IOSTD:string := "");

    port( D   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component INBUF
    generic (IOSTD:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal VCC_net_1, GND_net_1, CLK_c, RSTN_c, \SHIFT_INP_c[0]\, 
        \SHIFT_INP_c[1]\, \SHIFT_INP_c[2]\, \SHIFT_INP_c[3]\, 
        \SHIFT_INP_c[4]\, \SHIFT_INP_c[5]\, \SHIFT_INP_c[6]\, 
        \SHIFT_INP_c[7]\, \SHIFT_INP_c[8]\, \SHIFT_INP_c[9]\, 
        \SHIFT_INP_c[10]\, \SHIFT_INP_c[11]\, \SHIFT_INP_c[12]\, 
        \SHIFT_INP_c[13]\, \SHIFT_INP_c[14]\, \SHIFT_INP_c[15]\, 
        \SHIFT_INP_c[16]\, \SLL_OP_c[0]\, \SLL_OP_c[1]\, 
        \SLL_OP_c[2]\, \SLL_OP_c[3]\, \SLL_OP_c[4]\, 
        \SLL_OP_c[5]\, \SLL_OP_c[6]\, \SLL_OP_c[7]\, 
        \SLL_OP_c[8]\, \SLL_OP_c[9]\, \SLL_OP_c[10]\, 
        \SLL_OP_c[11]\, \SLL_OP_c[12]\, \SLL_OP_c[13]\, 
        \SLL_OP_c[14]\, \SLL_OP_c[15]\, \SLL_OP_c[16]\, 
        \SLL_OP_c[17]\, \SRL_OP_c[0]\, \SRL_OP_c[1]\, 
        \SRL_OP_c[2]\, \SRL_OP_c[3]\, \SRL_OP_c[4]\, 
        \SRL_OP_c[5]\, \SRL_OP_c[6]\, \SRL_OP_c[7]\, 
        \SRL_OP_c[8]\, \SRL_OP_c[9]\, \SRL_OP_c[10]\, 
        \SRL_OP_c[11]\, \SRL_OP_c[12]\, \SRL_OP_c[13]\, 
        \SRL_OP_c[14]\, \SRL_OP_c[15]\, \SRL_OP_c[16]\, 
        \SRL_OP_c[17]\ : std_logic;

    for all : Mult18x18
	Use entity work.Mult18x18(DEF_ARCH);
begin 


    U0 : Mult18x18
      port map(SLL_OP_c(17) => \SLL_OP_c[17]\, SLL_OP_c(16) => 
        \SLL_OP_c[16]\, SLL_OP_c(15) => \SLL_OP_c[15]\, 
        SLL_OP_c(14) => \SLL_OP_c[14]\, SLL_OP_c(13) => 
        \SLL_OP_c[13]\, SLL_OP_c(12) => \SLL_OP_c[12]\, 
        SLL_OP_c(11) => \SLL_OP_c[11]\, SLL_OP_c(10) => 
        \SLL_OP_c[10]\, SLL_OP_c(9) => \SLL_OP_c[9]\, SLL_OP_c(8)
         => \SLL_OP_c[8]\, SLL_OP_c(7) => \SLL_OP_c[7]\, 
        SLL_OP_c(6) => \SLL_OP_c[6]\, SLL_OP_c(5) => 
        \SLL_OP_c[5]\, SLL_OP_c(4) => \SLL_OP_c[4]\, SLL_OP_c(3)
         => \SLL_OP_c[3]\, SLL_OP_c(2) => \SLL_OP_c[2]\, 
        SLL_OP_c(1) => \SLL_OP_c[1]\, SLL_OP_c(0) => 
        \SLL_OP_c[0]\, SRL_OP_c(17) => \SRL_OP_c[17]\, 
        SRL_OP_c(16) => \SRL_OP_c[16]\, SRL_OP_c(15) => 
        \SRL_OP_c[15]\, SRL_OP_c(14) => \SRL_OP_c[14]\, 
        SRL_OP_c(13) => \SRL_OP_c[13]\, SRL_OP_c(12) => 
        \SRL_OP_c[12]\, SRL_OP_c(11) => \SRL_OP_c[11]\, 
        SRL_OP_c(10) => \SRL_OP_c[10]\, SRL_OP_c(9) => 
        \SRL_OP_c[9]\, SRL_OP_c(8) => \SRL_OP_c[8]\, SRL_OP_c(7)
         => \SRL_OP_c[7]\, SRL_OP_c(6) => \SRL_OP_c[6]\, 
        SRL_OP_c(5) => \SRL_OP_c[5]\, SRL_OP_c(4) => 
        \SRL_OP_c[4]\, SRL_OP_c(3) => \SRL_OP_c[3]\, SRL_OP_c(2)
         => \SRL_OP_c[2]\, SRL_OP_c(1) => \SRL_OP_c[1]\, 
        SRL_OP_c(0) => \SRL_OP_c[0]\, SHIFT_INP_c(16) => 
        \SHIFT_INP_c[16]\, SHIFT_INP_c(15) => \SHIFT_INP_c[15]\, 
        SHIFT_INP_c(14) => \SHIFT_INP_c[14]\, SHIFT_INP_c(13) => 
        \SHIFT_INP_c[13]\, SHIFT_INP_c(12) => \SHIFT_INP_c[12]\, 
        SHIFT_INP_c(11) => \SHIFT_INP_c[11]\, SHIFT_INP_c(10) => 
        \SHIFT_INP_c[10]\, SHIFT_INP_c(9) => \SHIFT_INP_c[9]\, 
        SHIFT_INP_c(8) => \SHIFT_INP_c[8]\, SHIFT_INP_c(7) => 
        \SHIFT_INP_c[7]\, SHIFT_INP_c(6) => \SHIFT_INP_c[6]\, 
        SHIFT_INP_c(5) => \SHIFT_INP_c[5]\, SHIFT_INP_c(4) => 
        \SHIFT_INP_c[4]\, SHIFT_INP_c(3) => \SHIFT_INP_c[3]\, 
        SHIFT_INP_c(2) => \SHIFT_INP_c[2]\, SHIFT_INP_c(1) => 
        \SHIFT_INP_c[1]\, SHIFT_INP_c(0) => \SHIFT_INP_c[0]\, 
        RSTN_c => RSTN_c, CLK_c => CLK_c);
    
    \SLL_OP_obuf[3]\ : OUTBUF
      port map(D => \SLL_OP_c[3]\, PAD => SLL_OP(3));
    
    \SLL_OP_obuf[1]\ : OUTBUF
      port map(D => \SLL_OP_c[1]\, PAD => SLL_OP(1));
    
    \SLL_OP_obuf[14]\ : OUTBUF
      port map(D => \SLL_OP_c[14]\, PAD => SLL_OP(14));
    
    \SRL_OP_obuf[12]\ : OUTBUF
      port map(D => \SRL_OP_c[12]\, PAD => SRL_OP(12));
    
    \SHIFT_INP_ibuf[9]\ : INBUF
      port map(PAD => SHIFT_INP(9), Y => \SHIFT_INP_c[9]\);
    
    \SHIFT_INP_ibuf[0]\ : INBUF
      port map(PAD => SHIFT_INP(0), Y => \SHIFT_INP_c[0]\);
    
    \SHIFT_INP_ibuf[4]\ : INBUF
      port map(PAD => SHIFT_INP(4), Y => \SHIFT_INP_c[4]\);
    
    \SLL_OP_obuf[0]\ : OUTBUF
      port map(D => \SLL_OP_c[0]\, PAD => SLL_OP(0));
    
    \SLL_OP_obuf[6]\ : OUTBUF
      port map(D => \SLL_OP_c[6]\, PAD => SLL_OP(6));
    
    \SLL_OP_obuf[16]\ : OUTBUF
      port map(D => \SLL_OP_c[16]\, PAD => SLL_OP(16));
    
    \SLL_OP_obuf[13]\ : OUTBUF
      port map(D => \SLL_OP_c[13]\, PAD => SLL_OP(13));
    
    \SHIFT_INP_ibuf[7]\ : INBUF
      port map(PAD => SHIFT_INP(7), Y => \SHIFT_INP_c[7]\);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \SLL_OP_obuf[10]\ : OUTBUF
      port map(D => \SLL_OP_c[10]\, PAD => SLL_OP(10));
    
    RSTN_ibuf : INBUF
      port map(PAD => RSTN, Y => RSTN_c);
    
    \SLL_OP_obuf[9]\ : OUTBUF
      port map(D => \SLL_OP_c[9]\, PAD => SLL_OP(9));
    
    \SHIFT_INP_ibuf[16]\ : INBUF
      port map(PAD => SHIFT_INP(16), Y => \SHIFT_INP_c[16]\);
    
    \SLL_OP_obuf[15]\ : OUTBUF
      port map(D => \SLL_OP_c[15]\, PAD => SLL_OP(15));
    
    \SHIFT_INP_ibuf[6]\ : INBUF
      port map(PAD => SHIFT_INP(6), Y => \SHIFT_INP_c[6]\);
    
    \SRL_OP_obuf[7]\ : OUTBUF
      port map(D => \SRL_OP_c[7]\, PAD => SRL_OP(7));
    
    \SRL_OP_obuf[4]\ : OUTBUF
      port map(D => \SRL_OP_c[4]\, PAD => SRL_OP(4));
    
    \SRL_OP_obuf[14]\ : OUTBUF
      port map(D => \SRL_OP_c[14]\, PAD => SRL_OP(14));
    
    \SHIFT_INP_ibuf[2]\ : INBUF
      port map(PAD => SHIFT_INP(2), Y => \SHIFT_INP_c[2]\);
    
    \SRL_OP_obuf[16]\ : OUTBUF
      port map(D => \SRL_OP_c[16]\, PAD => SRL_OP(16));
    
    \SLL_OP_obuf[12]\ : OUTBUF
      port map(D => \SLL_OP_c[12]\, PAD => SLL_OP(12));
    
    \SLL_OP_obuf[5]\ : OUTBUF
      port map(D => \SLL_OP_c[5]\, PAD => SLL_OP(5));
    
    \SHIFT_INP_ibuf[13]\ : INBUF
      port map(PAD => SHIFT_INP(13), Y => \SHIFT_INP_c[13]\);
    
    \SLL_OP_obuf[8]\ : OUTBUF
      port map(D => \SLL_OP_c[8]\, PAD => SLL_OP(8));
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    \SRL_OP_obuf[15]\ : OUTBUF
      port map(D => \SRL_OP_c[15]\, PAD => SRL_OP(15));
    
    \SRL_OP_obuf[3]\ : OUTBUF
      port map(D => \SRL_OP_c[3]\, PAD => SRL_OP(3));
    
    \SRL_OP_obuf[1]\ : OUTBUF
      port map(D => \SRL_OP_c[1]\, PAD => SRL_OP(1));
    
    \SLL_OP_obuf[2]\ : OUTBUF
      port map(D => \SLL_OP_c[2]\, PAD => SLL_OP(2));
    
    \SHIFT_INP_ibuf[3]\ : INBUF
      port map(PAD => SHIFT_INP(3), Y => \SHIFT_INP_c[3]\);
    
    \SHIFT_INP_ibuf[5]\ : INBUF
      port map(PAD => SHIFT_INP(5), Y => \SHIFT_INP_c[5]\);
    
    \SRL_OP_obuf[10]\ : OUTBUF
      port map(D => \SRL_OP_c[10]\, PAD => SRL_OP(10));
    
    \SLL_OP_obuf[17]\ : OUTBUF
      port map(D => \SLL_OP_c[17]\, PAD => SLL_OP(17));
    
    \SRL_OP_obuf[0]\ : OUTBUF
      port map(D => \SRL_OP_c[0]\, PAD => SRL_OP(0));
    
    \SRL_OP_obuf[6]\ : OUTBUF
      port map(D => \SRL_OP_c[6]\, PAD => SRL_OP(6));
    
    \SHIFT_INP_ibuf[11]\ : INBUF
      port map(PAD => SHIFT_INP(11), Y => \SHIFT_INP_c[11]\);
    
    \SHIFT_INP_ibuf[10]\ : INBUF
      port map(PAD => SHIFT_INP(10), Y => \SHIFT_INP_c[10]\);
    
    \SHIFT_INP_ibuf[12]\ : INBUF
      port map(PAD => SHIFT_INP(12), Y => \SHIFT_INP_c[12]\);
    
    \SRL_OP_obuf[9]\ : OUTBUF
      port map(D => \SRL_OP_c[9]\, PAD => SRL_OP(9));
    
    \SHIFT_INP_ibuf[14]\ : INBUF
      port map(PAD => SHIFT_INP(14), Y => \SHIFT_INP_c[14]\);
    
    \SRL_OP_obuf[11]\ : OUTBUF
      port map(D => \SRL_OP_c[11]\, PAD => SRL_OP(11));
    
    \SHIFT_INP_ibuf[1]\ : INBUF
      port map(PAD => SHIFT_INP(1), Y => \SHIFT_INP_c[1]\);
    
    \SRL_OP_obuf[17]\ : OUTBUF
      port map(D => \SRL_OP_c[17]\, PAD => SRL_OP(17));
    
    \SRL_OP_obuf[13]\ : OUTBUF
      port map(D => \SRL_OP_c[13]\, PAD => SRL_OP(13));
    
    \SHIFT_INP_ibuf[15]\ : INBUF
      port map(PAD => SHIFT_INP(15), Y => \SHIFT_INP_c[15]\);
    
    \SLL_OP_obuf[7]\ : OUTBUF
      port map(D => \SLL_OP_c[7]\, PAD => SLL_OP(7));
    
    \SLL_OP_obuf[4]\ : OUTBUF
      port map(D => \SLL_OP_c[4]\, PAD => SLL_OP(4));
    
    \SRL_OP_obuf[5]\ : OUTBUF
      port map(D => \SRL_OP_c[5]\, PAD => SRL_OP(5));
    
    \SLL_OP_obuf[11]\ : OUTBUF
      port map(D => \SLL_OP_c[11]\, PAD => SLL_OP(11));
    
    \SHIFT_INP_ibuf[8]\ : INBUF
      port map(PAD => SHIFT_INP(8), Y => \SHIFT_INP_c[8]\);
    
    CLK_ibuf : INBUF
      port map(PAD => CLK, Y => CLK_c);
    
    \SRL_OP_obuf[8]\ : OUTBUF
      port map(D => \SRL_OP_c[8]\, PAD => SRL_OP(8));
    
    \SRL_OP_obuf[2]\ : OUTBUF
      port map(D => \SRL_OP_c[2]\, PAD => SRL_OP(2));
    

end DEF_ARCH; 
