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    Synopsys Generic Technology Pre-mapping, Version mapact, Build 976R, Built May 23 2013 12:10:32
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version H-2013.03M-1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 57MB)

    DSPSF2
    Printing clock  summary report in "D:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Filters\Single MAC FIR Filters\MAC FIR 16-tap\MAC_FIR\synthesis\MAC_FIR_scck.rpt" file
    @N:MF249 :  | Running in 32-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 60MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 60MB)

    Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 60MB)

    Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 61MB)

    Clock Summary
    **************

    Start           Requested     Requested     Clock        Clock
    Clock           Frequency     Period        Type         Group
    ------------------------------------------------------------------------------
    MAC_FIR|clk     231.9 MHz     4.312         inferred     Autoconstr_clkgroup_0
    ==============================================================================

    @W:MT530 : mulacc_18x18_mulacc_18x18_0_hard_mult_acc.vhd(108) | Found inferred clock MAC_FIR|clk which controls 216 sequential elements including U0.mulacc_18x18_0.U0. This clock has no specified timing constraint which may adversely impact design performance.

    syn_allowed_resources : blockrams=69  set on top level netlist MAC_FIR
    Finished Pre Mapping Phase.@N: BN225 |Writing default property annotation file D:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Filters\Single MAC FIR Filters\MAC FIR 16-tap\MAC_FIR\synthesis\MAC_FIR.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 44MB peak: 79MB)

    Process took 0h:00m:02s realtime, 0h:00m:01s cputime
    # Wed Nov 06 13:26:20 2013

    ###########################################################]

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