@W: MT530 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\filters\single mac fir filters\mac fir 16-tap\mac_fir\component\work\mulacc_18x18\mulacc_18x18_0\mulacc_18x18_mulacc_18x18_0_hard_mult_acc.vhd":108:4:108:5|Found inferred clock MAC_FIR|clk which controls 216 sequential elements including U0.mulacc_18x18_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
