`

    #Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014
    #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1
    #OS: Windows 7 6.1
    #Hostname: W764-TADIGADAPA

    #Implementation: synthesis

    $ Start of Compile
    #Wed May 21 19:31:39 2014

    Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

    @N:CD720 : std.vhd(146) | Setting time resolution to ns
    @N: : Counter_44bit.vhd(24) | Top entity is set to Counter_44bit.
    VHDL syntax check successful!
    @N:CD231 : std1164.vhd(913) | Using onehot encoding for type mvl9plus ('U'="1000000000")
    @N:CD630 : Counter_44bit.vhd(24) | Synthesizing work.counter_44bit.cntr44bit_arch
    @N:CD630 : MultAcc.vhd(17) | Synthesizing work.multacc.rtl
    @N:CD630 : MultAcc_MultAcc_0_HARD_MULT_ACC.vhd(8) | Synthesizing work.multacc_multacc_0_hard_mult_acc.def_arch
    @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box
    Post processing for smartfusion2.vcc.syn_black_box
    @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box
    Post processing for smartfusion2.gnd.syn_black_box
    @N:CD630 : smartfusion2.vhd(695) | Synthesizing smartfusion2.macc.syn_black_box
    Post processing for smartfusion2.macc.syn_black_box
    Post processing for work.multacc_multacc_0_hard_mult_acc.def_arch
    Post processing for work.multacc.rtl
    Post processing for work.counter_44bit.cntr44bit_arch
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(1) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(2) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(3) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(4) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(5) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(6) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(7) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(8) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(9) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(10) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(11) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(12) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(13) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(14) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(15) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(16) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit A(17) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(1) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(2) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(3) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(4) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(5) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(6) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(7) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(8) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(9) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(10) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(11) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(12) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(13) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(14) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(15) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(16) to a constant 0
    @W:CL190 : Counter_44bit.vhd(116) | Optimizing register bit B(17) to a constant 0
    @W:CL279 : Counter_44bit.vhd(116) | Pruning register bits 17 to 1 of A(17 downto 0)
    @W:CL279 : Counter_44bit.vhd(116) | Pruning register bits 17 to 1 of B(17 downto 0)
    @END

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 19:31:39 2014

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Linked File: DSP
    Printing clock  summary report in "D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Counter_44bit\synthesis\Counter_44bit_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    @W:BN132 : counter_44bit.vhd(116) | Removing sequential instance B[0],  because it is equivalent to instance A[0]
    syn_allowed_resources : blockrams=69  set on top level netlist Counter_44bit

    Clock Summary
    **************

    Start                 Requested     Requested     Clock        Clock
    Clock                 Frequency     Period        Type         Group
    ------------------------------------------------------------------------------------
    Counter_44bit|CLK     621.5 MHz     1.609         inferred     Autoconstr_clkgroup_0
    System                1.0 MHz       1000.000      system       system_clkgroup
    ====================================================================================

    @W:MT530 : multacc_multacc_0_hard_mult_acc.vhd(105) | Found inferred clock Counter_44bit|CLK which controls 47 sequential elements including UUT.MultAcc_0.U0. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Counter_44bit\synthesis\Counter_44bit.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 133MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 19:31:41 2014

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    @N:FX271 : counter_44bit.vhd(84) | Instance "DFF0" with 45 loads replicated 3 times to improve timing
    @N:FX271 : counter_44bit.vhd(84) | Instance "DFF1" with 44 loads replicated 3 times to improve timing
    Timing driven replication report
    Added 6 Registers via timing driven replication
    Added 0 LUTs via timing driven replication

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    @N:FP130 :  | Promoting Net CLK_c on CLKINT  I_1
    @N:FP130 :  | Promoting Net RSTN_c on CLKINT  I_2

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    1 non-gated/non-generated clock tree(s) driving 55 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId0001        CLK                 port                   55         DFF1_fast
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Writing Analyst data base D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Counter_44bit\synthesis\Counter_44bit.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    I-2013.09M-SP1

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    @W:MT420 :  | Found inferred clock Counter_44bit|CLK with period 1.53ns. Please declare a user-defined clock on object "p:CLK"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed May 21 19:31:43 2014
    #

    Top view:               Counter_44bit
    Requested Frequency:    652.7 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: -0.270

                          Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock        Frequency     Frequency     Period        Period        Slack      Type         Group
    ---------------------------------------------------------------------------------------------------------------------------
    Counter_44bit|CLK     652.7 MHz     554.8 MHz     1.532         1.803         -0.270     inferred     Autoconstr_clkgroup_0
    System                1.0 MHz       NA            1000.000      NA            NA         system       system_clkgroup
    ===========================================================================================================================

    Clock Relationships
    *******************

    Clocks                                |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -----------------------------------------------------------------------------------------------------------------------------
    Starting           Ending             |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    -----------------------------------------------------------------------------------------------------------------------------
    Counter_44bit|CLK  System             |  1.532       0.461   |  No paths    -      |  No paths    -      |  No paths    -
    Counter_44bit|CLK  Counter_44bit|CLK  |  1.532       -0.270  |  No paths    -      |  No paths    -      |  No paths    -
    =============================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: Counter_44bit|CLK
    ====================================

    Starting Points with Worst Slack
    ********************************

                  Starting                                             Arrival
    Instance      Reference             Type     Pin     Net           Time        Slack
                  Clock
    -------------------------------------------------------------------------------------
    DFF0          Counter_44bit|CLK     SLE      Q       DFF0          0.076       -0.270
    DFF0_rep1     Counter_44bit|CLK     SLE      Q       DFF0_rep1     0.076       0.105
    DFF0_rep2     Counter_44bit|CLK     SLE      Q       DFF0_rep2     0.076       0.105
    DFF1_fast     Counter_44bit|CLK     SLE      Q       DFF1_fast     0.094       0.112
    DFF1          Counter_44bit|CLK     SLE      Q       DFF1          0.094       0.155
    DFF1_rep1     Counter_44bit|CLK     SLE      Q       DFF1_rep1     0.094       0.155
    DFF1_rep2     Counter_44bit|CLK     SLE      Q       DFF1_rep2     0.094       0.155
    DFF0_fast     Counter_44bit|CLK     SLE      Q       DFF0_fast     0.076       0.212
    A[0]          Counter_44bit|CLK     SLE      Q       B[0]          0.094       0.461
    C_in[0]       Counter_44bit|CLK     SLE      Q       C_in[0]       0.094       0.467
    =====================================================================================

    Ending Points with Worst Slack
    ******************************

                 Starting                                             Required
    Instance     Reference             Type     Pin     Net           Time         Slack
                 Clock
    -------------------------------------------------------------------------------------
    C_in[0]      Counter_44bit|CLK     SLE      D       C_in_3[0]     1.310        -0.270
    C_in[1]      Counter_44bit|CLK     SLE      D       C_in_3[1]     1.310        -0.270
    C_in[2]      Counter_44bit|CLK     SLE      D       C_in_3[2]     1.310        -0.270
    C_in[3]      Counter_44bit|CLK     SLE      D       C_in_3[3]     1.310        -0.270
    C_in[4]      Counter_44bit|CLK     SLE      D       C_in_3[4]     1.310        -0.270
    C_in[5]      Counter_44bit|CLK     SLE      D       C_in_3[5]     1.310        -0.270
    C_in[6]      Counter_44bit|CLK     SLE      D       C_in_3[6]     1.310        -0.270
    C_in[7]      Counter_44bit|CLK     SLE      D       C_in_3[7]     1.310        -0.270
    C_in[8]      Counter_44bit|CLK     SLE      D       C_in_3[8]     1.310        -0.270
    C_in[9]      Counter_44bit|CLK     SLE      D       C_in_3[9]     1.310        -0.270
    =====================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1.532
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         1.310

        - Propagation time:                      1.581
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.270

        Number of logic level(s):                1
        Starting point:                          DFF0 / Q
        Ending point:                            C_in[0] / D
        The start point is clocked by            Counter_44bit|CLK [rising] on pin CLK
        The end   point is clocked by            Counter_44bit|CLK [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    DFF0               SLE      Q        Out     0.076     0.076       -
    DFF0               Net      -        -       1.223     -           14
    C_in_RNO[0]        CFG4     B        In      -         1.300       -
    C_in_RNO[0]        CFG4     Y        Out     0.143     1.443       -
    C_in_3[0]          Net      -        -       0.138     -           1
    C_in[0]            SLE      D        In      -         1.581       -
    =============================================================================
    Total path delay (propagation time + setup) of 1.803 is 0.441(24.5%) logic and 1.361(75.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      1.532
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         1.310

        - Propagation time:                      1.581
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.270

        Number of logic level(s):                1
        Starting point:                          DFF0 / Q
        Ending point:                            C_in[9] / D
        The start point is clocked by            Counter_44bit|CLK [rising] on pin CLK
        The end   point is clocked by            Counter_44bit|CLK [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    DFF0               SLE      Q        Out     0.076     0.076       -
    DFF0               Net      -        -       1.223     -           14
    C_in_RNO[9]        CFG4     B        In      -         1.300       -
    C_in_RNO[9]        CFG4     Y        Out     0.143     1.443       -
    C_in_3[9]          Net      -        -       0.138     -           1
    C_in[9]            SLE      D        In      -         1.581       -
    =============================================================================
    Total path delay (propagation time + setup) of 1.803 is 0.441(24.5%) logic and 1.361(75.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      1.532
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         1.310

        - Propagation time:                      1.581
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.270

        Number of logic level(s):                1
        Starting point:                          DFF0 / Q
        Ending point:                            C_in[8] / D
        The start point is clocked by            Counter_44bit|CLK [rising] on pin CLK
        The end   point is clocked by            Counter_44bit|CLK [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    DFF0               SLE      Q        Out     0.076     0.076       -
    DFF0               Net      -        -       1.223     -           14
    C_in_RNO[8]        CFG4     B        In      -         1.300       -
    C_in_RNO[8]        CFG4     Y        Out     0.143     1.443       -
    C_in_3[8]          Net      -        -       0.138     -           1
    C_in[8]            SLE      D        In      -         1.581       -
    =============================================================================
    Total path delay (propagation time + setup) of 1.803 is 0.441(24.5%) logic and 1.361(75.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      1.532
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         1.310

        - Propagation time:                      1.581
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.270

        Number of logic level(s):                1
        Starting point:                          DFF0 / Q
        Ending point:                            C_in[7] / D
        The start point is clocked by            Counter_44bit|CLK [rising] on pin CLK
        The end   point is clocked by            Counter_44bit|CLK [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    DFF0               SLE      Q        Out     0.076     0.076       -
    DFF0               Net      -        -       1.223     -           14
    C_in_RNO[7]        CFG4     B        In      -         1.300       -
    C_in_RNO[7]        CFG4     Y        Out     0.143     1.443       -
    C_in_3[7]          Net      -        -       0.138     -           1
    C_in[7]            SLE      D        In      -         1.581       -
    =============================================================================
    Total path delay (propagation time + setup) of 1.803 is 0.441(24.5%) logic and 1.361(75.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      1.532
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         1.310

        - Propagation time:                      1.581
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.270

        Number of logic level(s):                1
        Starting point:                          DFF0 / Q
        Ending point:                            C_in[6] / D
        The start point is clocked by            Counter_44bit|CLK [rising] on pin CLK
        The end   point is clocked by            Counter_44bit|CLK [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    DFF0               SLE      Q        Out     0.076     0.076       -
    DFF0               Net      -        -       1.223     -           14
    C_in_RNO[6]        CFG4     B        In      -         1.300       -
    C_in_RNO[6]        CFG4     Y        Out     0.143     1.443       -
    C_in_3[6]          Net      -        -       0.138     -           1
    C_in[6]            SLE      D        In      -         1.581       -
    =============================================================================
    Total path delay (propagation time + setup) of 1.803 is 0.441(24.5%) logic and 1.361(75.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    ---------------------------------------
    Resource Usage Report for Counter_44bit

    Mapping to part: m2s050fbga896-1
    Cell usage:
    CLKINT          2 uses
    CFG1           1 use
    CFG2           1 use
    CFG4           44 uses

    Sequential Cells:
    SLE            53 uses

    DSP Blocks:    1
     MACC:         1 Mult

    I/O ports: 93
    I/O primitives: 93
    INBUF          49 uses
    OUTBUF         44 uses

    Global Clock Buffers: 2

    Total LUTs:    46

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 133MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 19:31:43 2014

    ###########################################################]

`