@W: MT530 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\asll_asrl_18bit\component\work\mult18x18\mult18x18_0\mult18x18_mult18x18_0_hard_mult.vhd":104:4:104:5|Found inferred clock ASLL_ASRL|CLK which controls 17 sequential elements including U0.Mult18x18_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
