`

    #Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014
    #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1
    #OS: Windows 7 6.1
    #Hostname: W764-TADIGADAPA

    #Implementation: synthesis

    $ Start of Compile
    #Wed May 21 19:20:46 2014

    Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    @N: : Fourinput_42bit_Adder.vhd(28) | Top entity is set to Fourinput_42bit_Adder.
    VHDL syntax check successful!
    @N:CD630 : Fourinput_42bit_Adder.vhd(28) | Synthesizing work.fourinput_42bit_adder.adder42bit_arch
    @N:CD630 : MultAdder_w_Din.vhd(17) | Synthesizing work.multadder_w_din.rtl
    @N:CD630 : MultAdder_w_Din_MultAdder_w_Din_0_HARD_MULT_ADDSUB.vhd(8) | Synthesizing work.multadder_w_din_multadder_w_din_0_hard_mult_addsub.def_arch
    @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box
    Post processing for smartfusion2.vcc.syn_black_box
    @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box
    Post processing for smartfusion2.gnd.syn_black_box
    @N:CD630 : smartfusion2.vhd(695) | Synthesizing smartfusion2.macc.syn_black_box
    Post processing for smartfusion2.macc.syn_black_box
    Post processing for work.multadder_w_din_multadder_w_din_0_hard_mult_addsub.def_arch
    Post processing for work.multadder_w_din.rtl
    @N:CD630 : MultAdder.vhd(17) | Synthesizing work.multadder.rtl
    @N:CD630 : MultAdder_MultAdder_0_HARD_MULT_ADDSUB.vhd(8) | Synthesizing work.multadder_multadder_0_hard_mult_addsub.def_arch
    @W:CD275 : MultAdder_MultAdder_0_HARD_MULT_ADDSUB.vhd(35) | Component declarations with different initial values are not supported.  Port cdin of component macc may have been given a different initial value in two different component declarations
    Post processing for work.multadder_multadder_0_hard_mult_addsub.def_arch
    Post processing for work.multadder.rtl
    Post processing for work.fourinput_42bit_adder.adder42bit_arch
    @END

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 19:20:46 2014

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Linked File: DSP
    Printing clock  summary report in "D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Fourinput_42bit_Adder\synthesis\Fourinput_42bit_Adder_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB)

    syn_allowed_resources : blockrams=69  set on top level netlist Fourinput_42bit_Adder

    Clock Summary
    **************

    Start                         Requested     Requested     Clock        Clock
    Clock                         Frequency     Period        Type         Group
    --------------------------------------------------------------------------------------------
    Fourinput_42bit_Adder|CLK     1.0 MHz       1000.000      inferred     Autoconstr_clkgroup_0
    System                        1.0 MHz       1000.000      system       system_clkgroup
    ============================================================================================

    @W:MT530 : multadder_multadder_0_hard_mult_addsub.vhd(112) | Found inferred clock Fourinput_42bit_Adder|CLK which controls 80 sequential elements including U0.MultAdder_0.U0. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Fourinput_42bit_Adder\synthesis\Fourinput_42bit_Adder.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 133MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 19:20:48 2014

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    @N:FP130 :  | Promoting Net CLK_c on CLKINT  I_1
    @N:FP130 :  | Promoting Net RSTN_c on CLKINT  I_2

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    1 non-gated/non-generated clock tree(s) driving 84 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId0001        CLK                 port                   84         D_in[10]
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Writing Analyst data base D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Fourinput_42bit_Adder\synthesis\Fourinput_42bit_Adder.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    I-2013.09M-SP1

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    @W:MT420 :  | Found inferred clock Fourinput_42bit_Adder|CLK with period 1000.00ns. Please declare a user-defined clock on object "p:CLK"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed May 21 19:20:49 2014
    #

    Top view:               Fourinput_42bit_Adder
    Requested Frequency:    1.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: -0.146

                                  Requested      Estimated      Requested     Estimated                 Clock        Clock
    Starting Clock                Frequency      Frequency      Period        Period        Slack       Type         Group
    --------------------------------------------------------------------------------------------------------------------------------------
    Fourinput_42bit_Adder|CLK     1.0 MHz        938.4 MHz      1000.000      1.066         998.934     inferred     Autoconstr_clkgroup_0
    System                        1211.1 MHz     1029.4 MHz     0.826         0.971         -0.146      system       system_clkgroup
    ======================================================================================================================================

    Clock Relationships
    *******************

    Clocks                             |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------
    Starting                   Ending  |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------
    System                     System  |  0.826       -0.146   |  No paths    -      |  No paths    -      |  No paths    -
    Fourinput_42bit_Adder|CLK  System  |  1000.000    998.934  |  No paths    -      |  No paths    -      |  No paths    -
    ===========================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: Fourinput_42bit_Adder|CLK
    ====================================

    Starting Points with Worst Slack
    ********************************

                 Starting                                                   Arrival
    Instance     Reference                     Type     Pin     Net         Time        Slack
                 Clock
    -------------------------------------------------------------------------------------------
    D_in[0]      Fourinput_42bit_Adder|CLK     SLE      Q       D_in[0]     0.094       998.934
    D_in[1]      Fourinput_42bit_Adder|CLK     SLE      Q       D_in[1]     0.094       998.934
    D_in[2]      Fourinput_42bit_Adder|CLK     SLE      Q       D_in[2]     0.094       998.934
    D_in[3]      Fourinput_42bit_Adder|CLK     SLE      Q       D_in[3]     0.094       998.934
    D_in[4]      Fourinput_42bit_Adder|CLK     SLE      Q       D_in[4]     0.094       998.934
    D_in[5]      Fourinput_42bit_Adder|CLK     SLE      Q       D_in[5]     0.094       998.934
    D_in[6]      Fourinput_42bit_Adder|CLK     SLE      Q       D_in[6]     0.094       998.934
    D_in[7]      Fourinput_42bit_Adder|CLK     SLE      Q       D_in[7]     0.094       998.934
    D_in[8]      Fourinput_42bit_Adder|CLK     SLE      Q       D_in[8]     0.094       998.934
    D_in[9]      Fourinput_42bit_Adder|CLK     SLE      Q       D_in[9]     0.094       998.934
    ===========================================================================================

    Ending Points with Worst Slack
    ******************************

                                Starting                                                    Required
    Instance                    Reference                     Type     Pin      Net         Time         Slack
                                Clock
    ------------------------------------------------------------------------------------------------------------
    U1.MultAdder_w_Din_0.U0     Fourinput_42bit_Adder|CLK     MACC     A[0]     D_in[0]     1000.000     998.934
    U1.MultAdder_w_Din_0.U0     Fourinput_42bit_Adder|CLK     MACC     A[0]     D_in[0]     1000.000     998.934
    U1.MultAdder_w_Din_0.U0     Fourinput_42bit_Adder|CLK     MACC     A[1]     D_in[1]     1000.000     998.934
    U1.MultAdder_w_Din_0.U0     Fourinput_42bit_Adder|CLK     MACC     A[1]     D_in[1]     1000.000     998.934
    U1.MultAdder_w_Din_0.U0     Fourinput_42bit_Adder|CLK     MACC     A[2]     D_in[2]     1000.000     998.934
    U1.MultAdder_w_Din_0.U0     Fourinput_42bit_Adder|CLK     MACC     A[2]     D_in[2]     1000.000     998.934
    U1.MultAdder_w_Din_0.U0     Fourinput_42bit_Adder|CLK     MACC     A[3]     D_in[3]     1000.000     998.934
    U1.MultAdder_w_Din_0.U0     Fourinput_42bit_Adder|CLK     MACC     A[3]     D_in[3]     1000.000     998.934
    U1.MultAdder_w_Din_0.U0     Fourinput_42bit_Adder|CLK     MACC     A[4]     D_in[4]     1000.000     998.934
    U1.MultAdder_w_Din_0.U0     Fourinput_42bit_Adder|CLK     MACC     A[4]     D_in[4]     1000.000     998.934
    ============================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         1000.000

        - Propagation time:                      1.066
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 998.934

        Number of logic level(s):                0
        Starting point:                          D_in[0] / Q
        Ending point:                            U1.MultAdder_w_Din_0.U0 / A[0]
        The start point is clocked by            Fourinput_42bit_Adder|CLK [rising] on pin CLK
        The end   point is clocked by            System [rising]

    Instance / Net                       Pin      Pin               Arrival     No. of
    Name                        Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------
    D_in[0]                     SLE      Q        Out     0.094     0.094       -
    D_in[0]                     Net      -        -       0.971     -           1
    U1.MultAdder_w_Din_0.U0     MACC     A[0]     In      -         1.066       -
    ======================================================================================
    Total path delay (propagation time + setup) of 1.066 is 0.094(8.8%) logic and 0.971(91.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                          Starting                                          Arrival
    Instance              Reference     Type     Pin          Net           Time        Slack
                          Clock
    ------------------------------------------------------------------------------------------
    U0.MultAdder_0.U0     System        MACC     CDOUT[0]     CDIN_0[0]     0.000       -0.146
    U0.MultAdder_0.U0     System        MACC     CDOUT[0]     CDIN_0[0]     0.000       -0.146
    U0.MultAdder_0.U0     System        MACC     CDOUT[1]     CDIN_0[1]     0.000       -0.146
    U0.MultAdder_0.U0     System        MACC     CDOUT[1]     CDIN_0[1]     0.000       -0.146
    U0.MultAdder_0.U0     System        MACC     CDOUT[2]     CDIN_0[2]     0.000       -0.146
    U0.MultAdder_0.U0     System        MACC     CDOUT[2]     CDIN_0[2]     0.000       -0.146
    U0.MultAdder_0.U0     System        MACC     CDOUT[3]     CDIN_0[3]     0.000       -0.146
    U0.MultAdder_0.U0     System        MACC     CDOUT[3]     CDIN_0[3]     0.000       -0.146
    U0.MultAdder_0.U0     System        MACC     CDOUT[4]     CDIN_0[4]     0.000       -0.146
    U0.MultAdder_0.U0     System        MACC     CDOUT[4]     CDIN_0[4]     0.000       -0.146
    ==========================================================================================

    Ending Points with Worst Slack
    ******************************

                                Starting                                         Required
    Instance                    Reference     Type     Pin         Net           Time         Slack
                                Clock
    ------------------------------------------------------------------------------------------------
    U1.MultAdder_w_Din_0.U0     System        MACC     CARRYIN     CARRYIN       0.826        -0.146
    U1.MultAdder_w_Din_0.U0     System        MACC     CARRYIN     CARRYIN       0.826        -0.146
    U1.MultAdder_w_Din_0.U0     System        MACC     CDIN[0]     CDIN_0[0]     0.826        -0.146
    U1.MultAdder_w_Din_0.U0     System        MACC     CDIN[0]     CDIN_0[0]     0.826        -0.146
    U1.MultAdder_w_Din_0.U0     System        MACC     CDIN[1]     CDIN_0[1]     0.826        -0.146
    U1.MultAdder_w_Din_0.U0     System        MACC     CDIN[1]     CDIN_0[1]     0.826        -0.146
    U1.MultAdder_w_Din_0.U0     System        MACC     CDIN[2]     CDIN_0[2]     0.826        -0.146
    U1.MultAdder_w_Din_0.U0     System        MACC     CDIN[2]     CDIN_0[2]     0.826        -0.146
    U1.MultAdder_w_Din_0.U0     System        MACC     CDIN[3]     CDIN_0[3]     0.826        -0.146
    U1.MultAdder_w_Din_0.U0     System        MACC     CDIN[3]     CDIN_0[3]     0.826        -0.146
    ================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -0.146

        Number of logic level(s):                0
        Starting point:                          U0.MultAdder_0.U0 / CDOUT[0]
        Ending point:                            U1.MultAdder_w_Din_0.U0 / CDIN[0]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                       Pin          Pin               Arrival     No. of
    Name                        Type     Name         Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------
    U0.MultAdder_0.U0           MACC     CDOUT[0]     Out     0.000     0.000       -
    CDIN_0[0]                   Net      -            -       0.971     -           1
    U1.MultAdder_w_Din_0.U0     MACC     CDIN[0]      In      -         0.971       -
    ==========================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -0.146

        Number of logic level(s):                0
        Starting point:                          U0.MultAdder_0.U0 / CDOUT[0]
        Ending point:                            U1.MultAdder_w_Din_0.U0 / CDIN[0]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                       Pin          Pin               Arrival     No. of
    Name                        Type     Name         Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------
    U0.MultAdder_0.U0           MACC     CDOUT[0]     Out     0.000     0.000       -
    CDIN_0[0]                   Net      -            -       0.971     -           1
    U1.MultAdder_w_Din_0.U0     MACC     CDIN[0]      In      -         0.971       -
    ==========================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -0.146

        Number of logic level(s):                0
        Starting point:                          U0.MultAdder_0.U0 / CDOUT[1]
        Ending point:                            U1.MultAdder_w_Din_0.U0 / CDIN[1]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                       Pin          Pin               Arrival     No. of
    Name                        Type     Name         Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------
    U0.MultAdder_0.U0           MACC     CDOUT[1]     Out     0.000     0.000       -
    CDIN_0[1]                   Net      -            -       0.971     -           1
    U1.MultAdder_w_Din_0.U0     MACC     CDIN[1]      In      -         0.971       -
    ==========================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -0.146

        Number of logic level(s):                0
        Starting point:                          U0.MultAdder_0.U0 / CDOUT[1]
        Ending point:                            U1.MultAdder_w_Din_0.U0 / CDIN[1]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                       Pin          Pin               Arrival     No. of
    Name                        Type     Name         Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------
    U0.MultAdder_0.U0           MACC     CDOUT[1]     Out     0.000     0.000       -
    CDIN_0[1]                   Net      -            -       0.971     -           1
    U1.MultAdder_w_Din_0.U0     MACC     CDIN[1]      In      -         0.971       -
    ==========================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -0.146

        Number of logic level(s):                0
        Starting point:                          U0.MultAdder_0.U0 / CDOUT[2]
        Ending point:                            U1.MultAdder_w_Din_0.U0 / CDIN[2]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                       Pin          Pin               Arrival     No. of
    Name                        Type     Name         Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------
    U0.MultAdder_0.U0           MACC     CDOUT[2]     Out     0.000     0.000       -
    CDIN_0[2]                   Net      -            -       0.971     -           1
    U1.MultAdder_w_Din_0.U0     MACC     CDIN[2]      In      -         0.971       -
    ==========================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    ---------------------------------------
    Resource Usage Report for Fourinput_42bit_Adder

    Mapping to part: m2s050fbga896-1
    Cell usage:
    CLKINT          2 uses

    Sequential Cells:
    SLE            80 uses

    DSP Blocks:    2
     MACC:         2 Mults

    I/O ports: 251
    I/O primitives: 251
    INBUF          162 uses
    OUTBUF         89 uses

    Global Clock Buffers: 2

    Total LUTs:    0

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 49MB peak: 133MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 19:20:49 2014

    ###########################################################]

`