`

    #Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014
    #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1
    #OS: Windows 7 6.1
    #Hostname: W764-TADIGADAPA

    #Implementation: synthesis

    $ Start of Compile
    #Wed May 21 18:10:07 2014

    Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

    @N:CD720 : std.vhd(146) | Setting time resolution to ns
    @N: : Mult32x32_multipleMACC.vhd(23) | Top entity is set to Mult32x32_multipleMACC.
    VHDL syntax check successful!
    @N:CD231 : std1164.vhd(913) | Using onehot encoding for type mvl9plus ('U'="1000000000")
    @N:CD630 : Mult32x32_multipleMACC.vhd(23) | Synthesizing work.mult32x32_multiplemacc.mult32x32_multiplemacc_arch
    Post processing for work.mult32x32_multiplemacc.mult32x32_multiplemacc_arch
    @END

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 18:10:07 2014

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Linked File: DSP
    Printing clock  summary report in "D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Wide Multiplier\Mult32x32_multiplieMACC\synthesis\Mult32x32_multipleMACC_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)

    syn_allowed_resources : blockrams=69,dsps=72  set on top level netlist Mult32x32_multipleMACC

    Clock Summary
    **************

    Start                          Requested     Requested     Clock        Clock
    Clock                          Frequency     Period        Type         Group
    ---------------------------------------------------------------------------------------------
    Mult32x32_multipleMACC|clk     217.5 MHz     4.598         inferred     Autoconstr_clkgroup_0
    =============================================================================================

    @W:MT530 : mult32x32_multiplemacc.vhd(67) | Found inferred clock Mult32x32_multipleMACC|clk which controls 256 sequential elements including Mul_result[63:0]. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Wide Multiplier\Mult32x32_multiplieMACC\synthesis\Mult32x32_multipleMACC.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 133MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 18:10:09 2014

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    @N:FF150 : mult32x32_multiplemacc.vhd(72) | Multiplier reg1_2[63:0] implemented with multiple MACC blocks using cascade/shift feature.

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 190MB peak: 190MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 140MB peak: 191MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 140MB peak: 191MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 140MB peak: 191MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 140MB peak: 191MB)

    Finished preparing to map (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 140MB peak: 191MB)

    Finished technology mapping (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 140MB peak: 191MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    @N:FX271 : mult32x32_multiplemacc.vhd(72) | Instance "inp_reg0[31]" with 5 loads replicated 1 times to improve timing
    Timing driven replication report
    Added 1 Registers via timing driven replication
    Added 0 LUTs via timing driven replication

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    @N:FP130 :  | Promoting Net clk_c on CLKINT  I_1
    @N:FP130 :  | Promoting Net reset_n_c on CLKINT  I_2

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 139MB peak: 191MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 140MB peak: 191MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    1 non-gated/non-generated clock tree(s) driving 154 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId0001        clk                 port                   154        WideMult_0_0
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Writing Analyst data base D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Wide Multiplier\Mult32x32_multiplieMACC\synthesis\Mult32x32_multipleMACC.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 138MB peak: 191MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    I-2013.09M-SP1

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 139MB peak: 191MB)

    @W:MT246 : mult32x32_multiplemacc.vhd(72) | Blackbox MACC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : mult32x32_multiplemacc.vhd(72) | Blackbox MACC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock Mult32x32_multipleMACC|clk with period 1.25ns. Please declare a user-defined clock on object "p:clk"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed May 21 18:10:23 2014
    #

    Top view:               Mult32x32_multipleMACC
    Requested Frequency:    802.6 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: -0.220

                                   Requested      Estimated     Requested     Estimated                Clock        Clock
    Starting Clock                 Frequency      Frequency     Period        Period        Slack      Type         Group
    -------------------------------------------------------------------------------------------------------------------------------------
    Mult32x32_multipleMACC|clk     802.6 MHz      682.2 MHz     1.246         1.466         -0.220     inferred     Autoconstr_clkgroup_0
    System                         1053.2 MHz     895.2 MHz     0.950         1.117         -0.168     system       system_clkgroup
    =====================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                  |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -----------------------------------------------------------------------------------------------------------------------------------------------
    Starting                    Ending                      |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    -----------------------------------------------------------------------------------------------------------------------------------------------
    System                      System                      |  0.950       -0.168  |  No paths    -      |  No paths    -      |  No paths    -
    System                      Mult32x32_multipleMACC|clk  |  1.246       -0.127  |  No paths    -      |  No paths    -      |  No paths    -
    Mult32x32_multipleMACC|clk  System                      |  1.246       0.009   |  No paths    -      |  No paths    -      |  No paths    -
    Mult32x32_multipleMACC|clk  Mult32x32_multipleMACC|clk  |  1.246       -0.220  |  No paths    -      |  No paths    -      |  No paths    -
    ===============================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: Mult32x32_multipleMACC|clk
    ====================================

    Starting Points with Worst Slack
    ********************************

                     Starting                                                         Arrival
    Instance         Reference                      Type     Pin     Net              Time        Slack
                     Clock
    ----------------------------------------------------------------------------------------------------
    inp_reg0[17]     Mult32x32_multipleMACC|clk     SLE      Q       inp_reg0[17]     0.087       -0.220
    inp_reg0[18]     Mult32x32_multipleMACC|clk     SLE      Q       inp_reg0[18]     0.087       -0.220
    inp_reg0[19]     Mult32x32_multipleMACC|clk     SLE      Q       inp_reg0[19]     0.087       -0.220
    inp_reg0[20]     Mult32x32_multipleMACC|clk     SLE      Q       inp_reg0[20]     0.087       -0.220
    inp_reg0[21]     Mult32x32_multipleMACC|clk     SLE      Q       inp_reg0[21]     0.087       -0.220
    inp_reg0[22]     Mult32x32_multipleMACC|clk     SLE      Q       inp_reg0[22]     0.087       -0.220
    inp_reg0[23]     Mult32x32_multipleMACC|clk     SLE      Q       inp_reg0[23]     0.087       -0.220
    inp_reg0[24]     Mult32x32_multipleMACC|clk     SLE      Q       inp_reg0[24]     0.087       -0.220
    inp_reg0[25]     Mult32x32_multipleMACC|clk     SLE      Q       inp_reg0[25]     0.087       -0.220
    inp_reg0[26]     Mult32x32_multipleMACC|clk     SLE      Q       inp_reg0[26]     0.087       -0.220
    ====================================================================================================

    Ending Points with Worst Slack
    ******************************

                     Starting                                                         Required
    Instance         Reference                      Type     Pin     Net              Time         Slack
                     Clock
    -----------------------------------------------------------------------------------------------------
    inp_reg1[17]     Mult32x32_multipleMACC|clk     SLE      D       inp_reg0[17]     0.991        -0.220
    inp_reg1[18]     Mult32x32_multipleMACC|clk     SLE      D       inp_reg0[18]     0.991        -0.220
    inp_reg1[19]     Mult32x32_multipleMACC|clk     SLE      D       inp_reg0[19]     0.991        -0.220
    inp_reg1[20]     Mult32x32_multipleMACC|clk     SLE      D       inp_reg0[20]     0.991        -0.220
    inp_reg1[21]     Mult32x32_multipleMACC|clk     SLE      D       inp_reg0[21]     0.991        -0.220
    inp_reg1[22]     Mult32x32_multipleMACC|clk     SLE      D       inp_reg0[22]     0.991        -0.220
    inp_reg1[23]     Mult32x32_multipleMACC|clk     SLE      D       inp_reg0[23]     0.991        -0.220
    inp_reg1[24]     Mult32x32_multipleMACC|clk     SLE      D       inp_reg0[24]     0.991        -0.220
    inp_reg1[25]     Mult32x32_multipleMACC|clk     SLE      D       inp_reg0[25]     0.991        -0.220
    inp_reg1[26]     Mult32x32_multipleMACC|clk     SLE      D       inp_reg0[26]     0.991        -0.220
    =====================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1.246
        - Setup time:                            0.255
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         0.991

        - Propagation time:                      1.210
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.220

        Number of logic level(s):                0
        Starting point:                          inp_reg0[17] / Q
        Ending point:                            inp_reg1[17] / D
        The start point is clocked by            Mult32x32_multipleMACC|clk [rising] on pin CLK
        The end   point is clocked by            Mult32x32_multipleMACC|clk [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    inp_reg0[17]       SLE      Q        Out     0.087     0.087       -
    inp_reg0[17]       Net      -        -       1.123     -           2
    inp_reg1[17]       SLE      D        In      -         1.210       -
    =============================================================================
    Total path delay (propagation time + setup) of 1.466 is 0.343(23.4%) logic and 1.123(76.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      1.246
        - Setup time:                            0.255
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         0.991

        - Propagation time:                      1.210
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.220

        Number of logic level(s):                0
        Starting point:                          inp_reg0[18] / Q
        Ending point:                            inp_reg1[18] / D
        The start point is clocked by            Mult32x32_multipleMACC|clk [rising] on pin CLK
        The end   point is clocked by            Mult32x32_multipleMACC|clk [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    inp_reg0[18]       SLE      Q        Out     0.087     0.087       -
    inp_reg0[18]       Net      -        -       1.123     -           2
    inp_reg1[18]       SLE      D        In      -         1.210       -
    =============================================================================
    Total path delay (propagation time + setup) of 1.466 is 0.343(23.4%) logic and 1.123(76.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      1.246
        - Setup time:                            0.255
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         0.991

        - Propagation time:                      1.210
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.220

        Number of logic level(s):                0
        Starting point:                          inp_reg0[19] / Q
        Ending point:                            inp_reg1[19] / D
        The start point is clocked by            Mult32x32_multipleMACC|clk [rising] on pin CLK
        The end   point is clocked by            Mult32x32_multipleMACC|clk [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    inp_reg0[19]       SLE      Q        Out     0.087     0.087       -
    inp_reg0[19]       Net      -        -       1.123     -           2
    inp_reg1[19]       SLE      D        In      -         1.210       -
    =============================================================================
    Total path delay (propagation time + setup) of 1.466 is 0.343(23.4%) logic and 1.123(76.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      1.246
        - Setup time:                            0.255
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         0.991

        - Propagation time:                      1.210
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.220

        Number of logic level(s):                0
        Starting point:                          inp_reg0[20] / Q
        Ending point:                            inp_reg1[20] / D
        The start point is clocked by            Mult32x32_multipleMACC|clk [rising] on pin CLK
        The end   point is clocked by            Mult32x32_multipleMACC|clk [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    inp_reg0[20]       SLE      Q        Out     0.087     0.087       -
    inp_reg0[20]       Net      -        -       1.123     -           2
    inp_reg1[20]       SLE      D        In      -         1.210       -
    =============================================================================
    Total path delay (propagation time + setup) of 1.466 is 0.343(23.4%) logic and 1.123(76.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      1.246
        - Setup time:                            0.255
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         0.991

        - Propagation time:                      1.210
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.220

        Number of logic level(s):                0
        Starting point:                          inp_reg0[21] / Q
        Ending point:                            inp_reg1[21] / D
        The start point is clocked by            Mult32x32_multipleMACC|clk [rising] on pin CLK
        The end   point is clocked by            Mult32x32_multipleMACC|clk [rising] on pin CLK

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    inp_reg0[21]       SLE      Q        Out     0.087     0.087       -
    inp_reg0[21]       Net      -        -       1.123     -           2
    inp_reg1[21]       SLE      D        In      -         1.210       -
    =============================================================================
    Total path delay (propagation time + setup) of 1.466 is 0.343(23.4%) logic and 1.123(76.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                     Starting                                                    Arrival
    Instance         Reference     Type     Pin          Net                     Time        Slack
                     Clock
    -----------------------------------------------------------------------------------------------
    WideMult_0_0     System        MACC     CDOUT[0]     WideMult_1_0_cas[0]     0.000       -0.168
    WideMult_0_0     System        MACC     CDOUT[0]     WideMult_1_0_cas[0]     0.000       -0.168
    WideMult_0_0     System        MACC     CDOUT[1]     WideMult_1_0_cas[1]     0.000       -0.168
    WideMult_0_0     System        MACC     CDOUT[1]     WideMult_1_0_cas[1]     0.000       -0.168
    WideMult_0_0     System        MACC     CDOUT[2]     WideMult_1_0_cas[2]     0.000       -0.168
    WideMult_0_0     System        MACC     CDOUT[2]     WideMult_1_0_cas[2]     0.000       -0.168
    WideMult_0_0     System        MACC     CDOUT[3]     WideMult_1_0_cas[3]     0.000       -0.168
    WideMult_0_0     System        MACC     CDOUT[3]     WideMult_1_0_cas[3]     0.000       -0.168
    WideMult_0_0     System        MACC     CDOUT[4]     WideMult_1_0_cas[4]     0.000       -0.168
    WideMult_0_0     System        MACC     CDOUT[4]     WideMult_1_0_cas[4]     0.000       -0.168
    ===============================================================================================

    Ending Points with Worst Slack
    ******************************

                     Starting                                                   Required
    Instance         Reference     Type     Pin         Net                     Time         Slack
                     Clock
    -----------------------------------------------------------------------------------------------
    WideMult_1_0     System        MACC     CDIN[0]     WideMult_1_0_cas[0]     0.950        -0.168
    WideMult_1_0     System        MACC     CDIN[0]     WideMult_1_0_cas[0]     0.950        -0.168
    WideMult_1_0     System        MACC     CDIN[1]     WideMult_1_0_cas[1]     0.950        -0.168
    WideMult_1_0     System        MACC     CDIN[1]     WideMult_1_0_cas[1]     0.950        -0.168
    WideMult_1_0     System        MACC     CDIN[2]     WideMult_1_0_cas[2]     0.950        -0.168
    WideMult_1_0     System        MACC     CDIN[2]     WideMult_1_0_cas[2]     0.950        -0.168
    WideMult_1_0     System        MACC     CDIN[3]     WideMult_1_0_cas[3]     0.950        -0.168
    WideMult_1_0     System        MACC     CDIN[3]     WideMult_1_0_cas[3]     0.950        -0.168
    WideMult_1_0     System        MACC     CDIN[4]     WideMult_1_0_cas[4]     0.950        -0.168
    WideMult_1_0     System        MACC     CDIN[4]     WideMult_1_0_cas[4]     0.950        -0.168
    ===============================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      0.950
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.950

        - Propagation time:                      1.117
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.168

        Number of logic level(s):                0
        Starting point:                          WideMult_0_0 / CDOUT[0]
        Ending point:                            WideMult_1_0 / CDIN[0]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                   Pin          Pin               Arrival     No. of
    Name                    Type     Name         Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------
    WideMult_0_0            MACC     CDOUT[0]     Out     0.000     0.000       -
    WideMult_1_0_cas[0]     Net      -            -       1.117     -           1
    WideMult_1_0            MACC     CDIN[0]      In      -         1.117       -
    ======================================================================================
    Total path delay (propagation time + setup) of 1.117 is 0.000(0.0%) logic and 1.117(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      0.950
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.950

        - Propagation time:                      1.117
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.168

        Number of logic level(s):                0
        Starting point:                          WideMult_0_0 / CDOUT[0]
        Ending point:                            WideMult_1_0 / CDIN[0]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                   Pin          Pin               Arrival     No. of
    Name                    Type     Name         Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------
    WideMult_0_0            MACC     CDOUT[0]     Out     0.000     0.000       -
    WideMult_1_0_cas[0]     Net      -            -       1.117     -           1
    WideMult_1_0            MACC     CDIN[0]      In      -         1.117       -
    ======================================================================================
    Total path delay (propagation time + setup) of 1.117 is 0.000(0.0%) logic and 1.117(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      0.950
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.950

        - Propagation time:                      1.117
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.168

        Number of logic level(s):                0
        Starting point:                          WideMult_0_0 / CDOUT[1]
        Ending point:                            WideMult_1_0 / CDIN[1]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                   Pin          Pin               Arrival     No. of
    Name                    Type     Name         Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------
    WideMult_0_0            MACC     CDOUT[1]     Out     0.000     0.000       -
    WideMult_1_0_cas[1]     Net      -            -       1.117     -           1
    WideMult_1_0            MACC     CDIN[1]      In      -         1.117       -
    ======================================================================================
    Total path delay (propagation time + setup) of 1.117 is 0.000(0.0%) logic and 1.117(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      0.950
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.950

        - Propagation time:                      1.117
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.168

        Number of logic level(s):                0
        Starting point:                          WideMult_0_0 / CDOUT[1]
        Ending point:                            WideMult_1_0 / CDIN[1]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                   Pin          Pin               Arrival     No. of
    Name                    Type     Name         Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------
    WideMult_0_0            MACC     CDOUT[1]     Out     0.000     0.000       -
    WideMult_1_0_cas[1]     Net      -            -       1.117     -           1
    WideMult_1_0            MACC     CDIN[1]      In      -         1.117       -
    ======================================================================================
    Total path delay (propagation time + setup) of 1.117 is 0.000(0.0%) logic and 1.117(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      0.950
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.950

        - Propagation time:                      1.117
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.168

        Number of logic level(s):                0
        Starting point:                          WideMult_0_0 / CDOUT[2]
        Ending point:                            WideMult_1_0 / CDIN[2]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                   Pin          Pin               Arrival     No. of
    Name                    Type     Name         Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------
    WideMult_0_0            MACC     CDOUT[2]     Out     0.000     0.000       -
    WideMult_1_0_cas[2]     Net      -            -       1.117     -           1
    WideMult_1_0            MACC     CDIN[2]      In      -         1.117       -
    ======================================================================================
    Total path delay (propagation time + setup) of 1.117 is 0.000(0.0%) logic and 1.117(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    ---------------------------------------
    Resource Usage Report for Mult32x32_multipleMACC

    Mapping to part: m2s050tfbga896std
    Cell usage:
    CLKINT          2 uses

    Sequential Cells:
    SLE            146 uses

    DSP Blocks:    4
     MACC:         1 Mult
     MACC:         3 MultAdds

    I/O ports: 130
    I/O primitives: 130
    INBUF          66 uses
    OUTBUF         64 uses

    Global Clock Buffers: 2

    Total LUTs:    0

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 49MB peak: 191MB)

    Process took 0h:00m:13s realtime, 0h:00m:13s cputime
    # Wed May 21 18:10:23 2014

    ###########################################################]

`