report \
    -type     timing \
    -analysis max \
    -format   xml \
    {D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\ASLL_ASRL_18bit\designer\ASLL_ASRL\ASLL_ASRL_maxdelay_timing_report.xml}
report \
    -type     timing \
    -analysis min \
    -format   xml \
    {D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\ASLL_ASRL_18bit\designer\ASLL_ASRL\ASLL_ASRL_mindelay_timing_report.xml}
report \
    -type     timing_violations \
    -analysis max \
    -format   xml \
    {D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\ASLL_ASRL_18bit\designer\ASLL_ASRL\ASLL_ASRL_maxdelay_timing_violations_report.xml}
report \
    -type     timing_violations \
    -analysis min \
    -format   xml \
    {D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\ASLL_ASRL_18bit\designer\ASLL_ASRL\ASLL_ASRL_mindelay_timing_violations_report.xml}
set has_violations {D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\ASLL_ASRL_18bit\designer\ASLL_ASRL\ASLL_ASRL_has_violations}
set fp [open $has_violations w]
puts $fp [has_violations -short]
close $fp
