`

    #Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014
    #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1
    #OS: Windows 7 6.1
    #Hostname: W764-TADIGADAPA

    #Implementation: synthesis

    $ Start of Compile
    #Wed May 21 19:41:08 2014

    Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

    @N:CD720 : std.vhd(146) | Setting time resolution to ns
    @N: : MAC_FIR.vhd(21) | Top entity is set to MAC_FIR.
    VHDL syntax check successful!
    @N:CD231 : std1164.vhd(913) | Using onehot encoding for type mvl9plus ('U'="1000000000")
    @N:CD630 : MAC_FIR.vhd(21) | Synthesizing work.mac_fir.mac_fir_arch
    @N:CD231 : MAC_FIR.vhd(144) | Using onehot encoding for type state (mac_idle="100000")
    @W:CD638 : MAC_FIR.vhd(212) | Signal portc_addr is undriven
    @W:CD638 : MAC_FIR.vhd(213) | Signal portc_din is undriven
    @W:CD638 : MAC_FIR.vhd(214) | Signal portb_coefaddr is undriven
    @W:CD638 : MAC_FIR.vhd(215) | Signal portb_inpaddr is undriven
    @N:CD630 : Inp_RAM1.vhd(17) | Synthesizing work.inp_ram1.rtl
    @N:CD630 : Inp_RAM1_Inp_RAM1_0_URAM.vhd(8) | Synthesizing work.inp_ram1_inp_ram1_0_uram.def_arch
    @N:CD630 : smartfusion2.vhd(620) | Synthesizing smartfusion2.ram64x18.syn_black_box
    Post processing for smartfusion2.ram64x18.syn_black_box
    @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box
    Post processing for smartfusion2.vcc.syn_black_box
    @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box
    Post processing for smartfusion2.gnd.syn_black_box
    Post processing for work.inp_ram1_inp_ram1_0_uram.def_arch
    Post processing for work.inp_ram1.rtl
    @N:CD630 : Coef_RAM1.vhd(17) | Synthesizing work.coef_ram1.rtl
    @N:CD630 : Coef_RAM1_Coef_RAM1_0_URAM.vhd(8) | Synthesizing work.coef_ram1_coef_ram1_0_uram.def_arch
    Post processing for work.coef_ram1_coef_ram1_0_uram.def_arch
    Post processing for work.coef_ram1.rtl
    @N:CD630 : Inp_RAM.vhd(17) | Synthesizing work.inp_ram.rtl
    @N:CD630 : Inp_RAM_Inp_RAM_0_URAM.vhd(8) | Synthesizing work.inp_ram_inp_ram_0_uram.def_arch
    Post processing for work.inp_ram_inp_ram_0_uram.def_arch
    Post processing for work.inp_ram.rtl
    @N:CD630 : Coef_RAM.vhd(17) | Synthesizing work.coef_ram.rtl
    @N:CD630 : Coef_RAM_Coef_RAM_0_URAM.vhd(8) | Synthesizing work.coef_ram_coef_ram_0_uram.def_arch
    Post processing for work.coef_ram_coef_ram_0_uram.def_arch
    Post processing for work.coef_ram.rtl
    @N:CD630 : mulacc_18x18.vhd(17) | Synthesizing work.mulacc_18x18.rtl
    @N:CD630 : mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC.vhd(8) | Synthesizing work.mulacc_18x18_mulacc_18x18_0_hard_mult_acc.def_arch
    @N:CD630 : smartfusion2.vhd(695) | Synthesizing smartfusion2.macc.syn_black_box
    Post processing for smartfusion2.macc.syn_black_box
    Post processing for work.mulacc_18x18_mulacc_18x18_0_hard_mult_acc.def_arch
    Post processing for work.mulacc_18x18.rtl
    Post processing for work.mac_fir.mac_fir_arch
    @W:CL252 : MAC_FIR.vhd(215) | Bit 0 of signal PORTB_Inpaddr is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(215) | Bit 1 of signal PORTB_Inpaddr is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(215) | Bit 2 of signal PORTB_Inpaddr is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(215) | Bit 3 of signal PORTB_Inpaddr is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(215) | Bit 4 of signal PORTB_Inpaddr is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(215) | Bit 5 of signal PORTB_Inpaddr is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(214) | Bit 0 of signal PORTB_Coefaddr is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(214) | Bit 1 of signal PORTB_Coefaddr is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(214) | Bit 2 of signal PORTB_Coefaddr is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(214) | Bit 3 of signal PORTB_Coefaddr is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(214) | Bit 4 of signal PORTB_Coefaddr is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(214) | Bit 5 of signal PORTB_Coefaddr is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(212) | Bit 0 of signal PORTC_ADDR is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(212) | Bit 1 of signal PORTC_ADDR is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(212) | Bit 2 of signal PORTC_ADDR is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(212) | Bit 3 of signal PORTC_ADDR is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(212) | Bit 4 of signal PORTC_ADDR is floating -- simulation mismatch possible.
    @W:CL252 : MAC_FIR.vhd(212) | Bit 5 of signal PORTC_ADDR is floating -- simulation mismatch possible.
    @W:CL169 : MAC_FIR.vhd(587) | Pruning register rden_2
    @W:CL271 : MAC_FIR.vhd(518) | Pruning bits 7 to 6 of inp_wraddr2_3(7 downto 0) -- not in use ...
    @W:CL271 : MAC_FIR.vhd(518) | Pruning bits 7 to 6 of inp_wraddr1_3(7 downto 0) -- not in use ...
    @W:CL271 : MAC_FIR.vhd(418) | Pruning bits 7 to 6 of inp_rdaddr2_3(7 downto 0) -- not in use ...
    @W:CL271 : MAC_FIR.vhd(418) | Pruning bits 7 to 6 of inp_rdaddr1_3(7 downto 0) -- not in use ...
    @W:CL271 : MAC_FIR.vhd(400) | Pruning bits 7 to 6 of Coef_rdaddr2_3(7 downto 0) -- not in use ...
    @W:CL271 : MAC_FIR.vhd(400) | Pruning bits 7 to 6 of Coef_rdaddr1_3(7 downto 0) -- not in use ...
    @W:CL245 : MAC_FIR.vhd(669) | Bit 0 of input b_addr of instance U2_1 is floating
    @W:CL245 : MAC_FIR.vhd(669) | Bit 1 of input b_addr of instance U2_1 is floating
    @W:CL245 : MAC_FIR.vhd(669) | Bit 2 of input b_addr of instance U2_1 is floating
    @W:CL245 : MAC_FIR.vhd(669) | Bit 3 of input b_addr of instance U2_1 is floating
    @W:CL245 : MAC_FIR.vhd(669) | Bit 4 of input b_addr of instance U2_1 is floating
    @W:CL245 : MAC_FIR.vhd(669) | Bit 5 of input b_addr of instance U2_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 0 of input b_addr of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 1 of input b_addr of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 2 of input b_addr of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 3 of input b_addr of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 4 of input b_addr of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 5 of input b_addr of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 0 of input c_addr of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 1 of input c_addr of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 2 of input c_addr of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 3 of input c_addr of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 4 of input c_addr of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 5 of input c_addr of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 0 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 1 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 2 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 3 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 4 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 5 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 6 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 7 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 8 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 9 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 10 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 11 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 12 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 13 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 14 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 15 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 16 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(652) | Bit 17 of input c_din of instance U1_1 is floating
    @W:CL245 : MAC_FIR.vhd(633) | Bit 0 of input b_addr of instance U2 is floating
    @W:CL245 : MAC_FIR.vhd(633) | Bit 1 of input b_addr of instance U2 is floating
    @W:CL245 : MAC_FIR.vhd(633) | Bit 2 of input b_addr of instance U2 is floating
    @W:CL245 : MAC_FIR.vhd(633) | Bit 3 of input b_addr of instance U2 is floating
    @W:CL245 : MAC_FIR.vhd(633) | Bit 4 of input b_addr of instance U2 is floating
    @W:CL245 : MAC_FIR.vhd(633) | Bit 5 of input b_addr of instance U2 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 0 of input b_addr of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 1 of input b_addr of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 2 of input b_addr of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 3 of input b_addr of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 4 of input b_addr of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 5 of input b_addr of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 0 of input c_addr of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 1 of input c_addr of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 2 of input c_addr of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 3 of input c_addr of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 4 of input c_addr of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 5 of input c_addr of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 0 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 1 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 2 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 3 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 4 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 5 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 6 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 7 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 8 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 9 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 10 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 11 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 12 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 13 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 14 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 15 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 16 of input c_din of instance U1 is floating
    @W:CL245 : MAC_FIR.vhd(616) | Bit 17 of input c_din of instance U1 is floating
    @N:CL201 : MAC_FIR.vhd(274) | Trying to extract state machine for register mac_state
    Extracted state machine for register mac_state
    State machine has 6 reachable states with original encodings of:
       000001
       000010
       000100
       001000
       010000
       100000
    @END

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 19:41:08 2014

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Linked File: DSP
    Printing clock  summary report in "D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\MAC FIR 16-tap\MAC_FIR\synthesis\MAC_FIR_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB)

    syn_allowed_resources : blockrams=69  set on top level netlist MAC_FIR

    Clock Summary
    **************

    Start           Requested     Requested     Clock        Clock
    Clock           Frequency     Period        Type         Group
    ------------------------------------------------------------------------------
    MAC_FIR|clk     231.9 MHz     4.312         inferred     Autoconstr_clkgroup_0
    System          1.0 MHz       1000.000      system       system_clkgroup
    ==============================================================================

    @W:MT530 : mulacc_18x18_mulacc_18x18_0_hard_mult_acc.vhd(108) | Found inferred clock MAC_FIR|clk which controls 216 sequential elements including U0.mulacc_18x18_0.U0. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\MAC FIR 16-tap\MAC_FIR\synthesis\MAC_FIR.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 134MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 19:41:09 2014

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Encoding state machine mac_state[0:5] (view:work.MAC_FIR(mac_fir_arch))
    original code -> new code
       000001 -> 000001
       000010 -> 000010
       000100 -> 000100
       001000 -> 001000
       010000 -> 010000
       100000 -> 100000
    @N: : mac_fir.vhd(433) | Found counter in view:work.MAC_FIR(mac_fir_arch) inst inp_rdaddr[7:0]

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		    -3.47ns		 184 /       216
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		    -3.47ns		 183 /       216
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		    -3.47ns		 183 /       216
    ------------------------------------------------------------

    @N:FP130 :  | Promoting Net reset_n_c on CLKINT  I_221
    @N:FP130 :  | Promoting Net clk_c on CLKINT  I_222

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    1 non-gated/non-generated clock tree(s) driving 218 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId0001        clk                 port                   218        inp_wraddr[0]
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Writing Analyst data base D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Single MAC FIR Filters\MAC FIR 16-tap\MAC_FIR\synthesis\MAC_FIR.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    I-2013.09M-SP1

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)

    @W:MT246 : inp_ram1_inp_ram1_0_uram.vhd(89) | Blackbox RAM64x18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock MAC_FIR|clk with period 3.05ns. Please declare a user-defined clock on object "p:clk"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed May 21 19:41:11 2014
    #

    Top view:               MAC_FIR
    Requested Frequency:    327.7 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: -0.538

                       Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group
    ------------------------------------------------------------------------------------------------------------------------
    MAC_FIR|clk        327.7 MHz     278.5 MHz     3.052         3.590         -0.538     inferred     Autoconstr_clkgroup_0
    System             1.0 MHz       1.0 MHz       1000.000      998.462       1.538      system       system_clkgroup
    ========================================================================================================================

    Clock Relationships
    *******************

    Clocks                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -----------------------------------------------------------------------------------------------------------------
    Starting     Ending       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    -----------------------------------------------------------------------------------------------------------------
    System       MAC_FIR|clk  |  3.052       1.538   |  No paths    -      |  No paths    -      |  No paths    -
    MAC_FIR|clk  System       |  3.052       0.437   |  No paths    -      |  No paths    -      |  No paths    -
    MAC_FIR|clk  MAC_FIR|clk  |  3.052       -0.538  |  No paths    -      |  No paths    -      |  No paths    -
    =================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: MAC_FIR|clk
    ====================================

    Starting Points with Worst Slack
    ********************************

                       Starting                                            Arrival
    Instance           Reference       Type     Pin     Net                Time        Slack
                       Clock
    -----------------------------------------------------------------------------------------
    inp_rdaddr[2]      MAC_FIR|clk     SLE      Q       inp_rdaddr[2]      0.094       -0.538
    inp_wraddr[6]      MAC_FIR|clk     SLE      Q       inp_wraddr[6]      0.094       -0.463
    inp_rdaddr[3]      MAC_FIR|clk     SLE      Q       inp_rdaddr[3]      0.094       -0.354
    inp_wraddr[5]      MAC_FIR|clk     SLE      Q       inp_wraddr[5]      0.094       -0.354
    inp_wraddr[1]      MAC_FIR|clk     SLE      Q       inp_wraddr[1]      0.076       -0.313
    inp_rdaddr[4]      MAC_FIR|clk     SLE      Q       inp_rdaddr[4]      0.094       -0.287
    Coef_rdaddr[1]     MAC_FIR|clk     SLE      Q       Coef_rdaddr[1]     0.094       -0.254
    inp_rdaddr[7]      MAC_FIR|clk     SLE      Q       inp_rdaddr[7]      0.094       -0.244
    Coef_rdaddr[0]     MAC_FIR|clk     SLE      Q       Coef_rdaddr[0]     0.094       -0.208
    inp_wraddr[3]      MAC_FIR|clk     SLE      Q       inp_wraddr[3]      0.094       -0.120
    =========================================================================================

    Ending Points with Worst Slack
    ******************************

                       Starting                                                     Required
    Instance           Reference       Type     Pin     Net                         Time         Slack
                       Clock
    ---------------------------------------------------------------------------------------------------
    inp_rdaddr[1]      MAC_FIR|clk     SLE      D       inp_rdaddr_lm[1]            2.830        -0.538
    inp_rdaddr[2]      MAC_FIR|clk     SLE      D       inp_rdaddr_lm[2]            2.830        -0.538
    inp_rdaddr[3]      MAC_FIR|clk     SLE      D       inp_rdaddr_lm[3]            2.830        -0.538
    inp_rdaddr[4]      MAC_FIR|clk     SLE      D       inp_rdaddr_lm[4]            2.830        -0.538
    inp_rdaddr[5]      MAC_FIR|clk     SLE      D       inp_rdaddr_lm[5]            2.830        -0.538
    inp_rdaddr[6]      MAC_FIR|clk     SLE      D       inp_rdaddr_lm[6]            2.830        -0.538
    inp_rdaddr[7]      MAC_FIR|clk     SLE      D       inp_rdaddr_lm[7]            2.830        -0.538
    inp_wraddr[3]      MAC_FIR|clk     SLE      D       un1_inp_wraddr_1_axbxc3     2.830        -0.463
    inp_rdaddr[0]      MAC_FIR|clk     SLE      D       inp_rdaddr_lm[0]            2.830        -0.328
    Coef_rdaddr[6]     MAC_FIR|clk     SLE      D       N_8_i_0                     2.830        -0.254
    ===================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      3.052
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.830

        - Propagation time:                      3.368
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.538

        Number of logic level(s):                3
        Starting point:                          inp_rdaddr[2] / Q
        Ending point:                            inp_rdaddr[1] / D
        The start point is clocked by            MAC_FIR|clk [rising] on pin CLK
        The end   point is clocked by            MAC_FIR|clk [rising] on pin CLK

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                          Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    inp_rdaddr[2]                 SLE      Q        Out     0.094     0.094       -
    inp_rdaddr[2]                 Net      -        -       0.676     -           4
    op_eq\.un72_mac_state_2_0     CFG4     D        In      -         0.770       -
    op_eq\.un72_mac_state_2_0     CFG4     Y        Out     0.384     1.155       -
    op_eq\.un72_mac_state_2_0     Net      -        -       0.548     -           2
    inp_rdaddr_1_sqmuxa           CFG4     D        In      -         1.703       -
    inp_rdaddr_1_sqmuxa           CFG4     Y        Out     0.411     2.114       -
    inp_rdaddr_1_sqmuxa           Net      -        -       0.706     -           8
    inp_rdaddr_lm_0[1]            CFG4     D        In      -         2.820       -
    inp_rdaddr_lm_0[1]            CFG4     Y        Out     0.411     3.230       -
    inp_rdaddr_lm[1]              Net      -        -       0.138     -           1
    inp_rdaddr[1]                 SLE      D        In      -         3.368       -
    ========================================================================================
    Total path delay (propagation time + setup) of 3.590 is 1.522(42.4%) logic and 2.068(57.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      3.052
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.830

        - Propagation time:                      3.368
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.538

        Number of logic level(s):                3
        Starting point:                          inp_rdaddr[2] / Q
        Ending point:                            inp_rdaddr[3] / D
        The start point is clocked by            MAC_FIR|clk [rising] on pin CLK
        The end   point is clocked by            MAC_FIR|clk [rising] on pin CLK

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                          Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    inp_rdaddr[2]                 SLE      Q        Out     0.094     0.094       -
    inp_rdaddr[2]                 Net      -        -       0.676     -           4
    op_eq\.un72_mac_state_2_0     CFG4     D        In      -         0.770       -
    op_eq\.un72_mac_state_2_0     CFG4     Y        Out     0.384     1.155       -
    op_eq\.un72_mac_state_2_0     Net      -        -       0.548     -           2
    inp_rdaddr_1_sqmuxa           CFG4     D        In      -         1.703       -
    inp_rdaddr_1_sqmuxa           CFG4     Y        Out     0.411     2.114       -
    inp_rdaddr_1_sqmuxa           Net      -        -       0.706     -           8
    inp_rdaddr_lm_0[3]            CFG4     D        In      -         2.820       -
    inp_rdaddr_lm_0[3]            CFG4     Y        Out     0.411     3.230       -
    inp_rdaddr_lm[3]              Net      -        -       0.138     -           1
    inp_rdaddr[3]                 SLE      D        In      -         3.368       -
    ========================================================================================
    Total path delay (propagation time + setup) of 3.590 is 1.522(42.4%) logic and 2.068(57.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      3.052
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.830

        - Propagation time:                      3.368
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.538

        Number of logic level(s):                3
        Starting point:                          inp_rdaddr[2] / Q
        Ending point:                            inp_rdaddr[6] / D
        The start point is clocked by            MAC_FIR|clk [rising] on pin CLK
        The end   point is clocked by            MAC_FIR|clk [rising] on pin CLK

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                          Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    inp_rdaddr[2]                 SLE      Q        Out     0.094     0.094       -
    inp_rdaddr[2]                 Net      -        -       0.676     -           4
    op_eq\.un72_mac_state_2_0     CFG4     D        In      -         0.770       -
    op_eq\.un72_mac_state_2_0     CFG4     Y        Out     0.384     1.155       -
    op_eq\.un72_mac_state_2_0     Net      -        -       0.548     -           2
    inp_rdaddr_1_sqmuxa           CFG4     D        In      -         1.703       -
    inp_rdaddr_1_sqmuxa           CFG4     Y        Out     0.411     2.114       -
    inp_rdaddr_1_sqmuxa           Net      -        -       0.706     -           8
    inp_rdaddr_lm_0[6]            CFG4     D        In      -         2.820       -
    inp_rdaddr_lm_0[6]            CFG4     Y        Out     0.411     3.230       -
    inp_rdaddr_lm[6]              Net      -        -       0.138     -           1
    inp_rdaddr[6]                 SLE      D        In      -         3.368       -
    ========================================================================================
    Total path delay (propagation time + setup) of 3.590 is 1.522(42.4%) logic and 2.068(57.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      3.052
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.830

        - Propagation time:                      3.368
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.538

        Number of logic level(s):                3
        Starting point:                          inp_rdaddr[2] / Q
        Ending point:                            inp_rdaddr[7] / D
        The start point is clocked by            MAC_FIR|clk [rising] on pin CLK
        The end   point is clocked by            MAC_FIR|clk [rising] on pin CLK

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                          Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    inp_rdaddr[2]                 SLE      Q        Out     0.094     0.094       -
    inp_rdaddr[2]                 Net      -        -       0.676     -           4
    op_eq\.un72_mac_state_2_0     CFG4     D        In      -         0.770       -
    op_eq\.un72_mac_state_2_0     CFG4     Y        Out     0.384     1.155       -
    op_eq\.un72_mac_state_2_0     Net      -        -       0.548     -           2
    inp_rdaddr_1_sqmuxa           CFG4     D        In      -         1.703       -
    inp_rdaddr_1_sqmuxa           CFG4     Y        Out     0.411     2.114       -
    inp_rdaddr_1_sqmuxa           Net      -        -       0.706     -           8
    inp_rdaddr_lm_0[7]            CFG4     D        In      -         2.820       -
    inp_rdaddr_lm_0[7]            CFG4     Y        Out     0.411     3.230       -
    inp_rdaddr_lm[7]              Net      -        -       0.138     -           1
    inp_rdaddr[7]                 SLE      D        In      -         3.368       -
    ========================================================================================
    Total path delay (propagation time + setup) of 3.590 is 1.522(42.4%) logic and 2.068(57.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      3.052
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.830

        - Propagation time:                      3.368
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.538

        Number of logic level(s):                3
        Starting point:                          inp_rdaddr[2] / Q
        Ending point:                            inp_rdaddr[5] / D
        The start point is clocked by            MAC_FIR|clk [rising] on pin CLK
        The end   point is clocked by            MAC_FIR|clk [rising] on pin CLK

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                          Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    inp_rdaddr[2]                 SLE      Q        Out     0.094     0.094       -
    inp_rdaddr[2]                 Net      -        -       0.676     -           4
    op_eq\.un72_mac_state_2_0     CFG4     D        In      -         0.770       -
    op_eq\.un72_mac_state_2_0     CFG4     Y        Out     0.384     1.155       -
    op_eq\.un72_mac_state_2_0     Net      -        -       0.548     -           2
    inp_rdaddr_1_sqmuxa           CFG4     D        In      -         1.703       -
    inp_rdaddr_1_sqmuxa           CFG4     Y        Out     0.411     2.114       -
    inp_rdaddr_1_sqmuxa           Net      -        -       0.706     -           8
    inp_rdaddr_lm_0[5]            CFG4     D        In      -         2.820       -
    inp_rdaddr_lm_0[5]            CFG4     Y        Out     0.411     3.230       -
    inp_rdaddr_lm[5]              Net      -        -       0.138     -           1
    inp_rdaddr[5]                 SLE      D        In      -         3.368       -
    ========================================================================================
    Total path delay (propagation time + setup) of 3.590 is 1.522(42.4%) logic and 2.068(57.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                         Starting                                                     Arrival
    Instance                                             Reference     Type         Pin           Net                 Time        Slack
                                                         Clock
    -----------------------------------------------------------------------------------------------------------------------------------
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[0]     Coef_rddata2[0]     0.000       1.538
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[1]     Coef_rddata2[1]     0.000       1.538
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[2]     Coef_rddata2[2]     0.000       1.538
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[3]     Coef_rddata2[3]     0.000       1.538
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[4]     Coef_rddata2[4]     0.000       1.538
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[5]     Coef_rddata2[5]     0.000       1.538
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[6]     Coef_rddata2[6]     0.000       1.538
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[7]     Coef_rddata2[7]     0.000       1.538
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[8]     Coef_rddata2[8]     0.000       1.538
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[9]     Coef_rddata2[9]     0.000       1.538
    ===================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                       Starting                                            Required
    Instance           Reference     Type     Pin     Net                  Time         Slack
                       Clock
    -----------------------------------------------------------------------------------------
    Coef_rddata[0]     System        SLE      D       Coef_rddata_3[0]     2.830        1.538
    Coef_rddata[1]     System        SLE      D       Coef_rddata_3[1]     2.830        1.538
    Coef_rddata[2]     System        SLE      D       Coef_rddata_3[2]     2.830        1.538
    Coef_rddata[3]     System        SLE      D       Coef_rddata_3[3]     2.830        1.538
    Coef_rddata[4]     System        SLE      D       Coef_rddata_3[4]     2.830        1.538
    Coef_rddata[5]     System        SLE      D       Coef_rddata_3[5]     2.830        1.538
    Coef_rddata[6]     System        SLE      D       Coef_rddata_3[6]     2.830        1.538
    Coef_rddata[7]     System        SLE      D       Coef_rddata_3[7]     2.830        1.538
    Coef_rddata[8]     System        SLE      D       Coef_rddata_3[8]     2.830        1.538
    Coef_rddata[9]     System        SLE      D       Coef_rddata_3[9]     2.830        1.538
    =========================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      3.052
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.830

        - Propagation time:                      1.291
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 1.538

        Number of logic level(s):                1
        Starting point:                          U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0 / A_DOUT[0]
        Ending point:                            Coef_rddata[0] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            MAC_FIR|clk [rising] on pin CLK

    Instance / Net                                                    Pin           Pin               Arrival     No. of
    Name                                                 Type         Name          Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------------------------
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     RAM64x18     A_DOUT[0]     Out     0.000     0.000       -
    Coef_rddata2[0]                                      Net          -             -       0.971     -           1
    Coef_rddata_3[0]                                     CFG3         C             In      -         0.971       -
    Coef_rddata_3[0]                                     CFG3         Y             Out     0.182     1.154       -
    Coef_rddata_3[0]                                     Net          -             -       0.138     -           1
    Coef_rddata[0]                                       SLE          D             In      -         1.291       -
    ========================================================================================================================
    Total path delay (propagation time + setup) of 1.513 is 0.404(26.7%) logic and 1.109(73.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    ---------------------------------------
    Resource Usage Report for MAC_FIR

    Mapping to part: m2s050fbga896-1
    Cell usage:
    CLKINT          2 uses
    CFG1           2 uses
    CFG2           57 uses
    CFG3           60 uses
    CFG4           55 uses

    Carry primitives used for arithmetic functions:
    ARI1           8 uses

    Sequential Cells:
    SLE            216 uses

    DSP Blocks:    1
     MACC:         1 Mult

    I/O ports: 67
    I/O primitives: 67
    INBUF          22 uses
    OUTBUF         45 uses

    Global Clock Buffers: 2

    RAM/ROM usage summary
    Block Rams (RAM64x18) : 4

    Total LUTs:    182

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 50MB peak: 135MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 19:41:11 2014

    ###########################################################]

`