`

    #Build: Synplify Pro G-2012.09M-SP1 , Build 013R, Feb 15 2013
    #install: C:\Microsemi\Libero_v11.0\Libero_v11.0\Synopsys\synplify_G201209MSP1
    #OS: Windows 7 6.1
    #Hostname: W7-TADIGADAPAP

    #Implementation: synthesis

    $ Start of Compile
    #Mon Apr 29 01:16:54 2013

    Synopsys VHDL Compiler, version comp201209rcp1, Build 245R, built Feb 20 2013
    @N: :  | Running in 32-bit mode
    Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    @N: : dotp_multadd.vhd(17) | Top entity is set to dotp_multadd.
    File C:\Microsemi\Libero_v11.0\Libero_v11.0\Synopsys\synplify_G201209MSP1\lib\generic\smartfusion2.vhd changed - recompiling
    File D:\Projects\Libero_11_0_0_23\Mathblock_widemult_exmp\Multsynopysis_impl\Extended_adder_2_input\component\work\dotp_multadd\dotp_multadd.vhd changed - recompiling
    VHDL syntax check successful!

    Compiler output is up to date.  No re-compile necessary

    @N:CD630 : dotp_multadd.vhd(17) | Synthesizing work.dotp_multadd.rtl
    @N:CD630 : dotp_multadd_dotp_multadd_0_HARD_MULT_ADDSUB.vhd(8) | Synthesizing work.dotp_multadd_dotp_multadd_0_hard_mult_addsub.def_arch
    @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box
    Post processing for smartfusion2.vcc.syn_black_box
    @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box
    Post processing for smartfusion2.gnd.syn_black_box
    @N:CD630 : smartfusion2.vhd(695) | Synthesizing smartfusion2.macc.syn_black_box
    Post processing for smartfusion2.macc.syn_black_box
    Post processing for work.dotp_multadd_dotp_multadd_0_hard_mult_addsub.def_arch
    Post processing for work.dotp_multadd.rtl
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Mon Apr 29 01:16:54 2013

    ###########################################################]

`
@A: : | premap output is up to date. No run necessary. To force a re-synthesis, select [Resynthesize All] in menu [Run]. Click link to view previous log file. Premap Report Linked File: dotp_multadd_premap.srr @A: : | fpga_mapper output is up to date. No run necessary. To force a re-synthesis, select [Resynthesize All] in menu [Run]. Click link to view previous log file. Map & Optimize Report Linked File: dotp_multadd_fpga_mapper.srr