----------------------------------------------------------------------
-- Created by Actel SmartDesign Mon Nov 04 18:09:30 2013
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic 
-- clock and reset pins connected.  If your design has special
-- clock/reset or testbench driver requirements then you should 
-- copy this file and modify it. 
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

    constant SYSCLK_PERIOD : time := 100 ns;

    signal SYSCLK : std_logic := '0';
    signal NSYSRESET : std_logic := '0';

    component multadd
        -- ports
        port( 
            -- Inputs
            A0_ACLR_N : in std_logic;
            A0_SCLR_N : in std_logic;
            A0_EN : in std_logic;
            B0_SCLR_N : in std_logic;
            B0_ACLR_N : in std_logic;
            B0_EN : in std_logic;
            P_ACLR_N : in std_logic;
            P_SCLR_N : in std_logic;
            P_EN : in std_logic;
            CLK : in std_logic;
            A0 : in std_logic_vector(17 downto 0);
            B0 : in std_logic_vector(17 downto 0);
            CDIN : in std_logic_vector(43 downto 0);

            -- Outputs
            P : out std_logic_vector(43 downto 0);
            CDOUT : out std_logic_vector(43 downto 0)

            -- Inouts

        );
    end component;

begin

    process
        variable vhdl_initial : BOOLEAN := TRUE;

    begin
        if ( vhdl_initial ) then
            -- Assert Reset
            NSYSRESET <= '0';
            wait for ( SYSCLK_PERIOD * 10 );
            
            NSYSRESET <= '1';
            wait;
        end if;
    end process;

    -- 10MHz Clock Driver
    SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );

    -- Instantiate Unit Under Test:  multadd
    multadd_0 : multadd
        -- port map
        port map( 
            -- Inputs
            A0_ACLR_N => '0',
            A0_SCLR_N => '0',
            A0_EN => '0',
            B0_SCLR_N => '0',
            B0_ACLR_N => '0',
            B0_EN => '0',
            P_ACLR_N => '0',
            P_SCLR_N => '0',
            P_EN => '0',
            CLK => SYSCLK,
            A0 => (others=> '0'),
            B0 => (others=> '0'),
            CDIN => (others=> '0'),

            -- Outputs
            P => open,
            CDOUT => open

            -- Inouts

        );

end behavioral;

