@W: MT530 :"d:\dsp reference guide\dsp reference guide\ref. guide design examples\liberov11.3\vhdl\wide multiplier\mult32x32\component\work\acc_0\acc_0_0\acc_0_acc_0_0_hard_mult_acc.vhd":111:4:111:5|Found inferred clock Mult32x32_SingleMACC|clk which controls 111 sequential elements including U1.acc_0_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
