----------------------------------------------------------------------
-- Created by Actel SmartDesign Thu Apr 18 14:55:40 2013
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic 
-- clock and reset pins connected.  If your design has special
-- clock/reset or testbench driver requirements then you should 
-- copy this file and modify it. 
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

    constant SYSCLK_PERIOD : time := 100 ns;

    signal SYSCLK : std_logic := '0';
    signal NSYSRESET : std_logic := '0';

    component top
        -- ports
        port( 
            -- Inputs
            CDSEL : in std_logic;
            ARSHFT17 : in std_logic;
            FDBKSEL : in std_logic;
            CLK : in std_logic_vector(1 downto 0);
            A_ARST_N : in std_logic_vector(1 downto 0);
            A : in std_logic_vector(17 downto 0);
            B : in std_logic_vector(17 downto 0);
            C : in std_logic_vector(43 downto 0);
            CDIN : in std_logic_vector(43 downto 0);
            P_ARST_N : in std_logic_vector(1 downto 0);
            C_ARST_N : in std_logic_vector(1 downto 0);
            B_ARST_N : in std_logic_vector(1 downto 0);
            C_EN : in std_logic_vector(1 downto 0);

            -- Outputs
            OVFL_CARRYOUT : out std_logic;
            P : out std_logic_vector(43 downto 0)

            -- Inouts

        );
    end component;

begin

    process
        variable vhdl_initial : BOOLEAN := TRUE;

    begin
        if ( vhdl_initial ) then
            -- Assert Reset
            NSYSRESET <= '0';
            wait for ( SYSCLK_PERIOD * 10 );
            
            NSYSRESET <= '1';
            wait;
        end if;
    end process;

    -- 10MHz Clock Driver
    SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );

    -- Instantiate Unit Under Test:  top
    top_0 : top
        -- port map
        port map( 
            -- Inputs
            CDSEL => '0',
            ARSHFT17 => NSYSRESET,
            FDBKSEL => '0',
            CLK => (others=> '0'),
            A_ARST_N => (others=> '0'),
            A => (others=> '0'),
            B => (others=> '0'),
            C => (others=> '0'),
            CDIN => (others=> '0'),
            P_ARST_N => (others=> '0'),
            C_ARST_N => (others=> '0'),
            B_ARST_N => (others=> '0'),
            C_EN => (others=> '0'),

            -- Outputs
            OVFL_CARRYOUT =>  open,
            P => open

            -- Inouts

        );

end behavioral;

