--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: testbench.vhd
-- File history:

--
-- Description		: 100-tap MAC FIR filter testbench
--
-- Targeted device	: Family	:: SmartFusion2  
-- 					  Die		:: M2S050T
--					  Package	:: 896 FBGA	
--
--			Author	: PHANIKIRAN T
--------------------------------------------------------------------------------

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity Symmetric_MAC_FIR_Testbench is
end Symmetric_MAC_FIR_Testbench;

architecture Symmetric_MACFIR_testbench_arch of Symmetric_MAC_FIR_Testbench is
   
component  Symmetric_MAC_FIR is
port(	clk				: in std_logic;
		reset_n			: in std_logic;
		Filter_En		: in std_logic;
		Xn_in			: in std_logic_vector(17 downto 0);
		Data_Valid		: in std_logic;
		rdy				: out std_logic;	
		Mac_out			: out std_logic_vector(43 downto 0)	   	   	             	     	     	     	            
         );
end component Symmetric_MAC_FIR;


CONSTANT clk_period : time := 10 ns;

signal clk			: STD_LOGIC:= '0';
signal reset_n		: STD_LOGIC:= '0';
signal rdy			: STD_LOGIC;
signal Data_Valid	: STD_LOGIC:= '0';	
signal Xn_in		: STD_LOGIC_VECTOR(17 downto 0):= (OTHERS=> '0');
signal Mac_out		: STD_LOGIC_VECTOR(43 downto 0);
signal stop 		: std_logic := '0';	
signal Filter_En 	: std_logic := '0';	

begin


UUT: Symmetric_MAC_FIR
		port map(	
				clk 		=> clk,
				reset_n 	=> reset_n,
				Filter_En	=> Filter_En,
				Xn_in 		=> Xn_in,
				Data_Valid 	=> Data_Valid,
				rdy			=> rdy,
				Mac_out		=> Mac_out
         );

 clk_proc1 :process
   begin
		IF(stop = '0')THEN
	        clk <= '0';
    	    wait for clk_period/2;
        	clk <= '1';
	        wait for clk_period/2;
		ELSE
			clk <= '0';
		END IF;
   end process;


 stim_proc: process
   begin
        	reset_n <='0';
        wait for 20 ns;
        	reset_n	<='1';
        wait;
  end process;


process(clk,reset_n)
begin
if(reset_n ='0')then
	Filter_En 	<=  '0';
else
	if(clk='1' and clk'event)then
		if(stop = '1')then
			Filter_En 	<= '0';
		elsif(stop = '0')then
			Filter_En 	<= '1';	
		end if;
	end if;
end if;
end process;


process(clk,reset_n)
begin
if(reset_n ='0')then
	Xn_in 		<=(others => '0');
	Data_Valid	<= '0';	
else
	if(clk='1' and clk'event)then
		if(rdy = '1')then
			Xn_in 		<= Xn_in + '1';
			Data_Valid	<= '1';
		else
			Data_Valid	<= '0';
		end if;
	end if;
end if;
end process;

			

process
begin
		wait until (Xn_in = "000000000011001000");
		wait until rising_edge(clk);
			stop <=  '1';
		report "TEST FINISHED!"
		severity failure;
		--wait;
end process;

end Symmetric_MACFIR_testbench_arch;
