--------------------------------------------------------------------------------
-- Company:
--
-- File: BarrelShifter_18bit.vhd
-- File history: Rev 1.0
--      
--
-- Description: 
--		This design illustrates the implementation of 18-bit barrel shifter using two mathblocks. 
--		In this design, rotate left(ROL) of 5 bits is performed.
-- 		In Mathblock, one operand is a constant fixed to 2^5 = 0x20(32)
--
-- Targeted device: <Family::SmartFusion2> <Die::M2S050> <Package::896 FBGA>
--
--------------------------------------------------------------------------------

LIBRARY IEEE;

USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;

ENTITY BarrelShifter_18bit IS
PORT (
    CLK 		: IN STD_LOGIC;
    RSTN 		: IN STD_LOGIC;
	INA 		: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
   	SHIFT_OP 	: OUT STD_LOGIC_VECTOR(17 DOWNTO 0)

	);
END BarrelShifter_18bit;


ARCHITECTURE  BarrelShift_Arch OF BarrelShifter_18bit IS

 -- COMPONENT DECLARATIONS

COMPONENT Mult18x18 IS
    -- Port list
    port(
        -- Inputs
        --A0        : in  std_logic_vector(17 downto 0);
        B0        : in  std_logic_vector(17 downto 0);
        B0_ACLR_N : in  std_logic;
        B0_EN     : in  std_logic;
        B0_SCLR_N : in  std_logic;
        CLK       : in  std_logic;

        -- Outputs
        CDOUT     : out std_logic_vector(43 downto 0);
        P         : out std_logic_vector(35 downto 0)
        );
END COMPONENT Mult18x18;

COMPONENT Mult18x18_barrShift is
    -- Port list
    port(
       -- Inputs
        ARSHFT17 : in  std_logic;
        B0       : in  std_logic_vector(17 downto 0);
        CDIN     : in  std_logic_vector(43 downto 0);
        CLK      : in  std_logic;
        P_ACLR_N : in  std_logic;
        P_EN     : in  std_logic;
        P_SCLR_N : in  std_logic;
        -- Outputs
        CDOUT    : out std_logic_vector(43 downto 0);
        P        : out std_logic_vector(43 downto 0)
        );
END  COMPONENT Mult18x18_barrShift;



 -- SIGNAL DECLARATIONS
 
SIGNAL VAL		: STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL INA_r	: STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL CDOUT 	: STD_LOGIC_VECTOR(43 DOWNTO 0);
SIGNAL RESULT 	: STD_LOGIC_VECTOR(43 DOWNTO 0);


BEGIN

PROCESS(RSTN,CLK)
BEGIN
	IF(RSTN = '0')THEN
		INA_r <= (OTHERS => '0');
	ELSE
		IF(rising_edge(CLK))THEN
			INA_r <= INA;			
		END IF;
	END IF;

END PROCESS;

VAL <= '0' & INA(17 DOWNTO 1);

-- Port list
   U0 : Mult18x18
		port map
		(
        -- Inputs
        	B0        =>  VAL,
	        B0_ACLR_N => '1',
    	    B0_EN     => '1',
        	B0_SCLR_N => '1',
	        CLK       => CLK,

    	 -- Outputs
        	CDOUT     => CDOUT,
	        P         => OPEN 
        );

	U1:Mult18x18_barrShift
	port map(
        -- Inputs
    	    ARSHFT17  => '1',
        	B0        => INA_r,
	        CDIN      => CDOUT,
    	    CLK        => CLK,
			P_ACLR_N  => '1',
        	P_EN      => '1',
	        P_SCLR_N  => '1',
        -- Outputs
        	CDOUT     => OPEN,
	        P         => RESULT
        );


SHIFT_OP <= RESULT(17 DOWNTO 0);



END BarrelShift_Arch;
