-- Version: v11.1 11.1.0.14

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity dotp_multadd_dotp_multadd_0_HARD_MULT_ADDSUB is

    port( Z        : out   std_logic_vector(43 downto 0);
          INPUTD_c : in    std_logic_vector(42 downto 0);
          INPUTA_c : in    std_logic_vector(17 downto 0);
          INPUTB_c : in    std_logic_vector(17 downto 0);
          INPUTC_c : in    std_logic_vector(42 downto 0);
          X        : out   std_logic;
          clk_c    : in    std_logic
        );

end dotp_multadd_dotp_multadd_0_HARD_MULT_ADDSUB;

architecture DEF_ARCH of 
        dotp_multadd_dotp_multadd_0_HARD_MULT_ADDSUB is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;
    signal nc34, nc9, nc13, nc23, nc33, nc16, nc26, nc27, nc17, 
        nc36, nc37, nc5, nc4, nc42, nc41, nc25, nc15, nc35, nc28, 
        nc18, nc38, nc1, nc2, nc22, nc12, nc21, nc11, nc3, nc32, 
        nc40, nc31, nc44, nc7, nc6, nc19, nc29, nc39, nc8, nc43, 
        nc20, nc10, nc24, nc14, nc30 : std_logic;

begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    U0 : MACC
      port map(CLK(1) => clk_c, CLK(0) => clk_c, A(17) => 
        INPUTA_c(17), A(16) => INPUTA_c(16), A(15) => 
        INPUTA_c(15), A(14) => INPUTA_c(14), A(13) => 
        INPUTA_c(13), A(12) => INPUTA_c(12), A(11) => 
        INPUTA_c(11), A(10) => INPUTA_c(10), A(9) => INPUTA_c(9), 
        A(8) => INPUTA_c(8), A(7) => INPUTA_c(7), A(6) => 
        INPUTA_c(6), A(5) => INPUTA_c(5), A(4) => INPUTA_c(4), 
        A(3) => INPUTA_c(3), A(2) => INPUTA_c(2), A(1) => 
        INPUTA_c(1), A(0) => INPUTA_c(0), A_EN(1) => VCC_net_1, 
        A_EN(0) => VCC_net_1, A_ARST_N(1) => VCC_net_1, 
        A_ARST_N(0) => VCC_net_1, A_SRST_N(1) => VCC_net_1, 
        A_SRST_N(0) => VCC_net_1, B(17) => INPUTB_c(17), B(16)
         => INPUTB_c(16), B(15) => INPUTB_c(15), B(14) => 
        INPUTB_c(14), B(13) => INPUTB_c(13), B(12) => 
        INPUTB_c(12), B(11) => INPUTB_c(11), B(10) => 
        INPUTB_c(10), B(9) => INPUTB_c(9), B(8) => INPUTB_c(8), 
        B(7) => INPUTB_c(7), B(6) => INPUTB_c(6), B(5) => 
        INPUTB_c(5), B(4) => INPUTB_c(4), B(3) => INPUTB_c(3), 
        B(2) => INPUTB_c(2), B(1) => INPUTB_c(1), B(0) => 
        INPUTB_c(0), B_EN(1) => VCC_net_1, B_EN(0) => VCC_net_1, 
        B_ARST_N(1) => VCC_net_1, B_ARST_N(0) => VCC_net_1, 
        B_SRST_N(1) => VCC_net_1, B_SRST_N(0) => VCC_net_1, C(43)
         => GND_net_1, C(42) => INPUTC_c(42), C(41) => 
        INPUTC_c(41), C(40) => INPUTC_c(40), C(39) => 
        INPUTC_c(39), C(38) => INPUTC_c(38), C(37) => 
        INPUTC_c(37), C(36) => INPUTC_c(36), C(35) => 
        INPUTC_c(35), C(34) => INPUTC_c(34), C(33) => 
        INPUTC_c(33), C(32) => INPUTC_c(32), C(31) => 
        INPUTC_c(31), C(30) => INPUTC_c(30), C(29) => 
        INPUTC_c(29), C(28) => INPUTC_c(28), C(27) => 
        INPUTC_c(27), C(26) => INPUTC_c(26), C(25) => 
        INPUTC_c(25), C(24) => INPUTC_c(24), C(23) => 
        INPUTC_c(23), C(22) => INPUTC_c(22), C(21) => 
        INPUTC_c(21), C(20) => INPUTC_c(20), C(19) => 
        INPUTC_c(19), C(18) => INPUTC_c(18), C(17) => 
        INPUTC_c(17), C(16) => INPUTC_c(16), C(15) => 
        INPUTC_c(15), C(14) => INPUTC_c(14), C(13) => 
        INPUTC_c(13), C(12) => INPUTC_c(12), C(11) => 
        INPUTC_c(11), C(10) => INPUTC_c(10), C(9) => INPUTC_c(9), 
        C(8) => INPUTC_c(8), C(7) => INPUTC_c(7), C(6) => 
        INPUTC_c(6), C(5) => INPUTC_c(5), C(4) => INPUTC_c(4), 
        C(3) => INPUTC_c(3), C(2) => INPUTC_c(2), C(1) => 
        INPUTC_c(1), C(0) => INPUTC_c(0), C_EN(1) => VCC_net_1, 
        C_EN(0) => VCC_net_1, C_ARST_N(1) => VCC_net_1, 
        C_ARST_N(0) => VCC_net_1, C_SRST_N(1) => VCC_net_1, 
        C_SRST_N(0) => VCC_net_1, P_EN(1) => VCC_net_1, P_EN(0)
         => VCC_net_1, P_ARST_N(1) => VCC_net_1, P_ARST_N(0) => 
        VCC_net_1, P_SRST_N(1) => VCC_net_1, P_SRST_N(0) => 
        VCC_net_1, FDBKSEL => GND_net_1, FDBKSEL_EN => VCC_net_1, 
        FDBKSEL_AL_N => VCC_net_1, FDBKSEL_SL_N => VCC_net_1, 
        CDSEL => VCC_net_1, CDSEL_EN => VCC_net_1, CDSEL_AL_N => 
        VCC_net_1, CDSEL_SL_N => VCC_net_1, ARSHFT17 => GND_net_1, 
        ARSHFT17_EN => VCC_net_1, ARSHFT17_AL_N => VCC_net_1, 
        ARSHFT17_SL_N => VCC_net_1, SUB => GND_net_1, SUB_EN => 
        VCC_net_1, SUB_AL_N => VCC_net_1, SUB_SL_N => VCC_net_1, 
        CARRYIN => GND_net_1, SIMD => GND_net_1, DOTP => 
        GND_net_1, OVFL_CARRYOUT_SEL => VCC_net_1, A_BYPASS(1)
         => GND_net_1, A_BYPASS(0) => GND_net_1, B_BYPASS(1) => 
        GND_net_1, B_BYPASS(0) => GND_net_1, C_BYPASS(1) => 
        GND_net_1, C_BYPASS(0) => GND_net_1, P_BYPASS(1) => 
        GND_net_1, P_BYPASS(0) => GND_net_1, FDBKSEL_BYPASS => 
        VCC_net_1, FDBKSEL_AD => GND_net_1, FDBKSEL_SD_N => 
        VCC_net_1, CDSEL_BYPASS => VCC_net_1, CDSEL_AD => 
        GND_net_1, CDSEL_SD_N => VCC_net_1, ARSHFT17_BYPASS => 
        VCC_net_1, ARSHFT17_AD => GND_net_1, ARSHFT17_SD_N => 
        VCC_net_1, SUB_BYPASS => VCC_net_1, SUB_AD => GND_net_1, 
        SUB_SD_N => VCC_net_1, CDIN(43) => GND_net_1, CDIN(42)
         => INPUTD_c(42), CDIN(41) => INPUTD_c(41), CDIN(40) => 
        INPUTD_c(40), CDIN(39) => INPUTD_c(39), CDIN(38) => 
        INPUTD_c(38), CDIN(37) => INPUTD_c(37), CDIN(36) => 
        INPUTD_c(36), CDIN(35) => INPUTD_c(35), CDIN(34) => 
        INPUTD_c(34), CDIN(33) => INPUTD_c(33), CDIN(32) => 
        INPUTD_c(32), CDIN(31) => INPUTD_c(31), CDIN(30) => 
        INPUTD_c(30), CDIN(29) => INPUTD_c(29), CDIN(28) => 
        INPUTD_c(28), CDIN(27) => INPUTD_c(27), CDIN(26) => 
        INPUTD_c(26), CDIN(25) => INPUTD_c(25), CDIN(24) => 
        INPUTD_c(24), CDIN(23) => INPUTD_c(23), CDIN(22) => 
        INPUTD_c(22), CDIN(21) => INPUTD_c(21), CDIN(20) => 
        INPUTD_c(20), CDIN(19) => INPUTD_c(19), CDIN(18) => 
        INPUTD_c(18), CDIN(17) => INPUTD_c(17), CDIN(16) => 
        INPUTD_c(16), CDIN(15) => INPUTD_c(15), CDIN(14) => 
        INPUTD_c(14), CDIN(13) => INPUTD_c(13), CDIN(12) => 
        INPUTD_c(12), CDIN(11) => INPUTD_c(11), CDIN(10) => 
        INPUTD_c(10), CDIN(9) => INPUTD_c(9), CDIN(8) => 
        INPUTD_c(8), CDIN(7) => INPUTD_c(7), CDIN(6) => 
        INPUTD_c(6), CDIN(5) => INPUTD_c(5), CDIN(4) => 
        INPUTD_c(4), CDIN(3) => INPUTD_c(3), CDIN(2) => 
        INPUTD_c(2), CDIN(1) => INPUTD_c(1), CDIN(0) => 
        INPUTD_c(0), CDOUT(43) => nc34, CDOUT(42) => nc9, 
        CDOUT(41) => nc13, CDOUT(40) => nc23, CDOUT(39) => nc33, 
        CDOUT(38) => nc16, CDOUT(37) => nc26, CDOUT(36) => nc27, 
        CDOUT(35) => nc17, CDOUT(34) => nc36, CDOUT(33) => nc37, 
        CDOUT(32) => nc5, CDOUT(31) => nc4, CDOUT(30) => nc42, 
        CDOUT(29) => nc41, CDOUT(28) => nc25, CDOUT(27) => nc15, 
        CDOUT(26) => nc35, CDOUT(25) => nc28, CDOUT(24) => nc18, 
        CDOUT(23) => nc38, CDOUT(22) => nc1, CDOUT(21) => nc2, 
        CDOUT(20) => nc22, CDOUT(19) => nc12, CDOUT(18) => nc21, 
        CDOUT(17) => nc11, CDOUT(16) => nc3, CDOUT(15) => nc32, 
        CDOUT(14) => nc40, CDOUT(13) => nc31, CDOUT(12) => nc44, 
        CDOUT(11) => nc7, CDOUT(10) => nc6, CDOUT(9) => nc19, 
        CDOUT(8) => nc29, CDOUT(7) => nc39, CDOUT(6) => nc8, 
        CDOUT(5) => nc43, CDOUT(4) => nc20, CDOUT(3) => nc10, 
        CDOUT(2) => nc24, CDOUT(1) => nc14, CDOUT(0) => nc30, 
        P(43) => Z(43), P(42) => Z(42), P(41) => Z(41), P(40) => 
        Z(40), P(39) => Z(39), P(38) => Z(38), P(37) => Z(37), 
        P(36) => Z(36), P(35) => Z(35), P(34) => Z(34), P(33) => 
        Z(33), P(32) => Z(32), P(31) => Z(31), P(30) => Z(30), 
        P(29) => Z(29), P(28) => Z(28), P(27) => Z(27), P(26) => 
        Z(26), P(25) => Z(25), P(24) => Z(24), P(23) => Z(23), 
        P(22) => Z(22), P(21) => Z(21), P(20) => Z(20), P(19) => 
        Z(19), P(18) => Z(18), P(17) => Z(17), P(16) => Z(16), 
        P(15) => Z(15), P(14) => Z(14), P(13) => Z(13), P(12) => 
        Z(12), P(11) => Z(11), P(10) => Z(10), P(9) => Z(9), P(8)
         => Z(8), P(7) => Z(7), P(6) => Z(6), P(5) => Z(5), P(4)
         => Z(4), P(3) => Z(3), P(2) => Z(2), P(1) => Z(1), P(0)
         => Z(0), OVFL_CARRYOUT => X);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity dotp_multadd is

    port( Z        : out   std_logic_vector(43 downto 0);
          INPUTD_c : in    std_logic_vector(42 downto 0);
          INPUTA_c : in    std_logic_vector(17 downto 0);
          INPUTB_c : in    std_logic_vector(17 downto 0);
          INPUTC_c : in    std_logic_vector(42 downto 0);
          X        : out   std_logic;
          clk_c    : in    std_logic
        );

end dotp_multadd;

architecture DEF_ARCH of dotp_multadd is 

  component dotp_multadd_dotp_multadd_0_HARD_MULT_ADDSUB
    port( Z        : out   std_logic_vector(43 downto 0);
          INPUTD_c : in    std_logic_vector(42 downto 0) := (others => 'U');
          INPUTA_c : in    std_logic_vector(17 downto 0) := (others => 'U');
          INPUTB_c : in    std_logic_vector(17 downto 0) := (others => 'U');
          INPUTC_c : in    std_logic_vector(42 downto 0) := (others => 'U');
          X        : out   std_logic;
          clk_c    : in    std_logic := 'U'
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

    for all : dotp_multadd_dotp_multadd_0_HARD_MULT_ADDSUB
	Use entity work.
        dotp_multadd_dotp_multadd_0_HARD_MULT_ADDSUB(DEF_ARCH);
begin 


    dotp_multadd_0 : dotp_multadd_dotp_multadd_0_HARD_MULT_ADDSUB
      port map(Z(43) => Z(43), Z(42) => Z(42), Z(41) => Z(41), 
        Z(40) => Z(40), Z(39) => Z(39), Z(38) => Z(38), Z(37) => 
        Z(37), Z(36) => Z(36), Z(35) => Z(35), Z(34) => Z(34), 
        Z(33) => Z(33), Z(32) => Z(32), Z(31) => Z(31), Z(30) => 
        Z(30), Z(29) => Z(29), Z(28) => Z(28), Z(27) => Z(27), 
        Z(26) => Z(26), Z(25) => Z(25), Z(24) => Z(24), Z(23) => 
        Z(23), Z(22) => Z(22), Z(21) => Z(21), Z(20) => Z(20), 
        Z(19) => Z(19), Z(18) => Z(18), Z(17) => Z(17), Z(16) => 
        Z(16), Z(15) => Z(15), Z(14) => Z(14), Z(13) => Z(13), 
        Z(12) => Z(12), Z(11) => Z(11), Z(10) => Z(10), Z(9) => 
        Z(9), Z(8) => Z(8), Z(7) => Z(7), Z(6) => Z(6), Z(5) => 
        Z(5), Z(4) => Z(4), Z(3) => Z(3), Z(2) => Z(2), Z(1) => 
        Z(1), Z(0) => Z(0), INPUTD_c(42) => INPUTD_c(42), 
        INPUTD_c(41) => INPUTD_c(41), INPUTD_c(40) => 
        INPUTD_c(40), INPUTD_c(39) => INPUTD_c(39), INPUTD_c(38)
         => INPUTD_c(38), INPUTD_c(37) => INPUTD_c(37), 
        INPUTD_c(36) => INPUTD_c(36), INPUTD_c(35) => 
        INPUTD_c(35), INPUTD_c(34) => INPUTD_c(34), INPUTD_c(33)
         => INPUTD_c(33), INPUTD_c(32) => INPUTD_c(32), 
        INPUTD_c(31) => INPUTD_c(31), INPUTD_c(30) => 
        INPUTD_c(30), INPUTD_c(29) => INPUTD_c(29), INPUTD_c(28)
         => INPUTD_c(28), INPUTD_c(27) => INPUTD_c(27), 
        INPUTD_c(26) => INPUTD_c(26), INPUTD_c(25) => 
        INPUTD_c(25), INPUTD_c(24) => INPUTD_c(24), INPUTD_c(23)
         => INPUTD_c(23), INPUTD_c(22) => INPUTD_c(22), 
        INPUTD_c(21) => INPUTD_c(21), INPUTD_c(20) => 
        INPUTD_c(20), INPUTD_c(19) => INPUTD_c(19), INPUTD_c(18)
         => INPUTD_c(18), INPUTD_c(17) => INPUTD_c(17), 
        INPUTD_c(16) => INPUTD_c(16), INPUTD_c(15) => 
        INPUTD_c(15), INPUTD_c(14) => INPUTD_c(14), INPUTD_c(13)
         => INPUTD_c(13), INPUTD_c(12) => INPUTD_c(12), 
        INPUTD_c(11) => INPUTD_c(11), INPUTD_c(10) => 
        INPUTD_c(10), INPUTD_c(9) => INPUTD_c(9), INPUTD_c(8) => 
        INPUTD_c(8), INPUTD_c(7) => INPUTD_c(7), INPUTD_c(6) => 
        INPUTD_c(6), INPUTD_c(5) => INPUTD_c(5), INPUTD_c(4) => 
        INPUTD_c(4), INPUTD_c(3) => INPUTD_c(3), INPUTD_c(2) => 
        INPUTD_c(2), INPUTD_c(1) => INPUTD_c(1), INPUTD_c(0) => 
        INPUTD_c(0), INPUTA_c(17) => INPUTA_c(17), INPUTA_c(16)
         => INPUTA_c(16), INPUTA_c(15) => INPUTA_c(15), 
        INPUTA_c(14) => INPUTA_c(14), INPUTA_c(13) => 
        INPUTA_c(13), INPUTA_c(12) => INPUTA_c(12), INPUTA_c(11)
         => INPUTA_c(11), INPUTA_c(10) => INPUTA_c(10), 
        INPUTA_c(9) => INPUTA_c(9), INPUTA_c(8) => INPUTA_c(8), 
        INPUTA_c(7) => INPUTA_c(7), INPUTA_c(6) => INPUTA_c(6), 
        INPUTA_c(5) => INPUTA_c(5), INPUTA_c(4) => INPUTA_c(4), 
        INPUTA_c(3) => INPUTA_c(3), INPUTA_c(2) => INPUTA_c(2), 
        INPUTA_c(1) => INPUTA_c(1), INPUTA_c(0) => INPUTA_c(0), 
        INPUTB_c(17) => INPUTB_c(17), INPUTB_c(16) => 
        INPUTB_c(16), INPUTB_c(15) => INPUTB_c(15), INPUTB_c(14)
         => INPUTB_c(14), INPUTB_c(13) => INPUTB_c(13), 
        INPUTB_c(12) => INPUTB_c(12), INPUTB_c(11) => 
        INPUTB_c(11), INPUTB_c(10) => INPUTB_c(10), INPUTB_c(9)
         => INPUTB_c(9), INPUTB_c(8) => INPUTB_c(8), INPUTB_c(7)
         => INPUTB_c(7), INPUTB_c(6) => INPUTB_c(6), INPUTB_c(5)
         => INPUTB_c(5), INPUTB_c(4) => INPUTB_c(4), INPUTB_c(3)
         => INPUTB_c(3), INPUTB_c(2) => INPUTB_c(2), INPUTB_c(1)
         => INPUTB_c(1), INPUTB_c(0) => INPUTB_c(0), INPUTC_c(42)
         => INPUTC_c(42), INPUTC_c(41) => INPUTC_c(41), 
        INPUTC_c(40) => INPUTC_c(40), INPUTC_c(39) => 
        INPUTC_c(39), INPUTC_c(38) => INPUTC_c(38), INPUTC_c(37)
         => INPUTC_c(37), INPUTC_c(36) => INPUTC_c(36), 
        INPUTC_c(35) => INPUTC_c(35), INPUTC_c(34) => 
        INPUTC_c(34), INPUTC_c(33) => INPUTC_c(33), INPUTC_c(32)
         => INPUTC_c(32), INPUTC_c(31) => INPUTC_c(31), 
        INPUTC_c(30) => INPUTC_c(30), INPUTC_c(29) => 
        INPUTC_c(29), INPUTC_c(28) => INPUTC_c(28), INPUTC_c(27)
         => INPUTC_c(27), INPUTC_c(26) => INPUTC_c(26), 
        INPUTC_c(25) => INPUTC_c(25), INPUTC_c(24) => 
        INPUTC_c(24), INPUTC_c(23) => INPUTC_c(23), INPUTC_c(22)
         => INPUTC_c(22), INPUTC_c(21) => INPUTC_c(21), 
        INPUTC_c(20) => INPUTC_c(20), INPUTC_c(19) => 
        INPUTC_c(19), INPUTC_c(18) => INPUTC_c(18), INPUTC_c(17)
         => INPUTC_c(17), INPUTC_c(16) => INPUTC_c(16), 
        INPUTC_c(15) => INPUTC_c(15), INPUTC_c(14) => 
        INPUTC_c(14), INPUTC_c(13) => INPUTC_c(13), INPUTC_c(12)
         => INPUTC_c(12), INPUTC_c(11) => INPUTC_c(11), 
        INPUTC_c(10) => INPUTC_c(10), INPUTC_c(9) => INPUTC_c(9), 
        INPUTC_c(8) => INPUTC_c(8), INPUTC_c(7) => INPUTC_c(7), 
        INPUTC_c(6) => INPUTC_c(6), INPUTC_c(5) => INPUTC_c(5), 
        INPUTC_c(4) => INPUTC_c(4), INPUTC_c(3) => INPUTC_c(3), 
        INPUTC_c(2) => INPUTC_c(2), INPUTC_c(1) => INPUTC_c(1), 
        INPUTC_c(0) => INPUTC_c(0), X => X, clk_c => clk_c);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Extended_adder_3_input is

    port( INPUTA    : in    std_logic_vector(17 downto 0);
          INPUTB    : in    std_logic_vector(17 downto 0);
          INPUTC    : in    std_logic_vector(51 downto 0);
          INPUTD    : in    std_logic_vector(51 downto 0);
          AddOutput : out   std_logic_vector(51 downto 0);
          clk       : in    std_logic;
          reset_n   : in    std_logic
        );

end Extended_adder_3_input;

architecture DEF_ARCH of Extended_adder_3_input is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component INBUF
    generic (IOSTD:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component OUTBUF
    generic (IOSTD:string := "");

    port( D   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component ARI1
    generic (INIT:std_logic_vector := x"0");

    port( A   : in    std_logic := 'U';
          B   : in    std_logic := 'U';
          C   : in    std_logic := 'U';
          D   : in    std_logic := 'U';
          FCI : in    std_logic := 'U';
          S   : out   std_logic;
          Y   : out   std_logic;
          FCO : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CLKINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component dotp_multadd
    port( Z        : out   std_logic_vector(43 downto 0);
          INPUTD_c : in    std_logic_vector(42 downto 0) := (others => 'U');
          INPUTA_c : in    std_logic_vector(17 downto 0) := (others => 'U');
          INPUTB_c : in    std_logic_vector(17 downto 0) := (others => 'U');
          INPUTC_c : in    std_logic_vector(42 downto 0) := (others => 'U');
          X        : out   std_logic;
          clk_c    : in    std_logic := 'U'
        );
  end component;

    signal \Z[0]\, \Z[1]\, \Z[2]\, \Z[3]\, \Z[4]\, \Z[5]\, 
        \Z[6]\, \Z[7]\, \Z[8]\, \Z[9]\, \Z[10]\, \Z[11]\, \Z[12]\, 
        \Z[13]\, \Z[14]\, \Z[15]\, \Z[16]\, \Z[17]\, \Z[18]\, 
        \Z[19]\, \Z[20]\, \Z[21]\, \Z[22]\, \Z[23]\, \Z[24]\, 
        \Z[25]\, \Z[26]\, \Z[27]\, \Z[28]\, \Z[29]\, \Z[30]\, 
        \Z[31]\, \Z[32]\, \Z[33]\, \Z[34]\, \Z[35]\, \Z[36]\, 
        \Z[37]\, \Z[38]\, \Z[39]\, \Z[40]\, \Z[41]\, \Z[42]\, 
        \Adderop_reg1[0]_net_1\, \Adderop_reg1[1]_net_1\, 
        \Adderop_reg1[2]_net_1\, \Adderop_reg1[3]_net_1\, 
        \Adderop_reg1[4]_net_1\, \Adderop_reg1[5]_net_1\, 
        \Adderop_reg1[6]_net_1\, \Adderop_reg1[7]_net_1\, 
        \Adderop_reg1[8]_net_1\, VCC_net_1, GND_net_1, X, \Z[43]\, 
        \INPUTC_reg0[0]_net_1\, \INPUTC_reg0[1]_net_1\, 
        \INPUTC_reg0[2]_net_1\, \INPUTC_reg0[3]_net_1\, 
        \INPUTC_reg0[4]_net_1\, \INPUTC_reg0[5]_net_1\, 
        \INPUTC_reg0[6]_net_1\, \INPUTC_reg0[7]_net_1\, 
        \INPUTC_reg0[8]_net_1\, \INPUTD_reg0[0]_net_1\, 
        \INPUTD_reg0[1]_net_1\, \INPUTD_reg0[2]_net_1\, 
        \INPUTD_reg0[3]_net_1\, \INPUTD_reg0[4]_net_1\, 
        \INPUTD_reg0[5]_net_1\, \INPUTD_reg0[6]_net_1\, 
        \INPUTD_reg0[7]_net_1\, \INPUTD_reg0[8]_net_1\, 
        \INPUTC_reg1[0]_net_1\, \INPUTC_reg1[1]_net_1\, 
        \INPUTC_reg1[2]_net_1\, \INPUTC_reg1[3]_net_1\, 
        \INPUTC_reg1[4]_net_1\, \INPUTC_reg1[5]_net_1\, 
        \INPUTC_reg1[6]_net_1\, \INPUTC_reg1[7]_net_1\, 
        \INPUTC_reg1[8]_net_1\, \INPUTD_reg1[0]_net_1\, 
        \INPUTD_reg1[1]_net_1\, \INPUTD_reg1[2]_net_1\, 
        \INPUTD_reg1[3]_net_1\, \INPUTD_reg1[4]_net_1\, 
        \INPUTD_reg1[5]_net_1\, \INPUTD_reg1[6]_net_1\, 
        \INPUTD_reg1[7]_net_1\, \INPUTD_reg1[8]_net_1\, \S\, 
        \Res_Upper_reg[0]_net_1\, \Res_Upper_reg[1]_net_1\, 
        \Res_Upper_reg[2]_net_1\, un2_adderop_reg_cry_1_S, 
        un2_adderop_reg_cry_2_S, un2_adderop_reg_cry_3_S, 
        un2_adderop_reg_cry_4_S, un2_adderop_reg_cry_5_S, 
        un2_adderop_reg_cry_6_S, un2_adderop_reg_cry_7_S, 
        un2_adderop_reg_s_8_S, \Adderop_reg[0]_net_1\, 
        \Adderop_reg[1]_net_1\, \Adderop_reg[2]_net_1\, 
        \Adderop_reg[3]_net_1\, \Adderop_reg[4]_net_1\, 
        \Adderop_reg[5]_net_1\, \Adderop_reg[6]_net_1\, 
        \Adderop_reg[7]_net_1\, \Adderop_reg[8]_net_1\, 
        un2_adderop_reg1_cry_1_S, un2_adderop_reg1_cry_2_S, 
        un2_adderop_reg1_cry_3_S, un2_adderop_reg1_cry_4_S, 
        un2_adderop_reg1_cry_5_S, un2_adderop_reg1_cry_6_S, 
        un2_adderop_reg1_cry_7_S, un2_adderop_reg1_s_8_S, clk_c, 
        reset_n_c, \INPUTA_c[0]\, \INPUTA_c[1]\, \INPUTA_c[2]\, 
        \INPUTA_c[3]\, \INPUTA_c[4]\, \INPUTA_c[5]\, 
        \INPUTA_c[6]\, \INPUTA_c[7]\, \INPUTA_c[8]\, 
        \INPUTA_c[9]\, \INPUTA_c[10]\, \INPUTA_c[11]\, 
        \INPUTA_c[12]\, \INPUTA_c[13]\, \INPUTA_c[14]\, 
        \INPUTA_c[15]\, \INPUTA_c[16]\, \INPUTA_c[17]\, 
        \INPUTB_c[0]\, \INPUTB_c[1]\, \INPUTB_c[2]\, 
        \INPUTB_c[3]\, \INPUTB_c[4]\, \INPUTB_c[5]\, 
        \INPUTB_c[6]\, \INPUTB_c[7]\, \INPUTB_c[8]\, 
        \INPUTB_c[9]\, \INPUTB_c[10]\, \INPUTB_c[11]\, 
        \INPUTB_c[12]\, \INPUTB_c[13]\, \INPUTB_c[14]\, 
        \INPUTB_c[15]\, \INPUTB_c[16]\, \INPUTB_c[17]\, 
        \INPUTC_c[0]\, \INPUTC_c[1]\, \INPUTC_c[2]\, 
        \INPUTC_c[3]\, \INPUTC_c[4]\, \INPUTC_c[5]\, 
        \INPUTC_c[6]\, \INPUTC_c[7]\, \INPUTC_c[8]\, 
        \INPUTC_c[9]\, \INPUTC_c[10]\, \INPUTC_c[11]\, 
        \INPUTC_c[12]\, \INPUTC_c[13]\, \INPUTC_c[14]\, 
        \INPUTC_c[15]\, \INPUTC_c[16]\, \INPUTC_c[17]\, 
        \INPUTC_c[18]\, \INPUTC_c[19]\, \INPUTC_c[20]\, 
        \INPUTC_c[21]\, \INPUTC_c[22]\, \INPUTC_c[23]\, 
        \INPUTC_c[24]\, \INPUTC_c[25]\, \INPUTC_c[26]\, 
        \INPUTC_c[27]\, \INPUTC_c[28]\, \INPUTC_c[29]\, 
        \INPUTC_c[30]\, \INPUTC_c[31]\, \INPUTC_c[32]\, 
        \INPUTC_c[33]\, \INPUTC_c[34]\, \INPUTC_c[35]\, 
        \INPUTC_c[36]\, \INPUTC_c[37]\, \INPUTC_c[38]\, 
        \INPUTC_c[39]\, \INPUTC_c[40]\, \INPUTC_c[41]\, 
        \INPUTC_c[42]\, \INPUTC_c[43]\, \INPUTC_c[44]\, 
        \INPUTC_c[45]\, \INPUTC_c[46]\, \INPUTC_c[47]\, 
        \INPUTC_c[48]\, \INPUTC_c[49]\, \INPUTC_c[50]\, 
        \INPUTC_c[51]\, \INPUTD_c[0]\, \INPUTD_c[1]\, 
        \INPUTD_c[2]\, \INPUTD_c[3]\, \INPUTD_c[4]\, 
        \INPUTD_c[5]\, \INPUTD_c[6]\, \INPUTD_c[7]\, 
        \INPUTD_c[8]\, \INPUTD_c[9]\, \INPUTD_c[10]\, 
        \INPUTD_c[11]\, \INPUTD_c[12]\, \INPUTD_c[13]\, 
        \INPUTD_c[14]\, \INPUTD_c[15]\, \INPUTD_c[16]\, 
        \INPUTD_c[17]\, \INPUTD_c[18]\, \INPUTD_c[19]\, 
        \INPUTD_c[20]\, \INPUTD_c[21]\, \INPUTD_c[22]\, 
        \INPUTD_c[23]\, \INPUTD_c[24]\, \INPUTD_c[25]\, 
        \INPUTD_c[26]\, \INPUTD_c[27]\, \INPUTD_c[28]\, 
        \INPUTD_c[29]\, \INPUTD_c[30]\, \INPUTD_c[31]\, 
        \INPUTD_c[32]\, \INPUTD_c[33]\, \INPUTD_c[34]\, 
        \INPUTD_c[35]\, \INPUTD_c[36]\, \INPUTD_c[37]\, 
        \INPUTD_c[38]\, \INPUTD_c[39]\, \INPUTD_c[40]\, 
        \INPUTD_c[41]\, \INPUTD_c[42]\, \INPUTD_c[43]\, 
        \INPUTD_c[44]\, \INPUTD_c[45]\, \INPUTD_c[46]\, 
        \INPUTD_c[47]\, \INPUTD_c[48]\, \INPUTD_c[49]\, 
        \INPUTD_c[50]\, \INPUTD_c[51]\, \un2_adderop_reg_cry_0\, 
        \un2_adderop_reg_cry_1\, \un2_adderop_reg_cry_2\, 
        \un2_adderop_reg_cry_3\, \un2_adderop_reg_cry_4\, 
        \un2_adderop_reg_cry_5\, \un2_adderop_reg_cry_6\, 
        \un2_adderop_reg_cry_7\, \un2_adderop_reg1_cry_0\, 
        \un2_adderop_reg1_cry_1\, \un2_adderop_reg1_cry_2\, 
        \un2_adderop_reg1_cry_3\, \un2_adderop_reg1_cry_4\, 
        \un2_adderop_reg1_cry_5\, \un2_adderop_reg1_cry_6\, 
        \un2_adderop_reg1_cry_7\, un2_adderop_reg_cry_0_Y, 
        un2_adderop_reg1_cry_0_Y, \reset_n_ibuf\, \clk_ibuf\
         : std_logic;

    for all : dotp_multadd
	Use entity work.dotp_multadd(DEF_ARCH);
begin 


    \INPUTC_reg1[2]\ : SLE
      port map(D => \INPUTC_reg0[2]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg1[2]_net_1\);
    
    \INPUTA_ibuf[2]\ : INBUF
      port map(PAD => INPUTA(2), Y => \INPUTA_c[2]\);
    
    \INPUTA_ibuf[6]\ : INBUF
      port map(PAD => INPUTA(6), Y => \INPUTA_c[6]\);
    
    \INPUTD_ibuf[4]\ : INBUF
      port map(PAD => INPUTD(4), Y => \INPUTD_c[4]\);
    
    \AddOutput_obuf[9]\ : OUTBUF
      port map(D => \Z[9]\, PAD => AddOutput(9));
    
    \INPUTC_ibuf[43]\ : INBUF
      port map(PAD => INPUTC(43), Y => \INPUTC_c[43]\);
    
    \INPUTD_reg1[4]\ : SLE
      port map(D => \INPUTD_reg0[4]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg1[4]_net_1\);
    
    \INPUTD_ibuf[7]\ : INBUF
      port map(PAD => INPUTD(7), Y => \INPUTD_c[7]\);
    
    \INPUTD_ibuf[19]\ : INBUF
      port map(PAD => INPUTD(19), Y => \INPUTD_c[19]\);
    
    \AddOutput_obuf[34]\ : OUTBUF
      port map(D => \Z[34]\, PAD => AddOutput(34));
    
    \INPUTD_ibuf[0]\ : INBUF
      port map(PAD => INPUTD(0), Y => \INPUTD_c[0]\);
    
    \INPUTC_ibuf[12]\ : INBUF
      port map(PAD => INPUTC(12), Y => \INPUTC_c[12]\);
    
    \INPUTD_ibuf[35]\ : INBUF
      port map(PAD => INPUTD(35), Y => \INPUTD_c[35]\);
    
    \INPUTC_reg0[4]\ : SLE
      port map(D => \INPUTC_c[47]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg0[4]_net_1\);
    
    \INPUTC_ibuf[20]\ : INBUF
      port map(PAD => INPUTC(20), Y => \INPUTC_c[20]\);
    
    \INPUTD_reg0[0]\ : SLE
      port map(D => \INPUTD_c[43]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg0[0]_net_1\);
    
    \INPUTC_reg0[1]\ : SLE
      port map(D => \INPUTC_c[44]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg0[1]_net_1\);
    
    \AddOutput_obuf[26]\ : OUTBUF
      port map(D => \Z[26]\, PAD => AddOutput(26));
    
    \INPUTD_reg1[3]\ : SLE
      port map(D => \INPUTD_reg0[3]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg1[3]_net_1\);
    
    \INPUTD_ibuf[10]\ : INBUF
      port map(PAD => INPUTD(10), Y => \INPUTD_c[10]\);
    
    \INPUTC_ibuf[19]\ : INBUF
      port map(PAD => INPUTC(19), Y => \INPUTC_c[19]\);
    
    \INPUTD_ibuf[43]\ : INBUF
      port map(PAD => INPUTD(43), Y => \INPUTD_c[43]\);
    
    \Adderop_reg[2]\ : SLE
      port map(D => un2_adderop_reg_cry_2_S, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg[2]_net_1\);
    
    \INPUTC_reg0[7]\ : SLE
      port map(D => \INPUTC_c[50]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg0[7]_net_1\);
    
    \INPUTB_ibuf[3]\ : INBUF
      port map(PAD => INPUTB(3), Y => \INPUTB_c[3]\);
    
    \INPUTD_ibuf[34]\ : INBUF
      port map(PAD => INPUTD(34), Y => \INPUTD_c[34]\);
    
    \INPUTD_ibuf[22]\ : INBUF
      port map(PAD => INPUTD(22), Y => \INPUTD_c[22]\);
    
    \INPUTD_reg1[8]\ : SLE
      port map(D => \INPUTD_reg0[8]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg1[8]_net_1\);
    
    un2_adderop_reg_s_8 : ARI1
      generic map(INIT => x"46600")

      port map(A => VCC_net_1, B => \INPUTC_reg1[8]_net_1\, C => 
        \INPUTD_reg1[8]_net_1\, D => GND_net_1, FCI => 
        \un2_adderop_reg_cry_7\, S => un2_adderop_reg_s_8_S, Y
         => OPEN, FCO => OPEN);
    
    un2_adderop_reg_cry_5 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \INPUTC_reg1[5]_net_1\, B => 
        \INPUTD_reg1[5]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => \un2_adderop_reg_cry_4\, S => 
        un2_adderop_reg_cry_5_S, Y => OPEN, FCO => 
        \un2_adderop_reg_cry_5\);
    
    \INPUTC_ibuf[28]\ : INBUF
      port map(PAD => INPUTC(28), Y => \INPUTC_c[28]\);
    
    \Adderop_reg1[7]\ : SLE
      port map(D => un2_adderop_reg1_cry_7_S, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg1[7]_net_1\);
    
    \INPUTD_ibuf[3]\ : INBUF
      port map(PAD => INPUTD(3), Y => \INPUTD_c[3]\);
    
    \INPUTC_ibuf[13]\ : INBUF
      port map(PAD => INPUTC(13), Y => \INPUTC_c[13]\);
    
    \INPUTC_ibuf[36]\ : INBUF
      port map(PAD => INPUTC(36), Y => \INPUTC_c[36]\);
    
    \INPUTD_ibuf[28]\ : INBUF
      port map(PAD => INPUTD(28), Y => \INPUTD_c[28]\);
    
    \INPUTA_ibuf[5]\ : INBUF
      port map(PAD => INPUTA(5), Y => \INPUTA_c[5]\);
    
    \AddOutput_obuf[3]\ : OUTBUF
      port map(D => \Z[3]\, PAD => AddOutput(3));
    
    un2_adderop_reg_cry_3 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \INPUTC_reg1[3]_net_1\, B => 
        \INPUTD_reg1[3]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => \un2_adderop_reg_cry_2\, S => 
        un2_adderop_reg_cry_3_S, Y => OPEN, FCO => 
        \un2_adderop_reg_cry_3\);
    
    \AddOutput_obuf[33]\ : OUTBUF
      port map(D => \Z[33]\, PAD => AddOutput(33));
    
    \INPUTC_ibuf[41]\ : INBUF
      port map(PAD => INPUTC(41), Y => \INPUTC_c[41]\);
    
    \AddOutput_obuf[50]\ : OUTBUF
      port map(D => \Adderop_reg1[7]_net_1\, PAD => AddOutput(50));
    
    un2_adderop_reg1_cry_3 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \Adderop_reg[3]_net_1\, B => 
        \Res_Upper_reg[2]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => \un2_adderop_reg1_cry_2\, S => 
        un2_adderop_reg1_cry_3_S, Y => OPEN, FCO => 
        \un2_adderop_reg1_cry_3\);
    
    \AddOutput_obuf[0]\ : OUTBUF
      port map(D => \Z[0]\, PAD => AddOutput(0));
    
    \Adderop_reg[1]\ : SLE
      port map(D => un2_adderop_reg_cry_1_S, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg[1]_net_1\);
    
    \INPUTD_reg1[5]\ : SLE
      port map(D => \INPUTD_reg0[5]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg1[5]_net_1\);
    
    \INPUTD_ibuf[13]\ : INBUF
      port map(PAD => INPUTD(13), Y => \INPUTD_c[13]\);
    
    \AddOutput_obuf[31]\ : OUTBUF
      port map(D => \Z[31]\, PAD => AddOutput(31));
    
    \Adderop_reg1[5]\ : SLE
      port map(D => un2_adderop_reg1_cry_5_S, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg1[5]_net_1\);
    
    \AddOutput_obuf[42]\ : OUTBUF
      port map(D => \Z[42]\, PAD => AddOutput(42));
    
    \INPUTD_reg0[3]\ : SLE
      port map(D => \INPUTD_c[46]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg0[3]_net_1\);
    
    \AddOutput_obuf[17]\ : OUTBUF
      port map(D => \Z[17]\, PAD => AddOutput(17));
    
    \AddOutput_obuf[40]\ : OUTBUF
      port map(D => \Z[40]\, PAD => AddOutput(40));
    
    \INPUTC_ibuf[40]\ : INBUF
      port map(PAD => INPUTC(40), Y => \INPUTC_c[40]\);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    \INPUTC_reg0[6]\ : SLE
      port map(D => \INPUTC_c[49]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg0[6]_net_1\);
    
    \INPUTB_ibuf[9]\ : INBUF
      port map(PAD => INPUTB(9), Y => \INPUTB_c[9]\);
    
    \INPUTA_ibuf[15]\ : INBUF
      port map(PAD => INPUTA(15), Y => \INPUTA_c[15]\);
    
    \AddOutput_obuf[48]\ : OUTBUF
      port map(D => \Adderop_reg1[5]_net_1\, PAD => AddOutput(48));
    
    \AddOutput_obuf[15]\ : OUTBUF
      port map(D => \Z[15]\, PAD => AddOutput(15));
    
    reset_n_ibuf : INBUF
      port map(PAD => reset_n, Y => \reset_n_ibuf\);
    
    \INPUTC_ibuf[34]\ : INBUF
      port map(PAD => INPUTC(34), Y => \INPUTC_c[34]\);
    
    \INPUTA_ibuf[11]\ : INBUF
      port map(PAD => INPUTA(11), Y => \INPUTA_c[11]\);
    
    \INPUTD_ibuf[27]\ : INBUF
      port map(PAD => INPUTD(27), Y => \INPUTD_c[27]\);
    
    un2_adderop_reg_cry_1 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \INPUTC_reg1[1]_net_1\, B => 
        \INPUTD_reg1[1]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => \un2_adderop_reg_cry_0\, S => 
        un2_adderop_reg_cry_1_S, Y => OPEN, FCO => 
        \un2_adderop_reg_cry_1\);
    
    \INPUTC_ibuf[11]\ : INBUF
      port map(PAD => INPUTC(11), Y => \INPUTC_c[11]\);
    
    \INPUTA_ibuf[1]\ : INBUF
      port map(PAD => INPUTA(1), Y => \INPUTA_c[1]\);
    
    \INPUTD_ibuf[9]\ : INBUF
      port map(PAD => INPUTD(9), Y => \INPUTD_c[9]\);
    
    \INPUTD_ibuf[42]\ : INBUF
      port map(PAD => INPUTD(42), Y => \INPUTD_c[42]\);
    
    \INPUTD_ibuf[36]\ : INBUF
      port map(PAD => INPUTD(36), Y => \INPUTD_c[36]\);
    
    \INPUTC_ibuf[37]\ : INBUF
      port map(PAD => INPUTC(37), Y => \INPUTC_c[37]\);
    
    \INPUTC_ibuf[48]\ : INBUF
      port map(PAD => INPUTC(48), Y => \INPUTC_c[48]\);
    
    \INPUTD_ibuf[48]\ : INBUF
      port map(PAD => INPUTD(48), Y => \INPUTD_c[48]\);
    
    S : CFG2
      generic map(INIT => x"8")

      port map(A => X, B => \Z[43]\, Y => \S\);
    
    \INPUTC_ibuf[25]\ : INBUF
      port map(PAD => INPUTC(25), Y => \INPUTC_c[25]\);
    
    \INPUTD_reg1[7]\ : SLE
      port map(D => \INPUTD_reg0[7]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg1[7]_net_1\);
    
    \INPUTC_reg1[1]\ : SLE
      port map(D => \INPUTC_reg0[1]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg1[1]_net_1\);
    
    \INPUTB_ibuf[15]\ : INBUF
      port map(PAD => INPUTB(15), Y => \INPUTB_c[15]\);
    
    \AddOutput_obuf[27]\ : OUTBUF
      port map(D => \Z[27]\, PAD => AddOutput(27));
    
    \Adderop_reg1[3]\ : SLE
      port map(D => un2_adderop_reg1_cry_3_S, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg1[3]_net_1\);
    
    \INPUTC_reg0[5]\ : SLE
      port map(D => \INPUTC_c[48]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg0[5]_net_1\);
    
    \INPUTC_ibuf[4]\ : INBUF
      port map(PAD => INPUTC(4), Y => \INPUTC_c[4]\);
    
    \INPUTC_ibuf[10]\ : INBUF
      port map(PAD => INPUTC(10), Y => \INPUTC_c[10]\);
    
    \INPUTC_ibuf[7]\ : INBUF
      port map(PAD => INPUTC(7), Y => \INPUTC_c[7]\);
    
    \AddOutput_obuf[49]\ : OUTBUF
      port map(D => \Adderop_reg1[6]_net_1\, PAD => AddOutput(49));
    
    \INPUTC_ibuf[0]\ : INBUF
      port map(PAD => INPUTC(0), Y => \INPUTC_c[0]\);
    
    \AddOutput_obuf[25]\ : OUTBUF
      port map(D => \Z[25]\, PAD => AddOutput(25));
    
    \Adderop_reg1[2]\ : SLE
      port map(D => un2_adderop_reg1_cry_2_S, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg1[2]_net_1\);
    
    \INPUTB_ibuf[2]\ : INBUF
      port map(PAD => INPUTB(2), Y => \INPUTB_c[2]\);
    
    \INPUTB_ibuf[6]\ : INBUF
      port map(PAD => INPUTB(6), Y => \INPUTB_c[6]\);
    
    \INPUTB_ibuf[14]\ : INBUF
      port map(PAD => INPUTB(14), Y => \INPUTB_c[14]\);
    
    \INPUTD_ibuf[12]\ : INBUF
      port map(PAD => INPUTD(12), Y => \INPUTD_c[12]\);
    
    \INPUTC_reg1[0]\ : SLE
      port map(D => \INPUTC_reg0[0]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg1[0]_net_1\);
    
    \AddOutput_obuf[6]\ : OUTBUF
      port map(D => \Z[6]\, PAD => AddOutput(6));
    
    \INPUTC_ibuf[18]\ : INBUF
      port map(PAD => INPUTC(18), Y => \INPUTC_c[18]\);
    
    \INPUTD_ibuf[31]\ : INBUF
      port map(PAD => INPUTD(31), Y => \INPUTD_c[31]\);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \INPUTD_ibuf[2]\ : INBUF
      port map(PAD => INPUTD(2), Y => \INPUTD_c[2]\);
    
    \INPUTD_ibuf[6]\ : INBUF
      port map(PAD => INPUTD(6), Y => \INPUTD_c[6]\);
    
    \INPUTD_ibuf[18]\ : INBUF
      port map(PAD => INPUTD(18), Y => \INPUTD_c[18]\);
    
    \AddOutput_obuf[14]\ : OUTBUF
      port map(D => \Z[14]\, PAD => AddOutput(14));
    
    \INPUTA_ibuf[8]\ : INBUF
      port map(PAD => INPUTA(8), Y => \INPUTA_c[8]\);
    
    \INPUTD_ibuf[47]\ : INBUF
      port map(PAD => INPUTD(47), Y => \INPUTD_c[47]\);
    
    \AddOutput_obuf[32]\ : OUTBUF
      port map(D => \Z[32]\, PAD => AddOutput(32));
    
    \INPUTD_reg0[2]\ : SLE
      port map(D => \INPUTD_c[45]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg0[2]_net_1\);
    
    \INPUTC_ibuf[3]\ : INBUF
      port map(PAD => INPUTC(3), Y => \INPUTC_c[3]\);
    
    \AddOutput_obuf[8]\ : OUTBUF
      port map(D => \Z[8]\, PAD => AddOutput(8));
    
    \AddOutput_obuf[30]\ : OUTBUF
      port map(D => \Z[30]\, PAD => AddOutput(30));
    
    un2_adderop_reg_cry_4 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \INPUTC_reg1[4]_net_1\, B => 
        \INPUTD_reg1[4]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => \un2_adderop_reg_cry_3\, S => 
        un2_adderop_reg_cry_4_S, Y => OPEN, FCO => 
        \un2_adderop_reg_cry_4\);
    
    \INPUTD_ibuf[25]\ : INBUF
      port map(PAD => INPUTD(25), Y => \INPUTD_c[25]\);
    
    \INPUTD_reg0[8]\ : SLE
      port map(D => \INPUTD_c[51]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg0[8]_net_1\);
    
    \INPUTD_ibuf[39]\ : INBUF
      port map(PAD => INPUTD(39), Y => \INPUTD_c[39]\);
    
    \AddOutput_obuf[46]\ : OUTBUF
      port map(D => \Adderop_reg1[3]_net_1\, PAD => AddOutput(46));
    
    reset_n_ibuf_RNILECB : CLKINT
      port map(A => \reset_n_ibuf\, Y => reset_n_c);
    
    \INPUTC_ibuf[32]\ : INBUF
      port map(PAD => INPUTC(32), Y => \INPUTC_c[32]\);
    
    \INPUTA_ibuf[13]\ : INBUF
      port map(PAD => INPUTA(13), Y => \INPUTA_c[13]\);
    
    \AddOutput_obuf[38]\ : OUTBUF
      port map(D => \Z[38]\, PAD => AddOutput(38));
    
    \INPUTD_reg1[2]\ : SLE
      port map(D => \INPUTD_reg0[2]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg1[2]_net_1\);
    
    \Adderop_reg1[4]\ : SLE
      port map(D => un2_adderop_reg1_cry_4_S, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg1[4]_net_1\);
    
    un2_adderop_reg_cry_6 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \INPUTC_reg1[6]_net_1\, B => 
        \INPUTD_reg1[6]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => \un2_adderop_reg_cry_5\, S => 
        un2_adderop_reg_cry_6_S, Y => OPEN, FCO => 
        \un2_adderop_reg_cry_6\);
    
    \INPUTC_ibuf[45]\ : INBUF
      port map(PAD => INPUTC(45), Y => \INPUTC_c[45]\);
    
    \INPUTB_ibuf[5]\ : INBUF
      port map(PAD => INPUTB(5), Y => \INPUTB_c[5]\);
    
    un2_adderop_reg1_cry_7 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \Adderop_reg[7]_net_1\, B => 
        \Res_Upper_reg[2]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => \un2_adderop_reg1_cry_6\, S => 
        un2_adderop_reg1_cry_7_S, Y => OPEN, FCO => 
        \un2_adderop_reg1_cry_7\);
    
    \INPUTD_ibuf[24]\ : INBUF
      port map(PAD => INPUTD(24), Y => \INPUTD_c[24]\);
    
    \INPUTD_ibuf[30]\ : INBUF
      port map(PAD => INPUTD(30), Y => \INPUTD_c[30]\);
    
    \INPUTC_reg1[6]\ : SLE
      port map(D => \INPUTC_reg0[6]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg1[6]_net_1\);
    
    \INPUTC_ibuf[39]\ : INBUF
      port map(PAD => INPUTC(39), Y => \INPUTC_c[39]\);
    
    \Adderop_reg1[1]\ : SLE
      port map(D => un2_adderop_reg1_cry_1_S, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg1[1]_net_1\);
    
    \INPUTD_reg0[4]\ : SLE
      port map(D => \INPUTD_c[47]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg0[4]_net_1\);
    
    \AddOutput_obuf[24]\ : OUTBUF
      port map(D => \Z[24]\, PAD => AddOutput(24));
    
    \INPUTD_ibuf[5]\ : INBUF
      port map(PAD => INPUTD(5), Y => \INPUTD_c[5]\);
    
    clk_ibuf : INBUF
      port map(PAD => clk, Y => \clk_ibuf\);
    
    un2_adderop_reg1_s_8 : ARI1
      generic map(INIT => x"46600")

      port map(A => VCC_net_1, B => \Adderop_reg[8]_net_1\, C => 
        \Res_Upper_reg[2]_net_1\, D => GND_net_1, FCI => 
        \un2_adderop_reg1_cry_7\, S => un2_adderop_reg1_s_8_S, Y
         => OPEN, FCO => OPEN);
    
    \INPUTD_reg0[1]\ : SLE
      port map(D => \INPUTD_c[44]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg0[1]_net_1\);
    
    \AddOutput_obuf[13]\ : OUTBUF
      port map(D => \Z[13]\, PAD => AddOutput(13));
    
    \INPUTD_ibuf[17]\ : INBUF
      port map(PAD => INPUTD(17), Y => \INPUTD_c[17]\);
    
    \INPUTC_ibuf[26]\ : INBUF
      port map(PAD => INPUTC(26), Y => \INPUTC_c[26]\);
    
    \INPUTB_ibuf[10]\ : INBUF
      port map(PAD => INPUTB(10), Y => \INPUTB_c[10]\);
    
    \Adderop_reg1[0]\ : SLE
      port map(D => un2_adderop_reg1_cry_0_Y, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg1[0]_net_1\);
    
    \INPUTD_reg0[7]\ : SLE
      port map(D => \INPUTD_c[50]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg0[7]_net_1\);
    
    \AddOutput_obuf[5]\ : OUTBUF
      port map(D => \Z[5]\, PAD => AddOutput(5));
    
    \INPUTC_ibuf[33]\ : INBUF
      port map(PAD => INPUTC(33), Y => \INPUTC_c[33]\);
    
    \AddOutput_obuf[11]\ : OUTBUF
      port map(D => \Z[11]\, PAD => AddOutput(11));
    
    \AddOutput_obuf[39]\ : OUTBUF
      port map(D => \Z[39]\, PAD => AddOutput(39));
    
    \INPUTA_ibuf[14]\ : INBUF
      port map(PAD => INPUTA(14), Y => \INPUTA_c[14]\);
    
    \INPUTC_ibuf[9]\ : INBUF
      port map(PAD => INPUTC(9), Y => \INPUTC_c[9]\);
    
    \Adderop_reg1[6]\ : SLE
      port map(D => un2_adderop_reg1_cry_6_S, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg1[6]_net_1\);
    
    \INPUTC_ibuf[15]\ : INBUF
      port map(PAD => INPUTC(15), Y => \INPUTC_c[15]\);
    
    \Adderop_reg[7]\ : SLE
      port map(D => un2_adderop_reg_cry_7_S, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg[7]_net_1\);
    
    \AddOutput_obuf[4]\ : OUTBUF
      port map(D => \Z[4]\, PAD => AddOutput(4));
    
    un2_adderop_reg1_cry_5 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \Adderop_reg[5]_net_1\, B => 
        \Res_Upper_reg[2]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => \un2_adderop_reg1_cry_4\, S => 
        un2_adderop_reg1_cry_5_S, Y => OPEN, FCO => 
        \un2_adderop_reg1_cry_5\);
    
    \INPUTD_ibuf[51]\ : INBUF
      port map(PAD => INPUTD(51), Y => \INPUTD_c[51]\);
    
    \INPUTB_ibuf[1]\ : INBUF
      port map(PAD => INPUTB(1), Y => \INPUTB_c[1]\);
    
    \AddOutput_obuf[1]\ : OUTBUF
      port map(D => \Z[1]\, PAD => AddOutput(1));
    
    \INPUTD_ibuf[33]\ : INBUF
      port map(PAD => INPUTD(33), Y => \INPUTD_c[33]\);
    
    \INPUTD_ibuf[45]\ : INBUF
      port map(PAD => INPUTD(45), Y => \INPUTD_c[45]\);
    
    un2_adderop_reg_cry_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \INPUTC_reg1[0]_net_1\, B => 
        \INPUTD_reg1[0]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => GND_net_1, S => OPEN, Y => un2_adderop_reg_cry_0_Y, 
        FCO => \un2_adderop_reg_cry_0\);
    
    \AddOutput_obuf[23]\ : OUTBUF
      port map(D => \Z[23]\, PAD => AddOutput(23));
    
    \INPUTD_ibuf[1]\ : INBUF
      port map(PAD => INPUTD(1), Y => \INPUTD_c[1]\);
    
    \INPUTC_ibuf[24]\ : INBUF
      port map(PAD => INPUTC(24), Y => \INPUTC_c[24]\);
    
    \AddOutput_obuf[2]\ : OUTBUF
      port map(D => \Z[2]\, PAD => AddOutput(2));
    
    \INPUTB_ibuf[13]\ : INBUF
      port map(PAD => INPUTB(13), Y => \INPUTB_c[13]\);
    
    un2_adderop_reg_cry_2 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \INPUTC_reg1[2]_net_1\, B => 
        \INPUTD_reg1[2]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => \un2_adderop_reg_cry_1\, S => 
        un2_adderop_reg_cry_2_S, Y => OPEN, FCO => 
        \un2_adderop_reg_cry_2\);
    
    \INPUTD_ibuf[44]\ : INBUF
      port map(PAD => INPUTD(44), Y => \INPUTD_c[44]\);
    
    \INPUTC_reg1[4]\ : SLE
      port map(D => \INPUTC_reg0[4]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg1[4]_net_1\);
    
    \AddOutput_obuf[21]\ : OUTBUF
      port map(D => \Z[21]\, PAD => AddOutput(21));
    
    un2_adderop_reg1_cry_1 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \Adderop_reg[1]_net_1\, B => 
        \Res_Upper_reg[1]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => \un2_adderop_reg1_cry_0\, S => 
        un2_adderop_reg1_cry_1_S, Y => OPEN, FCO => 
        \un2_adderop_reg1_cry_1\);
    
    \INPUTD_ibuf[26]\ : INBUF
      port map(PAD => INPUTD(26), Y => \INPUTD_c[26]\);
    
    \INPUTC_ibuf[27]\ : INBUF
      port map(PAD => INPUTC(27), Y => \INPUTC_c[27]\);
    
    \AddOutput_obuf[7]\ : OUTBUF
      port map(D => \Z[7]\, PAD => AddOutput(7));
    
    \AddOutput_obuf[36]\ : OUTBUF
      port map(D => \Z[36]\, PAD => AddOutput(36));
    
    \INPUTC_ibuf[31]\ : INBUF
      port map(PAD => INPUTC(31), Y => \INPUTC_c[31]\);
    
    \INPUTD_reg0[6]\ : SLE
      port map(D => \INPUTD_c[49]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg0[6]_net_1\);
    
    \INPUTA_ibuf[16]\ : INBUF
      port map(PAD => INPUTA(16), Y => \INPUTA_c[16]\);
    
    \Adderop_reg[6]\ : SLE
      port map(D => un2_adderop_reg_cry_6_S, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg[6]_net_1\);
    
    \INPUTC_ibuf[46]\ : INBUF
      port map(PAD => INPUTC(46), Y => \INPUTC_c[46]\);
    
    clk_ibuf_RNIVTI2 : CLKINT
      port map(A => \clk_ibuf\, Y => clk_c);
    
    \INPUTC_reg0[0]\ : SLE
      port map(D => \INPUTC_c[43]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg0[0]_net_1\);
    
    \INPUTC_ibuf[2]\ : INBUF
      port map(PAD => INPUTC(2), Y => \INPUTC_c[2]\);
    
    \INPUTC_ibuf[6]\ : INBUF
      port map(PAD => INPUTC(6), Y => \INPUTC_c[6]\);
    
    \INPUTC_reg1[3]\ : SLE
      port map(D => \INPUTC_reg0[3]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg1[3]_net_1\);
    
    \AddOutput_obuf[47]\ : OUTBUF
      port map(D => \Adderop_reg1[4]_net_1\, PAD => AddOutput(47));
    
    un2_adderop_reg1_cry_4 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \Adderop_reg[4]_net_1\, B => 
        \Res_Upper_reg[2]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => \un2_adderop_reg1_cry_3\, S => 
        un2_adderop_reg1_cry_4_S, Y => OPEN, FCO => 
        \un2_adderop_reg1_cry_4\);
    
    \INPUTD_ibuf[50]\ : INBUF
      port map(PAD => INPUTD(50), Y => \INPUTD_c[50]\);
    
    \INPUTD_ibuf[15]\ : INBUF
      port map(PAD => INPUTD(15), Y => \INPUTD_c[15]\);
    
    \Adderop_reg[8]\ : SLE
      port map(D => un2_adderop_reg_s_8_S, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg[8]_net_1\);
    
    \INPUTA_ibuf[17]\ : INBUF
      port map(PAD => INPUTA(17), Y => \INPUTA_c[17]\);
    
    \INPUTA_ibuf[4]\ : INBUF
      port map(PAD => INPUTA(4), Y => \INPUTA_c[4]\);
    
    un2_adderop_reg_cry_7 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \INPUTC_reg1[7]_net_1\, B => 
        \INPUTD_reg1[7]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => \un2_adderop_reg_cry_6\, S => 
        un2_adderop_reg_cry_7_S, Y => OPEN, FCO => 
        \un2_adderop_reg_cry_7\);
    
    \AddOutput_obuf[45]\ : OUTBUF
      port map(D => \Adderop_reg1[2]_net_1\, PAD => AddOutput(45));
    
    \INPUTA_ibuf[7]\ : INBUF
      port map(PAD => INPUTA(7), Y => \INPUTA_c[7]\);
    
    \INPUTC_reg1[8]\ : SLE
      port map(D => \INPUTC_reg0[8]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg1[8]_net_1\);
    
    \INPUTA_ibuf[0]\ : INBUF
      port map(PAD => INPUTA(0), Y => \INPUTA_c[0]\);
    
    \INPUTC_ibuf[30]\ : INBUF
      port map(PAD => INPUTC(30), Y => \INPUTC_c[30]\);
    
    \INPUTB_ibuf[8]\ : INBUF
      port map(PAD => INPUTB(8), Y => \INPUTB_c[8]\);
    
    \INPUTB_ibuf[16]\ : INBUF
      port map(PAD => INPUTB(16), Y => \INPUTB_c[16]\);
    
    \INPUTD_ibuf[14]\ : INBUF
      port map(PAD => INPUTD(14), Y => \INPUTD_c[14]\);
    
    \INPUTD_reg1[1]\ : SLE
      port map(D => \INPUTD_reg0[1]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg1[1]_net_1\);
    
    \INPUTD_reg0[5]\ : SLE
      port map(D => \INPUTD_c[48]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg0[5]_net_1\);
    
    \Adderop_reg[3]\ : SLE
      port map(D => un2_adderop_reg_cry_3_S, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg[3]_net_1\);
    
    \INPUTD_ibuf[21]\ : INBUF
      port map(PAD => INPUTD(21), Y => \INPUTD_c[21]\);
    
    \INPUTD_ibuf[8]\ : INBUF
      port map(PAD => INPUTD(8), Y => \INPUTD_c[8]\);
    
    \INPUTB_ibuf[12]\ : INBUF
      port map(PAD => INPUTB(12), Y => \INPUTB_c[12]\);
    
    \INPUTD_ibuf[32]\ : INBUF
      port map(PAD => INPUTD(32), Y => \INPUTD_c[32]\);
    
    \INPUTC_ibuf[16]\ : INBUF
      port map(PAD => INPUTC(16), Y => \INPUTC_c[16]\);
    
    \AddOutput_obuf[12]\ : OUTBUF
      port map(D => \Z[12]\, PAD => AddOutput(12));
    
    \Adderop_reg[5]\ : SLE
      port map(D => un2_adderop_reg_cry_5_S, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg[5]_net_1\);
    
    \INPUTC_reg1[5]\ : SLE
      port map(D => \INPUTC_reg0[5]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg1[5]_net_1\);
    
    \INPUTC_ibuf[44]\ : INBUF
      port map(PAD => INPUTC(44), Y => \INPUTC_c[44]\);
    
    \INPUTC_ibuf[38]\ : INBUF
      port map(PAD => INPUTC(38), Y => \INPUTC_c[38]\);
    
    \AddOutput_obuf[10]\ : OUTBUF
      port map(D => \Z[10]\, PAD => AddOutput(10));
    
    \Adderop_reg[4]\ : SLE
      port map(D => un2_adderop_reg_cry_4_S, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg[4]_net_1\);
    
    \INPUTC_ibuf[5]\ : INBUF
      port map(PAD => INPUTC(5), Y => \INPUTC_c[5]\);
    
    \INPUTD_ibuf[38]\ : INBUF
      port map(PAD => INPUTD(38), Y => \INPUTD_c[38]\);
    
    un2_adderop_reg1_cry_2 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \Adderop_reg[2]_net_1\, B => 
        \Res_Upper_reg[2]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => \un2_adderop_reg1_cry_1\, S => 
        un2_adderop_reg1_cry_2_S, Y => OPEN, FCO => 
        \un2_adderop_reg1_cry_2\);
    
    \INPUTA_ibuf[3]\ : INBUF
      port map(PAD => INPUTA(3), Y => \INPUTA_c[3]\);
    
    \INPUTA_ibuf[10]\ : INBUF
      port map(PAD => INPUTA(10), Y => \INPUTA_c[10]\);
    
    \AddOutput_obuf[18]\ : OUTBUF
      port map(D => \Z[18]\, PAD => AddOutput(18));
    
    \INPUTD_reg1[0]\ : SLE
      port map(D => \INPUTD_reg0[0]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg1[0]_net_1\);
    
    \INPUTD_ibuf[46]\ : INBUF
      port map(PAD => INPUTD(46), Y => \INPUTD_c[46]\);
    
    \INPUTC_ibuf[47]\ : INBUF
      port map(PAD => INPUTC(47), Y => \INPUTC_c[47]\);
    
    \INPUTB_ibuf[17]\ : INBUF
      port map(PAD => INPUTB(17), Y => \INPUTB_c[17]\);
    
    \INPUTC_reg0[3]\ : SLE
      port map(D => \INPUTC_c[46]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg0[3]_net_1\);
    
    \INPUTD_ibuf[29]\ : INBUF
      port map(PAD => INPUTD(29), Y => \INPUTD_c[29]\);
    
    un2_adderop_reg1_cry_6 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \Adderop_reg[6]_net_1\, B => 
        \Res_Upper_reg[2]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => \un2_adderop_reg1_cry_5\, S => 
        un2_adderop_reg1_cry_6_S, Y => OPEN, FCO => 
        \un2_adderop_reg1_cry_6\);
    
    \INPUTC_ibuf[22]\ : INBUF
      port map(PAD => INPUTC(22), Y => \INPUTC_c[22]\);
    
    \Res_Upper_reg[2]\ : SLE
      port map(D => \S\, CLK => clk_c, EN => VCC_net_1, ALn => 
        reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => 
        \Res_Upper_reg[2]_net_1\);
    
    \INPUTD_ibuf[20]\ : INBUF
      port map(PAD => INPUTD(20), Y => \INPUTD_c[20]\);
    
    \INPUTC_ibuf[51]\ : INBUF
      port map(PAD => INPUTC(51), Y => \INPUTC_c[51]\);
    
    \INPUTC_ibuf[29]\ : INBUF
      port map(PAD => INPUTC(29), Y => \INPUTC_c[29]\);
    
    U0 : dotp_multadd
      port map(Z(43) => \Z[43]\, Z(42) => \Z[42]\, Z(41) => 
        \Z[41]\, Z(40) => \Z[40]\, Z(39) => \Z[39]\, Z(38) => 
        \Z[38]\, Z(37) => \Z[37]\, Z(36) => \Z[36]\, Z(35) => 
        \Z[35]\, Z(34) => \Z[34]\, Z(33) => \Z[33]\, Z(32) => 
        \Z[32]\, Z(31) => \Z[31]\, Z(30) => \Z[30]\, Z(29) => 
        \Z[29]\, Z(28) => \Z[28]\, Z(27) => \Z[27]\, Z(26) => 
        \Z[26]\, Z(25) => \Z[25]\, Z(24) => \Z[24]\, Z(23) => 
        \Z[23]\, Z(22) => \Z[22]\, Z(21) => \Z[21]\, Z(20) => 
        \Z[20]\, Z(19) => \Z[19]\, Z(18) => \Z[18]\, Z(17) => 
        \Z[17]\, Z(16) => \Z[16]\, Z(15) => \Z[15]\, Z(14) => 
        \Z[14]\, Z(13) => \Z[13]\, Z(12) => \Z[12]\, Z(11) => 
        \Z[11]\, Z(10) => \Z[10]\, Z(9) => \Z[9]\, Z(8) => \Z[8]\, 
        Z(7) => \Z[7]\, Z(6) => \Z[6]\, Z(5) => \Z[5]\, Z(4) => 
        \Z[4]\, Z(3) => \Z[3]\, Z(2) => \Z[2]\, Z(1) => \Z[1]\, 
        Z(0) => \Z[0]\, INPUTD_c(42) => \INPUTD_c[42]\, 
        INPUTD_c(41) => \INPUTD_c[41]\, INPUTD_c(40) => 
        \INPUTD_c[40]\, INPUTD_c(39) => \INPUTD_c[39]\, 
        INPUTD_c(38) => \INPUTD_c[38]\, INPUTD_c(37) => 
        \INPUTD_c[37]\, INPUTD_c(36) => \INPUTD_c[36]\, 
        INPUTD_c(35) => \INPUTD_c[35]\, INPUTD_c(34) => 
        \INPUTD_c[34]\, INPUTD_c(33) => \INPUTD_c[33]\, 
        INPUTD_c(32) => \INPUTD_c[32]\, INPUTD_c(31) => 
        \INPUTD_c[31]\, INPUTD_c(30) => \INPUTD_c[30]\, 
        INPUTD_c(29) => \INPUTD_c[29]\, INPUTD_c(28) => 
        \INPUTD_c[28]\, INPUTD_c(27) => \INPUTD_c[27]\, 
        INPUTD_c(26) => \INPUTD_c[26]\, INPUTD_c(25) => 
        \INPUTD_c[25]\, INPUTD_c(24) => \INPUTD_c[24]\, 
        INPUTD_c(23) => \INPUTD_c[23]\, INPUTD_c(22) => 
        \INPUTD_c[22]\, INPUTD_c(21) => \INPUTD_c[21]\, 
        INPUTD_c(20) => \INPUTD_c[20]\, INPUTD_c(19) => 
        \INPUTD_c[19]\, INPUTD_c(18) => \INPUTD_c[18]\, 
        INPUTD_c(17) => \INPUTD_c[17]\, INPUTD_c(16) => 
        \INPUTD_c[16]\, INPUTD_c(15) => \INPUTD_c[15]\, 
        INPUTD_c(14) => \INPUTD_c[14]\, INPUTD_c(13) => 
        \INPUTD_c[13]\, INPUTD_c(12) => \INPUTD_c[12]\, 
        INPUTD_c(11) => \INPUTD_c[11]\, INPUTD_c(10) => 
        \INPUTD_c[10]\, INPUTD_c(9) => \INPUTD_c[9]\, INPUTD_c(8)
         => \INPUTD_c[8]\, INPUTD_c(7) => \INPUTD_c[7]\, 
        INPUTD_c(6) => \INPUTD_c[6]\, INPUTD_c(5) => 
        \INPUTD_c[5]\, INPUTD_c(4) => \INPUTD_c[4]\, INPUTD_c(3)
         => \INPUTD_c[3]\, INPUTD_c(2) => \INPUTD_c[2]\, 
        INPUTD_c(1) => \INPUTD_c[1]\, INPUTD_c(0) => 
        \INPUTD_c[0]\, INPUTA_c(17) => \INPUTA_c[17]\, 
        INPUTA_c(16) => \INPUTA_c[16]\, INPUTA_c(15) => 
        \INPUTA_c[15]\, INPUTA_c(14) => \INPUTA_c[14]\, 
        INPUTA_c(13) => \INPUTA_c[13]\, INPUTA_c(12) => 
        \INPUTA_c[12]\, INPUTA_c(11) => \INPUTA_c[11]\, 
        INPUTA_c(10) => \INPUTA_c[10]\, INPUTA_c(9) => 
        \INPUTA_c[9]\, INPUTA_c(8) => \INPUTA_c[8]\, INPUTA_c(7)
         => \INPUTA_c[7]\, INPUTA_c(6) => \INPUTA_c[6]\, 
        INPUTA_c(5) => \INPUTA_c[5]\, INPUTA_c(4) => 
        \INPUTA_c[4]\, INPUTA_c(3) => \INPUTA_c[3]\, INPUTA_c(2)
         => \INPUTA_c[2]\, INPUTA_c(1) => \INPUTA_c[1]\, 
        INPUTA_c(0) => \INPUTA_c[0]\, INPUTB_c(17) => 
        \INPUTB_c[17]\, INPUTB_c(16) => \INPUTB_c[16]\, 
        INPUTB_c(15) => \INPUTB_c[15]\, INPUTB_c(14) => 
        \INPUTB_c[14]\, INPUTB_c(13) => \INPUTB_c[13]\, 
        INPUTB_c(12) => \INPUTB_c[12]\, INPUTB_c(11) => 
        \INPUTB_c[11]\, INPUTB_c(10) => \INPUTB_c[10]\, 
        INPUTB_c(9) => \INPUTB_c[9]\, INPUTB_c(8) => 
        \INPUTB_c[8]\, INPUTB_c(7) => \INPUTB_c[7]\, INPUTB_c(6)
         => \INPUTB_c[6]\, INPUTB_c(5) => \INPUTB_c[5]\, 
        INPUTB_c(4) => \INPUTB_c[4]\, INPUTB_c(3) => 
        \INPUTB_c[3]\, INPUTB_c(2) => \INPUTB_c[2]\, INPUTB_c(1)
         => \INPUTB_c[1]\, INPUTB_c(0) => \INPUTB_c[0]\, 
        INPUTC_c(42) => \INPUTC_c[42]\, INPUTC_c(41) => 
        \INPUTC_c[41]\, INPUTC_c(40) => \INPUTC_c[40]\, 
        INPUTC_c(39) => \INPUTC_c[39]\, INPUTC_c(38) => 
        \INPUTC_c[38]\, INPUTC_c(37) => \INPUTC_c[37]\, 
        INPUTC_c(36) => \INPUTC_c[36]\, INPUTC_c(35) => 
        \INPUTC_c[35]\, INPUTC_c(34) => \INPUTC_c[34]\, 
        INPUTC_c(33) => \INPUTC_c[33]\, INPUTC_c(32) => 
        \INPUTC_c[32]\, INPUTC_c(31) => \INPUTC_c[31]\, 
        INPUTC_c(30) => \INPUTC_c[30]\, INPUTC_c(29) => 
        \INPUTC_c[29]\, INPUTC_c(28) => \INPUTC_c[28]\, 
        INPUTC_c(27) => \INPUTC_c[27]\, INPUTC_c(26) => 
        \INPUTC_c[26]\, INPUTC_c(25) => \INPUTC_c[25]\, 
        INPUTC_c(24) => \INPUTC_c[24]\, INPUTC_c(23) => 
        \INPUTC_c[23]\, INPUTC_c(22) => \INPUTC_c[22]\, 
        INPUTC_c(21) => \INPUTC_c[21]\, INPUTC_c(20) => 
        \INPUTC_c[20]\, INPUTC_c(19) => \INPUTC_c[19]\, 
        INPUTC_c(18) => \INPUTC_c[18]\, INPUTC_c(17) => 
        \INPUTC_c[17]\, INPUTC_c(16) => \INPUTC_c[16]\, 
        INPUTC_c(15) => \INPUTC_c[15]\, INPUTC_c(14) => 
        \INPUTC_c[14]\, INPUTC_c(13) => \INPUTC_c[13]\, 
        INPUTC_c(12) => \INPUTC_c[12]\, INPUTC_c(11) => 
        \INPUTC_c[11]\, INPUTC_c(10) => \INPUTC_c[10]\, 
        INPUTC_c(9) => \INPUTC_c[9]\, INPUTC_c(8) => 
        \INPUTC_c[8]\, INPUTC_c(7) => \INPUTC_c[7]\, INPUTC_c(6)
         => \INPUTC_c[6]\, INPUTC_c(5) => \INPUTC_c[5]\, 
        INPUTC_c(4) => \INPUTC_c[4]\, INPUTC_c(3) => 
        \INPUTC_c[3]\, INPUTC_c(2) => \INPUTC_c[2]\, INPUTC_c(1)
         => \INPUTC_c[1]\, INPUTC_c(0) => \INPUTC_c[0]\, X => X, 
        clk_c => clk_c);
    
    \AddOutput_obuf[44]\ : OUTBUF
      port map(D => \Adderop_reg1[1]_net_1\, PAD => AddOutput(44));
    
    \AddOutput_obuf[22]\ : OUTBUF
      port map(D => \Z[22]\, PAD => AddOutput(22));
    
    \INPUTC_ibuf[14]\ : INBUF
      port map(PAD => INPUTC(14), Y => \INPUTC_c[14]\);
    
    \AddOutput_obuf[20]\ : OUTBUF
      port map(D => \Z[20]\, PAD => AddOutput(20));
    
    \Res_Upper_reg[1]\ : SLE
      port map(D => X, CLK => clk_c, EN => VCC_net_1, ALn => 
        reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => 
        \Res_Upper_reg[1]_net_1\);
    
    \AddOutput_obuf[37]\ : OUTBUF
      port map(D => \Z[37]\, PAD => AddOutput(37));
    
    \AddOutput_obuf[19]\ : OUTBUF
      port map(D => \Z[19]\, PAD => AddOutput(19));
    
    \AddOutput_obuf[28]\ : OUTBUF
      port map(D => \Z[28]\, PAD => AddOutput(28));
    
    un2_adderop_reg1_cry_0 : ARI1
      generic map(INIT => x"555AA")

      port map(A => \Adderop_reg[0]_net_1\, B => 
        \Res_Upper_reg[0]_net_1\, C => GND_net_1, D => GND_net_1, 
        FCI => GND_net_1, S => OPEN, Y => 
        un2_adderop_reg1_cry_0_Y, FCO => \un2_adderop_reg1_cry_0\);
    
    \INPUTD_ibuf[16]\ : INBUF
      port map(PAD => INPUTD(16), Y => \INPUTD_c[16]\);
    
    \INPUTC_reg1[7]\ : SLE
      port map(D => \INPUTC_reg0[7]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg1[7]_net_1\);
    
    \INPUTC_ibuf[17]\ : INBUF
      port map(PAD => INPUTC(17), Y => \INPUTC_c[17]\);
    
    \INPUTC_ibuf[1]\ : INBUF
      port map(PAD => INPUTC(1), Y => \INPUTC_c[1]\);
    
    \Adderop_reg[0]\ : SLE
      port map(D => un2_adderop_reg_cry_0_Y, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg[0]_net_1\);
    
    \INPUTD_ibuf[37]\ : INBUF
      port map(PAD => INPUTD(37), Y => \INPUTD_c[37]\);
    
    \INPUTC_ibuf[23]\ : INBUF
      port map(PAD => INPUTC(23), Y => \INPUTC_c[23]\);
    
    \INPUTD_ibuf[41]\ : INBUF
      port map(PAD => INPUTD(41), Y => \INPUTD_c[41]\);
    
    \INPUTD_reg1[6]\ : SLE
      port map(D => \INPUTD_reg0[6]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTD_reg1[6]_net_1\);
    
    \AddOutput_obuf[35]\ : OUTBUF
      port map(D => \Z[35]\, PAD => AddOutput(35));
    
    \INPUTC_ibuf[50]\ : INBUF
      port map(PAD => INPUTC(50), Y => \INPUTC_c[50]\);
    
    \INPUTA_ibuf[9]\ : INBUF
      port map(PAD => INPUTA(9), Y => \INPUTA_c[9]\);
    
    \INPUTA_ibuf[12]\ : INBUF
      port map(PAD => INPUTA(12), Y => \INPUTA_c[12]\);
    
    \INPUTB_ibuf[11]\ : INBUF
      port map(PAD => INPUTB(11), Y => \INPUTB_c[11]\);
    
    \AddOutput_obuf[51]\ : OUTBUF
      port map(D => \Adderop_reg1[8]_net_1\, PAD => AddOutput(51));
    
    \INPUTC_ibuf[35]\ : INBUF
      port map(PAD => INPUTC(35), Y => \INPUTC_c[35]\);
    
    \Res_Upper_reg[0]\ : SLE
      port map(D => \Z[43]\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => 
        \Res_Upper_reg[0]_net_1\);
    
    \INPUTD_ibuf[23]\ : INBUF
      port map(PAD => INPUTD(23), Y => \INPUTD_c[23]\);
    
    \Adderop_reg1[8]\ : SLE
      port map(D => un2_adderop_reg1_s_8_S, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Adderop_reg1[8]_net_1\);
    
    \INPUTD_ibuf[49]\ : INBUF
      port map(PAD => INPUTD(49), Y => \INPUTD_c[49]\);
    
    \AddOutput_obuf[43]\ : OUTBUF
      port map(D => \Adderop_reg1[0]_net_1\, PAD => AddOutput(43));
    
    \INPUTC_ibuf[42]\ : INBUF
      port map(PAD => INPUTC(42), Y => \INPUTC_c[42]\);
    
    \AddOutput_obuf[29]\ : OUTBUF
      port map(D => \Z[29]\, PAD => AddOutput(29));
    
    \AddOutput_obuf[16]\ : OUTBUF
      port map(D => \Z[16]\, PAD => AddOutput(16));
    
    \AddOutput_obuf[41]\ : OUTBUF
      port map(D => \Z[41]\, PAD => AddOutput(41));
    
    \INPUTD_ibuf[11]\ : INBUF
      port map(PAD => INPUTD(11), Y => \INPUTD_c[11]\);
    
    \INPUTD_ibuf[40]\ : INBUF
      port map(PAD => INPUTD(40), Y => \INPUTD_c[40]\);
    
    \INPUTC_reg0[2]\ : SLE
      port map(D => \INPUTC_c[45]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg0[2]_net_1\);
    
    \INPUTC_ibuf[49]\ : INBUF
      port map(PAD => INPUTC(49), Y => \INPUTC_c[49]\);
    
    \INPUTB_ibuf[4]\ : INBUF
      port map(PAD => INPUTB(4), Y => \INPUTB_c[4]\);
    
    \INPUTC_ibuf[21]\ : INBUF
      port map(PAD => INPUTC(21), Y => \INPUTC_c[21]\);
    
    \INPUTC_reg0[8]\ : SLE
      port map(D => \INPUTC_c[51]\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \INPUTC_reg0[8]_net_1\);
    
    \INPUTB_ibuf[7]\ : INBUF
      port map(PAD => INPUTB(7), Y => \INPUTB_c[7]\);
    
    \INPUTB_ibuf[0]\ : INBUF
      port map(PAD => INPUTB(0), Y => \INPUTB_c[0]\);
    
    \INPUTC_ibuf[8]\ : INBUF
      port map(PAD => INPUTC(8), Y => \INPUTC_c[8]\);
    

end DEF_ARCH; 
