@N|Running in 64-bit mode
@N: CD720 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ns
@N:"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_3_input\hdl\Extended_adder_3_input.vhd":23:7:23:28|Top entity is set to Extended_adder_3_input.
@N: CD231 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vhd2008\std1164.vhd":913:16:913:17|Using onehot encoding for type mvl9plus ('U'="1000000000")
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_3_input\hdl\Extended_adder_3_input.vhd":23:7:23:28|Synthesizing work.extended_adder_3_input.extended_adder_3_input_arch 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_3_input\component\work\dotp_multadd\dotp_multadd.vhd":17:7:17:18|Synthesizing work.dotp_multadd.rtl 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_3_input\component\work\dotp_multadd\dotp_multadd_0\dotp_multadd_dotp_multadd_0_HARD_MULT_ADDSUB.vhd":8:7:8:50|Synthesizing work.dotp_multadd_dotp_multadd_0_hard_mult_addsub.def_arch 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":575:10:575:12|Synthesizing smartfusion2.vcc.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":569:10:569:12|Synthesizing smartfusion2.gnd.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.vhd":695:10:695:13|Synthesizing smartfusion2.macc.syn_black_box 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_3_input\component\work\dotp_multadd1\dotp_multadd1.vhd":17:7:17:19|Synthesizing work.dotp_multadd1.rtl 
@N: CD630 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_3_input\component\work\dotp_multadd1\dotp_multadd1_0\dotp_multadd1_dotp_multadd1_0_HARD_MULT_ADDSUB.vhd":8:7:8:52|Synthesizing work.dotp_multadd1_dotp_multadd1_0_hard_mult_addsub.def_arch 

