--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: Transpose_FIR.vhd
-- File history:Ver1.0
--    
--
-- Description: This Design illustrates the implementation of 16-Tap Transpose FIR 
--				
-- Targeted device: <Family::SmartFusion2> <Die::M2S050> <Package::896 FBGA>

--
--------------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use IEEE.numeric_std.all;

entity Transpose_FIR is

generic ( N : integer := 16 );

port (
    	Clk 	: in std_logic;
    	resetn	: in std_logic;
		Xn_in	: in std_logic_vector(17 downto 0);
		
		FIR_O	: out std_logic_vector(43 downto 0)	 
);
end Transpose_FIR;

architecture Transpose_FIR_arch of Transpose_FIR is
   


component multadd is
    -- Port list
    port(
        -- Inputs
        A0        : in  std_logic_vector(17 downto 0);
        A0_ACLR_N : in  std_logic;
        A0_EN     : in  std_logic;
        A0_SCLR_N : in  std_logic;
        B0        : in  std_logic_vector(17 downto 0);
        B0_ACLR_N : in  std_logic;
        B0_EN     : in  std_logic;
        B0_SCLR_N : in  std_logic;
        CDIN      : in  std_logic_vector(43 downto 0);
        CLK       : in  std_logic;
        P_ACLR_N  : in  std_logic;
        P_EN      : in  std_logic;
        P_SCLR_N  : in  std_logic;
        -- Outputs
        CDOUT     : out std_logic_vector(43 downto 0);
        P         : out std_logic_vector(43 downto 0)
        );
end component multadd;

-- signal, component etc. declarations

TYPE CDIN_ARRAY1 IS ARRAY (0 to N) OF std_logic_vector(43 DOWNTO 0);
TYPE Coef_ARRAY1 IS ARRAY (0 to N) OF std_logic_vector(17 DOWNTO 0);

signal CDIN : CDIN_ARRAY1;
signal P	: CDIN_ARRAY1;

signal Xreg : std_logic_vector(17 DOWNTO 0);
signal Coef : Coef_ARRAY1 := (	"000000000000000000",-->0

								"000000000000000101",-->  5				
								"000000000000000011",-->  3				
								"000000000000000111",-->  7				
								"111111111111111100",--> -4				
								"000000000000000001",-->  1				
								"111111111111111110",--> -2				
								"111111111111111111",--> -1				
								"000000000000000100",-->  4

								"000000000000000101",-->  5				
								"000000000000000011",-->  3				
								"000000000000000111",-->  7				
								"111111111111111100",--> -4				
								"000000000000000001",-->  1				
								"111111111111111110",--> -2				
								"111111111111111111",--> -1				
								"000000000000000100"
								
								);


begin

   
	process(clk, resetn)
	begin
		if (resetn = '0') then
			Xreg  <= (others => '0');  
		else
			if(rising_edge(clk))then
				Xreg	<= Xn_in;
			end if;
		end if;
	end process;
		

 U1: for i in 1 to N generate
		
	
			UUT_1: multadd 
			port map(
				-- Inputs
 					A0  		=> Xreg,
			  		A0_ACLR_N 	=> resetn,
        			A0_EN     	=> '1',
       				A0_SCLR_N 	=> '1',
        			B0        	=> Coef(N+1-i),
        			B0_ACLR_N 	=> resetn,
        			B0_EN     	=> '1',
        			B0_SCLR_N 	=> '1',
        			CDIN      	=> CDIN(i-1),
        			CLK         => Clk,
        			P_ACLR_N  	=> resetn,
        			P_EN      	=> '1',
        			P_SCLR_N  	=> '1',
       			 -- Outputs
        			CDOUT     	=> CDIN(i),
        			P         	=> P(i)
				);


 		end generate;

FIR_O <= P(N);
CDIN(0)<= (others => '0');



end Transpose_FIR_arch;