-- Version: v11.1 SP2 11.1.2.19

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Inp_RAM_Inp_RAM_0_URAM is

    port( inp_rddata     : out   std_logic_vector(17 downto 0);
          inp_rdaddr     : in    std_logic_vector(2 downto 0);
          inp_wraddr     : in    std_logic_vector(2 downto 0);
          inp_wrdata_dly : in    std_logic_vector(17 downto 0);
          clk_c          : in    std_logic;
          inp_coef_rden  : in    std_logic;
          Data_Valid_dly : in    std_logic
        );

end Inp_RAM_Inp_RAM_0_URAM;

architecture DEF_ARCH of Inp_RAM_Inp_RAM_0_URAM is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component RAM64x18
    generic (MEMORYFILE:string := "");

    port( A_DOUT        : out   std_logic_vector(17 downto 0);
          B_DOUT        : out   std_logic_vector(17 downto 0);
          BUSY          : out   std_logic;
          A_ADDR_CLK    : in    std_logic := 'U';
          A_DOUT_CLK    : in    std_logic := 'U';
          A_ADDR_SRST_N : in    std_logic := 'U';
          A_DOUT_SRST_N : in    std_logic := 'U';
          A_ADDR_ARST_N : in    std_logic := 'U';
          A_DOUT_ARST_N : in    std_logic := 'U';
          A_ADDR_EN     : in    std_logic := 'U';
          A_DOUT_EN     : in    std_logic := 'U';
          A_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          B_ADDR_CLK    : in    std_logic := 'U';
          B_DOUT_CLK    : in    std_logic := 'U';
          B_ADDR_SRST_N : in    std_logic := 'U';
          B_DOUT_SRST_N : in    std_logic := 'U';
          B_ADDR_ARST_N : in    std_logic := 'U';
          B_DOUT_ARST_N : in    std_logic := 'U';
          B_ADDR_EN     : in    std_logic := 'U';
          B_DOUT_EN     : in    std_logic := 'U';
          B_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          C_CLK         : in    std_logic := 'U';
          C_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          C_DIN         : in    std_logic_vector(17 downto 0) := (others => 'U');
          C_WEN         : in    std_logic := 'U';
          C_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_EN          : in    std_logic := 'U';
          A_ADDR_LAT    : in    std_logic := 'U';
          A_DOUT_LAT    : in    std_logic := 'U';
          A_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          B_EN          : in    std_logic := 'U';
          B_ADDR_LAT    : in    std_logic := 'U';
          B_DOUT_LAT    : in    std_logic := 'U';
          B_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          C_EN          : in    std_logic := 'U';
          C_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          SII_LOCK      : in    std_logic := 'U'
        );
  end component;

    signal VCC_net_1, GND_net_1 : std_logic;
    signal nc1, nc8, nc13, nc16, nc9, nc14, nc5, nc15, nc3, nc10, 
        nc7, nc17, nc4, nc12, nc2, nc18, nc6, nc11 : std_logic;

begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    Inp_RAM_Inp_RAM_0_URAM_R0C0 : RAM64x18
      generic map(MEMORYFILE => "Inp_RAM_Inp_RAM_0_URAM_R0C0.mem"
        )

      port map(A_DOUT(17) => inp_rddata(17), A_DOUT(16) => 
        inp_rddata(16), A_DOUT(15) => inp_rddata(15), A_DOUT(14)
         => inp_rddata(14), A_DOUT(13) => inp_rddata(13), 
        A_DOUT(12) => inp_rddata(12), A_DOUT(11) => 
        inp_rddata(11), A_DOUT(10) => inp_rddata(10), A_DOUT(9)
         => inp_rddata(9), A_DOUT(8) => inp_rddata(8), A_DOUT(7)
         => inp_rddata(7), A_DOUT(6) => inp_rddata(6), A_DOUT(5)
         => inp_rddata(5), A_DOUT(4) => inp_rddata(4), A_DOUT(3)
         => inp_rddata(3), A_DOUT(2) => inp_rddata(2), A_DOUT(1)
         => inp_rddata(1), A_DOUT(0) => inp_rddata(0), B_DOUT(17)
         => nc1, B_DOUT(16) => nc8, B_DOUT(15) => nc13, 
        B_DOUT(14) => nc16, B_DOUT(13) => nc9, B_DOUT(12) => nc14, 
        B_DOUT(11) => nc5, B_DOUT(10) => nc15, B_DOUT(9) => nc3, 
        B_DOUT(8) => nc10, B_DOUT(7) => nc7, B_DOUT(6) => nc17, 
        B_DOUT(5) => nc4, B_DOUT(4) => nc12, B_DOUT(3) => nc2, 
        B_DOUT(2) => nc18, B_DOUT(1) => nc6, B_DOUT(0) => nc11, 
        BUSY => OPEN, A_ADDR_CLK => clk_c, A_DOUT_CLK => clk_c, 
        A_ADDR_SRST_N => VCC_net_1, A_DOUT_SRST_N => VCC_net_1, 
        A_ADDR_ARST_N => VCC_net_1, A_DOUT_ARST_N => VCC_net_1, 
        A_ADDR_EN => VCC_net_1, A_DOUT_EN => VCC_net_1, A_BLK(1)
         => inp_coef_rden, A_BLK(0) => VCC_net_1, A_ADDR(9) => 
        GND_net_1, A_ADDR(8) => GND_net_1, A_ADDR(7) => GND_net_1, 
        A_ADDR(6) => inp_rdaddr(2), A_ADDR(5) => inp_rdaddr(1), 
        A_ADDR(4) => inp_rdaddr(0), A_ADDR(3) => GND_net_1, 
        A_ADDR(2) => GND_net_1, A_ADDR(1) => GND_net_1, A_ADDR(0)
         => GND_net_1, B_ADDR_CLK => VCC_net_1, B_DOUT_CLK => 
        clk_c, B_ADDR_SRST_N => VCC_net_1, B_DOUT_SRST_N => 
        VCC_net_1, B_ADDR_ARST_N => VCC_net_1, B_DOUT_ARST_N => 
        VCC_net_1, B_ADDR_EN => VCC_net_1, B_DOUT_EN => VCC_net_1, 
        B_BLK(1) => GND_net_1, B_BLK(0) => VCC_net_1, B_ADDR(9)
         => GND_net_1, B_ADDR(8) => GND_net_1, B_ADDR(7) => 
        GND_net_1, B_ADDR(6) => GND_net_1, B_ADDR(5) => GND_net_1, 
        B_ADDR(4) => GND_net_1, B_ADDR(3) => GND_net_1, B_ADDR(2)
         => GND_net_1, B_ADDR(1) => GND_net_1, B_ADDR(0) => 
        GND_net_1, C_CLK => clk_c, C_ADDR(9) => GND_net_1, 
        C_ADDR(8) => GND_net_1, C_ADDR(7) => GND_net_1, C_ADDR(6)
         => inp_wraddr(2), C_ADDR(5) => inp_wraddr(1), C_ADDR(4)
         => inp_wraddr(0), C_ADDR(3) => GND_net_1, C_ADDR(2) => 
        GND_net_1, C_ADDR(1) => GND_net_1, C_ADDR(0) => GND_net_1, 
        C_DIN(17) => inp_wrdata_dly(17), C_DIN(16) => 
        inp_wrdata_dly(16), C_DIN(15) => inp_wrdata_dly(15), 
        C_DIN(14) => inp_wrdata_dly(14), C_DIN(13) => 
        inp_wrdata_dly(13), C_DIN(12) => inp_wrdata_dly(12), 
        C_DIN(11) => inp_wrdata_dly(11), C_DIN(10) => 
        inp_wrdata_dly(10), C_DIN(9) => inp_wrdata_dly(9), 
        C_DIN(8) => inp_wrdata_dly(8), C_DIN(7) => 
        inp_wrdata_dly(7), C_DIN(6) => inp_wrdata_dly(6), 
        C_DIN(5) => inp_wrdata_dly(5), C_DIN(4) => 
        inp_wrdata_dly(4), C_DIN(3) => inp_wrdata_dly(3), 
        C_DIN(2) => inp_wrdata_dly(2), C_DIN(1) => 
        inp_wrdata_dly(1), C_DIN(0) => inp_wrdata_dly(0), C_WEN
         => VCC_net_1, C_BLK(1) => Data_Valid_dly, C_BLK(0) => 
        VCC_net_1, A_EN => VCC_net_1, A_ADDR_LAT => GND_net_1, 
        A_DOUT_LAT => GND_net_1, A_WIDTH(2) => VCC_net_1, 
        A_WIDTH(1) => GND_net_1, A_WIDTH(0) => GND_net_1, B_EN
         => VCC_net_1, B_ADDR_LAT => VCC_net_1, B_DOUT_LAT => 
        GND_net_1, B_WIDTH(2) => VCC_net_1, B_WIDTH(1) => 
        GND_net_1, B_WIDTH(0) => GND_net_1, C_EN => VCC_net_1, 
        C_WIDTH(2) => VCC_net_1, C_WIDTH(1) => GND_net_1, 
        C_WIDTH(0) => GND_net_1, SII_LOCK => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Inp_RAM is

    port( inp_rddata     : out   std_logic_vector(17 downto 0);
          inp_rdaddr     : in    std_logic_vector(2 downto 0);
          inp_wraddr     : in    std_logic_vector(2 downto 0);
          inp_wrdata_dly : in    std_logic_vector(17 downto 0);
          clk_c          : in    std_logic;
          inp_coef_rden  : in    std_logic;
          Data_Valid_dly : in    std_logic
        );

end Inp_RAM;

architecture DEF_ARCH of Inp_RAM is 

  component Inp_RAM_Inp_RAM_0_URAM
    port( inp_rddata     : out   std_logic_vector(17 downto 0);
          inp_rdaddr     : in    std_logic_vector(2 downto 0) := (others => 'U');
          inp_wraddr     : in    std_logic_vector(2 downto 0) := (others => 'U');
          inp_wrdata_dly : in    std_logic_vector(17 downto 0) := (others => 'U');
          clk_c          : in    std_logic := 'U';
          inp_coef_rden  : in    std_logic := 'U';
          Data_Valid_dly : in    std_logic := 'U'
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

    for all : Inp_RAM_Inp_RAM_0_URAM
	Use entity work.Inp_RAM_Inp_RAM_0_URAM(DEF_ARCH);
begin 


    Inp_RAM_0 : Inp_RAM_Inp_RAM_0_URAM
      port map(inp_rddata(17) => inp_rddata(17), inp_rddata(16)
         => inp_rddata(16), inp_rddata(15) => inp_rddata(15), 
        inp_rddata(14) => inp_rddata(14), inp_rddata(13) => 
        inp_rddata(13), inp_rddata(12) => inp_rddata(12), 
        inp_rddata(11) => inp_rddata(11), inp_rddata(10) => 
        inp_rddata(10), inp_rddata(9) => inp_rddata(9), 
        inp_rddata(8) => inp_rddata(8), inp_rddata(7) => 
        inp_rddata(7), inp_rddata(6) => inp_rddata(6), 
        inp_rddata(5) => inp_rddata(5), inp_rddata(4) => 
        inp_rddata(4), inp_rddata(3) => inp_rddata(3), 
        inp_rddata(2) => inp_rddata(2), inp_rddata(1) => 
        inp_rddata(1), inp_rddata(0) => inp_rddata(0), 
        inp_rdaddr(2) => inp_rdaddr(2), inp_rdaddr(1) => 
        inp_rdaddr(1), inp_rdaddr(0) => inp_rdaddr(0), 
        inp_wraddr(2) => inp_wraddr(2), inp_wraddr(1) => 
        inp_wraddr(1), inp_wraddr(0) => inp_wraddr(0), 
        inp_wrdata_dly(17) => inp_wrdata_dly(17), 
        inp_wrdata_dly(16) => inp_wrdata_dly(16), 
        inp_wrdata_dly(15) => inp_wrdata_dly(15), 
        inp_wrdata_dly(14) => inp_wrdata_dly(14), 
        inp_wrdata_dly(13) => inp_wrdata_dly(13), 
        inp_wrdata_dly(12) => inp_wrdata_dly(12), 
        inp_wrdata_dly(11) => inp_wrdata_dly(11), 
        inp_wrdata_dly(10) => inp_wrdata_dly(10), 
        inp_wrdata_dly(9) => inp_wrdata_dly(9), inp_wrdata_dly(8)
         => inp_wrdata_dly(8), inp_wrdata_dly(7) => 
        inp_wrdata_dly(7), inp_wrdata_dly(6) => inp_wrdata_dly(6), 
        inp_wrdata_dly(5) => inp_wrdata_dly(5), inp_wrdata_dly(4)
         => inp_wrdata_dly(4), inp_wrdata_dly(3) => 
        inp_wrdata_dly(3), inp_wrdata_dly(2) => inp_wrdata_dly(2), 
        inp_wrdata_dly(1) => inp_wrdata_dly(1), inp_wrdata_dly(0)
         => inp_wrdata_dly(0), clk_c => clk_c, inp_coef_rden => 
        inp_coef_rden, Data_Valid_dly => Data_Valid_dly);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC is

    port( Yn_out      : out   std_logic_vector(43 downto 0);
          inp_rddata  : in    std_logic_vector(17 downto 0);
          Coef_rddata : in    std_logic_vector(17 downto 0);
          reset_n_c   : in    std_logic;
          clk_c       : in    std_logic
        );

end mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC;

architecture DEF_ARCH of 
        mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;
    signal nc34, nc9, nc13, nc23, nc33, nc16, nc26, nc27, nc17, 
        nc36, nc37, nc5, nc4, nc42, nc41, nc25, nc15, nc35, nc28, 
        nc18, nc38, nc1, nc2, nc22, nc12, nc21, nc11, nc3, nc32, 
        nc40, nc31, nc44, nc7, nc6, nc19, nc29, nc39, nc8, nc43, 
        nc20, nc10, nc24, nc14, nc30 : std_logic;

begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    U0 : MACC
      port map(CLK(1) => clk_c, CLK(0) => clk_c, A(17) => 
        inp_rddata(17), A(16) => inp_rddata(16), A(15) => 
        inp_rddata(15), A(14) => inp_rddata(14), A(13) => 
        inp_rddata(13), A(12) => inp_rddata(12), A(11) => 
        inp_rddata(11), A(10) => inp_rddata(10), A(9) => 
        inp_rddata(9), A(8) => inp_rddata(8), A(7) => 
        inp_rddata(7), A(6) => inp_rddata(6), A(5) => 
        inp_rddata(5), A(4) => inp_rddata(4), A(3) => 
        inp_rddata(3), A(2) => inp_rddata(2), A(1) => 
        inp_rddata(1), A(0) => inp_rddata(0), A_EN(1) => 
        VCC_net_1, A_EN(0) => VCC_net_1, A_ARST_N(1) => reset_n_c, 
        A_ARST_N(0) => reset_n_c, A_SRST_N(1) => VCC_net_1, 
        A_SRST_N(0) => VCC_net_1, B(17) => Coef_rddata(17), B(16)
         => Coef_rddata(16), B(15) => Coef_rddata(15), B(14) => 
        Coef_rddata(14), B(13) => Coef_rddata(13), B(12) => 
        Coef_rddata(12), B(11) => Coef_rddata(11), B(10) => 
        Coef_rddata(10), B(9) => Coef_rddata(9), B(8) => 
        Coef_rddata(8), B(7) => Coef_rddata(7), B(6) => 
        Coef_rddata(6), B(5) => Coef_rddata(5), B(4) => 
        Coef_rddata(4), B(3) => Coef_rddata(3), B(2) => 
        Coef_rddata(2), B(1) => Coef_rddata(1), B(0) => 
        Coef_rddata(0), B_EN(1) => VCC_net_1, B_EN(0) => 
        VCC_net_1, B_ARST_N(1) => reset_n_c, B_ARST_N(0) => 
        reset_n_c, B_SRST_N(1) => VCC_net_1, B_SRST_N(0) => 
        VCC_net_1, C(43) => GND_net_1, C(42) => GND_net_1, C(41)
         => GND_net_1, C(40) => GND_net_1, C(39) => GND_net_1, 
        C(38) => GND_net_1, C(37) => GND_net_1, C(36) => 
        GND_net_1, C(35) => GND_net_1, C(34) => GND_net_1, C(33)
         => GND_net_1, C(32) => GND_net_1, C(31) => GND_net_1, 
        C(30) => GND_net_1, C(29) => GND_net_1, C(28) => 
        GND_net_1, C(27) => GND_net_1, C(26) => GND_net_1, C(25)
         => GND_net_1, C(24) => GND_net_1, C(23) => GND_net_1, 
        C(22) => GND_net_1, C(21) => GND_net_1, C(20) => 
        GND_net_1, C(19) => GND_net_1, C(18) => GND_net_1, C(17)
         => GND_net_1, C(16) => GND_net_1, C(15) => GND_net_1, 
        C(14) => GND_net_1, C(13) => GND_net_1, C(12) => 
        GND_net_1, C(11) => GND_net_1, C(10) => GND_net_1, C(9)
         => GND_net_1, C(8) => GND_net_1, C(7) => GND_net_1, C(6)
         => GND_net_1, C(5) => GND_net_1, C(4) => GND_net_1, C(3)
         => GND_net_1, C(2) => GND_net_1, C(1) => GND_net_1, C(0)
         => GND_net_1, C_EN(1) => VCC_net_1, C_EN(0) => VCC_net_1, 
        C_ARST_N(1) => VCC_net_1, C_ARST_N(0) => VCC_net_1, 
        C_SRST_N(1) => VCC_net_1, C_SRST_N(0) => VCC_net_1, 
        P_EN(1) => VCC_net_1, P_EN(0) => VCC_net_1, P_ARST_N(1)
         => reset_n_c, P_ARST_N(0) => reset_n_c, P_SRST_N(1) => 
        VCC_net_1, P_SRST_N(0) => VCC_net_1, FDBKSEL => VCC_net_1, 
        FDBKSEL_EN => VCC_net_1, FDBKSEL_AL_N => VCC_net_1, 
        FDBKSEL_SL_N => VCC_net_1, CDSEL => GND_net_1, CDSEL_EN
         => VCC_net_1, CDSEL_AL_N => VCC_net_1, CDSEL_SL_N => 
        VCC_net_1, ARSHFT17 => GND_net_1, ARSHFT17_EN => 
        VCC_net_1, ARSHFT17_AL_N => VCC_net_1, ARSHFT17_SL_N => 
        VCC_net_1, SUB => GND_net_1, SUB_EN => VCC_net_1, 
        SUB_AL_N => VCC_net_1, SUB_SL_N => VCC_net_1, CARRYIN => 
        GND_net_1, SIMD => GND_net_1, DOTP => GND_net_1, 
        OVFL_CARRYOUT_SEL => GND_net_1, A_BYPASS(1) => GND_net_1, 
        A_BYPASS(0) => GND_net_1, B_BYPASS(1) => GND_net_1, 
        B_BYPASS(0) => GND_net_1, C_BYPASS(1) => VCC_net_1, 
        C_BYPASS(0) => VCC_net_1, P_BYPASS(1) => GND_net_1, 
        P_BYPASS(0) => GND_net_1, FDBKSEL_BYPASS => VCC_net_1, 
        FDBKSEL_AD => GND_net_1, FDBKSEL_SD_N => VCC_net_1, 
        CDSEL_BYPASS => VCC_net_1, CDSEL_AD => GND_net_1, 
        CDSEL_SD_N => VCC_net_1, ARSHFT17_BYPASS => VCC_net_1, 
        ARSHFT17_AD => GND_net_1, ARSHFT17_SD_N => VCC_net_1, 
        SUB_BYPASS => VCC_net_1, SUB_AD => GND_net_1, SUB_SD_N
         => VCC_net_1, CDIN(43) => GND_net_1, CDIN(42) => 
        GND_net_1, CDIN(41) => GND_net_1, CDIN(40) => GND_net_1, 
        CDIN(39) => GND_net_1, CDIN(38) => GND_net_1, CDIN(37)
         => GND_net_1, CDIN(36) => GND_net_1, CDIN(35) => 
        GND_net_1, CDIN(34) => GND_net_1, CDIN(33) => GND_net_1, 
        CDIN(32) => GND_net_1, CDIN(31) => GND_net_1, CDIN(30)
         => GND_net_1, CDIN(29) => GND_net_1, CDIN(28) => 
        GND_net_1, CDIN(27) => GND_net_1, CDIN(26) => GND_net_1, 
        CDIN(25) => GND_net_1, CDIN(24) => GND_net_1, CDIN(23)
         => GND_net_1, CDIN(22) => GND_net_1, CDIN(21) => 
        GND_net_1, CDIN(20) => GND_net_1, CDIN(19) => GND_net_1, 
        CDIN(18) => GND_net_1, CDIN(17) => GND_net_1, CDIN(16)
         => GND_net_1, CDIN(15) => GND_net_1, CDIN(14) => 
        GND_net_1, CDIN(13) => GND_net_1, CDIN(12) => GND_net_1, 
        CDIN(11) => GND_net_1, CDIN(10) => GND_net_1, CDIN(9) => 
        GND_net_1, CDIN(8) => GND_net_1, CDIN(7) => GND_net_1, 
        CDIN(6) => GND_net_1, CDIN(5) => GND_net_1, CDIN(4) => 
        GND_net_1, CDIN(3) => GND_net_1, CDIN(2) => GND_net_1, 
        CDIN(1) => GND_net_1, CDIN(0) => GND_net_1, CDOUT(43) => 
        nc34, CDOUT(42) => nc9, CDOUT(41) => nc13, CDOUT(40) => 
        nc23, CDOUT(39) => nc33, CDOUT(38) => nc16, CDOUT(37) => 
        nc26, CDOUT(36) => nc27, CDOUT(35) => nc17, CDOUT(34) => 
        nc36, CDOUT(33) => nc37, CDOUT(32) => nc5, CDOUT(31) => 
        nc4, CDOUT(30) => nc42, CDOUT(29) => nc41, CDOUT(28) => 
        nc25, CDOUT(27) => nc15, CDOUT(26) => nc35, CDOUT(25) => 
        nc28, CDOUT(24) => nc18, CDOUT(23) => nc38, CDOUT(22) => 
        nc1, CDOUT(21) => nc2, CDOUT(20) => nc22, CDOUT(19) => 
        nc12, CDOUT(18) => nc21, CDOUT(17) => nc11, CDOUT(16) => 
        nc3, CDOUT(15) => nc32, CDOUT(14) => nc40, CDOUT(13) => 
        nc31, CDOUT(12) => nc44, CDOUT(11) => nc7, CDOUT(10) => 
        nc6, CDOUT(9) => nc19, CDOUT(8) => nc29, CDOUT(7) => nc39, 
        CDOUT(6) => nc8, CDOUT(5) => nc43, CDOUT(4) => nc20, 
        CDOUT(3) => nc10, CDOUT(2) => nc24, CDOUT(1) => nc14, 
        CDOUT(0) => nc30, P(43) => Yn_out(43), P(42) => 
        Yn_out(42), P(41) => Yn_out(41), P(40) => Yn_out(40), 
        P(39) => Yn_out(39), P(38) => Yn_out(38), P(37) => 
        Yn_out(37), P(36) => Yn_out(36), P(35) => Yn_out(35), 
        P(34) => Yn_out(34), P(33) => Yn_out(33), P(32) => 
        Yn_out(32), P(31) => Yn_out(31), P(30) => Yn_out(30), 
        P(29) => Yn_out(29), P(28) => Yn_out(28), P(27) => 
        Yn_out(27), P(26) => Yn_out(26), P(25) => Yn_out(25), 
        P(24) => Yn_out(24), P(23) => Yn_out(23), P(22) => 
        Yn_out(22), P(21) => Yn_out(21), P(20) => Yn_out(20), 
        P(19) => Yn_out(19), P(18) => Yn_out(18), P(17) => 
        Yn_out(17), P(16) => Yn_out(16), P(15) => Yn_out(15), 
        P(14) => Yn_out(14), P(13) => Yn_out(13), P(12) => 
        Yn_out(12), P(11) => Yn_out(11), P(10) => Yn_out(10), 
        P(9) => Yn_out(9), P(8) => Yn_out(8), P(7) => Yn_out(7), 
        P(6) => Yn_out(6), P(5) => Yn_out(5), P(4) => Yn_out(4), 
        P(3) => Yn_out(3), P(2) => Yn_out(2), P(1) => Yn_out(1), 
        P(0) => Yn_out(0), OVFL_CARRYOUT => OPEN);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity mulacc_18x18 is

    port( Yn_out      : out   std_logic_vector(43 downto 0);
          inp_rddata  : in    std_logic_vector(17 downto 0);
          Coef_rddata : in    std_logic_vector(17 downto 0);
          reset_n_c   : in    std_logic;
          clk_c       : in    std_logic
        );

end mulacc_18x18;

architecture DEF_ARCH of mulacc_18x18 is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC
    port( Yn_out      : out   std_logic_vector(43 downto 0);
          inp_rddata  : in    std_logic_vector(17 downto 0) := (others => 'U');
          Coef_rddata : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_n_c   : in    std_logic := 'U';
          clk_c       : in    std_logic := 'U'
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

    for all : mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC
	Use entity work.
        mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC(DEF_ARCH);
begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    mulacc_18x18_0 : mulacc_18x18_mulacc_18x18_0_HARD_MULT_ACC
      port map(Yn_out(43) => Yn_out(43), Yn_out(42) => Yn_out(42), 
        Yn_out(41) => Yn_out(41), Yn_out(40) => Yn_out(40), 
        Yn_out(39) => Yn_out(39), Yn_out(38) => Yn_out(38), 
        Yn_out(37) => Yn_out(37), Yn_out(36) => Yn_out(36), 
        Yn_out(35) => Yn_out(35), Yn_out(34) => Yn_out(34), 
        Yn_out(33) => Yn_out(33), Yn_out(32) => Yn_out(32), 
        Yn_out(31) => Yn_out(31), Yn_out(30) => Yn_out(30), 
        Yn_out(29) => Yn_out(29), Yn_out(28) => Yn_out(28), 
        Yn_out(27) => Yn_out(27), Yn_out(26) => Yn_out(26), 
        Yn_out(25) => Yn_out(25), Yn_out(24) => Yn_out(24), 
        Yn_out(23) => Yn_out(23), Yn_out(22) => Yn_out(22), 
        Yn_out(21) => Yn_out(21), Yn_out(20) => Yn_out(20), 
        Yn_out(19) => Yn_out(19), Yn_out(18) => Yn_out(18), 
        Yn_out(17) => Yn_out(17), Yn_out(16) => Yn_out(16), 
        Yn_out(15) => Yn_out(15), Yn_out(14) => Yn_out(14), 
        Yn_out(13) => Yn_out(13), Yn_out(12) => Yn_out(12), 
        Yn_out(11) => Yn_out(11), Yn_out(10) => Yn_out(10), 
        Yn_out(9) => Yn_out(9), Yn_out(8) => Yn_out(8), Yn_out(7)
         => Yn_out(7), Yn_out(6) => Yn_out(6), Yn_out(5) => 
        Yn_out(5), Yn_out(4) => Yn_out(4), Yn_out(3) => Yn_out(3), 
        Yn_out(2) => Yn_out(2), Yn_out(1) => Yn_out(1), Yn_out(0)
         => Yn_out(0), inp_rddata(17) => inp_rddata(17), 
        inp_rddata(16) => inp_rddata(16), inp_rddata(15) => 
        inp_rddata(15), inp_rddata(14) => inp_rddata(14), 
        inp_rddata(13) => inp_rddata(13), inp_rddata(12) => 
        inp_rddata(12), inp_rddata(11) => inp_rddata(11), 
        inp_rddata(10) => inp_rddata(10), inp_rddata(9) => 
        inp_rddata(9), inp_rddata(8) => inp_rddata(8), 
        inp_rddata(7) => inp_rddata(7), inp_rddata(6) => 
        inp_rddata(6), inp_rddata(5) => inp_rddata(5), 
        inp_rddata(4) => inp_rddata(4), inp_rddata(3) => 
        inp_rddata(3), inp_rddata(2) => inp_rddata(2), 
        inp_rddata(1) => inp_rddata(1), inp_rddata(0) => 
        inp_rddata(0), Coef_rddata(17) => Coef_rddata(17), 
        Coef_rddata(16) => Coef_rddata(16), Coef_rddata(15) => 
        Coef_rddata(15), Coef_rddata(14) => Coef_rddata(14), 
        Coef_rddata(13) => Coef_rddata(13), Coef_rddata(12) => 
        Coef_rddata(12), Coef_rddata(11) => Coef_rddata(11), 
        Coef_rddata(10) => Coef_rddata(10), Coef_rddata(9) => 
        Coef_rddata(9), Coef_rddata(8) => Coef_rddata(8), 
        Coef_rddata(7) => Coef_rddata(7), Coef_rddata(6) => 
        Coef_rddata(6), Coef_rddata(5) => Coef_rddata(5), 
        Coef_rddata(4) => Coef_rddata(4), Coef_rddata(3) => 
        Coef_rddata(3), Coef_rddata(2) => Coef_rddata(2), 
        Coef_rddata(1) => Coef_rddata(1), Coef_rddata(0) => 
        Coef_rddata(0), reset_n_c => reset_n_c, clk_c => clk_c);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Coef_RAM_Coef_RAM_0_URAM is

    port( Coef_rddata   : out   std_logic_vector(17 downto 0);
          Coef_rdaddr   : in    std_logic_vector(2 downto 0);
          clk_c         : in    std_logic;
          inp_coef_rden : in    std_logic
        );

end Coef_RAM_Coef_RAM_0_URAM;

architecture DEF_ARCH of Coef_RAM_Coef_RAM_0_URAM is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component RAM64x18
    generic (MEMORYFILE:string := "");

    port( A_DOUT        : out   std_logic_vector(17 downto 0);
          B_DOUT        : out   std_logic_vector(17 downto 0);
          BUSY          : out   std_logic;
          A_ADDR_CLK    : in    std_logic := 'U';
          A_DOUT_CLK    : in    std_logic := 'U';
          A_ADDR_SRST_N : in    std_logic := 'U';
          A_DOUT_SRST_N : in    std_logic := 'U';
          A_ADDR_ARST_N : in    std_logic := 'U';
          A_DOUT_ARST_N : in    std_logic := 'U';
          A_ADDR_EN     : in    std_logic := 'U';
          A_DOUT_EN     : in    std_logic := 'U';
          A_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          B_ADDR_CLK    : in    std_logic := 'U';
          B_DOUT_CLK    : in    std_logic := 'U';
          B_ADDR_SRST_N : in    std_logic := 'U';
          B_DOUT_SRST_N : in    std_logic := 'U';
          B_ADDR_ARST_N : in    std_logic := 'U';
          B_DOUT_ARST_N : in    std_logic := 'U';
          B_ADDR_EN     : in    std_logic := 'U';
          B_DOUT_EN     : in    std_logic := 'U';
          B_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          C_CLK         : in    std_logic := 'U';
          C_ADDR        : in    std_logic_vector(9 downto 0) := (others => 'U');
          C_DIN         : in    std_logic_vector(17 downto 0) := (others => 'U');
          C_WEN         : in    std_logic := 'U';
          C_BLK         : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_EN          : in    std_logic := 'U';
          A_ADDR_LAT    : in    std_logic := 'U';
          A_DOUT_LAT    : in    std_logic := 'U';
          A_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          B_EN          : in    std_logic := 'U';
          B_ADDR_LAT    : in    std_logic := 'U';
          B_DOUT_LAT    : in    std_logic := 'U';
          B_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          C_EN          : in    std_logic := 'U';
          C_WIDTH       : in    std_logic_vector(2 downto 0) := (others => 'U');
          SII_LOCK      : in    std_logic := 'U'
        );
  end component;

    signal VCC_net_1, GND_net_1 : std_logic;
    signal nc1, nc8, nc13, nc16, nc9, nc14, nc5, nc15, nc3, nc10, 
        nc7, nc17, nc4, nc12, nc2, nc18, nc6, nc11 : std_logic;

begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    Coef_RAM_Coef_RAM_0_URAM_R0C0 : RAM64x18

              generic map(MEMORYFILE => "Coef_RAM_Coef_RAM_0_URAM_R0C0.mem"
        )

      port map(A_DOUT(17) => Coef_rddata(17), A_DOUT(16) => 
        Coef_rddata(16), A_DOUT(15) => Coef_rddata(15), 
        A_DOUT(14) => Coef_rddata(14), A_DOUT(13) => 
        Coef_rddata(13), A_DOUT(12) => Coef_rddata(12), 
        A_DOUT(11) => Coef_rddata(11), A_DOUT(10) => 
        Coef_rddata(10), A_DOUT(9) => Coef_rddata(9), A_DOUT(8)
         => Coef_rddata(8), A_DOUT(7) => Coef_rddata(7), 
        A_DOUT(6) => Coef_rddata(6), A_DOUT(5) => Coef_rddata(5), 
        A_DOUT(4) => Coef_rddata(4), A_DOUT(3) => Coef_rddata(3), 
        A_DOUT(2) => Coef_rddata(2), A_DOUT(1) => Coef_rddata(1), 
        A_DOUT(0) => Coef_rddata(0), B_DOUT(17) => nc1, 
        B_DOUT(16) => nc8, B_DOUT(15) => nc13, B_DOUT(14) => nc16, 
        B_DOUT(13) => nc9, B_DOUT(12) => nc14, B_DOUT(11) => nc5, 
        B_DOUT(10) => nc15, B_DOUT(9) => nc3, B_DOUT(8) => nc10, 
        B_DOUT(7) => nc7, B_DOUT(6) => nc17, B_DOUT(5) => nc4, 
        B_DOUT(4) => nc12, B_DOUT(3) => nc2, B_DOUT(2) => nc18, 
        B_DOUT(1) => nc6, B_DOUT(0) => nc11, BUSY => OPEN, 
        A_ADDR_CLK => VCC_net_1, A_DOUT_CLK => clk_c, 
        A_ADDR_SRST_N => VCC_net_1, A_DOUT_SRST_N => VCC_net_1, 
        A_ADDR_ARST_N => VCC_net_1, A_DOUT_ARST_N => VCC_net_1, 
        A_ADDR_EN => VCC_net_1, A_DOUT_EN => VCC_net_1, A_BLK(1)
         => inp_coef_rden, A_BLK(0) => VCC_net_1, A_ADDR(9) => 
        GND_net_1, A_ADDR(8) => GND_net_1, A_ADDR(7) => GND_net_1, 
        A_ADDR(6) => Coef_rdaddr(2), A_ADDR(5) => Coef_rdaddr(1), 
        A_ADDR(4) => Coef_rdaddr(0), A_ADDR(3) => GND_net_1, 
        A_ADDR(2) => GND_net_1, A_ADDR(1) => GND_net_1, A_ADDR(0)
         => GND_net_1, B_ADDR_CLK => VCC_net_1, B_DOUT_CLK => 
        clk_c, B_ADDR_SRST_N => VCC_net_1, B_DOUT_SRST_N => 
        VCC_net_1, B_ADDR_ARST_N => VCC_net_1, B_DOUT_ARST_N => 
        VCC_net_1, B_ADDR_EN => VCC_net_1, B_DOUT_EN => VCC_net_1, 
        B_BLK(1) => GND_net_1, B_BLK(0) => VCC_net_1, B_ADDR(9)
         => GND_net_1, B_ADDR(8) => GND_net_1, B_ADDR(7) => 
        GND_net_1, B_ADDR(6) => GND_net_1, B_ADDR(5) => GND_net_1, 
        B_ADDR(4) => GND_net_1, B_ADDR(3) => GND_net_1, B_ADDR(2)
         => GND_net_1, B_ADDR(1) => GND_net_1, B_ADDR(0) => 
        GND_net_1, C_CLK => clk_c, C_ADDR(9) => GND_net_1, 
        C_ADDR(8) => GND_net_1, C_ADDR(7) => GND_net_1, C_ADDR(6)
         => GND_net_1, C_ADDR(5) => GND_net_1, C_ADDR(4) => 
        GND_net_1, C_ADDR(3) => GND_net_1, C_ADDR(2) => GND_net_1, 
        C_ADDR(1) => GND_net_1, C_ADDR(0) => GND_net_1, C_DIN(17)
         => GND_net_1, C_DIN(16) => GND_net_1, C_DIN(15) => 
        GND_net_1, C_DIN(14) => GND_net_1, C_DIN(13) => GND_net_1, 
        C_DIN(12) => GND_net_1, C_DIN(11) => GND_net_1, C_DIN(10)
         => GND_net_1, C_DIN(9) => GND_net_1, C_DIN(8) => 
        GND_net_1, C_DIN(7) => GND_net_1, C_DIN(6) => GND_net_1, 
        C_DIN(5) => GND_net_1, C_DIN(4) => GND_net_1, C_DIN(3)
         => GND_net_1, C_DIN(2) => GND_net_1, C_DIN(1) => 
        GND_net_1, C_DIN(0) => GND_net_1, C_WEN => VCC_net_1, 
        C_BLK(1) => GND_net_1, C_BLK(0) => VCC_net_1, A_EN => 
        VCC_net_1, A_ADDR_LAT => VCC_net_1, A_DOUT_LAT => 
        GND_net_1, A_WIDTH(2) => VCC_net_1, A_WIDTH(1) => 
        GND_net_1, A_WIDTH(0) => GND_net_1, B_EN => VCC_net_1, 
        B_ADDR_LAT => VCC_net_1, B_DOUT_LAT => GND_net_1, 
        B_WIDTH(2) => VCC_net_1, B_WIDTH(1) => GND_net_1, 
        B_WIDTH(0) => GND_net_1, C_EN => VCC_net_1, C_WIDTH(2)
         => VCC_net_1, C_WIDTH(1) => GND_net_1, C_WIDTH(0) => 
        GND_net_1, SII_LOCK => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Coef_RAM is

    port( Coef_rddata   : out   std_logic_vector(17 downto 0);
          Coef_rdaddr   : in    std_logic_vector(2 downto 0);
          clk_c         : in    std_logic;
          inp_coef_rden : in    std_logic
        );

end Coef_RAM;

architecture DEF_ARCH of Coef_RAM is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component Coef_RAM_Coef_RAM_0_URAM
    port( Coef_rddata   : out   std_logic_vector(17 downto 0);
          Coef_rdaddr   : in    std_logic_vector(2 downto 0) := (others => 'U');
          clk_c         : in    std_logic := 'U';
          inp_coef_rden : in    std_logic := 'U'
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

    for all : Coef_RAM_Coef_RAM_0_URAM
	Use entity work.Coef_RAM_Coef_RAM_0_URAM(DEF_ARCH);
begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    Coef_RAM_0 : Coef_RAM_Coef_RAM_0_URAM
      port map(Coef_rddata(17) => Coef_rddata(17), 
        Coef_rddata(16) => Coef_rddata(16), Coef_rddata(15) => 
        Coef_rddata(15), Coef_rddata(14) => Coef_rddata(14), 
        Coef_rddata(13) => Coef_rddata(13), Coef_rddata(12) => 
        Coef_rddata(12), Coef_rddata(11) => Coef_rddata(11), 
        Coef_rddata(10) => Coef_rddata(10), Coef_rddata(9) => 
        Coef_rddata(9), Coef_rddata(8) => Coef_rddata(8), 
        Coef_rddata(7) => Coef_rddata(7), Coef_rddata(6) => 
        Coef_rddata(6), Coef_rddata(5) => Coef_rddata(5), 
        Coef_rddata(4) => Coef_rddata(4), Coef_rddata(3) => 
        Coef_rddata(3), Coef_rddata(2) => Coef_rddata(2), 
        Coef_rddata(1) => Coef_rddata(1), Coef_rddata(0) => 
        Coef_rddata(0), Coef_rdaddr(2) => Coef_rdaddr(2), 
        Coef_rdaddr(1) => Coef_rdaddr(1), Coef_rdaddr(0) => 
        Coef_rdaddr(0), clk_c => clk_c, inp_coef_rden => 
        inp_coef_rden);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity MAC_FIR is

    port( Xn_in      : in    std_logic_vector(17 downto 0);
          Mac_out    : out   std_logic_vector(43 downto 0);
          clk        : in    std_logic;
          reset_n    : in    std_logic;
          Filter_En  : in    std_logic;
          Data_Valid : in    std_logic;
          rdy        : out   std_logic
        );

end MAC_FIR;

architecture DEF_ARCH of MAC_FIR is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component INBUF
    generic (IOSTD:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OUTBUF
    generic (IOSTD:string := "");

    port( D   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component CFG1
    generic (INIT:std_logic_vector := x"0");

    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CLKINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component Inp_RAM
    port( inp_rddata     : out   std_logic_vector(17 downto 0);
          inp_rdaddr     : in    std_logic_vector(2 downto 0) := (others => 'U');
          inp_wraddr     : in    std_logic_vector(2 downto 0) := (others => 'U');
          inp_wrdata_dly : in    std_logic_vector(17 downto 0) := (others => 'U');
          clk_c          : in    std_logic := 'U';
          inp_coef_rden  : in    std_logic := 'U';
          Data_Valid_dly : in    std_logic := 'U'
        );
  end component;

  component mulacc_18x18
    port( Yn_out      : out   std_logic_vector(43 downto 0);
          inp_rddata  : in    std_logic_vector(17 downto 0) := (others => 'U');
          Coef_rddata : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_n_c   : in    std_logic := 'U';
          clk_c       : in    std_logic := 'U'
        );
  end component;

  component Coef_RAM
    port( Coef_rddata   : out   std_logic_vector(17 downto 0);
          Coef_rdaddr   : in    std_logic_vector(2 downto 0) := (others => 'U');
          clk_c         : in    std_logic := 'U';
          inp_coef_rden : in    std_logic := 'U'
        );
  end component;

    signal \rdy_sig\, \inp_rddata[0]\, \inp_rddata[1]\, 
        \inp_rddata[2]\, \inp_rddata[3]\, \inp_rddata[4]\, 
        \inp_rddata[5]\, \inp_rddata[6]\, \inp_rddata[7]\, 
        \inp_rddata[8]\, \inp_rddata[9]\, \inp_rddata[10]\, 
        \inp_rddata[11]\, \inp_rddata[12]\, \inp_rddata[13]\, 
        \inp_rddata[14]\, \inp_rddata[15]\, \inp_rddata[16]\, 
        \inp_rddata[17]\, VCC_net_1, \Coef_rddata[0]\, 
        \Coef_rddata[1]\, \Coef_rddata[2]\, \Coef_rddata[3]\, 
        \Coef_rddata[4]\, \Coef_rddata[5]\, \Coef_rddata[6]\, 
        \Coef_rddata[7]\, \Coef_rddata[8]\, \Coef_rddata[9]\, 
        \Coef_rddata[10]\, \Coef_rddata[11]\, \Coef_rddata[12]\, 
        \Coef_rddata[13]\, \Coef_rddata[14]\, \Coef_rddata[15]\, 
        \Coef_rddata[16]\, \Coef_rddata[17]\, \Yn_out[0]\, 
        \Yn_out[1]\, \Yn_out[2]\, \Yn_out[3]\, \Yn_out[4]\, 
        \Yn_out[5]\, \Yn_out[6]\, \Yn_out[7]\, \Yn_out[8]\, 
        \Yn_out[9]\, \Yn_out[10]\, \Yn_out[11]\, \Yn_out[12]\, 
        \Yn_out[13]\, \Yn_out[14]\, \Yn_out[15]\, \Yn_out[16]\, 
        \Yn_out[17]\, \Yn_out[18]\, \Yn_out[19]\, \Yn_out[20]\, 
        \Yn_out[21]\, \Yn_out[22]\, \Yn_out[23]\, \Yn_out[24]\, 
        \Yn_out[25]\, \Yn_out[26]\, \Yn_out[27]\, \Yn_out[28]\, 
        \Yn_out[29]\, \Yn_out[30]\, \Yn_out[31]\, \Yn_out[32]\, 
        \Yn_out[33]\, \Yn_out[34]\, \Yn_out[35]\, \Yn_out[36]\, 
        \Yn_out[37]\, \Yn_out[38]\, \Yn_out[39]\, \Yn_out[40]\, 
        \Yn_out[41]\, \Yn_out[42]\, \Yn_out[43]\, 
        \Coef_rdaddr[0]_net_1\, \Coef_rdaddr[1]_net_1\, 
        \Coef_rdaddr[2]_net_1\, \inp_coef_rden\, GND_net_1, 
        \inp_rdaddr[0]_net_1\, \inp_rdaddr[1]_net_1\, 
        \inp_rdaddr[2]_net_1\, \inp_wraddr[0]_net_1\, 
        \inp_wraddr[1]_net_1\, \inp_wraddr[2]_net_1\, 
        \Data_Valid_dly\, \inp_wrdata_dly[0]_net_1\, 
        \inp_wrdata_dly[1]_net_1\, \inp_wrdata_dly[2]_net_1\, 
        \inp_wrdata_dly[3]_net_1\, \inp_wrdata_dly[4]_net_1\, 
        \inp_wrdata_dly[5]_net_1\, \inp_wrdata_dly[6]_net_1\, 
        \inp_wrdata_dly[7]_net_1\, \inp_wrdata_dly[8]_net_1\, 
        \inp_wrdata_dly[9]_net_1\, \inp_wrdata_dly[10]_net_1\, 
        \inp_wrdata_dly[11]_net_1\, \inp_wrdata_dly[12]_net_1\, 
        \inp_wrdata_dly[13]_net_1\, \inp_wrdata_dly[14]_net_1\, 
        \inp_wrdata_dly[15]_net_1\, \inp_wrdata_dly[16]_net_1\, 
        \inp_wrdata_dly[17]_net_1\, \mac_state[0]_net_1\, 
        \Transferdone\, \new_inprdaddr[1]_net_1\, 
        \rdy_cnt[0]_net_1\, \rdy_cnt[1]_net_1\, \FiltOp_done\, 
        \inp_wrdata[0]_net_1\, \inp_wrdata[1]_net_1\, 
        \inp_wrdata[2]_net_1\, \inp_wrdata[3]_net_1\, 
        \inp_wrdata[4]_net_1\, \inp_wrdata[5]_net_1\, 
        \inp_wrdata[6]_net_1\, \inp_wrdata[7]_net_1\, 
        \inp_wrdata[8]_net_1\, \inp_wrdata[9]_net_1\, 
        \inp_wrdata[10]_net_1\, \inp_wrdata[11]_net_1\, 
        \inp_wrdata[12]_net_1\, \inp_wrdata[13]_net_1\, 
        \inp_wrdata[14]_net_1\, \inp_wrdata[15]_net_1\, 
        \inp_wrdata[16]_net_1\, \inp_wrdata[17]_net_1\, \clr\, 
        \clrsig\, \mac_state[4]_net_1\, \mac_state[2]_net_1\, 
        \mac_state[1]_net_1\, \op_eq.filtop_done3_net_1\, 
        \new_inprdaddr[0]_net_1\, \new_inprdaddr[2]_net_1\, 
        \transferdone8\, \rdy_cnt[2]_net_1\, \mac_state[3]_net_1\, 
        \mac_state[5]_net_1\, \inp_wraddr_2[1]_net_1\, 
        \inp_wraddr_2[2]_net_1\, \rdy_cnt_3[0]_net_1\, 
        \rdy_cnt_3[2]_net_1\, \Coef_rdaddr_2[0]_net_1\, 
        \Coef_rdaddr_2[2]_net_1\, \Coef_rdaddr_RNO[1]_net_1\, 
        \rdy_cnt_RNO[1]_net_1\, \mac_state_ns[1]_net_1\, 
        \mac_state_ns[2]_net_1\, \mac_state_ns[3]_net_1\, 
        \mac_state_ns[4]_net_1\, \mac_state_ns[0]\, 
        \inp_rdaddr_4[0]_net_1\, \inp_rdaddr_4[1]_net_1\, 
        \inp_rdaddr_4[2]_net_1\, N_118, clk_c, reset_n_c, 
        Filter_En_c, \Xn_in_c[0]\, \Xn_in_c[1]\, \Xn_in_c[2]\, 
        \Xn_in_c[3]\, \Xn_in_c[4]\, \Xn_in_c[5]\, \Xn_in_c[6]\, 
        \Xn_in_c[7]\, \Xn_in_c[8]\, \Xn_in_c[9]\, \Xn_in_c[10]\, 
        \Xn_in_c[11]\, \Xn_in_c[12]\, \Xn_in_c[13]\, 
        \Xn_in_c[14]\, \Xn_in_c[15]\, \Xn_in_c[16]\, 
        \Xn_in_c[17]\, Data_Valid_c, \Mac_out_c[0]\, 
        \Mac_out_c[1]\, \Mac_out_c[2]\, \Mac_out_c[3]\, 
        \Mac_out_c[4]\, \Mac_out_c[5]\, \Mac_out_c[6]\, 
        \Mac_out_c[7]\, \Mac_out_c[8]\, \Mac_out_c[9]\, 
        \Mac_out_c[10]\, \Mac_out_c[11]\, \Mac_out_c[12]\, 
        \Mac_out_c[13]\, \Mac_out_c[14]\, \Mac_out_c[15]\, 
        \Mac_out_c[16]\, \Mac_out_c[17]\, \Mac_out_c[18]\, 
        \Mac_out_c[19]\, \Mac_out_c[20]\, \Mac_out_c[21]\, 
        \Mac_out_c[22]\, \Mac_out_c[23]\, \Mac_out_c[24]\, 
        \Mac_out_c[25]\, \Mac_out_c[26]\, \Mac_out_c[27]\, 
        \Mac_out_c[28]\, \Mac_out_c[29]\, \Mac_out_c[30]\, 
        \Mac_out_c[31]\, \Mac_out_c[32]\, \Mac_out_c[33]\, 
        \Mac_out_c[34]\, \Mac_out_c[35]\, \Mac_out_c[36]\, 
        \Mac_out_c[37]\, \Mac_out_c[38]\, \Mac_out_c[39]\, 
        \Mac_out_c[40]\, \Mac_out_c[41]\, \Mac_out_c[42]\, 
        \Mac_out_c[43]\, mac_state_1_sqmuxa, N_130, N_49, N_48, 
        N_47, inp_rdaddr_4_sn_N_4_mux, N_132, CO0_1, 
        \new_inprdaddr_2[2]_net_1\, \new_inprdaddr_2[1]_net_1\, 
        \mac_state_ns_a2_1[0]_net_1\, N_118_i_0, N_120_i_0, 
        N_112_i_0, N_131_i_0, \new_inprdaddr_i_0[0]\, 
        \inp_wraddr_i_0[0]\, \clk_ibuf\, \reset_n_ibuf\
         : std_logic;

    for all : Inp_RAM
	Use entity work.Inp_RAM(DEF_ARCH);
    for all : mulacc_18x18
	Use entity work.mulacc_18x18(DEF_ARCH);
    for all : Coef_RAM
	Use entity work.Coef_RAM(DEF_ARCH);
begin 


    inp_coef_rden : SLE
      port map(D => VCC_net_1, CLK => clk_c, EN => N_118_i_0, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \inp_coef_rden\);
    
    \Mac_out[23]\ : SLE
      port map(D => \Yn_out[23]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[23]\);
    
    \Xn_in_ibuf[12]\ : INBUF
      port map(PAD => Xn_in(12), Y => \Xn_in_c[12]\);
    
    \Mac_out[19]\ : SLE
      port map(D => \Yn_out[19]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[19]\);
    
    \inp_rdaddr_4_RNO[0]\ : CFG2
      generic map(INIT => x"6")

      port map(A => mac_state_1_sqmuxa, B => 
        \inp_rdaddr[0]_net_1\, Y => N_47);
    
    \Mac_out[43]\ : SLE
      port map(D => \Yn_out[43]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[43]\);
    
    \inp_wrdata[7]\ : SLE
      port map(D => \Xn_in_c[7]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[7]_net_1\);
    
    \Coef_rdaddr[2]\ : SLE
      port map(D => \Coef_rdaddr_2[2]_net_1\, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rdaddr[2]_net_1\);
    
    \inp_wrdata_dly[9]\ : SLE
      port map(D => \inp_wrdata[9]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[9]_net_1\);
    
    \Xn_in_ibuf[16]\ : INBUF
      port map(PAD => Xn_in(16), Y => \Xn_in_c[16]\);
    
    \Coef_rdaddr_2[2]\ : CFG4
      generic map(INIT => x"60CC")

      port map(A => \mac_state[1]_net_1\, B => 
        \Coef_rdaddr[2]_net_1\, C => \Coef_rdaddr[1]_net_1\, D
         => \Coef_rdaddr[0]_net_1\, Y => \Coef_rdaddr_2[2]_net_1\);
    
    \Xn_in_ibuf[6]\ : INBUF
      port map(PAD => Xn_in(6), Y => \Xn_in_c[6]\);
    
    \Mac_out[30]\ : SLE
      port map(D => \Yn_out[30]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[30]\);
    
    \inp_wrdata_dly[5]\ : SLE
      port map(D => \inp_wrdata[5]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[5]_net_1\);
    
    \mac_state[4]\ : SLE
      port map(D => \mac_state_ns[1]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \mac_state[4]_net_1\);
    
    \inp_wraddr[0]\ : SLE
      port map(D => \inp_wraddr_i_0[0]\, CLK => clk_c, EN => 
        \Data_Valid_dly\, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wraddr[0]_net_1\);
    
    \Mac_out_obuf[42]\ : OUTBUF
      port map(D => \Mac_out_c[42]\, PAD => Mac_out(42));
    
    \Mac_out_obuf[32]\ : OUTBUF
      port map(D => \Mac_out_c[32]\, PAD => Mac_out(32));
    
    \inp_rdaddr_RNI0S7B[2]\ : CFG4
      generic map(INIT => x"0080")

      port map(A => \inp_rdaddr[0]_net_1\, B => 
        mac_state_1_sqmuxa, C => \inp_rdaddr[2]_net_1\, D => 
        \inp_rdaddr[1]_net_1\, Y => inp_rdaddr_4_sn_N_4_mux);
    
    \Mac_out_obuf[15]\ : OUTBUF
      port map(D => \Mac_out_c[15]\, PAD => Mac_out(15));
    
    Data_Valid_dly : SLE
      port map(D => Data_Valid_c, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Data_Valid_dly\);
    
    \inp_wrdata_dly[0]\ : SLE
      port map(D => \inp_wrdata[0]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[0]_net_1\);
    
    \Mac_out_obuf[36]\ : OUTBUF
      port map(D => \Mac_out_c[36]\, PAD => Mac_out(36));
    
    \Mac_out_obuf[22]\ : OUTBUF
      port map(D => \Mac_out_c[22]\, PAD => Mac_out(22));
    
    \inp_wrdata[5]\ : SLE
      port map(D => \Xn_in_c[5]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[5]_net_1\);
    
    \mac_state[2]\ : SLE
      port map(D => \mac_state_ns[3]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \mac_state[2]_net_1\);
    
    \inp_rdaddr_4[0]\ : CFG4
      generic map(INIT => x"0D08")

      port map(A => \mac_state[0]_net_1\, B => 
        \new_inprdaddr[0]_net_1\, C => inp_rdaddr_4_sn_N_4_mux, D
         => N_47, Y => \inp_rdaddr_4[0]_net_1\);
    
    \inp_wrdata_dly[15]\ : SLE
      port map(D => \inp_wrdata[15]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[15]_net_1\);
    
    Transferdone : SLE
      port map(D => \transferdone8\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Transferdone\);
    
    \Mac_out_obuf[41]\ : OUTBUF
      port map(D => \Mac_out_c[41]\, PAD => Mac_out(41));
    
    \Mac_out[8]\ : SLE
      port map(D => \Yn_out[8]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[8]\);
    
    \mac_state[5]\ : SLE
      port map(D => \mac_state_ns[0]\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => GND_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \mac_state[5]_net_1\);
    
    \Mac_out[31]\ : SLE
      port map(D => \Yn_out[31]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[31]\);
    
    \Mac_out_obuf[31]\ : OUTBUF
      port map(D => \Mac_out_c[31]\, PAD => Mac_out(31));
    
    \inp_rdaddr[0]\ : SLE
      port map(D => \inp_rdaddr_4[0]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_rdaddr[0]_net_1\);
    
    \Mac_out_obuf[26]\ : OUTBUF
      port map(D => \Mac_out_c[26]\, PAD => Mac_out(26));
    
    \mac_state_ns[1]\ : CFG4
      generic map(INIT => x"B3A0")

      port map(A => Filter_En_c, B => Data_Valid_c, C => 
        \mac_state[5]_net_1\, D => \mac_state[4]_net_1\, Y => 
        \mac_state_ns[1]_net_1\);
    
    \Xn_in_ibuf[17]\ : INBUF
      port map(PAD => Xn_in(17), Y => \Xn_in_c[17]\);
    
    \Mac_out[28]\ : SLE
      port map(D => \Yn_out[28]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[28]\);
    
    transferdone8 : CFG4
      generic map(INIT => x"0200")

      port map(A => \rdy_cnt[2]_net_1\, B => \rdy_cnt[1]_net_1\, 
        C => \rdy_cnt[0]_net_1\, D => \mac_state[3]_net_1\, Y => 
        \transferdone8\);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    \Mac_out_obuf[40]\ : OUTBUF
      port map(D => \Mac_out_c[40]\, PAD => Mac_out(40));
    
    \Mac_out_obuf[21]\ : OUTBUF
      port map(D => \Mac_out_c[21]\, PAD => Mac_out(21));
    
    \Xn_in_ibuf[8]\ : INBUF
      port map(PAD => Xn_in(8), Y => \Xn_in_c[8]\);
    
    \Mac_out_obuf[30]\ : OUTBUF
      port map(D => \Mac_out_c[30]\, PAD => Mac_out(30));
    
    \inp_rdaddr_4_RNO[2]\ : CFG4
      generic map(INIT => x"78F0")

      port map(A => \inp_rdaddr[0]_net_1\, B => 
        mac_state_1_sqmuxa, C => \inp_rdaddr[2]_net_1\, D => 
        \inp_rdaddr[1]_net_1\, Y => N_49);
    
    \Mac_out_obuf[1]\ : OUTBUF
      port map(D => \Mac_out_c[1]\, PAD => Mac_out(1));
    
    \inp_wrdata[8]\ : SLE
      port map(D => \Xn_in_c[8]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[8]_net_1\);
    
    \Xn_in_ibuf[10]\ : INBUF
      port map(PAD => Xn_in(10), Y => \Xn_in_c[10]\);
    
    reset_n_ibuf : INBUF
      port map(PAD => reset_n, Y => \reset_n_ibuf\);
    
    \mac_state_ns[4]\ : CFG4
      generic map(INIT => x"FFF8")

      port map(A => Filter_En_c, B => \mac_state[0]_net_1\, C => 
        N_130, D => mac_state_1_sqmuxa, Y => 
        \mac_state_ns[4]_net_1\);
    
    \inp_wrdata[2]\ : SLE
      port map(D => \Xn_in_c[2]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[2]_net_1\);
    
    \Mac_out[13]\ : SLE
      port map(D => \Yn_out[13]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[13]\);
    
    \Mac_out[32]\ : SLE
      port map(D => \Yn_out[32]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[32]\);
    
    \Mac_out_obuf[20]\ : OUTBUF
      port map(D => \Mac_out_c[20]\, PAD => Mac_out(20));
    
    inp_coef_rden_RNO : CFG1
      generic map(INIT => x"1")

      port map(A => N_118, Y => N_118_i_0);
    
    \inp_wraddr_2[1]\ : CFG3
      generic map(INIT => x"1C")

      port map(A => \inp_wraddr[2]_net_1\, B => 
        \inp_wraddr[1]_net_1\, C => \inp_wraddr[0]_net_1\, Y => 
        \inp_wraddr_2[1]_net_1\);
    
    \Mac_out_obuf[18]\ : OUTBUF
      port map(D => \Mac_out_c[18]\, PAD => Mac_out(18));
    
    rdy_sig_RNO : CFG4
      generic map(INIT => x"FFFE")

      port map(A => \mac_state[0]_net_1\, B => \FiltOp_done\, C
         => \mac_state[4]_net_1\, D => \Transferdone\, Y => 
        N_131_i_0);
    
    rdy_obuf : OUTBUF
      port map(D => \rdy_sig\, PAD => rdy);
    
    \Mac_out_obuf[8]\ : OUTBUF
      port map(D => \Mac_out_c[8]\, PAD => Mac_out(8));
    
    \rdy_cnt_RNINCJO[0]\ : CFG3
      generic map(INIT => x"40")

      port map(A => \Transferdone\, B => \rdy_sig\, C => 
        \rdy_cnt[0]_net_1\, Y => CO0_1);
    
    \Mac_out_obuf[14]\ : OUTBUF
      port map(D => \Mac_out_c[14]\, PAD => Mac_out(14));
    
    \Mac_out[7]\ : SLE
      port map(D => \Yn_out[7]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[7]\);
    
    \inp_wrdata[13]\ : SLE
      port map(D => \Xn_in_c[13]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[13]_net_1\);
    
    \Xn_in_ibuf[3]\ : INBUF
      port map(PAD => Xn_in(3), Y => \Xn_in_c[3]\);
    
    \Mac_out_obuf[0]\ : OUTBUF
      port map(D => \Mac_out_c[0]\, PAD => Mac_out(0));
    
    \inp_wraddr[2]\ : SLE
      port map(D => \inp_wraddr_2[2]_net_1\, CLK => clk_c, EN => 
        \Data_Valid_dly\, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wraddr[2]_net_1\);
    
    \Xn_in_ibuf[5]\ : INBUF
      port map(PAD => Xn_in(5), Y => \Xn_in_c[5]\);
    
    \Mac_out[37]\ : SLE
      port map(D => \Yn_out[37]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[37]\);
    
    clrsig : SLE
      port map(D => N_120_i_0, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \clrsig\);
    
    \inp_wrdata[17]\ : SLE
      port map(D => \Xn_in_c[17]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[17]_net_1\);
    
    \Mac_out[5]\ : SLE
      port map(D => \Yn_out[5]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[5]\);
    
    \Mac_out[20]\ : SLE
      port map(D => \Yn_out[20]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[20]\);
    
    \inp_wrdata[1]\ : SLE
      port map(D => \Xn_in_c[1]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[1]_net_1\);
    
    \Mac_out_obuf[7]\ : OUTBUF
      port map(D => \Mac_out_c[7]\, PAD => Mac_out(7));
    
    \Mac_out[40]\ : SLE
      port map(D => \Yn_out[40]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[40]\);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \inp_wrdata[15]\ : SLE
      port map(D => \Xn_in_c[15]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[15]_net_1\);
    
    \inp_wrdata[16]\ : SLE
      port map(D => \Xn_in_c[16]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[16]_net_1\);
    
    \Mac_out_obuf[37]\ : OUTBUF
      port map(D => \Mac_out_c[37]\, PAD => Mac_out(37));
    
    \Coef_rdaddr_2[0]\ : CFG4
      generic map(INIT => x"51AA")

      port map(A => \mac_state[1]_net_1\, B => 
        \Coef_rdaddr[2]_net_1\, C => \Coef_rdaddr[1]_net_1\, D
         => \Coef_rdaddr[0]_net_1\, Y => \Coef_rdaddr_2[0]_net_1\);
    
    \Mac_out[36]\ : SLE
      port map(D => \Yn_out[36]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[36]\);
    
    \inp_wrdata_dly[3]\ : SLE
      port map(D => \inp_wrdata[3]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[3]_net_1\);
    
    \inp_wrdata_dly[2]\ : SLE
      port map(D => \inp_wrdata[2]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[2]_net_1\);
    
    \inp_rdaddr_4[1]\ : CFG4
      generic map(INIT => x"0D08")

      port map(A => \mac_state[0]_net_1\, B => 
        \new_inprdaddr[1]_net_1\, C => inp_rdaddr_4_sn_N_4_mux, D
         => N_48, Y => \inp_rdaddr_4[1]_net_1\);
    
    FiltOp_done : SLE
      port map(D => \op_eq.filtop_done3_net_1\, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \FiltOp_done\);
    
    \inp_rdaddr_4_RNO[1]\ : CFG3
      generic map(INIT => x"78")

      port map(A => \inp_rdaddr[0]_net_1\, B => 
        mac_state_1_sqmuxa, C => \inp_rdaddr[1]_net_1\, Y => N_48);
    
    \Mac_out_obuf[39]\ : OUTBUF
      port map(D => \Mac_out_c[39]\, PAD => Mac_out(39));
    
    \Mac_out_obuf[27]\ : OUTBUF
      port map(D => \Mac_out_c[27]\, PAD => Mac_out(27));
    
    \Mac_out[18]\ : SLE
      port map(D => \Yn_out[18]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[18]\);
    
    \new_inprdaddr_2[2]\ : CFG3
      generic map(INIT => x"4A")

      port map(A => \new_inprdaddr[2]_net_1\, B => 
        \new_inprdaddr[1]_net_1\, C => \new_inprdaddr[0]_net_1\, 
        Y => \new_inprdaddr_2[2]_net_1\);
    
    reset_n_ibuf_RNILECB : CLKINT
      port map(A => \reset_n_ibuf\, Y => reset_n_c);
    
    \Mac_out[21]\ : SLE
      port map(D => \Yn_out[21]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[21]\);
    
    \Mac_out[6]\ : SLE
      port map(D => \Yn_out[6]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[6]\);
    
    \Mac_out_obuf[43]\ : OUTBUF
      port map(D => \Mac_out_c[43]\, PAD => Mac_out(43));
    
    \Mac_out_obuf[29]\ : OUTBUF
      port map(D => \Mac_out_c[29]\, PAD => Mac_out(29));
    
    \Mac_out_obuf[33]\ : OUTBUF
      port map(D => \Mac_out_c[33]\, PAD => Mac_out(33));
    
    \Xn_in_ibuf[11]\ : INBUF
      port map(PAD => Xn_in(11), Y => \Xn_in_c[11]\);
    
    \Mac_out[41]\ : SLE
      port map(D => \Yn_out[41]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[41]\);
    
    \inp_wrdata[4]\ : SLE
      port map(D => \Xn_in_c[4]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[4]_net_1\);
    
    \inp_wrdata_dly[17]\ : SLE
      port map(D => \inp_wrdata[17]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[17]_net_1\);
    
    \Mac_out_obuf[23]\ : OUTBUF
      port map(D => \Mac_out_c[23]\, PAD => Mac_out(23));
    
    \Mac_out_obuf[2]\ : OUTBUF
      port map(D => \Mac_out_c[2]\, PAD => Mac_out(2));
    
    \inp_wrdata[9]\ : SLE
      port map(D => \Xn_in_c[9]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[9]_net_1\);
    
    clk_ibuf : INBUF
      port map(PAD => clk, Y => \clk_ibuf\);
    
    \Mac_out[35]\ : SLE
      port map(D => \Yn_out[35]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[35]\);
    
    \Mac_out_obuf[12]\ : OUTBUF
      port map(D => \Mac_out_c[12]\, PAD => Mac_out(12));
    
    \inp_wrdata[11]\ : SLE
      port map(D => \Xn_in_c[11]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[11]_net_1\);
    
    \Mac_out[22]\ : SLE
      port map(D => \Yn_out[22]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[22]\);
    
    \Mac_out[2]\ : SLE
      port map(D => \Yn_out[2]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[2]\);
    
    \mac_state_ns_a2_1[0]\ : CFG2
      generic map(INIT => x"1")

      port map(A => \mac_state[2]_net_1\, B => 
        \mac_state[4]_net_1\, Y => \mac_state_ns_a2_1[0]_net_1\);
    
    clr : SLE
      port map(D => \clrsig\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \clr\);
    
    \new_inprdaddr_2[1]\ : CFG3
      generic map(INIT => x"1C")

      port map(A => \new_inprdaddr[2]_net_1\, B => 
        \new_inprdaddr[1]_net_1\, C => \new_inprdaddr[0]_net_1\, 
        Y => \new_inprdaddr_2[1]_net_1\);
    
    \mac_state_ns_a2_0[4]\ : CFG3
      generic map(INIT => x"20")

      port map(A => \Data_Valid_dly\, B => Data_Valid_c, C => 
        \mac_state[2]_net_1\, Y => N_130);
    
    \Mac_out[42]\ : SLE
      port map(D => \Yn_out[42]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[42]\);
    
    \Mac_out[34]\ : SLE
      port map(D => \Yn_out[34]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[34]\);
    
    \Mac_out_obuf[16]\ : OUTBUF
      port map(D => \Mac_out_c[16]\, PAD => Mac_out(16));
    
    \mac_state_ns[2]\ : CFG4
      generic map(INIT => x"F222")

      port map(A => \mac_state[3]_net_1\, B => \Transferdone\, C
         => Data_Valid_c, D => \mac_state[4]_net_1\, Y => 
        \mac_state_ns[2]_net_1\);
    
    \Xn_in_ibuf[15]\ : INBUF
      port map(PAD => Xn_in(15), Y => \Xn_in_c[15]\);
    
    \Mac_out_obuf[4]\ : OUTBUF
      port map(D => \Mac_out_c[4]\, PAD => Mac_out(4));
    
    \Mac_out_obuf[11]\ : OUTBUF
      port map(D => \Mac_out_c[11]\, PAD => Mac_out(11));
    
    \inp_wrdata[10]\ : SLE
      port map(D => \Xn_in_c[10]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[10]_net_1\);
    
    \inp_wrdata_dly[7]\ : SLE
      port map(D => \inp_wrdata[7]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[7]_net_1\);
    
    \Xn_in_ibuf[7]\ : INBUF
      port map(PAD => Xn_in(7), Y => \Xn_in_c[7]\);
    
    \mac_state_ns_a2[0]\ : CFG4
      generic map(INIT => x"0100")

      port map(A => Filter_En_c, B => \mac_state[3]_net_1\, C => 
        \mac_state[1]_net_1\, D => \mac_state_ns_a2_1[0]_net_1\, 
        Y => \mac_state_ns[0]\);
    
    mac_state_1_sqmuxa_0_a2 : CFG2
      generic map(INIT => x"4")

      port map(A => \FiltOp_done\, B => \mac_state[1]_net_1\, Y
         => mac_state_1_sqmuxa);
    
    \Mac_out[39]\ : SLE
      port map(D => \Yn_out[39]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[39]\);
    
    \Mac_out[10]\ : SLE
      port map(D => \Yn_out[10]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[10]\);
    
    \Mac_out_obuf[10]\ : OUTBUF
      port map(D => \Mac_out_c[10]\, PAD => Mac_out(10));
    
    \Mac_out[27]\ : SLE
      port map(D => \Yn_out[27]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[27]\);
    
    \Mac_out[1]\ : SLE
      port map(D => \Yn_out[1]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[1]\);
    
    \new_inprdaddr[1]\ : SLE
      port map(D => \new_inprdaddr_2[1]_net_1\, CLK => clk_c, EN
         => \FiltOp_done\, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \new_inprdaddr[1]_net_1\);
    
    \inp_rdaddr_4[2]\ : CFG4
      generic map(INIT => x"0D08")

      port map(A => \mac_state[0]_net_1\, B => 
        \new_inprdaddr[2]_net_1\, C => inp_rdaddr_4_sn_N_4_mux, D
         => N_49, Y => \inp_rdaddr_4[2]_net_1\);
    
    \inp_wrdata_dly[13]\ : SLE
      port map(D => \inp_wrdata[13]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[13]_net_1\);
    
    \Mac_out_obuf[5]\ : OUTBUF
      port map(D => \Mac_out_c[5]\, PAD => Mac_out(5));
    
    \mac_state[3]\ : SLE
      port map(D => \mac_state_ns[2]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \mac_state[3]_net_1\);
    
    \inp_wrdata_dly[12]\ : SLE
      port map(D => \inp_wrdata[12]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[12]_net_1\);
    
    \inp_wrdata_dly[11]\ : SLE
      port map(D => \inp_wrdata[11]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[11]_net_1\);
    
    \inp_wrdata[6]\ : SLE
      port map(D => \Xn_in_c[6]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[6]_net_1\);
    
    \Mac_out[3]\ : SLE
      port map(D => \Yn_out[3]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[3]\);
    
    \inp_wrdata_dly[16]\ : SLE
      port map(D => \inp_wrdata[16]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[16]_net_1\);
    
    \rdy_cnt[2]\ : SLE
      port map(D => \rdy_cnt_3[2]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \rdy_cnt[2]_net_1\);
    
    \new_inprdaddr[2]\ : SLE
      port map(D => \new_inprdaddr_2[2]_net_1\, CLK => clk_c, EN
         => \FiltOp_done\, ALn => reset_n_c, ADn => VCC_net_1, 
        SLn => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q
         => \new_inprdaddr[2]_net_1\);
    
    \inp_wrdata_dly[4]\ : SLE
      port map(D => \inp_wrdata[4]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[4]_net_1\);
    
    \Mac_out[26]\ : SLE
      port map(D => \Yn_out[26]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[26]\);
    
    clk_ibuf_RNIVTI2 : CLKINT
      port map(A => \clk_ibuf\, Y => clk_c);
    
    \Mac_out[11]\ : SLE
      port map(D => \Yn_out[11]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[11]\);
    
    \inp_rdaddr[1]\ : SLE
      port map(D => \inp_rdaddr_4[1]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_rdaddr[1]_net_1\);
    
    \inp_wraddr_2[2]\ : CFG3
      generic map(INIT => x"4A")

      port map(A => \inp_wraddr[2]_net_1\, B => 
        \inp_wraddr[1]_net_1\, C => \inp_wraddr[0]_net_1\, Y => 
        \inp_wraddr_2[2]_net_1\);
    
    \inp_wrdata[3]\ : SLE
      port map(D => \Xn_in_c[3]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[3]_net_1\);
    
    \inp_rdaddr[2]\ : SLE
      port map(D => \inp_rdaddr_4[2]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_rdaddr[2]_net_1\);
    
    \inp_wrdata[0]\ : SLE
      port map(D => \Xn_in_c[0]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[0]_net_1\);
    
    \inp_wrdata_dly[14]\ : SLE
      port map(D => \inp_wrdata[14]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[14]_net_1\);
    
    \Xn_in_ibuf[13]\ : INBUF
      port map(PAD => Xn_in(13), Y => \Xn_in_c[13]\);
    
    clrsig_RNO : CFG2
      generic map(INIT => x"E")

      port map(A => \mac_state[0]_net_1\, B => 
        \mac_state[2]_net_1\, Y => N_120_i_0);
    
    \Mac_out[12]\ : SLE
      port map(D => \Yn_out[12]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[12]\);
    
    \Mac_out[4]\ : SLE
      port map(D => \Yn_out[4]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[4]\);
    
    \Xn_in_ibuf[9]\ : INBUF
      port map(PAD => Xn_in(9), Y => \Xn_in_c[9]\);
    
    \inp_wrdata[12]\ : SLE
      port map(D => \Xn_in_c[12]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[12]_net_1\);
    
    \Mac_out[25]\ : SLE
      port map(D => \Yn_out[25]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[25]\);
    
    \Xn_in_ibuf[4]\ : INBUF
      port map(PAD => Xn_in(4), Y => \Xn_in_c[4]\);
    
    \Mac_out_obuf[17]\ : OUTBUF
      port map(D => \Mac_out_c[17]\, PAD => Mac_out(17));
    
    \inp_wrdata_dly[6]\ : SLE
      port map(D => \inp_wrdata[6]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[6]_net_1\);
    
    \rdy_cnt_3[2]\ : CFG4
      generic map(INIT => x"060A")

      port map(A => \rdy_cnt[2]_net_1\, B => \rdy_cnt[1]_net_1\, 
        C => \Transferdone\, D => CO0_1, Y => 
        \rdy_cnt_3[2]_net_1\);
    
    \Mac_out[24]\ : SLE
      port map(D => \Yn_out[24]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[24]\);
    
    \Mac_out_obuf[19]\ : OUTBUF
      port map(D => \Mac_out_c[19]\, PAD => Mac_out(19));
    
    \Xn_in_ibuf[0]\ : INBUF
      port map(PAD => Xn_in(0), Y => \Xn_in_c[0]\);
    
    \Mac_out[33]\ : SLE
      port map(D => \Yn_out[33]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[33]\);
    
    \inp_wraddr_RNO[0]\ : CFG1
      generic map(INIT => x"1")

      port map(A => \inp_wraddr[0]_net_1\, Y => 
        \inp_wraddr_i_0[0]\);
    
    \Mac_out_obuf[35]\ : OUTBUF
      port map(D => \Mac_out_c[35]\, PAD => Mac_out(35));
    
    \Mac_out[9]\ : SLE
      port map(D => \Yn_out[9]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[9]\);
    
    \inp_wrdata[14]\ : SLE
      port map(D => \Xn_in_c[14]\, CLK => clk_c, EN => 
        Data_Valid_c, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata[14]_net_1\);
    
    \Mac_out_obuf[13]\ : OUTBUF
      port map(D => \Mac_out_c[13]\, PAD => Mac_out(13));
    
    U2 : Inp_RAM
      port map(inp_rddata(17) => \inp_rddata[17]\, inp_rddata(16)
         => \inp_rddata[16]\, inp_rddata(15) => \inp_rddata[15]\, 
        inp_rddata(14) => \inp_rddata[14]\, inp_rddata(13) => 
        \inp_rddata[13]\, inp_rddata(12) => \inp_rddata[12]\, 
        inp_rddata(11) => \inp_rddata[11]\, inp_rddata(10) => 
        \inp_rddata[10]\, inp_rddata(9) => \inp_rddata[9]\, 
        inp_rddata(8) => \inp_rddata[8]\, inp_rddata(7) => 
        \inp_rddata[7]\, inp_rddata(6) => \inp_rddata[6]\, 
        inp_rddata(5) => \inp_rddata[5]\, inp_rddata(4) => 
        \inp_rddata[4]\, inp_rddata(3) => \inp_rddata[3]\, 
        inp_rddata(2) => \inp_rddata[2]\, inp_rddata(1) => 
        \inp_rddata[1]\, inp_rddata(0) => \inp_rddata[0]\, 
        inp_rdaddr(2) => \inp_rdaddr[2]_net_1\, inp_rdaddr(1) => 
        \inp_rdaddr[1]_net_1\, inp_rdaddr(0) => 
        \inp_rdaddr[0]_net_1\, inp_wraddr(2) => 
        \inp_wraddr[2]_net_1\, inp_wraddr(1) => 
        \inp_wraddr[1]_net_1\, inp_wraddr(0) => 
        \inp_wraddr[0]_net_1\, inp_wrdata_dly(17) => 
        \inp_wrdata_dly[17]_net_1\, inp_wrdata_dly(16) => 
        \inp_wrdata_dly[16]_net_1\, inp_wrdata_dly(15) => 
        \inp_wrdata_dly[15]_net_1\, inp_wrdata_dly(14) => 
        \inp_wrdata_dly[14]_net_1\, inp_wrdata_dly(13) => 
        \inp_wrdata_dly[13]_net_1\, inp_wrdata_dly(12) => 
        \inp_wrdata_dly[12]_net_1\, inp_wrdata_dly(11) => 
        \inp_wrdata_dly[11]_net_1\, inp_wrdata_dly(10) => 
        \inp_wrdata_dly[10]_net_1\, inp_wrdata_dly(9) => 
        \inp_wrdata_dly[9]_net_1\, inp_wrdata_dly(8) => 
        \inp_wrdata_dly[8]_net_1\, inp_wrdata_dly(7) => 
        \inp_wrdata_dly[7]_net_1\, inp_wrdata_dly(6) => 
        \inp_wrdata_dly[6]_net_1\, inp_wrdata_dly(5) => 
        \inp_wrdata_dly[5]_net_1\, inp_wrdata_dly(4) => 
        \inp_wrdata_dly[4]_net_1\, inp_wrdata_dly(3) => 
        \inp_wrdata_dly[3]_net_1\, inp_wrdata_dly(2) => 
        \inp_wrdata_dly[2]_net_1\, inp_wrdata_dly(1) => 
        \inp_wrdata_dly[1]_net_1\, inp_wrdata_dly(0) => 
        \inp_wrdata_dly[0]_net_1\, clk_c => clk_c, inp_coef_rden
         => \inp_coef_rden\, Data_Valid_dly => \Data_Valid_dly\);
    
    \inp_wraddr[1]\ : SLE
      port map(D => \inp_wraddr_2[1]_net_1\, CLK => clk_c, EN => 
        \Data_Valid_dly\, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wraddr[1]_net_1\);
    
    \Mac_out[17]\ : SLE
      port map(D => \Yn_out[17]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[17]\);
    
    \Mac_out_obuf[25]\ : OUTBUF
      port map(D => \Mac_out_c[25]\, PAD => Mac_out(25));
    
    \Mac_out[29]\ : SLE
      port map(D => \Yn_out[29]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[29]\);
    
    U0 : mulacc_18x18
      port map(Yn_out(43) => \Yn_out[43]\, Yn_out(42) => 
        \Yn_out[42]\, Yn_out(41) => \Yn_out[41]\, Yn_out(40) => 
        \Yn_out[40]\, Yn_out(39) => \Yn_out[39]\, Yn_out(38) => 
        \Yn_out[38]\, Yn_out(37) => \Yn_out[37]\, Yn_out(36) => 
        \Yn_out[36]\, Yn_out(35) => \Yn_out[35]\, Yn_out(34) => 
        \Yn_out[34]\, Yn_out(33) => \Yn_out[33]\, Yn_out(32) => 
        \Yn_out[32]\, Yn_out(31) => \Yn_out[31]\, Yn_out(30) => 
        \Yn_out[30]\, Yn_out(29) => \Yn_out[29]\, Yn_out(28) => 
        \Yn_out[28]\, Yn_out(27) => \Yn_out[27]\, Yn_out(26) => 
        \Yn_out[26]\, Yn_out(25) => \Yn_out[25]\, Yn_out(24) => 
        \Yn_out[24]\, Yn_out(23) => \Yn_out[23]\, Yn_out(22) => 
        \Yn_out[22]\, Yn_out(21) => \Yn_out[21]\, Yn_out(20) => 
        \Yn_out[20]\, Yn_out(19) => \Yn_out[19]\, Yn_out(18) => 
        \Yn_out[18]\, Yn_out(17) => \Yn_out[17]\, Yn_out(16) => 
        \Yn_out[16]\, Yn_out(15) => \Yn_out[15]\, Yn_out(14) => 
        \Yn_out[14]\, Yn_out(13) => \Yn_out[13]\, Yn_out(12) => 
        \Yn_out[12]\, Yn_out(11) => \Yn_out[11]\, Yn_out(10) => 
        \Yn_out[10]\, Yn_out(9) => \Yn_out[9]\, Yn_out(8) => 
        \Yn_out[8]\, Yn_out(7) => \Yn_out[7]\, Yn_out(6) => 
        \Yn_out[6]\, Yn_out(5) => \Yn_out[5]\, Yn_out(4) => 
        \Yn_out[4]\, Yn_out(3) => \Yn_out[3]\, Yn_out(2) => 
        \Yn_out[2]\, Yn_out(1) => \Yn_out[1]\, Yn_out(0) => 
        \Yn_out[0]\, inp_rddata(17) => \inp_rddata[17]\, 
        inp_rddata(16) => \inp_rddata[16]\, inp_rddata(15) => 
        \inp_rddata[15]\, inp_rddata(14) => \inp_rddata[14]\, 
        inp_rddata(13) => \inp_rddata[13]\, inp_rddata(12) => 
        \inp_rddata[12]\, inp_rddata(11) => \inp_rddata[11]\, 
        inp_rddata(10) => \inp_rddata[10]\, inp_rddata(9) => 
        \inp_rddata[9]\, inp_rddata(8) => \inp_rddata[8]\, 
        inp_rddata(7) => \inp_rddata[7]\, inp_rddata(6) => 
        \inp_rddata[6]\, inp_rddata(5) => \inp_rddata[5]\, 
        inp_rddata(4) => \inp_rddata[4]\, inp_rddata(3) => 
        \inp_rddata[3]\, inp_rddata(2) => \inp_rddata[2]\, 
        inp_rddata(1) => \inp_rddata[1]\, inp_rddata(0) => 
        \inp_rddata[0]\, Coef_rddata(17) => \Coef_rddata[17]\, 
        Coef_rddata(16) => \Coef_rddata[16]\, Coef_rddata(15) => 
        \Coef_rddata[15]\, Coef_rddata(14) => \Coef_rddata[14]\, 
        Coef_rddata(13) => \Coef_rddata[13]\, Coef_rddata(12) => 
        \Coef_rddata[12]\, Coef_rddata(11) => \Coef_rddata[11]\, 
        Coef_rddata(10) => \Coef_rddata[10]\, Coef_rddata(9) => 
        \Coef_rddata[9]\, Coef_rddata(8) => \Coef_rddata[8]\, 
        Coef_rddata(7) => \Coef_rddata[7]\, Coef_rddata(6) => 
        \Coef_rddata[6]\, Coef_rddata(5) => \Coef_rddata[5]\, 
        Coef_rddata(4) => \Coef_rddata[4]\, Coef_rddata(3) => 
        \Coef_rddata[3]\, Coef_rddata(2) => \Coef_rddata[2]\, 
        Coef_rddata(1) => \Coef_rddata[1]\, Coef_rddata(0) => 
        \Coef_rddata[0]\, reset_n_c => reset_n_c, clk_c => clk_c);
    
    \Mac_out_obuf[6]\ : OUTBUF
      port map(D => \Mac_out_c[6]\, PAD => Mac_out(6));
    
    \Xn_in_ibuf[1]\ : INBUF
      port map(PAD => Xn_in(1), Y => \Xn_in_c[1]\);
    
    \rdy_cnt_RNO[1]\ : CFG2
      generic map(INIT => x"6")

      port map(A => CO0_1, B => \rdy_cnt[1]_net_1\, Y => 
        \rdy_cnt_RNO[1]_net_1\);
    
    \inp_wrdata_dly[8]\ : SLE
      port map(D => \inp_wrdata[8]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[8]_net_1\);
    
    \Mac_out_obuf[3]\ : OUTBUF
      port map(D => \Mac_out_c[3]\, PAD => Mac_out(3));
    
    \Mac_out[16]\ : SLE
      port map(D => \Yn_out[16]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[16]\);
    
    \Xn_in_ibuf[2]\ : INBUF
      port map(PAD => Xn_in(2), Y => \Xn_in_c[2]\);
    
    \new_inprdaddr_RNO[0]\ : CFG1
      generic map(INIT => x"1")

      port map(A => \new_inprdaddr[0]_net_1\, Y => 
        \new_inprdaddr_i_0[0]\);
    
    \Mac_out_obuf[9]\ : OUTBUF
      port map(D => \Mac_out_c[9]\, PAD => Mac_out(9));
    
    U1 : Coef_RAM
      port map(Coef_rddata(17) => \Coef_rddata[17]\, 
        Coef_rddata(16) => \Coef_rddata[16]\, Coef_rddata(15) => 
        \Coef_rddata[15]\, Coef_rddata(14) => \Coef_rddata[14]\, 
        Coef_rddata(13) => \Coef_rddata[13]\, Coef_rddata(12) => 
        \Coef_rddata[12]\, Coef_rddata(11) => \Coef_rddata[11]\, 
        Coef_rddata(10) => \Coef_rddata[10]\, Coef_rddata(9) => 
        \Coef_rddata[9]\, Coef_rddata(8) => \Coef_rddata[8]\, 
        Coef_rddata(7) => \Coef_rddata[7]\, Coef_rddata(6) => 
        \Coef_rddata[6]\, Coef_rddata(5) => \Coef_rddata[5]\, 
        Coef_rddata(4) => \Coef_rddata[4]\, Coef_rddata(3) => 
        \Coef_rddata[3]\, Coef_rddata(2) => \Coef_rddata[2]\, 
        Coef_rddata(1) => \Coef_rddata[1]\, Coef_rddata(0) => 
        \Coef_rddata[0]\, Coef_rdaddr(2) => 
        \Coef_rdaddr[2]_net_1\, Coef_rdaddr(1) => 
        \Coef_rdaddr[1]_net_1\, Coef_rdaddr(0) => 
        \Coef_rdaddr[0]_net_1\, clk_c => clk_c, inp_coef_rden => 
        \inp_coef_rden\);
    
    \new_inprdaddr[0]\ : SLE
      port map(D => \new_inprdaddr_i_0[0]\, CLK => clk_c, EN => 
        \FiltOp_done\, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \new_inprdaddr[0]_net_1\);
    
    \rdy_cnt[1]\ : SLE
      port map(D => \rdy_cnt_RNO[1]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \rdy_cnt[1]_net_1\);
    
    Initdone_0_o2 : CFG2
      generic map(INIT => x"D")

      port map(A => \Data_Valid_dly\, B => Data_Valid_c, Y => 
        N_118);
    
    \op_eq.filtop_done3\ : CFG3
      generic map(INIT => x"02")

      port map(A => \Coef_rdaddr[2]_net_1\, B => 
        \Coef_rdaddr[1]_net_1\, C => \Coef_rdaddr[0]_net_1\, Y
         => \op_eq.filtop_done3_net_1\);
    
    \mac_state_ns[3]\ : CFG4
      generic map(INIT => x"ECA0")

      port map(A => \mac_state[3]_net_1\, B => 
        \mac_state[2]_net_1\, C => \Transferdone\, D => N_118, Y
         => \mac_state_ns[3]_net_1\);
    
    \mac_state_RNO[0]\ : CFG2
      generic map(INIT => x"8")

      port map(A => \FiltOp_done\, B => \mac_state[1]_net_1\, Y
         => N_112_i_0);
    
    \Mac_out_obuf[38]\ : OUTBUF
      port map(D => \Mac_out_c[38]\, PAD => Mac_out(38));
    
    \Mac_out[0]\ : SLE
      port map(D => \Yn_out[0]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[0]\);
    
    \Coef_rdaddr_RNO[1]\ : CFG4
      generic map(INIT => x"52F0")

      port map(A => \mac_state[1]_net_1\, B => 
        \Coef_rdaddr[2]_net_1\, C => \Coef_rdaddr[1]_net_1\, D
         => \Coef_rdaddr[0]_net_1\, Y => 
        \Coef_rdaddr_RNO[1]_net_1\);
    
    \Mac_out[15]\ : SLE
      port map(D => \Yn_out[15]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[15]\);
    
    Filter_En_ibuf : INBUF
      port map(PAD => Filter_En, Y => Filter_En_c);
    
    rdy_sig : SLE
      port map(D => N_132, CLK => clk_c, EN => N_131_i_0, ALn => 
        reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \rdy_sig\);
    
    \Mac_out_obuf[34]\ : OUTBUF
      port map(D => \Mac_out_c[34]\, PAD => Mac_out(34));
    
    \Mac_out[38]\ : SLE
      port map(D => \Yn_out[38]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[38]\);
    
    \mac_state[0]\ : SLE
      port map(D => N_112_i_0, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \mac_state[0]_net_1\);
    
    \Mac_out_obuf[28]\ : OUTBUF
      port map(D => \Mac_out_c[28]\, PAD => Mac_out(28));
    
    \inp_wrdata_dly[10]\ : SLE
      port map(D => \inp_wrdata[10]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[10]_net_1\);
    
    \mac_state[1]\ : SLE
      port map(D => \mac_state_ns[4]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \mac_state[1]_net_1\);
    
    Data_Valid_ibuf : INBUF
      port map(PAD => Data_Valid, Y => Data_Valid_c);
    
    \Xn_in_ibuf[14]\ : INBUF
      port map(PAD => Xn_in(14), Y => \Xn_in_c[14]\);
    
    \Mac_out[14]\ : SLE
      port map(D => \Yn_out[14]\, CLK => clk_c, EN => \clr\, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Mac_out_c[14]\);
    
    \rdy_cnt[0]\ : SLE
      port map(D => \rdy_cnt_3[0]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \rdy_cnt[0]_net_1\);
    
    \rdy_cnt_3[0]\ : CFG3
      generic map(INIT => x"14")

      port map(A => \Transferdone\, B => \rdy_sig\, C => 
        \rdy_cnt[0]_net_1\, Y => \rdy_cnt_3[0]_net_1\);
    
    \Mac_out_obuf[24]\ : OUTBUF
      port map(D => \Mac_out_c[24]\, PAD => Mac_out(24));
    
    \inp_wrdata_dly[1]\ : SLE
      port map(D => \inp_wrdata[1]_net_1\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \inp_wrdata_dly[1]_net_1\);
    
    un1_Transferdone_1_0_a2 : CFG2
      generic map(INIT => x"1")

      port map(A => \Transferdone\, B => \mac_state[0]_net_1\, Y
         => N_132);
    
    \Coef_rdaddr[0]\ : SLE
      port map(D => \Coef_rdaddr_2[0]_net_1\, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rdaddr[0]_net_1\);
    
    \Coef_rdaddr[1]\ : SLE
      port map(D => \Coef_rdaddr_RNO[1]_net_1\, CLK => clk_c, EN
         => VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn
         => VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Coef_rdaddr[1]_net_1\);
    

end DEF_ARCH; 
