@W: CD275 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_3_input\component\work\dotp_multadd1\dotp_multadd1_0\dotp_multadd1_dotp_multadd1_0_HARD_MULT_ADDSUB.vhd":25:12:25:15|Component declarations with different initial values are not supported.  Port cdin of component macc may have been given a different initial value in two different component declarations
@W: CL279 :"D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Extended Adder\Extended_adder_3_input\hdl\Extended_adder_3_input.vhd":200:2:200:3|Pruning register bits 8 to 3 of Res_Upper_reg(8 downto 0)  

