----------------------------------------------------------------------
-- Created by Actel SmartDesign Thu Oct 31 19:31:29 2013
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic 
-- clock and reset pins connected.  If your design has special
-- clock/reset or testbench driver requirements then you should 
-- copy this file and modify it. 
----------------------------------------------------------------------

--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: Transpose_FIR_testbench.vhd
-- File history:

-- Description: 
--
-- <Description here>
--
-- Targeted device: <Family::SmartFusion2> <Die::M2S050> <Package::896 FBGA>
-- Author: <Name>
--
--------------------------------------------------------------------------------


library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;


entity Transpose_FIR_testbench is
end Transpose_FIR_testbench;


architecture testbench_arch of Transpose_FIR_testbench is

component Transpose_FIR is
generic (
			N 	: integer := 16
		);
port (
    	Clk 	: in std_logic;
    	resetn	: in std_logic;
		Xn_in	: in std_logic_vector(17 downto 0);
		FIR_O	: out std_logic_vector(43 downto 0)	 
);
end component Transpose_FIR;

CONSTANT clk_period : time := 10 ns;

signal clk		: STD_LOGIC:= '0';
signal reset_n	: STD_LOGIC:= '0';

signal Xn_in	: STD_LOGIC_VECTOR(17 downto 0)	:= (OTHERS=> '0');
signal CDIN		: STD_LOGIC_VECTOR(43 downto 0) := (OTHERS=> '0');
signal FIR_O	: STD_LOGIC_VECTOR(43 downto 0);
SIGNAL stop 	: std_logic := '0';	


begin


UUT: Transpose_FIR
		generic map( N => 16)
		port map(	
				clk 	=> clk,
				resetn  => reset_n,
				Xn_in 	=> Xn_in,
				
				FIR_O	=> FIR_O
         );

--- clock and reset generation 

 clk_proc :process
   begin
		IF(stop = '0')THEN
	        clk <= '0';
    	    wait for clk_period/2;
        	clk <= '1';
	        wait for clk_period/2;
		ELSE
			clk <= '0';
		END IF;
   end process;

  stim_proc: process
   begin

        reset_n 	<='0';
        wait for 20 ns;
        reset_n	<='1';
        wait;
  end process;


-- Data vectors to 8-Tap FIR filter


	Stim_data: process(clk,reset_n)
	begin
		if(reset_n ='0')then
			Xn_in <=(others => '0');
		else
			if(clk='1' and clk'event)then
				if(stop = '0')then
					Xn_in <= Xn_in + '1';
				end if;
			end if;
		end if;
	end process;



	process
	begin
			wait until (Xn_in = "001100100");
			wait until rising_edge(clk);
				stop <=  '1';
		
			report "TEST FINISHED!"
			severity failure;

	end process;


end testbench_arch;
