`

    Synopsys Generic Technology Mapper, Version mapact, Build 976R, Built May 23 2013 12:10:32
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version H-2013.03M-1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 57MB)

    @N:MF249 :  | Running in 32-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 58MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 60MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)

    Encoding state machine mac_state[0:5] (view:work.MAC_FIR(mac_fir_arch))
    original code -> new code
       000001 -> 000001
       000010 -> 000010
       000100 -> 000100
       001000 -> 001000
       010000 -> 010000
       100000 -> 100000
    @N: : mac_fir.vhd(433) | Found counter in view:work.MAC_FIR(mac_fir_arch) inst inp_rdaddr[7:0]

    Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)

    Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 77MB peak: 79MB)

    Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 77MB peak: 79MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:01s		    -3.47ns		 189 /       216
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:01s		    -3.47ns		 189 /       216
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:01s		    -3.47ns		 189 /       216
    ------------------------------------------------------------

    @N:FP130 :  | Promoting Net clk_c on CLKINT  I_220
    @N:FP130 :  | Promoting Net reset_n_c on CLKINT  I_221

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 77MB peak: 79MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 77MB peak: 79MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    1 non-gated/non-generated clock tree(s) driving 218 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId0001       clk                 port                   218        inp_wraddr[0]
    =======================================================================================
    ===== Gated/Generated Clocks =====
    ************** None **************
    ----------------------------------
    ==================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Writing Analyst data base D:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Filters\Single MAC FIR Filters\MAC FIR 16-tap\MAC_FIR\synthesis\MAC_FIR.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 77MB peak: 79MB)

    Writing EDIF Netlist and constraint files
    H-2013.03M-1

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 78MB peak: 79MB)

    @W:MT246 : inp_ram1_inp_ram1_0_uram.vhd(89) | Blackbox RAM64x18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock MAC_FIR|clk with period 2.99ns. Please declare a user-defined clock on object "p:clk"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed Nov 06 13:26:25 2013
    #

    Top view:               MAC_FIR
    Requested Frequency:    334.7 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: -0.527

                       Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group
    ------------------------------------------------------------------------------------------------------------------------
    MAC_FIR|clk        334.7 MHz     284.5 MHz     2.988         3.515         -0.527     inferred     Autoconstr_clkgroup_0
    System             1.0 MHz       1.0 MHz       1000.000      998.526       1.474      system       system_clkgroup
    ========================================================================================================================

    Clock Relationships
    *******************

    Clocks                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -----------------------------------------------------------------------------------------------------------------
    Starting     Ending       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    -----------------------------------------------------------------------------------------------------------------
    System       MAC_FIR|clk  |  2.988       1.474   |  No paths    -      |  No paths    -      |  No paths    -
    MAC_FIR|clk  System       |  2.988       0.373   |  No paths    -      |  No paths    -      |  No paths    -
    MAC_FIR|clk  MAC_FIR|clk  |  2.988       -0.527  |  No paths    -      |  No paths    -      |  No paths    -
    =================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: MAC_FIR|clk
    ====================================

    Starting Points with Worst Slack
    ********************************

                         Starting                                              Arrival
    Instance             Reference       Type     Pin     Net                  Time        Slack
                         Clock
    ---------------------------------------------------------------------------------------------
    inp_wraddr[6]        MAC_FIR|clk     SLE      Q       inp_wraddr[6]        0.094       -0.527
    new_inprdaddr[4]     MAC_FIR|clk     SLE      Q       new_inprdaddr[4]     0.076       -0.433
    inp_wraddr[5]        MAC_FIR|clk     SLE      Q       inp_wraddr[5]        0.094       -0.418
    inp_wraddr[0]        MAC_FIR|clk     SLE      Q       inp_wraddr[0]        0.076       -0.401
    Coef_rdaddr[1]       MAC_FIR|clk     SLE      Q       Coef_rdaddr[1]       0.094       -0.318
    Coef_rdaddr[0]       MAC_FIR|clk     SLE      Q       Coef_rdaddr[0]       0.094       -0.273
    new_inprdaddr[5]     MAC_FIR|clk     SLE      Q       new_inprdaddr[5]     0.094       -0.255
    inp_rdaddr[2]        MAC_FIR|clk     SLE      Q       inp_rdaddr[2]        0.076       -0.245
    inp_rdaddr[3]        MAC_FIR|clk     SLE      Q       inp_rdaddr[3]        0.076       -0.206
    inp_wraddr[2]        MAC_FIR|clk     SLE      Q       inp_wraddr[2]        0.094       -0.190
    =============================================================================================

    Ending Points with Worst Slack
    ******************************

                         Starting                                                             Required
    Instance             Reference       Type     Pin     Net                                 Time         Slack
                         Clock
    -------------------------------------------------------------------------------------------------------------
    inp_wraddr[3]        MAC_FIR|clk     SLE      D       un1_inp_wraddr_1_axbxc3             2.766        -0.527
    inp_wraddr[2]        MAC_FIR|clk     SLE      D       inp_wraddr_2_i_2_N_3_mux            2.766        -0.501
    new_inprdaddr[6]     MAC_FIR|clk     SLE      D       new_inprdaddr_2[6]                  2.766        -0.433
    Coef_rdaddr[6]       MAC_FIR|clk     SLE      D       N_8_i_0                             2.766        -0.318
    inp_wraddr[1]        MAC_FIR|clk     SLE      D       un1_inp_wraddr_1_axbxc1_N_2_i_0     2.766        -0.316
    inp_wraddr[4]        MAC_FIR|clk     SLE      D       un1_inp_wraddr_1_axbxc4             2.766        -0.260
    inp_wraddr[7]        MAC_FIR|clk     SLE      D       un1_inp_wraddr_1_axbxc7             2.766        -0.260
    inp_wraddr[5]        MAC_FIR|clk     SLE      D       N_27_i_0                            2.766        -0.250
    inp_wraddr[6]        MAC_FIR|clk     SLE      D       N_29_i_0                            2.766        -0.250
    inp_rdaddr[0]        MAC_FIR|clk     SLE      D       inp_rdaddr_lm[0]                    2.766        -0.245
    =============================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      2.988
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.766

        - Propagation time:                      3.293
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.527

        Number of logic level(s):                3
        Starting point:                          inp_wraddr[6] / Q
        Ending point:                            inp_wraddr[3] / D
        The start point is clocked by            MAC_FIR|clk [rising] on pin CLK
        The end   point is clocked by            MAC_FIR|clk [rising] on pin CLK

    Instance / Net                       Pin      Pin               Arrival     No. of
    Name                        Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------
    inp_wraddr[6]               SLE      Q        Out     0.094     0.094       -
    inp_wraddr[6]               Net      -        -       0.912     -           17
    inp_wraddr_2_i_a0_0[6]      CFG2     A        In      -         1.006       -
    inp_wraddr_2_i_a0_0[6]      CFG2     Y        Out     0.076     1.082       -
    inp_wraddr_2_i_a0_0[6]      Net      -        -       0.548     -           2
    un2_data_valid_dly_i_a2     CFG4     D        In      -         1.630       -
    un2_data_valid_dly_i_a2     CFG4     Y        Out     0.408     2.038       -
    un2_data_valid_dly_i_a2     Net      -        -       0.706     -           8
    un1_inp_wraddr_1_axbxc3     CFG4     D        In      -         2.744       -
    un1_inp_wraddr_1_axbxc3     CFG4     Y        Out     0.411     3.155       -
    un1_inp_wraddr_1_axbxc3     Net      -        -       0.138     -           1
    inp_wraddr[3]               SLE      D        In      -         3.293       -
    ======================================================================================
    Total path delay (propagation time + setup) of 3.515 is 1.211(34.5%) logic and 2.304(65.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      2.988
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.766

        - Propagation time:                      3.266
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.501

        Number of logic level(s):                3
        Starting point:                          inp_wraddr[6] / Q
        Ending point:                            inp_wraddr[2] / D
        The start point is clocked by            MAC_FIR|clk [rising] on pin CLK
        The end   point is clocked by            MAC_FIR|clk [rising] on pin CLK

    Instance / Net                        Pin      Pin               Arrival     No. of
    Name                         Type     Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------
    inp_wraddr[6]                SLE      Q        Out     0.094     0.094       -
    inp_wraddr[6]                Net      -        -       0.912     -           17
    inp_wraddr_2_i_a0_0[6]       CFG2     A        In      -         1.006       -
    inp_wraddr_2_i_a0_0[6]       CFG2     Y        Out     0.076     1.082       -
    inp_wraddr_2_i_a0_0[6]       Net      -        -       0.548     -           2
    un2_data_valid_dly_i_a2      CFG4     D        In      -         1.630       -
    un2_data_valid_dly_i_a2      CFG4     Y        Out     0.408     2.038       -
    un2_data_valid_dly_i_a2      Net      -        -       0.706     -           8
    inp_wraddr_2_i_2_m1_e        CFG4     D        In      -         2.744       -
    inp_wraddr_2_i_2_m1_e        CFG4     Y        Out     0.384     3.128       -
    inp_wraddr_2_i_2_N_3_mux     Net      -        -       0.138     -           1
    inp_wraddr[2]                SLE      D        In      -         3.266       -
    =======================================================================================
    Total path delay (propagation time + setup) of 3.488 is 1.185(34.0%) logic and 2.304(66.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      2.988
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.766

        - Propagation time:                      3.199
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.433

        Number of logic level(s):                3
        Starting point:                          new_inprdaddr[4] / Q
        Ending point:                            new_inprdaddr[6] / D
        The start point is clocked by            MAC_FIR|clk [rising] on pin CLK
        The end   point is clocked by            MAC_FIR|clk [rising] on pin CLK

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                          Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    new_inprdaddr[4]              SLE      Q        Out     0.076     0.076       -
    new_inprdaddr[4]              Net      -        -       0.676     -           4
    op_eq\.un15_filtop_done_4     CFG4     D        In      -         0.752       -
    op_eq\.un15_filtop_done_4     CFG4     Y        Out     0.411     1.163       -
    op_eq\.un15_filtop_done_4     Net      -        -       0.483     -           1
    op_eq\.un15_filtop_done       CFG4     D        In      -         1.646       -
    op_eq\.un15_filtop_done       CFG4     Y        Out     0.408     2.055       -
    op_eq\.un15_filtop_done       Net      -        -       0.622     -           4
    new_inprdaddr_2[6]            CFG4     D        In      -         2.677       -
    new_inprdaddr_2[6]            CFG4     Y        Out     0.384     3.061       -
    new_inprdaddr_2[6]            Net      -        -       0.138     -           1
    new_inprdaddr[6]              SLE      D        In      -         3.199       -
    ========================================================================================
    Total path delay (propagation time + setup) of 3.421 is 1.502(43.9%) logic and 1.919(56.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      2.988
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.766

        - Propagation time:                      3.183
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.418

        Number of logic level(s):                3
        Starting point:                          inp_wraddr[5] / Q
        Ending point:                            inp_wraddr[3] / D
        The start point is clocked by            MAC_FIR|clk [rising] on pin CLK
        The end   point is clocked by            MAC_FIR|clk [rising] on pin CLK

    Instance / Net                       Pin      Pin               Arrival     No. of
    Name                        Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------
    inp_wraddr[5]               SLE      Q        Out     0.094     0.094       -
    inp_wraddr[5]               Net      -        -       0.735     -           6
    inp_wraddr_2_i_a0_0[6]      CFG2     B        In      -         0.830       -
    inp_wraddr_2_i_a0_0[6]      CFG2     Y        Out     0.143     0.972       -
    inp_wraddr_2_i_a0_0[6]      Net      -        -       0.548     -           2
    un2_data_valid_dly_i_a2     CFG4     D        In      -         1.520       -
    un2_data_valid_dly_i_a2     CFG4     Y        Out     0.408     1.929       -
    un2_data_valid_dly_i_a2     Net      -        -       0.706     -           8
    un1_inp_wraddr_1_axbxc3     CFG4     D        In      -         2.635       -
    un1_inp_wraddr_1_axbxc3     CFG4     Y        Out     0.411     3.046       -
    un1_inp_wraddr_1_axbxc3     Net      -        -       0.138     -           1
    inp_wraddr[3]               SLE      D        In      -         3.183       -
    ======================================================================================
    Total path delay (propagation time + setup) of 3.405 is 1.278(37.5%) logic and 2.127(62.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      2.988
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.766

        - Propagation time:                      3.166
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.401

        Number of logic level(s):                3
        Starting point:                          inp_wraddr[0] / Q
        Ending point:                            inp_wraddr[3] / D
        The start point is clocked by            MAC_FIR|clk [rising] on pin CLK
        The end   point is clocked by            MAC_FIR|clk [rising] on pin CLK

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                          Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    inp_wraddr[0]                 SLE      Q        Out     0.076     0.076       -
    inp_wraddr[0]                 Net      -        -       0.759     -           7
    un2_data_valid_dly_i_a2_2     CFG4     D        In      -         0.835       -
    un2_data_valid_dly_i_a2_2     CFG4     Y        Out     0.411     1.246       -
    un2_data_valid_dly_i_a2_2     Net      -        -       0.483     -           1
    un2_data_valid_dly_i_a2       CFG4     C        In      -         1.729       -
    un2_data_valid_dly_i_a2       CFG4     Y        Out     0.182     1.911       -
    un2_data_valid_dly_i_a2       Net      -        -       0.706     -           8
    un1_inp_wraddr_1_axbxc3       CFG4     D        In      -         2.617       -
    un1_inp_wraddr_1_axbxc3       CFG4     Y        Out     0.411     3.028       -
    un1_inp_wraddr_1_axbxc3       Net      -        -       0.138     -           1
    inp_wraddr[3]                 SLE      D        In      -         3.166       -
    ========================================================================================
    Total path delay (propagation time + setup) of 3.388 is 1.302(38.4%) logic and 2.086(61.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                         Starting                                                     Arrival
    Instance                                             Reference     Type         Pin           Net                 Time        Slack
                                                         Clock
    -----------------------------------------------------------------------------------------------------------------------------------
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[0]     Coef_rddata2[0]     0.000       1.474
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[1]     Coef_rddata2[1]     0.000       1.474
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[2]     Coef_rddata2[2]     0.000       1.474
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[3]     Coef_rddata2[3]     0.000       1.474
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[4]     Coef_rddata2[4]     0.000       1.474
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[5]     Coef_rddata2[5]     0.000       1.474
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[6]     Coef_rddata2[6]     0.000       1.474
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[7]     Coef_rddata2[7]     0.000       1.474
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[8]     Coef_rddata2[8]     0.000       1.474
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     System        RAM64x18     A_DOUT[9]     Coef_rddata2[9]     0.000       1.474
    ===================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                       Starting                                            Required
    Instance           Reference     Type     Pin     Net                  Time         Slack
                       Clock
    -----------------------------------------------------------------------------------------
    Coef_rddata[0]     System        SLE      D       Coef_rddata_3[0]     2.766        1.474
    Coef_rddata[1]     System        SLE      D       Coef_rddata_3[1]     2.766        1.474
    Coef_rddata[2]     System        SLE      D       Coef_rddata_3[2]     2.766        1.474
    Coef_rddata[3]     System        SLE      D       Coef_rddata_3[3]     2.766        1.474
    Coef_rddata[4]     System        SLE      D       Coef_rddata_3[4]     2.766        1.474
    Coef_rddata[5]     System        SLE      D       Coef_rddata_3[5]     2.766        1.474
    Coef_rddata[6]     System        SLE      D       Coef_rddata_3[6]     2.766        1.474
    Coef_rddata[7]     System        SLE      D       Coef_rddata_3[7]     2.766        1.474
    Coef_rddata[8]     System        SLE      D       Coef_rddata_3[8]     2.766        1.474
    Coef_rddata[9]     System        SLE      D       Coef_rddata_3[9]     2.766        1.474
    =========================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      2.988
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         2.766

        - Propagation time:                      1.291
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 1.474

        Number of logic level(s):                1
        Starting point:                          U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0 / A_DOUT[0]
        Ending point:                            Coef_rddata[0] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            MAC_FIR|clk [rising] on pin CLK

    Instance / Net                                                    Pin           Pin               Arrival     No. of
    Name                                                 Type         Name          Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------------------------
    U1_1.Coef_RAM1_0.Coef_RAM1_Coef_RAM1_0_URAM_R0C0     RAM64x18     A_DOUT[0]     Out     0.000     0.000       -
    Coef_rddata2[0]                                      Net          -             -       0.971     -           1
    Coef_rddata_3[0]                                     CFG3         C             In      -         0.971       -
    Coef_rddata_3[0]                                     CFG3         Y             Out     0.182     1.154       -
    Coef_rddata_3[0]                                     Net          -             -       0.138     -           1
    Coef_rddata[0]                                       SLE          D             In      -         1.291       -
    ========================================================================================================================
    Total path delay (propagation time + setup) of 1.513 is 0.404(26.7%) logic and 1.109(73.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    ---------------------------------------
    Resource Usage Report for MAC_FIR

    Mapping to part: m2s050fbga896-1
    Cell usage:
    CLKINT          2 uses
    RAM64x18        4 uses
    CFG1           2 uses
    CFG2           65 uses
    CFG3           60 uses
    CFG4           54 uses

    Carry primitives used for arithmetic functions:
    ARI1           8 uses

    Sequential Cells:
    SLE            216 uses
    Registers not packed on I/O Pads:      216

    DSP Blocks:    1
     MACC:         1 Mult

    I/O ports: 67
    I/O primitives: 67
    INBUF          22 uses
    OUTBUF         45 uses

    Global Clock Buffers: 2

    RAM/ROM usage summary
    Block Rams (RAM64x18) : 4
    Total LUTs:    181

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 34MB peak: 79MB)

    Process took 0h:00m:03s realtime, 0h:00m:02s cputime
    # Wed Nov 06 13:26:25 2013

    ###########################################################]

`