--------------------------------------------------------------------------------
-- Company: MICROSEMI
--
-- File: TESTBENCH.vhd
--
-- File history:
--      v1.0: APR 14-06-13: 
--
-- Description		: Testbench for Mult32x32 using single MACC
--
-- Targeted device	: Family	:: SmartFusion2  
-- 					  Die		:: M2S050T
--					  Package	:: 896 FBGA	
--			Author	: PHANIKIRAN T
--------------------------------------------------------------------------------

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;


entity TESTBENCH is
end TESTBENCH;


architecture testbench_arch of TESTBENCH is

component Mult32x32_SingleMACC is
	port(
			clk	: in  std_logic;
		reset_n	: in  std_logic;
		mul_en	: in  std_logic;	
			A	: in  std_logic_vector(31 downto 0);
			B	: in  std_logic_vector(31 downto 0); 
		Result	: out std_logic_vector(63 downto 0);	 	   	   	             	     	     	     	            
		mul_result_valid	: out  std_logic	
         );
end component Mult32x32_SingleMACC;

CONSTANT clk_period : time := 10 ns;

signal clk		: STD_LOGIC;
signal reset_n	: STD_LOGIC;

signal A		: STD_LOGIC_VECTOR(31 downto 0);
signal B		: STD_LOGIC_VECTOR(31 downto 0);
signal Result	: STD_LOGIC_VECTOR(63 downto 0);

SIGNAL mul_en 				: std_logic := '0';
SIGNAL mul_result_valid 	: std_logic;	
SIGNAL stop 	: std_logic := '0';	


begin


UUT: Mult32x32_SingleMACC
		port map(	
				clk 	=> clk,
				reset_n => reset_n,
				mul_en	=> mul_en,
				A 		=> A,
				B 		=> B,	
				Result	=> Result,
				mul_result_valid => mul_result_valid
         );

 clk_proc :process
   begin
		IF(stop = '0')THEN
	        clk <= '0';
    	    wait for clk_period/2;
        	clk <= '1';
	        wait for clk_period/2;
		ELSE
			clk <= '0';
		END IF;
   end process;

  stim_proc: process
   begin

        	reset_n 	<='0';
        wait for 20 ns;
        	reset_n	<='1';
        wait;
  end process;


	test_proc: process
	begin
  
		wait until (reset_n = '1');
		wait until rising_edge(clk);
		A		<= x"AAAABBBB";
		B		<= x"4CCCDDDD";
		mul_en 	<= '1';
		wait until rising_edge(clk);
		mul_en <= '0';
  		wait until (mul_result_valid = '1'); 

		wait until rising_edge(clk);
		A		<= x"5AAABBBB";
		B		<= x"CCCCDDDD";
		mul_en <= '1';
		wait until rising_edge(clk);
		mul_en <= '0';
  		wait until (mul_result_valid = '1'); 

		wait until rising_edge(clk);
		A 		<= x"5AAABBBB";
		B 		<= x"4CCCDDDD";
		mul_en 	<= '1';
		wait until rising_edge(clk);
		mul_en <= '0';
  		wait until (mul_result_valid = '1'); 

		wait until rising_edge(clk);
		A		<= x"AAAABBBB";
		B		<= x"CCCCDDDD";
		mul_en	<= '1';
		wait until rising_edge(clk);
		mul_en <= '0'; 
		wait for 200 ns;
		wait until rising_edge(clk);
		stop <= '1';
		--assert FALSE
	    report "TEST FINISHED!"
	    severity failure;
wait;
    end process;
end testbench_arch;
