-- Version: v11.0 11.0.0.23

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity acc_0_acc_0_0_HARD_MULT_ACC is

    port( B0        : in    std_logic_vector(17 downto 0);
          A0        : in    std_logic_vector(17 downto 0);
          P_29      : out   std_logic;
          P_28      : out   std_logic;
          P_27      : out   std_logic;
          P_26      : out   std_logic;
          P_25      : out   std_logic;
          P_24      : out   std_logic;
          P_23      : out   std_logic;
          P_22      : out   std_logic;
          P_21      : out   std_logic;
          P_20      : out   std_logic;
          P_19      : out   std_logic;
          P_18      : out   std_logic;
          P_17      : out   std_logic;
          P_16      : out   std_logic;
          P_15      : out   std_logic;
          P_14      : out   std_logic;
          P_13      : out   std_logic;
          P_12      : out   std_logic;
          P_11      : out   std_logic;
          P_10      : out   std_logic;
          P_9       : out   std_logic;
          P_8       : out   std_logic;
          P_7       : out   std_logic;
          P_6       : out   std_logic;
          P_5       : out   std_logic;
          P_4       : out   std_logic;
          P_3       : out   std_logic;
          P_2       : out   std_logic;
          P_1       : out   std_logic;
          P_0       : out   std_logic;
          ARSHFT17  : in    std_logic;
          clk_c     : in    std_logic;
          N_70_i_0  : in    std_logic;
          reset_n_c : in    std_logic
        );

end acc_0_acc_0_0_HARD_MULT_ACC;

architecture DEF_ARCH of acc_0_acc_0_0_HARD_MULT_ACC is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component MACC
    port( CLK               : in    std_logic_vector(1 downto 0) := (others => 'U');
          A                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          A_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          A_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B                 : in    std_logic_vector(17 downto 0) := (others => 'U');
          B_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C                 : in    std_logic_vector(43 downto 0) := (others => 'U');
          C_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_EN              : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_ARST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_SRST_N          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL           : in    std_logic := 'U';
          FDBKSEL_EN        : in    std_logic := 'U';
          FDBKSEL_AL_N      : in    std_logic := 'U';
          FDBKSEL_SL_N      : in    std_logic := 'U';
          CDSEL             : in    std_logic := 'U';
          CDSEL_EN          : in    std_logic := 'U';
          CDSEL_AL_N        : in    std_logic := 'U';
          CDSEL_SL_N        : in    std_logic := 'U';
          ARSHFT17          : in    std_logic := 'U';
          ARSHFT17_EN       : in    std_logic := 'U';
          ARSHFT17_AL_N     : in    std_logic := 'U';
          ARSHFT17_SL_N     : in    std_logic := 'U';
          SUB               : in    std_logic := 'U';
          SUB_EN            : in    std_logic := 'U';
          SUB_AL_N          : in    std_logic := 'U';
          SUB_SL_N          : in    std_logic := 'U';
          CARRYIN           : in    std_logic := 'U';
          SIMD              : in    std_logic := 'U';
          DOTP              : in    std_logic := 'U';
          OVFL_CARRYOUT_SEL : in    std_logic := 'U';
          A_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          B_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          C_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          P_BYPASS          : in    std_logic_vector(1 downto 0) := (others => 'U');
          FDBKSEL_BYPASS    : in    std_logic := 'U';
          FDBKSEL_AD        : in    std_logic := 'U';
          FDBKSEL_SD_N      : in    std_logic := 'U';
          CDSEL_BYPASS      : in    std_logic := 'U';
          CDSEL_AD          : in    std_logic := 'U';
          CDSEL_SD_N        : in    std_logic := 'U';
          ARSHFT17_BYPASS   : in    std_logic := 'U';
          ARSHFT17_AD       : in    std_logic := 'U';
          ARSHFT17_SD_N     : in    std_logic := 'U';
          SUB_BYPASS        : in    std_logic := 'U';
          SUB_AD            : in    std_logic := 'U';
          SUB_SD_N          : in    std_logic := 'U';
          CDIN              : in    std_logic_vector(43 downto 0) := (others => 'U');
          CDOUT             : out   std_logic_vector(43 downto 0);
          P                 : out   std_logic_vector(43 downto 0);
          OVFL_CARRYOUT     : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;
    signal nc47, nc34, nc9, nc13, nc23, nc55, nc33, nc16, nc26, 
        nc45, nc58, nc27, nc17, nc36, nc48, nc37, nc5, nc52, nc51, 
        nc4, nc42, nc41, nc25, nc15, nc35, nc49, nc28, nc18, nc38, 
        nc1, nc2, nc50, nc22, nc12, nc21, nc11, nc54, nc3, nc32, 
        nc40, nc31, nc44, nc7, nc6, nc19, nc29, nc53, nc39, nc8, 
        nc43, nc56, nc20, nc10, nc57, nc24, nc14, nc46, nc30
         : std_logic;

begin 


    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    U0 : MACC
      port map(CLK(1) => clk_c, CLK(0) => clk_c, A(17) => A0(17), 
        A(16) => A0(16), A(15) => A0(15), A(14) => A0(14), A(13)
         => A0(13), A(12) => A0(12), A(11) => A0(11), A(10) => 
        A0(10), A(9) => A0(9), A(8) => A0(8), A(7) => A0(7), A(6)
         => A0(6), A(5) => A0(5), A(4) => A0(4), A(3) => A0(3), 
        A(2) => A0(2), A(1) => A0(1), A(0) => A0(0), A_EN(1) => 
        VCC_net_1, A_EN(0) => VCC_net_1, A_ARST_N(1) => reset_n_c, 
        A_ARST_N(0) => reset_n_c, A_SRST_N(1) => VCC_net_1, 
        A_SRST_N(0) => VCC_net_1, B(17) => B0(17), B(16) => 
        B0(16), B(15) => B0(15), B(14) => B0(14), B(13) => B0(13), 
        B(12) => B0(12), B(11) => B0(11), B(10) => B0(10), B(9)
         => B0(9), B(8) => B0(8), B(7) => B0(7), B(6) => B0(6), 
        B(5) => B0(5), B(4) => B0(4), B(3) => B0(3), B(2) => 
        B0(2), B(1) => B0(1), B(0) => B0(0), B_EN(1) => VCC_net_1, 
        B_EN(0) => VCC_net_1, B_ARST_N(1) => reset_n_c, 
        B_ARST_N(0) => reset_n_c, B_SRST_N(1) => VCC_net_1, 
        B_SRST_N(0) => VCC_net_1, C(43) => GND_net_1, C(42) => 
        GND_net_1, C(41) => GND_net_1, C(40) => GND_net_1, C(39)
         => GND_net_1, C(38) => GND_net_1, C(37) => GND_net_1, 
        C(36) => GND_net_1, C(35) => GND_net_1, C(34) => 
        GND_net_1, C(33) => GND_net_1, C(32) => GND_net_1, C(31)
         => GND_net_1, C(30) => GND_net_1, C(29) => GND_net_1, 
        C(28) => GND_net_1, C(27) => GND_net_1, C(26) => 
        GND_net_1, C(25) => GND_net_1, C(24) => GND_net_1, C(23)
         => GND_net_1, C(22) => GND_net_1, C(21) => GND_net_1, 
        C(20) => GND_net_1, C(19) => GND_net_1, C(18) => 
        GND_net_1, C(17) => GND_net_1, C(16) => GND_net_1, C(15)
         => GND_net_1, C(14) => GND_net_1, C(13) => GND_net_1, 
        C(12) => GND_net_1, C(11) => GND_net_1, C(10) => 
        GND_net_1, C(9) => GND_net_1, C(8) => GND_net_1, C(7) => 
        GND_net_1, C(6) => GND_net_1, C(5) => GND_net_1, C(4) => 
        GND_net_1, C(3) => GND_net_1, C(2) => GND_net_1, C(1) => 
        GND_net_1, C(0) => GND_net_1, C_EN(1) => VCC_net_1, 
        C_EN(0) => VCC_net_1, C_ARST_N(1) => reset_n_c, 
        C_ARST_N(0) => reset_n_c, C_SRST_N(1) => VCC_net_1, 
        C_SRST_N(0) => VCC_net_1, P_EN(1) => VCC_net_1, P_EN(0)
         => VCC_net_1, P_ARST_N(1) => reset_n_c, P_ARST_N(0) => 
        reset_n_c, P_SRST_N(1) => N_70_i_0, P_SRST_N(0) => 
        N_70_i_0, FDBKSEL => VCC_net_1, FDBKSEL_EN => VCC_net_1, 
        FDBKSEL_AL_N => VCC_net_1, FDBKSEL_SL_N => VCC_net_1, 
        CDSEL => GND_net_1, CDSEL_EN => VCC_net_1, CDSEL_AL_N => 
        VCC_net_1, CDSEL_SL_N => VCC_net_1, ARSHFT17 => ARSHFT17, 
        ARSHFT17_EN => VCC_net_1, ARSHFT17_AL_N => reset_n_c, 
        ARSHFT17_SL_N => N_70_i_0, SUB => GND_net_1, SUB_EN => 
        VCC_net_1, SUB_AL_N => VCC_net_1, SUB_SL_N => VCC_net_1, 
        CARRYIN => GND_net_1, SIMD => GND_net_1, DOTP => 
        GND_net_1, OVFL_CARRYOUT_SEL => VCC_net_1, A_BYPASS(1)
         => GND_net_1, A_BYPASS(0) => GND_net_1, B_BYPASS(1) => 
        GND_net_1, B_BYPASS(0) => GND_net_1, C_BYPASS(1) => 
        GND_net_1, C_BYPASS(0) => GND_net_1, P_BYPASS(1) => 
        GND_net_1, P_BYPASS(0) => GND_net_1, FDBKSEL_BYPASS => 
        VCC_net_1, FDBKSEL_AD => GND_net_1, FDBKSEL_SD_N => 
        VCC_net_1, CDSEL_BYPASS => VCC_net_1, CDSEL_AD => 
        GND_net_1, CDSEL_SD_N => VCC_net_1, ARSHFT17_BYPASS => 
        GND_net_1, ARSHFT17_AD => GND_net_1, ARSHFT17_SD_N => 
        VCC_net_1, SUB_BYPASS => VCC_net_1, SUB_AD => GND_net_1, 
        SUB_SD_N => VCC_net_1, CDIN(43) => GND_net_1, CDIN(42)
         => GND_net_1, CDIN(41) => GND_net_1, CDIN(40) => 
        GND_net_1, CDIN(39) => GND_net_1, CDIN(38) => GND_net_1, 
        CDIN(37) => GND_net_1, CDIN(36) => GND_net_1, CDIN(35)
         => GND_net_1, CDIN(34) => GND_net_1, CDIN(33) => 
        GND_net_1, CDIN(32) => GND_net_1, CDIN(31) => GND_net_1, 
        CDIN(30) => GND_net_1, CDIN(29) => GND_net_1, CDIN(28)
         => GND_net_1, CDIN(27) => GND_net_1, CDIN(26) => 
        GND_net_1, CDIN(25) => GND_net_1, CDIN(24) => GND_net_1, 
        CDIN(23) => GND_net_1, CDIN(22) => GND_net_1, CDIN(21)
         => GND_net_1, CDIN(20) => GND_net_1, CDIN(19) => 
        GND_net_1, CDIN(18) => GND_net_1, CDIN(17) => GND_net_1, 
        CDIN(16) => GND_net_1, CDIN(15) => GND_net_1, CDIN(14)
         => GND_net_1, CDIN(13) => GND_net_1, CDIN(12) => 
        GND_net_1, CDIN(11) => GND_net_1, CDIN(10) => GND_net_1, 
        CDIN(9) => GND_net_1, CDIN(8) => GND_net_1, CDIN(7) => 
        GND_net_1, CDIN(6) => GND_net_1, CDIN(5) => GND_net_1, 
        CDIN(4) => GND_net_1, CDIN(3) => GND_net_1, CDIN(2) => 
        GND_net_1, CDIN(1) => GND_net_1, CDIN(0) => GND_net_1, 
        CDOUT(43) => nc47, CDOUT(42) => nc34, CDOUT(41) => nc9, 
        CDOUT(40) => nc13, CDOUT(39) => nc23, CDOUT(38) => nc55, 
        CDOUT(37) => nc33, CDOUT(36) => nc16, CDOUT(35) => nc26, 
        CDOUT(34) => nc45, CDOUT(33) => nc58, CDOUT(32) => nc27, 
        CDOUT(31) => nc17, CDOUT(30) => nc36, CDOUT(29) => nc48, 
        CDOUT(28) => nc37, CDOUT(27) => nc5, CDOUT(26) => nc52, 
        CDOUT(25) => nc51, CDOUT(24) => nc4, CDOUT(23) => nc42, 
        CDOUT(22) => nc41, CDOUT(21) => nc25, CDOUT(20) => nc15, 
        CDOUT(19) => nc35, CDOUT(18) => nc49, CDOUT(17) => nc28, 
        CDOUT(16) => nc18, CDOUT(15) => nc38, CDOUT(14) => nc1, 
        CDOUT(13) => nc2, CDOUT(12) => nc50, CDOUT(11) => nc22, 
        CDOUT(10) => nc12, CDOUT(9) => nc21, CDOUT(8) => nc11, 
        CDOUT(7) => nc54, CDOUT(6) => nc3, CDOUT(5) => nc32, 
        CDOUT(4) => nc40, CDOUT(3) => nc31, CDOUT(2) => nc44, 
        CDOUT(1) => nc7, CDOUT(0) => nc6, P(43) => nc19, P(42)
         => nc29, P(41) => nc53, P(40) => nc39, P(39) => nc8, 
        P(38) => nc43, P(37) => nc56, P(36) => nc20, P(35) => 
        nc10, P(34) => nc57, P(33) => nc24, P(32) => nc14, P(31)
         => nc46, P(30) => nc30, P(29) => P_29, P(28) => P_28, 
        P(27) => P_27, P(26) => P_26, P(25) => P_25, P(24) => 
        P_24, P(23) => P_23, P(22) => P_22, P(21) => P_21, P(20)
         => P_20, P(19) => P_19, P(18) => P_18, P(17) => P_17, 
        P(16) => P_16, P(15) => P_15, P(14) => P_14, P(13) => 
        P_13, P(12) => P_12, P(11) => P_11, P(10) => P_10, P(9)
         => P_9, P(8) => P_8, P(7) => P_7, P(6) => P_6, P(5) => 
        P_5, P(4) => P_4, P(3) => P_3, P(2) => P_2, P(1) => P_1, 
        P(0) => P_0, OVFL_CARRYOUT => OPEN);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity acc_0 is

    port( P         : out   std_logic_vector(29 downto 0);
          A0        : in    std_logic_vector(17 downto 0);
          B0        : in    std_logic_vector(17 downto 0);
          reset_n_c : in    std_logic;
          N_70_i_0  : in    std_logic;
          clk_c     : in    std_logic;
          ARSHFT17  : in    std_logic
        );

end acc_0;

architecture DEF_ARCH of acc_0 is 

  component acc_0_acc_0_0_HARD_MULT_ACC
    port( B0        : in    std_logic_vector(17 downto 0) := (others => 'U');
          A0        : in    std_logic_vector(17 downto 0) := (others => 'U');
          P_29      : out   std_logic;
          P_28      : out   std_logic;
          P_27      : out   std_logic;
          P_26      : out   std_logic;
          P_25      : out   std_logic;
          P_24      : out   std_logic;
          P_23      : out   std_logic;
          P_22      : out   std_logic;
          P_21      : out   std_logic;
          P_20      : out   std_logic;
          P_19      : out   std_logic;
          P_18      : out   std_logic;
          P_17      : out   std_logic;
          P_16      : out   std_logic;
          P_15      : out   std_logic;
          P_14      : out   std_logic;
          P_13      : out   std_logic;
          P_12      : out   std_logic;
          P_11      : out   std_logic;
          P_10      : out   std_logic;
          P_9       : out   std_logic;
          P_8       : out   std_logic;
          P_7       : out   std_logic;
          P_6       : out   std_logic;
          P_5       : out   std_logic;
          P_4       : out   std_logic;
          P_3       : out   std_logic;
          P_2       : out   std_logic;
          P_1       : out   std_logic;
          P_0       : out   std_logic;
          ARSHFT17  : in    std_logic := 'U';
          clk_c     : in    std_logic := 'U';
          N_70_i_0  : in    std_logic := 'U';
          reset_n_c : in    std_logic := 'U'
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal GND_net_1, VCC_net_1 : std_logic;

    for all : acc_0_acc_0_0_HARD_MULT_ACC
	Use entity work.acc_0_acc_0_0_HARD_MULT_ACC(DEF_ARCH);
begin 


    acc_0_0 : acc_0_acc_0_0_HARD_MULT_ACC
      port map(B0(17) => B0(17), B0(16) => B0(16), B0(15) => 
        B0(15), B0(14) => B0(14), B0(13) => B0(13), B0(12) => 
        B0(12), B0(11) => B0(11), B0(10) => B0(10), B0(9) => 
        B0(9), B0(8) => B0(8), B0(7) => B0(7), B0(6) => B0(6), 
        B0(5) => B0(5), B0(4) => B0(4), B0(3) => B0(3), B0(2) => 
        B0(2), B0(1) => B0(1), B0(0) => B0(0), A0(17) => A0(17), 
        A0(16) => A0(16), A0(15) => A0(15), A0(14) => A0(14), 
        A0(13) => A0(13), A0(12) => A0(12), A0(11) => A0(11), 
        A0(10) => A0(10), A0(9) => A0(9), A0(8) => A0(8), A0(7)
         => A0(7), A0(6) => A0(6), A0(5) => A0(5), A0(4) => A0(4), 
        A0(3) => A0(3), A0(2) => A0(2), A0(1) => A0(1), A0(0) => 
        A0(0), P_29 => P(29), P_28 => P(28), P_27 => P(27), P_26
         => P(26), P_25 => P(25), P_24 => P(24), P_23 => P(23), 
        P_22 => P(22), P_21 => P(21), P_20 => P(20), P_19 => 
        P(19), P_18 => P(18), P_17 => P(17), P_16 => P(16), P_15
         => P(15), P_14 => P(14), P_13 => P(13), P_12 => P(12), 
        P_11 => P(11), P_10 => P(10), P_9 => P(9), P_8 => P(8), 
        P_7 => P(7), P_6 => P(6), P_5 => P(5), P_4 => P(4), P_3
         => P(3), P_2 => P(2), P_1 => P(1), P_0 => P(0), ARSHFT17
         => ARSHFT17, clk_c => clk_c, N_70_i_0 => N_70_i_0, 
        reset_n_c => reset_n_c);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library SmartFusion2;
use SmartFusion2.all;

entity Mult32x32_SF2 is

    port( A                : in    std_logic_vector(31 downto 0);
          B                : in    std_logic_vector(31 downto 0);
          Result           : out   std_logic_vector(63 downto 0);
          clk              : in    std_logic;
          reset_n          : in    std_logic;
          mul_en           : in    std_logic;
          mul_result_valid : out   std_logic
        );

end Mult32x32_SF2;

architecture DEF_ARCH of Mult32x32_SF2 is 

  component SLE
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          EN  : in    std_logic := 'U';
          ALn : in    std_logic := 'U';
          ADn : in    std_logic := 'U';
          SLn : in    std_logic := 'U';
          SD  : in    std_logic := 'U';
          LAT : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component OUTBUF
    generic (IOSTD:string := "");

    port( D   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component INBUF
    generic (IOSTD:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component CFG4
    generic (INIT:std_logic_vector := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          D : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CFG3
    generic (INIT:std_logic_vector := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component CFG2
    generic (INIT:std_logic_vector := x"0");

    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component CLKINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component acc_0
    port( P         : out   std_logic_vector(29 downto 0);
          A0        : in    std_logic_vector(17 downto 0) := (others => 'U');
          B0        : in    std_logic_vector(17 downto 0) := (others => 'U');
          reset_n_c : in    std_logic := 'U';
          N_70_i_0  : in    std_logic := 'U';
          clk_c     : in    std_logic := 'U';
          ARSHFT17  : in    std_logic := 'U'
        );
  end component;

    signal \A0(0)\, \A0(1)\, \A0(2)\, \A0(3)\, \A0(4)\, \A0(5)\, 
        \A0(6)\, \A0(7)\, \A0(8)\, \A0(9)\, \A0(10)\, \A0(11)\, 
        \A0(12)\, \A0(13)\, \A0(14)\, \A0(15)\, \A0(16)\, 
        \A0(17)\, VCC_net_1, \ARSHFT17\, \B0(0)\, \B0(1)\, 
        \B0(2)\, \B0(3)\, \B0(4)\, \B0(5)\, \B0(6)\, \B0(7)\, 
        \B0(8)\, \B0(9)\, \B0(10)\, \B0(11)\, \B0(12)\, \B0(13)\, 
        \B0(14)\, \B0(15)\, \B0(16)\, \B0(17)\, GND_net_1, \P(0)\, 
        \P(1)\, \P(2)\, \P(3)\, \P(4)\, \P(5)\, \P(6)\, \P(7)\, 
        \P(8)\, \P(9)\, \P(10)\, \P(11)\, \P(12)\, \P(13)\, 
        \P(14)\, \P(15)\, \P(16)\, \P(17)\, \P(18)\, \P(19)\, 
        \P(20)\, \P(21)\, \P(22)\, \P(23)\, \P(24)\, \P(25)\, 
        \P(26)\, \P(27)\, \P(28)\, \P(29)\, \A0_4(17)\, 
        \B0_3(17)\, \Curr_State(0)\, \Curr_State(1)\, 
        \Curr_State(2)\, \Curr_State(3)\, Curr_State_23_d, 
        ARSHFT17_3, \Curr_State_ns(0)\, \A0_4(0)\, \A0_4(1)\, 
        \A0_4(2)\, \A0_4(3)\, \A0_4(4)\, \A0_4(5)\, \A0_4(6)\, 
        \A0_4(7)\, \A0_4(8)\, \A0_4(9)\, \A0_4(10)\, \A0_4(11)\, 
        \A0_4(12)\, \A0_4(13)\, \A0_4(14)\, \A0_4(15)\, 
        \A0_4(16)\, \B0_3(0)\, \B0_3(1)\, \B0_3(2)\, \B0_3(3)\, 
        \B0_3(4)\, \B0_3(5)\, \B0_3(6)\, \B0_3(7)\, \B0_3(8)\, 
        \B0_3(9)\, \B0_3(10)\, \B0_3(11)\, \B0_3(12)\, \B0_3(13)\, 
        \B0_3(14)\, \B0_3(15)\, \B0_3(16)\, m7, m5, A0_4_sn_N_3, 
        B0_3_sn_N_7, clk_c, reset_n_c, mul_en_c, \A_c(0)\, 
        \A_c(1)\, \A_c(2)\, \A_c(3)\, \A_c(4)\, \A_c(5)\, 
        \A_c(6)\, \A_c(7)\, \A_c(8)\, \A_c(9)\, \A_c(10)\, 
        \A_c(11)\, \A_c(12)\, \A_c(13)\, \A_c(14)\, \A_c(15)\, 
        \A_c(16)\, \A_c(17)\, \A_c(18)\, \A_c(19)\, \A_c(20)\, 
        \A_c(21)\, \A_c(22)\, \A_c(23)\, \A_c(24)\, \A_c(25)\, 
        \A_c(26)\, \A_c(27)\, \A_c(28)\, \A_c(29)\, \A_c(30)\, 
        \A_c(31)\, \B_c(0)\, \B_c(1)\, \B_c(2)\, \B_c(3)\, 
        \B_c(4)\, \B_c(5)\, \B_c(6)\, \B_c(7)\, \B_c(8)\, 
        \B_c(9)\, \B_c(10)\, \B_c(11)\, \B_c(12)\, \B_c(13)\, 
        \B_c(14)\, \B_c(15)\, \B_c(16)\, \B_c(17)\, \B_c(18)\, 
        \B_c(19)\, \B_c(20)\, \B_c(21)\, \B_c(22)\, \B_c(23)\, 
        \B_c(24)\, \B_c(25)\, \B_c(26)\, \B_c(27)\, \B_c(28)\, 
        \B_c(29)\, \B_c(30)\, \B_c(31)\, \Result_c(0)\, 
        \Result_c(1)\, \Result_c(2)\, \Result_c(3)\, 
        \Result_c(4)\, \Result_c(5)\, \Result_c(6)\, 
        \Result_c(7)\, \Result_c(8)\, \Result_c(9)\, 
        \Result_c(10)\, \Result_c(11)\, \Result_c(12)\, 
        \Result_c(13)\, \Result_c(14)\, \Result_c(15)\, 
        \Result_c(16)\, \Result_c(17)\, \Result_c(18)\, 
        \Result_c(19)\, \Result_c(20)\, \Result_c(21)\, 
        \Result_c(22)\, \Result_c(23)\, \Result_c(24)\, 
        \Result_c(25)\, \Result_c(26)\, \Result_c(27)\, 
        \Result_c(28)\, \Result_c(29)\, \Result_c(30)\, 
        \Result_c(31)\, \Result_c(32)\, \Result_c(33)\, 
        \Result_c(34)\, \Result_c(35)\, \Result_c(36)\, 
        \Result_c(37)\, \Result_c(38)\, \Result_c(39)\, 
        \Result_c(40)\, \Result_c(41)\, \Result_c(42)\, 
        \Result_c(43)\, \Result_c(44)\, \Result_c(45)\, 
        \Result_c(46)\, \Result_c(47)\, \Result_c(48)\, 
        \Result_c(49)\, \Result_c(50)\, \Result_c(51)\, 
        \Result_c(52)\, \Result_c(53)\, \Result_c(54)\, 
        \Result_c(55)\, \Result_c(56)\, \Result_c(57)\, 
        \Result_c(58)\, \Result_c(59)\, \Result_c(60)\, 
        \Result_c(61)\, \Result_c(62)\, \Result_c(63)\, 
        \Resultce(34)\, \Resultce(17)\, \Resultce(0)\, 
        \Curr_State_ns_3_0_.m3_e_0_net_1\, N_70_i_0, 
        \Curr_State_fast(0)\, \Curr_State_ns_fast(0)\, 
        \Curr_State_0_rep1\, \Curr_State_ns_rep1(0)\, 
        \Curr_State_fast(1)\, N_893_fast, \Curr_State_fast(2)\, 
        N_892_fast, \clk_ibuf\, \reset_n_ibuf\ : std_logic;

    for all : acc_0
	Use entity work.acc_0(DEF_ARCH);
begin 


    Curr_State_0_rep1 : SLE
      port map(D => \Curr_State_ns_rep1(0)\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Curr_State_0_rep1\);
    
    \Result_obuf[60]\ : OUTBUF
      port map(D => \Result_c(60)\, PAD => Result(60));
    
    \Result_obuf[15]\ : OUTBUF
      port map(D => \Result_c(15)\, PAD => Result(15));
    
    \B_ibuf[2]\ : INBUF
      port map(PAD => B(2), Y => \B_c(2)\);
    
    \Result[38]\ : SLE
      port map(D => \P(4)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(38)\);
    
    \A_ibuf[26]\ : INBUF
      port map(PAD => A(26), Y => \A_c(26)\);
    
    \A0[9]\ : SLE
      port map(D => \A0_4(9)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \A0(9)\);
    
    \A0_4[1]\ : CFG4
      generic map(INIT => x"3210")

      port map(A => \Curr_State_0_rep1\, B => A0_4_sn_N_3, C => 
        \A_c(18)\, D => \A_c(1)\, Y => \A0_4(1)\);
    
    \A0_4[15]\ : CFG4
      generic map(INIT => x"3120")

      port map(A => \Curr_State(0)\, B => A0_4_sn_N_3, C => 
        \A_c(15)\, D => \A_c(31)\, Y => \A0_4(15)\);
    
    \B0[7]\ : SLE
      port map(D => \B0_3(7)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \B0(7)\);
    
    \B_ibuf[17]\ : INBUF
      port map(PAD => B(17), Y => \B_c(17)\);
    
    \Result_obuf[38]\ : OUTBUF
      port map(D => \Result_c(38)\, PAD => Result(38));
    
    \Result[49]\ : SLE
      port map(D => \P(15)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(49)\);
    
    \Result[12]\ : SLE
      port map(D => \P(12)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(12)\);
    
    \Result_obuf[21]\ : OUTBUF
      port map(D => \Result_c(21)\, PAD => Result(21));
    
    \B_ibuf[26]\ : INBUF
      port map(PAD => B(26), Y => \B_c(26)\);
    
    \Result[43]\ : SLE
      port map(D => \P(9)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(43)\);
    
    \Result_obuf[62]\ : OUTBUF
      port map(D => \Result_c(62)\, PAD => Result(62));
    
    \Result_obuf[34]\ : OUTBUF
      port map(D => \Result_c(34)\, PAD => Result(34));
    
    \Result[46]\ : SLE
      port map(D => \P(12)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(46)\);
    
    \A0_4[6]\ : CFG4
      generic map(INIT => x"3210")

      port map(A => \Curr_State_0_rep1\, B => A0_4_sn_N_3, C => 
        \A_c(23)\, D => \A_c(6)\, Y => \A0_4(6)\);
    
    \Result[18]\ : SLE
      port map(D => \P(1)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(18)\);
    
    \B_ibuf[23]\ : INBUF
      port map(PAD => B(23), Y => \B_c(23)\);
    
    \Result_obuf[45]\ : OUTBUF
      port map(D => \Result_c(45)\, PAD => Result(45));
    
    \A_ibuf[25]\ : INBUF
      port map(PAD => A(25), Y => \A_c(25)\);
    
    \A_ibuf[31]\ : INBUF
      port map(PAD => A(31), Y => \A_c(31)\);
    
    \A0[5]\ : SLE
      port map(D => \A0_4(5)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \A0(5)\);
    
    \A0_4[11]\ : CFG4
      generic map(INIT => x"3210")

      port map(A => \Curr_State(0)\, B => A0_4_sn_N_3, C => 
        \A_c(28)\, D => \A_c(11)\, Y => \A0_4(11)\);
    
    \Result_obuf[29]\ : OUTBUF
      port map(D => \Result_c(29)\, PAD => Result(29));
    
    \B0[16]\ : SLE
      port map(D => \B0_3(16)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \B0(16)\);
    
    \Resultce[34]\ : CFG3
      generic map(INIT => x"80")

      port map(A => \Curr_State_fast(2)\, B => 
        \Curr_State_fast(0)\, C => \Curr_State(1)\, Y => 
        \Resultce(34)\);
    
    \B0_RNO[17]\ : CFG4
      generic map(INIT => x"1080")

      port map(A => \Curr_State(1)\, B => \Curr_State(0)\, C => 
        \B_c(31)\, D => \Curr_State(2)\, Y => \B0_3(17)\);
    
    \A0[1]\ : SLE
      port map(D => \A0_4(1)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \A0(1)\);
    
    \Result_obuf[26]\ : OUTBUF
      port map(D => \Result_c(26)\, PAD => Result(26));
    
    \Result[3]\ : SLE
      port map(D => \P(3)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(3)\);
    
    \A_ibuf[12]\ : INBUF
      port map(PAD => A(12), Y => \A_c(12)\);
    
    \Result_obuf[18]\ : OUTBUF
      port map(D => \Result_c(18)\, PAD => Result(18));
    
    \Curr_State_fast_RNIMB43_0[0]\ : CFG3
      generic map(INIT => x"A9")

      port map(A => \Curr_State_fast(2)\, B => 
        \Curr_State_fast(1)\, C => \Curr_State_fast(0)\, Y => 
        A0_4_sn_N_3);
    
    \B_ibuf[4]\ : INBUF
      port map(PAD => B(4), Y => \B_c(4)\);
    
    \B_ibuf[25]\ : INBUF
      port map(PAD => B(25), Y => \B_c(25)\);
    
    \B0[8]\ : SLE
      port map(D => \B0_3(8)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \B0(8)\);
    
    \Result_obuf[53]\ : OUTBUF
      port map(D => \Result_c(53)\, PAD => Result(53));
    
    \Result[24]\ : SLE
      port map(D => \P(7)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(24)\);
    
    \Resultce[17]\ : CFG3
      generic map(INIT => x"20")

      port map(A => \Curr_State(1)\, B => \Curr_State_0_rep1\, C
         => \Curr_State(2)\, Y => \Resultce(17)\);
    
    \B_ibuf[9]\ : INBUF
      port map(PAD => B(9), Y => \B_c(9)\);
    
    \Result_obuf[14]\ : OUTBUF
      port map(D => \Result_c(14)\, PAD => Result(14));
    
    \A_ibuf[21]\ : INBUF
      port map(PAD => A(21), Y => \A_c(21)\);
    
    \Result_obuf[9]\ : OUTBUF
      port map(D => \Result_c(9)\, PAD => Result(9));
    
    \A_ibuf[13]\ : INBUF
      port map(PAD => A(13), Y => \A_c(13)\);
    
    \A0[15]\ : SLE
      port map(D => \A0_4(15)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \A0(15)\);
    
    \Result[20]\ : SLE
      port map(D => \P(3)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(20)\);
    
    \B_ibuf[7]\ : INBUF
      port map(PAD => B(7), Y => \B_c(7)\);
    
    \Result_obuf[2]\ : OUTBUF
      port map(D => \Result_c(2)\, PAD => Result(2));
    
    \Curr_State_fast[0]\ : SLE
      port map(D => \Curr_State_ns_fast(0)\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Curr_State_fast(0)\);
    
    \B0_3[15]\ : CFG4
      generic map(INIT => x"0A0C")

      port map(A => \B_c(31)\, B => \B_c(15)\, C => A0_4_sn_N_3, 
        D => B0_3_sn_N_7, Y => \B0_3(15)\);
    
    \B0_3[11]\ : CFG4
      generic map(INIT => x"00AC")

      port map(A => \B_c(28)\, B => \B_c(11)\, C => B0_3_sn_N_7, 
        D => A0_4_sn_N_3, Y => \B0_3(11)\);
    
    \Result_obuf[48]\ : OUTBUF
      port map(D => \Result_c(48)\, PAD => Result(48));
    
    \B_ibuf[11]\ : INBUF
      port map(PAD => B(11), Y => \B_c(11)\);
    
    \B0_3[9]\ : CFG4
      generic map(INIT => x"00AC")

      port map(A => \B_c(26)\, B => \B_c(9)\, C => B0_3_sn_N_7, D
         => A0_4_sn_N_3, Y => \B0_3(9)\);
    
    \GND\ : GND
      port map(Y => GND_net_1);
    
    \A_ibuf[2]\ : INBUF
      port map(PAD => A(2), Y => \A_c(2)\);
    
    \Result[34]\ : SLE
      port map(D => \P(0)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(34)\);
    
    \Result_obuf[5]\ : OUTBUF
      port map(D => \Result_c(5)\, PAD => Result(5));
    
    \B_ibuf[6]\ : INBUF
      port map(PAD => B(6), Y => \B_c(6)\);
    
    \A0_4[0]\ : CFG4
      generic map(INIT => x"3210")

      port map(A => \Curr_State_0_rep1\, B => A0_4_sn_N_3, C => 
        \A_c(17)\, D => \A_c(0)\, Y => \A0_4(0)\);
    
    \Result_obuf[44]\ : OUTBUF
      port map(D => \Result_c(44)\, PAD => Result(44));
    
    \A0_4[2]\ : CFG4
      generic map(INIT => x"3210")

      port map(A => \Curr_State_0_rep1\, B => A0_4_sn_N_3, C => 
        \A_c(19)\, D => \A_c(2)\, Y => \A0_4(2)\);
    
    reset_n_ibuf : INBUF
      port map(PAD => reset_n, Y => \reset_n_ibuf\);
    
    \Result_obuf[55]\ : OUTBUF
      port map(D => \Result_c(55)\, PAD => Result(55));
    
    \B0[4]\ : SLE
      port map(D => \B0_3(4)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \B0(4)\);
    
    \Result_obuf[37]\ : OUTBUF
      port map(D => \Result_c(37)\, PAD => Result(37));
    
    \A_ibuf[28]\ : INBUF
      port map(PAD => A(28), Y => \A_c(28)\);
    
    \Result_obuf[6]\ : OUTBUF
      port map(D => \Result_c(6)\, PAD => Result(6));
    
    \Result[30]\ : SLE
      port map(D => \P(13)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(30)\);
    
    \Result_obuf[30]\ : OUTBUF
      port map(D => \Result_c(30)\, PAD => Result(30));
    
    \Resultce[0]\ : CFG3
      generic map(INIT => x"10")

      port map(A => \Curr_State(1)\, B => \Curr_State_0_rep1\, C
         => \Curr_State(2)\, Y => \Resultce(0)\);
    
    mul_en_ibuf : INBUF
      port map(PAD => mul_en, Y => mul_en_c);
    
    \B0[12]\ : SLE
      port map(D => \B0_3(12)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \B0(12)\);
    
    \Result[14]\ : SLE
      port map(D => \P(14)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(14)\);
    
    \B_ibuf[30]\ : INBUF
      port map(PAD => B(30), Y => \B_c(30)\);
    
    \A0[2]\ : SLE
      port map(D => \A0_4(2)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \A0(2)\);
    
    \Result[5]\ : SLE
      port map(D => \P(5)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(5)\);
    
    \Result[25]\ : SLE
      port map(D => \P(8)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(25)\);
    
    \B0[14]\ : SLE
      port map(D => \B0_3(14)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \B0(14)\);
    
    \Result[57]\ : SLE
      port map(D => \P(23)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(57)\);
    
    \Result_obuf[17]\ : OUTBUF
      port map(D => \Result_c(17)\, PAD => Result(17));
    
    \Result[10]\ : SLE
      port map(D => \P(10)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(10)\);
    
    \B0[11]\ : SLE
      port map(D => \B0_3(11)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \B0(11)\);
    
    \A0_4[14]\ : CFG4
      generic map(INIT => x"3120")

      port map(A => \Curr_State(0)\, B => A0_4_sn_N_3, C => 
        \A_c(14)\, D => \A_c(31)\, Y => \A0_4(14)\);
    
    \A_ibuf[4]\ : INBUF
      port map(PAD => A(4), Y => \A_c(4)\);
    
    \Result[62]\ : SLE
      port map(D => \P(28)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(62)\);
    
    \Curr_State_ns_3_0_.m3_e_0\ : CFG2
      generic map(INIT => x"1")

      port map(A => \Curr_State_fast(1)\, B => mul_en_c, Y => 
        \Curr_State_ns_3_0_.m3_e_0_net_1\);
    
    \Result_obuf[23]\ : OUTBUF
      port map(D => \Result_c(23)\, PAD => Result(23));
    
    \B0[3]\ : SLE
      port map(D => \B0_3(3)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \B0(3)\);
    
    \A_ibuf[9]\ : INBUF
      port map(PAD => A(9), Y => \A_c(9)\);
    
    \Result_obuf[32]\ : OUTBUF
      port map(D => \Result_c(32)\, PAD => Result(32));
    
    \Result_obuf[10]\ : OUTBUF
      port map(D => \Result_c(10)\, PAD => Result(10));
    
    \A_ibuf[14]\ : INBUF
      port map(PAD => A(14), Y => \A_c(14)\);
    
    \A_ibuf[10]\ : INBUF
      port map(PAD => A(10), Y => \A_c(10)\);
    
    \Result_obuf[58]\ : OUTBUF
      port map(D => \Result_c(58)\, PAD => Result(58));
    
    Curr_State_s7_0_a3 : CFG3
      generic map(INIT => x"80")

      port map(A => \Curr_State(2)\, B => \Curr_State(1)\, C => 
        \Curr_State(0)\, Y => Curr_State_23_d);
    
    \B_ibuf[20]\ : INBUF
      port map(PAD => B(20), Y => \B_c(20)\);
    
    \Result[0]\ : SLE
      port map(D => \P(0)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(0)\);
    
    \Result[21]\ : SLE
      port map(D => \P(4)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(21)\);
    
    \Curr_State_ns_3_0_.m7_fast\ : CFG3
      generic map(INIT => x"6A")

      port map(A => \Curr_State_fast(2)\, B => \Curr_State(1)\, C
         => \Curr_State(0)\, Y => N_892_fast);
    
    \Result[35]\ : SLE
      port map(D => \P(1)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(35)\);
    
    \B0_3[3]\ : CFG4
      generic map(INIT => x"00AC")

      port map(A => \B_c(20)\, B => \B_c(3)\, C => B0_3_sn_N_7, D
         => A0_4_sn_N_3, Y => \B0_3(3)\);
    
    \A_ibuf[7]\ : INBUF
      port map(PAD => A(7), Y => \A_c(7)\);
    
    \A_ibuf[19]\ : INBUF
      port map(PAD => A(19), Y => \A_c(19)\);
    
    \Curr_State_fast[1]\ : SLE
      port map(D => N_893_fast, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \Curr_State_fast(1)\);
    
    \Result_obuf[61]\ : OUTBUF
      port map(D => \Result_c(61)\, PAD => Result(61));
    
    \B_ibuf[19]\ : INBUF
      port map(PAD => B(19), Y => \B_c(19)\);
    
    \A0_4[9]\ : CFG4
      generic map(INIT => x"3210")

      port map(A => \Curr_State(0)\, B => A0_4_sn_N_3, C => 
        \A_c(26)\, D => \A_c(9)\, Y => \A0_4(9)\);
    
    \A0_4[8]\ : CFG4
      generic map(INIT => x"3210")

      port map(A => \Curr_State(0)\, B => A0_4_sn_N_3, C => 
        \A_c(25)\, D => \A_c(8)\, Y => \A0_4(8)\);
    
    \VCC\ : VCC
      port map(Y => VCC_net_1);
    
    \Result_obuf[54]\ : OUTBUF
      port map(D => \Result_c(54)\, PAD => Result(54));
    
    \Curr_State[1]\ : SLE
      port map(D => m5, CLK => clk_c, EN => VCC_net_1, ALn => 
        reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Curr_State(1)\);
    
    \B0_3[8]\ : CFG4
      generic map(INIT => x"00AC")

      port map(A => \B_c(25)\, B => \B_c(8)\, C => B0_3_sn_N_7, D
         => A0_4_sn_N_3, Y => \B0_3(8)\);
    
    \A0[16]\ : SLE
      port map(D => \A0_4(16)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \A0(16)\);
    
    \Result_obuf[7]\ : OUTBUF
      port map(D => \Result_c(7)\, PAD => Result(7));
    
    \A0_4[5]\ : CFG4
      generic map(INIT => x"3210")

      port map(A => \Curr_State_0_rep1\, B => A0_4_sn_N_3, C => 
        \A_c(22)\, D => \A_c(5)\, Y => \A0_4(5)\);
    
    \Curr_State_ns_3_0_.m5_fast\ : CFG2
      generic map(INIT => x"6")

      port map(A => \Curr_State(0)\, B => \Curr_State_fast(1)\, Y
         => N_893_fast);
    
    \Curr_State_ns_3_0_.m5\ : CFG2
      generic map(INIT => x"6")

      port map(A => \Curr_State(0)\, B => \Curr_State(1)\, Y => 
        m5);
    
    \Result_obuf[47]\ : OUTBUF
      port map(D => \Result_c(47)\, PAD => Result(47));
    
    \Result[47]\ : SLE
      port map(D => \P(13)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(47)\);
    
    \Result_obuf[12]\ : OUTBUF
      port map(D => \Result_c(12)\, PAD => Result(12));
    
    \B_ibuf[8]\ : INBUF
      port map(PAD => B(8), Y => \B_c(8)\);
    
    \B_ibuf[28]\ : INBUF
      port map(PAD => B(28), Y => \B_c(28)\);
    
    \Result_obuf[40]\ : OUTBUF
      port map(D => \Result_c(40)\, PAD => Result(40));
    
    \B_ibuf[3]\ : INBUF
      port map(PAD => B(3), Y => \B_c(3)\);
    
    \A_ibuf[6]\ : INBUF
      port map(PAD => A(6), Y => \A_c(6)\);
    
    \A0[0]\ : SLE
      port map(D => \A0_4(0)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \A0(0)\);
    
    \Result[2]\ : SLE
      port map(D => \P(2)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(2)\);
    
    ARSHFT17 : SLE
      port map(D => ARSHFT17_3, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \ARSHFT17\);
    
    \Result[15]\ : SLE
      port map(D => \P(15)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(15)\);
    
    \B0_3[7]\ : CFG4
      generic map(INIT => x"00AC")

      port map(A => \B_c(24)\, B => \B_c(7)\, C => B0_3_sn_N_7, D
         => A0_4_sn_N_3, Y => \B0_3(7)\);
    
    \A_ibuf[16]\ : INBUF
      port map(PAD => A(16), Y => \A_c(16)\);
    
    \Result_obuf[25]\ : OUTBUF
      port map(D => \Result_c(25)\, PAD => Result(25));
    
    \Result[52]\ : SLE
      port map(D => \P(18)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(52)\);
    
    \Result[31]\ : SLE
      port map(D => \P(14)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(31)\);
    
    reset_n_ibuf_RNILECB : CLKINT
      port map(A => \reset_n_ibuf\, Y => reset_n_c);
    
    \B0_3[6]\ : CFG4
      generic map(INIT => x"00AC")

      port map(A => \B_c(23)\, B => \B_c(6)\, C => B0_3_sn_N_7, D
         => A0_4_sn_N_3, Y => \B0_3(6)\);
    
    \B_ibuf[22]\ : INBUF
      port map(PAD => B(22), Y => \B_c(22)\);
    
    \Result[58]\ : SLE
      port map(D => \P(24)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(58)\);
    
    \B_ibuf[16]\ : INBUF
      port map(PAD => B(16), Y => \B_c(16)\);
    
    \B0[6]\ : SLE
      port map(D => \B0_3(6)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \B0(6)\);
    
    \A0_4[10]\ : CFG4
      generic map(INIT => x"3210")

      port map(A => \Curr_State(0)\, B => A0_4_sn_N_3, C => 
        \A_c(27)\, D => \A_c(10)\, Y => \A0_4(10)\);
    
    \B0_3[4]\ : CFG4
      generic map(INIT => x"00AC")

      port map(A => \B_c(21)\, B => \B_c(4)\, C => B0_3_sn_N_7, D
         => A0_4_sn_N_3, Y => \B0_3(4)\);
    
    \Result_obuf[42]\ : OUTBUF
      port map(D => \Result_c(42)\, PAD => Result(42));
    
    \B_ibuf[13]\ : INBUF
      port map(PAD => B(13), Y => \B_c(13)\);
    
    \B0_3[13]\ : CFG4
      generic map(INIT => x"00AC")

      port map(A => \B_c(30)\, B => \B_c(13)\, C => B0_3_sn_N_7, 
        D => A0_4_sn_N_3, Y => \B0_3(13)\);
    
    \A_ibuf[15]\ : INBUF
      port map(PAD => A(15), Y => \A_c(15)\);
    
    clk_ibuf : INBUF
      port map(PAD => clk, Y => \clk_ibuf\);
    
    \A0_4[13]\ : CFG4
      generic map(INIT => x"3210")

      port map(A => \Curr_State(0)\, B => A0_4_sn_N_3, C => 
        \A_c(30)\, D => \A_c(13)\, Y => \A0_4(13)\);
    
    \Result[4]\ : SLE
      port map(D => \P(4)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(4)\);
    
    \Result[29]\ : SLE
      port map(D => \P(12)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(29)\);
    
    \Result[11]\ : SLE
      port map(D => \P(11)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(11)\);
    
    \A0[7]\ : SLE
      port map(D => \A0_4(7)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \A0(7)\);
    
    \Curr_State_RNIKEMH[3]\ : CFG4
      generic map(INIT => x"FFFE")

      port map(A => \Curr_State(2)\, B => \Curr_State(1)\, C => 
        \Curr_State_0_rep1\, D => \Curr_State(3)\, Y => N_70_i_0);
    
    \B0_3[14]\ : CFG4
      generic map(INIT => x"0A0C")

      port map(A => \B_c(31)\, B => \B_c(14)\, C => A0_4_sn_N_3, 
        D => B0_3_sn_N_7, Y => \B0_3(14)\);
    
    \Result[23]\ : SLE
      port map(D => \P(6)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(23)\);
    
    \Curr_State_ns_3_0_.m4_rep1\ : CFG4
      generic map(INIT => x"0203")

      port map(A => \Curr_State(2)\, B => \Curr_State_0_rep1\, C
         => \Curr_State(3)\, D => 
        \Curr_State_ns_3_0_.m3_e_0_net_1\, Y => 
        \Curr_State_ns_rep1(0)\);
    
    \Result[26]\ : SLE
      port map(D => \P(9)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(26)\);
    
    \Result[42]\ : SLE
      port map(D => \P(8)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(42)\);
    
    \B_ibuf[15]\ : INBUF
      port map(PAD => B(15), Y => \B_c(15)\);
    
    \Result_obuf[57]\ : OUTBUF
      port map(D => \Result_c(57)\, PAD => Result(57));
    
    \Result_obuf[28]\ : OUTBUF
      port map(D => \Result_c(28)\, PAD => Result(28));
    
    \B_ibuf[1]\ : INBUF
      port map(PAD => B(1), Y => \B_c(1)\);
    
    \Result[48]\ : SLE
      port map(D => \P(14)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(48)\);
    
    \Curr_State_fast[2]\ : SLE
      port map(D => N_892_fast, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => 
        \Curr_State_fast(2)\);
    
    \Result_obuf[50]\ : OUTBUF
      port map(D => \Result_c(50)\, PAD => Result(50));
    
    \A_ibuf[11]\ : INBUF
      port map(PAD => A(11), Y => \A_c(11)\);
    
    \Result_obuf[24]\ : OUTBUF
      port map(D => \Result_c(24)\, PAD => Result(24));
    
    \Result_obuf[1]\ : OUTBUF
      port map(D => \Result_c(1)\, PAD => Result(1));
    
    mul_result_valid_obuf : OUTBUF
      port map(D => \Curr_State(3)\, PAD => mul_result_valid);
    
    \Result[60]\ : SLE
      port map(D => \P(26)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(60)\);
    
    \Result[39]\ : SLE
      port map(D => \P(5)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(39)\);
    
    \B0[10]\ : SLE
      port map(D => \B0_3(10)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \B0(10)\);
    
    \Result[6]\ : SLE
      port map(D => \P(6)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(6)\);
    
    \B_ibuf[24]\ : INBUF
      port map(PAD => B(24), Y => \B_c(24)\);
    
    \A0[8]\ : SLE
      port map(D => \A0_4(8)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \A0(8)\);
    
    \Result[33]\ : SLE
      port map(D => \P(16)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(33)\);
    
    \Result[36]\ : SLE
      port map(D => \P(2)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(36)\);
    
    \A_ibuf[8]\ : INBUF
      port map(PAD => A(8), Y => \A_c(8)\);
    
    \A_ibuf[3]\ : INBUF
      port map(PAD => A(3), Y => \A_c(3)\);
    
    \B0_3[1]\ : CFG4
      generic map(INIT => x"00AC")

      port map(A => \B_c(18)\, B => \B_c(1)\, C => B0_3_sn_N_7, D
         => A0_4_sn_N_3, Y => \B0_3(1)\);
    
    \B0[9]\ : SLE
      port map(D => \B0_3(9)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \B0(9)\);
    
    \Result_obuf[31]\ : OUTBUF
      port map(D => \Result_c(31)\, PAD => Result(31));
    
    \Result_obuf[52]\ : OUTBUF
      port map(D => \Result_c(52)\, PAD => Result(52));
    
    \Result_obuf[63]\ : OUTBUF
      port map(D => \Result_c(63)\, PAD => Result(63));
    
    \Result[19]\ : SLE
      port map(D => \P(2)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(19)\);
    
    \A0_4[16]\ : CFG4
      generic map(INIT => x"3120")

      port map(A => \Curr_State(0)\, B => A0_4_sn_N_3, C => 
        \A_c(16)\, D => \A_c(31)\, Y => \A0_4(16)\);
    
    \A0[10]\ : SLE
      port map(D => \A0_4(10)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \A0(10)\);
    
    \A_ibuf[27]\ : INBUF
      port map(PAD => A(27), Y => \A_c(27)\);
    
    \A_ibuf[18]\ : INBUF
      port map(PAD => A(18), Y => \A_c(18)\);
    
    \Result_obuf[8]\ : OUTBUF
      port map(D => \Result_c(8)\, PAD => Result(8));
    
    \Result_obuf[39]\ : OUTBUF
      port map(D => \Result_c(39)\, PAD => Result(39));
    
    \Result[54]\ : SLE
      port map(D => \P(20)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(54)\);
    
    \Result[13]\ : SLE
      port map(D => \P(13)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(13)\);
    
    \B0_3[10]\ : CFG4
      generic map(INIT => x"00AC")

      port map(A => \B_c(27)\, B => \B_c(10)\, C => B0_3_sn_N_7, 
        D => A0_4_sn_N_3, Y => \B0_3(10)\);
    
    \Result[16]\ : SLE
      port map(D => \P(16)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(16)\);
    
    clk_ibuf_RNIVTI2 : CLKINT
      port map(A => \clk_ibuf\, Y => clk_c);
    
    \Result_obuf[36]\ : OUTBUF
      port map(D => \Result_c(36)\, PAD => Result(36));
    
    \Result[9]\ : SLE
      port map(D => \P(9)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(9)\);
    
    \B_ibuf[0]\ : INBUF
      port map(PAD => B(0), Y => \B_c(0)\);
    
    \B0[5]\ : SLE
      port map(D => \B0_3(5)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \B0(5)\);
    
    \A0[17]\ : SLE
      port map(D => \A0_4(17)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \A0(17)\);
    
    \Result[50]\ : SLE
      port map(D => \P(16)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(50)\);
    
    \B_ibuf[27]\ : INBUF
      port map(PAD => B(27), Y => \B_c(27)\);
    
    \B0[1]\ : SLE
      port map(D => \B0_3(1)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \B0(1)\);
    
    \A0[4]\ : SLE
      port map(D => \A0_4(4)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \A0(4)\);
    
    \Result_obuf[11]\ : OUTBUF
      port map(D => \Result_c(11)\, PAD => Result(11));
    
    \B0_3[0]\ : CFG4
      generic map(INIT => x"00AC")

      port map(A => \B_c(17)\, B => \B_c(0)\, C => B0_3_sn_N_7, D
         => A0_4_sn_N_3, Y => \B0_3(0)\);
    
    \Result_obuf[19]\ : OUTBUF
      port map(D => \Result_c(19)\, PAD => Result(19));
    
    \Result_obuf[27]\ : OUTBUF
      port map(D => \Result_c(27)\, PAD => Result(27));
    
    \Result_obuf[3]\ : OUTBUF
      port map(D => \Result_c(3)\, PAD => Result(3));
    
    \B0_3[5]\ : CFG4
      generic map(INIT => x"00AC")

      port map(A => \B_c(22)\, B => \B_c(5)\, C => B0_3_sn_N_7, D
         => A0_4_sn_N_3, Y => \B0_3(5)\);
    
    \A_ibuf[1]\ : INBUF
      port map(PAD => A(1), Y => \A_c(1)\);
    
    \Result[44]\ : SLE
      port map(D => \P(10)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(44)\);
    
    \Result_obuf[16]\ : OUTBUF
      port map(D => \Result_c(16)\, PAD => Result(16));
    
    \B_ibuf[10]\ : INBUF
      port map(PAD => B(10), Y => \B_c(10)\);
    
    \Result_obuf[20]\ : OUTBUF
      port map(D => \Result_c(20)\, PAD => Result(20));
    
    \Result[61]\ : SLE
      port map(D => \P(27)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(61)\);
    
    \Result[8]\ : SLE
      port map(D => \P(8)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(8)\);
    
    \A_ibuf[22]\ : INBUF
      port map(PAD => A(22), Y => \A_c(22)\);
    
    \A0[12]\ : SLE
      port map(D => \A0_4(12)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \A0(12)\);
    
    \Result_obuf[41]\ : OUTBUF
      port map(D => \Result_c(41)\, PAD => Result(41));
    
    \Result[40]\ : SLE
      port map(D => \P(6)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(40)\);
    
    \B_ibuf[31]\ : INBUF
      port map(PAD => B(31), Y => \B_c(31)\);
    
    \A0[3]\ : SLE
      port map(D => \A0_4(3)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \A0(3)\);
    
    \A0_4[7]\ : CFG4
      generic map(INIT => x"3210")

      port map(A => \Curr_State_0_rep1\, B => A0_4_sn_N_3, C => 
        \A_c(24)\, D => \A_c(7)\, Y => \A0_4(7)\);
    
    \Result[55]\ : SLE
      port map(D => \P(21)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(55)\);
    
    \Result_obuf[49]\ : OUTBUF
      port map(D => \Result_c(49)\, PAD => Result(49));
    
    \Result_obuf[0]\ : OUTBUF
      port map(D => \Result_c(0)\, PAD => Result(0));
    
    \B_ibuf[18]\ : INBUF
      port map(PAD => B(18), Y => \B_c(18)\);
    
    \A_ibuf[23]\ : INBUF
      port map(PAD => A(23), Y => \A_c(23)\);
    
    \Curr_State_ns_3_0_.m4\ : CFG4
      generic map(INIT => x"0051")

      port map(A => \Curr_State(0)\, B => 
        \Curr_State_ns_3_0_.m3_e_0_net_1\, C => \Curr_State(2)\, 
        D => \Curr_State(3)\, Y => \Curr_State_ns(0)\);
    
    \Result_obuf[46]\ : OUTBUF
      port map(D => \Result_c(46)\, PAD => Result(46));
    
    \Result_obuf[22]\ : OUTBUF
      port map(D => \Result_c(22)\, PAD => Result(22));
    
    \A0_RNO[17]\ : CFG4
      generic map(INIT => x"1020")

      port map(A => \Curr_State(1)\, B => \Curr_State(0)\, C => 
        \A_c(31)\, D => \Curr_State(2)\, Y => \A0_4(17)\);
    
    ARSHFT17_3_0_a3 : CFG3
      generic map(INIT => x"06")

      port map(A => \Curr_State(2)\, B => \Curr_State(1)\, C => 
        \Curr_State(0)\, Y => ARSHFT17_3);
    
    \Result[27]\ : SLE
      port map(D => \P(10)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(27)\);
    
    \B0[15]\ : SLE
      port map(D => \B0_3(15)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \B0(15)\);
    
    \A0[13]\ : SLE
      port map(D => \A0_4(13)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \A0(13)\);
    
    \Curr_State[2]\ : SLE
      port map(D => m7, CLK => clk_c, EN => VCC_net_1, ALn => 
        reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \Curr_State(2)\);
    
    \B_ibuf[21]\ : INBUF
      port map(PAD => B(21), Y => \B_c(21)\);
    
    \Result[7]\ : SLE
      port map(D => \P(7)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(7)\);
    
    \Curr_State_fast_RNIMB43[0]\ : CFG3
      generic map(INIT => x"EA")

      port map(A => \Curr_State_fast(2)\, B => 
        \Curr_State_fast(1)\, C => \Curr_State_fast(0)\, Y => 
        B0_3_sn_N_7);
    
    \B_ibuf[5]\ : INBUF
      port map(PAD => B(5), Y => \B_c(5)\);
    
    \B_ibuf[12]\ : INBUF
      port map(PAD => B(12), Y => \B_c(12)\);
    
    \A0_4[12]\ : CFG4
      generic map(INIT => x"3210")

      port map(A => \Curr_State(0)\, B => A0_4_sn_N_3, C => 
        \A_c(29)\, D => \A_c(12)\, Y => \A0_4(12)\);
    
    \B0[2]\ : SLE
      port map(D => \B0_3(2)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \B0(2)\);
    
    \A_ibuf[0]\ : INBUF
      port map(PAD => A(0), Y => \A_c(0)\);
    
    \Result[51]\ : SLE
      port map(D => \P(17)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(51)\);
    
    \A0[14]\ : SLE
      port map(D => \A0_4(14)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \A0(14)\);
    
    \Result_obuf[33]\ : OUTBUF
      port map(D => \Result_c(33)\, PAD => Result(33));
    
    \Result[45]\ : SLE
      port map(D => \P(11)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(45)\);
    
    \B0_3[12]\ : CFG4
      generic map(INIT => x"00AC")

      port map(A => \B_c(29)\, B => \B_c(12)\, C => B0_3_sn_N_7, 
        D => A0_4_sn_N_3, Y => \B0_3(12)\);
    
    \Curr_State_ns_3_0_.m4_fast\ : CFG4
      generic map(INIT => x"0023")

      port map(A => \Curr_State(2)\, B => \Curr_State_fast(0)\, C
         => \Curr_State_ns_3_0_.m3_e_0_net_1\, D => 
        \Curr_State(3)\, Y => \Curr_State_ns_fast(0)\);
    
    \A_ibuf[30]\ : INBUF
      port map(PAD => A(30), Y => \A_c(30)\);
    
    \Result[63]\ : SLE
      port map(D => \P(29)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(63)\);
    
    \Result[37]\ : SLE
      port map(D => \P(3)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(37)\);
    
    U1 : acc_0
      port map(P(29) => \P(29)\, P(28) => \P(28)\, P(27) => 
        \P(27)\, P(26) => \P(26)\, P(25) => \P(25)\, P(24) => 
        \P(24)\, P(23) => \P(23)\, P(22) => \P(22)\, P(21) => 
        \P(21)\, P(20) => \P(20)\, P(19) => \P(19)\, P(18) => 
        \P(18)\, P(17) => \P(17)\, P(16) => \P(16)\, P(15) => 
        \P(15)\, P(14) => \P(14)\, P(13) => \P(13)\, P(12) => 
        \P(12)\, P(11) => \P(11)\, P(10) => \P(10)\, P(9) => 
        \P(9)\, P(8) => \P(8)\, P(7) => \P(7)\, P(6) => \P(6)\, 
        P(5) => \P(5)\, P(4) => \P(4)\, P(3) => \P(3)\, P(2) => 
        \P(2)\, P(1) => \P(1)\, P(0) => \P(0)\, A0(17) => 
        \A0(17)\, A0(16) => \A0(16)\, A0(15) => \A0(15)\, A0(14)
         => \A0(14)\, A0(13) => \A0(13)\, A0(12) => \A0(12)\, 
        A0(11) => \A0(11)\, A0(10) => \A0(10)\, A0(9) => \A0(9)\, 
        A0(8) => \A0(8)\, A0(7) => \A0(7)\, A0(6) => \A0(6)\, 
        A0(5) => \A0(5)\, A0(4) => \A0(4)\, A0(3) => \A0(3)\, 
        A0(2) => \A0(2)\, A0(1) => \A0(1)\, A0(0) => \A0(0)\, 
        B0(17) => \B0(17)\, B0(16) => \B0(16)\, B0(15) => 
        \B0(15)\, B0(14) => \B0(14)\, B0(13) => \B0(13)\, B0(12)
         => \B0(12)\, B0(11) => \B0(11)\, B0(10) => \B0(10)\, 
        B0(9) => \B0(9)\, B0(8) => \B0(8)\, B0(7) => \B0(7)\, 
        B0(6) => \B0(6)\, B0(5) => \B0(5)\, B0(4) => \B0(4)\, 
        B0(3) => \B0(3)\, B0(2) => \B0(2)\, B0(1) => \B0(1)\, 
        B0(0) => \B0(0)\, reset_n_c => reset_n_c, N_70_i_0 => 
        N_70_i_0, clk_c => clk_c, ARSHFT17 => \ARSHFT17\);
    
    \Result_obuf[51]\ : OUTBUF
      port map(D => \Result_c(51)\, PAD => Result(51));
    
    \A0_4[4]\ : CFG4
      generic map(INIT => x"3210")

      port map(A => \Curr_State_0_rep1\, B => A0_4_sn_N_3, C => 
        \A_c(21)\, D => \A_c(4)\, Y => \A0_4(4)\);
    
    \Curr_State[0]\ : SLE
      port map(D => \Curr_State_ns(0)\, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Curr_State(0)\);
    
    \A0[6]\ : SLE
      port map(D => \A0_4(6)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \A0(6)\);
    
    \B0_3[2]\ : CFG4
      generic map(INIT => x"00AC")

      port map(A => \B_c(19)\, B => \B_c(2)\, C => B0_3_sn_N_7, D
         => A0_4_sn_N_3, Y => \B0_3(2)\);
    
    \Result_obuf[59]\ : OUTBUF
      port map(D => \Result_c(59)\, PAD => Result(59));
    
    \Curr_State_ns_3_0_.m7\ : CFG3
      generic map(INIT => x"6A")

      port map(A => \Curr_State(2)\, B => \Curr_State(1)\, C => 
        \Curr_State(0)\, Y => m7);
    
    \Result_obuf[4]\ : OUTBUF
      port map(D => \Result_c(4)\, PAD => Result(4));
    
    \Result_obuf[13]\ : OUTBUF
      port map(D => \Result_c(13)\, PAD => Result(13));
    
    \Result[41]\ : SLE
      port map(D => \P(7)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(41)\);
    
    \Result_obuf[56]\ : OUTBUF
      port map(D => \Result_c(56)\, PAD => Result(56));
    
    \Result[22]\ : SLE
      port map(D => \P(5)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(22)\);
    
    \B0[17]\ : SLE
      port map(D => \B0_3(17)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \B0(17)\);
    
    \A0[11]\ : SLE
      port map(D => \A0_4(11)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \A0(11)\);
    
    \Result[17]\ : SLE
      port map(D => \P(0)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(17)\);
    
    \A0_4[3]\ : CFG4
      generic map(INIT => x"3210")

      port map(A => \Curr_State_0_rep1\, B => A0_4_sn_N_3, C => 
        \A_c(20)\, D => \A_c(3)\, Y => \A0_4(3)\);
    
    \Result_obuf[35]\ : OUTBUF
      port map(D => \Result_c(35)\, PAD => Result(35));
    
    \B0[13]\ : SLE
      port map(D => \B0_3(13)\, CLK => clk_c, EN => VCC_net_1, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \B0(13)\);
    
    \A_ibuf[24]\ : INBUF
      port map(PAD => A(24), Y => \A_c(24)\);
    
    \A_ibuf[20]\ : INBUF
      port map(PAD => A(20), Y => \A_c(20)\);
    
    \B_ibuf[14]\ : INBUF
      port map(PAD => B(14), Y => \B_c(14)\);
    
    \Curr_State[3]\ : SLE
      port map(D => Curr_State_23_d, CLK => clk_c, EN => 
        VCC_net_1, ALn => reset_n_c, ADn => VCC_net_1, SLn => 
        VCC_net_1, SD => GND_net_1, LAT => GND_net_1, Q => 
        \Curr_State(3)\);
    
    \Result[28]\ : SLE
      port map(D => \P(11)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(28)\);
    
    \B0[0]\ : SLE
      port map(D => \B0_3(0)\, CLK => clk_c, EN => VCC_net_1, ALn
         => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD => 
        GND_net_1, LAT => GND_net_1, Q => \B0(0)\);
    
    \Result[59]\ : SLE
      port map(D => \P(25)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(59)\);
    
    \A_ibuf[29]\ : INBUF
      port map(PAD => A(29), Y => \A_c(29)\);
    
    \B_ibuf[29]\ : INBUF
      port map(PAD => B(29), Y => \B_c(29)\);
    
    \B0_3[16]\ : CFG4
      generic map(INIT => x"0A0C")

      port map(A => \B_c(31)\, B => \B_c(16)\, C => A0_4_sn_N_3, 
        D => B0_3_sn_N_7, Y => \B0_3(16)\);
    
    \Result[53]\ : SLE
      port map(D => \P(19)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(53)\);
    
    \Result[56]\ : SLE
      port map(D => \P(22)\, CLK => clk_c, EN => \Resultce(34)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(56)\);
    
    \Result_obuf[43]\ : OUTBUF
      port map(D => \Result_c(43)\, PAD => Result(43));
    
    \A_ibuf[17]\ : INBUF
      port map(PAD => A(17), Y => \A_c(17)\);
    
    \Result[1]\ : SLE
      port map(D => \P(1)\, CLK => clk_c, EN => \Resultce(0)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(1)\);
    
    \Result[32]\ : SLE
      port map(D => \P(15)\, CLK => clk_c, EN => \Resultce(17)\, 
        ALn => reset_n_c, ADn => VCC_net_1, SLn => VCC_net_1, SD
         => GND_net_1, LAT => GND_net_1, Q => \Result_c(32)\);
    
    \A_ibuf[5]\ : INBUF
      port map(PAD => A(5), Y => \A_c(5)\);
    

end DEF_ARCH; 
