--------------------------------------------------------------------------------
-- Company: MICROSEMI
--
-- File: ExtendedAdder_testbech.vhd
--
-- File history:
--      v1.0: APR 27-04-13: 
--
-- Description	  : 3-input Extended addition Test bench
-- 					A simple testbench provides inputs(A,B,C,D) to the Extended_adder_3_input
--
-- Targeted device: Family		:: SmartFusion2  
-- 					  Die		:: M2S050T
--					  Package	:: 896 FBGA
--		Author	  : PHANIKIRAN T
--------------------------------------------------------------------------------


library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity ExtendedAdder_testbench is
end ExtendedAdder_testbench;

architecture behavioral of ExtendedAdder_testbench is

component Extended_adder_3_input is
port(	clk			: in std_logic;
		reset_n		: in std_logic;

		INPUTA		: in std_logic_vector(17 downto 0);
		INPUTB		: in std_logic_vector(17 downto 0);
		INPUTC		: in std_logic_vector(51 downto 0);
		INPUTD		: in std_logic_vector(51 downto 0);

		AddOutput	: out std_logic_vector(51 downto 0)
		
         );
end component Extended_adder_3_input;

CONSTANT clk_period : time := 10 ns;
signal clk		: STD_LOGIC:= '0';
signal reset_n	: STD_LOGIC:= '0';

signal Xn_in	: STD_LOGIC_VECTOR(8 downto 0):= (OTHERS=> '0');
signal INPUTA	: STD_LOGIC_VECTOR(17 downto 0):=(OTHERS=> '0');
signal INPUTB	: STD_LOGIC_VECTOR(17 downto 0):=(OTHERS=> '0');
signal INPUTC	: STD_LOGIC_VECTOR(51 downto 0):=(OTHERS=> '0');
signal INPUTD	: STD_LOGIC_VECTOR(51 downto 0):=(OTHERS=> '0');

signal AddOutput: STD_LOGIC_VECTOR(51 downto 0);
SIGNAL stop 	: std_logic := '0';	


begin


UUT: Extended_adder_3_input
		port map(	
				clk 	=> clk,
				reset_n => reset_n,
				INPUTA	=> INPUTA,
				INPUTB	=> INPUTB,
				INPUTC	=> INPUTC,
				INPUTD	=> INPUTD,
				AddOutput => AddOutput
         );

--- clock and reset generation 

 clk_proc :process
   begin
		IF(stop = '0')THEN
	        clk <= '0';
    	    wait for clk_period/2;
        	clk <= '1';
	        wait for clk_period/2;
		ELSE
			clk <= '0';
		END IF;
   end process;

  stim_proc: process
   begin

        reset_n <='0';
        wait for 20 ns;
        reset_n	<='1';
        wait;
  end process;

-- Data vectors to 6-Tap FIR filter


process(clk,reset_n)
begin
if(reset_n ='0')then
	Xn_in <=(others => '0');
else
	if(clk='1' and clk'event)then
		if(stop = '0')then
			Xn_in <= Xn_in + '1';
		end if;
	end if;
end if;
end process;



process
begin
		wait until (reset_n ='1');
		wait until rising_edge(clk);
		INPUTA	<= "000000000000011010";
		INPUTB	<= "000000000000011010";
		INPUTC	<= X"7ACCC6ADCDCAF";
		INPUTD	<= X"99C55234F0985";--res = 1149218E2BE634
		wait for 60 ns;
		wait until rising_edge(clk);
		INPUTC	<= X"0122BCBBBBAA6";
		INPUTD	<= X"03456666332BD";--res = 4682321EED63
		wait for 60 ns;
		wait until rising_edge(clk);
		INPUTC	<= X"AACCC6ADCDCAF";
		INPUTD	<= X"EEBDC16458754";--res = 1998A881226403
		wait for 100 ns;
		wait until rising_edge(clk);
			stop <=  '1';
		
		report "TEST FINISHED!"
		severity failure;
		--wait;
end process;

end behavioral;

