Project Settings
Project Name | Extended_adder_2_input_syn | Implementation Name | synthesis
Top Module | work.Extended_adder_2_input | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
Compile Input | Complete | 10 | 4 | 0 | - | 0m:01s | - | 5/21/2014 6:23:20 PM
Pre-mapping | Complete | 3 | 1 | 0 | 0m:00s | 0m:00s | 133MB | 5/21/2014 6:23:21 PM
Map & Optimize | Complete | 10 | 1 | 0 | 0m:00s | 0m:01s | 133MB | 5/21/2014 6:23:23 PM
Area Summary
Carry Cells | 8 | Sequential Cells | 52
DSP Blocks (MACC) (dsp_used) | 1 | I/O Cells | 142
Global Clock Buffers | 2 | LUTs (total_luts) | 8
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
Extended_adder_2_input|clk | 100.0 MHz | NA | NA
System | 100.0 MHz | 319.0 MHz | 6.865
Optimizations Summary
Combined Clock Conversion | 1 / 0 |  |