--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: Extendedadder_2_input.vhd
-- File history:
--      <Revision number>: <Date>: <Comments>
--      <Revision number>: <Date>: <Comments>
--      <Revision number>: <Date>: <Comments>
--
-- Description: 
--
-- <Description here>
--
-- Targeted device: <Family::SmartFusion2> <Die::M2S050T> <Package::896 FBGA>
-- Author: <Name>
--
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
-- Company: MICROSEMI
--
-- File: Extendedadder_Testbech.vhd
--
-- File history:
--      v1.0: APR 27-04-13: 
--
-- Description	  : 6 tap Systolic FIR filter testbench
--
-- Targeted device: Family		:: SmartFusion2  
-- 					  Die		:: M2S050T
--					  Package	:: 896 FBGA
--		Author	  : PHANIKIRAN T
--------------------------------------------------------------------------------

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;


entity Extendedadder_Testbech is
end Extendedadder_Testbech;


architecture testbench_arch of Extendedadder_Testbech is

component FIR_6tap is
	port(clk			: in std_logic;
		reset_n			: in std_logic;
		Xn_in			: in std_logic_vector(8 downto 0);
		Yn_out			: out std_logic_vector(34 downto 0)	 	   	   	             	     	     	     	            
         );
end component FIR_6tap;


CONSTANT clk_period : time := 10 ns;

signal clk		: STD_LOGIC:= '0';
signal reset_n	: STD_LOGIC:= '0';

signal Xn_in	: STD_LOGIC_VECTOR(8 downto 0):= (OTHERS=> '0');
signal Yn_out	: STD_LOGIC_VECTOR(34 downto 0);

SIGNAL stop 	: std_logic := '0';	


begin


UUT: FIR_6tap
		port map(	
				clk 	=> clk,
				reset_n => reset_n,
				Xn_in 	=> Xn_in,
				Yn_out	=> Yn_out
         );

--- clock and reset generation 

 clk_proc :process
   begin
		IF(stop = '0')THEN
	        clk <= '0';
    	    wait for clk_period/2;
        	clk <= '1';
	        wait for clk_period/2;
		ELSE
			clk <= '0';
		END IF;
   end process;

  stim_proc: process
   begin

        reset_n 	<='0';
        wait for 20 ns;
        reset_n	<='1';
        wait;
  end process;


-- Data vectors to 6-Tap FIR filter


process(clk,reset_n)
begin
if(reset_n ='0')then
	Xn_in <=(others => '0');
else
	if(clk='1' and clk'event)then
		if(stop = '0')then
			Xn_in <= Xn_in + '1';
		end if;
	end if;
end if;
end process;



process
begin
		wait until (Xn_in = "001100100");
		wait until rising_edge(clk);
			stop <=  '1';
		
		report "TEST FINISHED!"
		severity failure;
		--wait;
end process;
end testbench_arch;

