`

    #Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014
    #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1
    #OS: Windows 7 6.1
    #Hostname: W764-TADIGADAPA

    #Implementation: synthesis

    $ Start of Compile
    #Wed May 21 20:34:13 2014

    Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    @N: : Systolic_Symmetric_FIR.vhd(23) | Top entity is set to Systolic_Symmetric_FIR.
    VHDL syntax check successful!
    @N:CD630 : Systolic_Symmetric_FIR.vhd(23) | Synthesizing work.systolic_symmetric_fir.systolicfir_filter_arch
    @W:CD638 : Systolic_Symmetric_FIR.vhd(94) | Signal P_0 is undriven
    @W:CD638 : Systolic_Symmetric_FIR.vhd(97) | Signal coef is undriven
    @W:CD638 : Systolic_Symmetric_FIR.vhd(108) | Signal y is undriven
    @N:CD630 : multadd_0.vhd(17) | Synthesizing work.multadd_0.rtl
    @N:CD630 : multadd_0_multadd_0_0_HARD_MULT_ADDSUB.vhd(8) | Synthesizing work.multadd_0_multadd_0_0_hard_mult_addsub.def_arch
    @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box
    Post processing for smartfusion2.vcc.syn_black_box
    @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box
    Post processing for smartfusion2.gnd.syn_black_box
    @N:CD630 : smartfusion2.vhd(695) | Synthesizing smartfusion2.macc.syn_black_box
    Post processing for smartfusion2.macc.syn_black_box
    Post processing for work.multadd_0_multadd_0_0_hard_mult_addsub.def_arch
    Post processing for work.multadd_0.rtl
    Post processing for work.systolic_symmetric_fir.systolicfir_filter_arch
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 0 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 1 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 2 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 3 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 4 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 5 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 6 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 7 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 8 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 9 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 10 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 11 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 12 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 13 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 14 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 15 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 16 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 17 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 18 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 19 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 20 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 21 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 22 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 23 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 24 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 25 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 26 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 27 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 28 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 29 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 30 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 31 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 32 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 33 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 34 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 35 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 36 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 37 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 38 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 39 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 40 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 41 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 42 of signal P_0 is floating -- simulation mismatch possible.
    @W:CL252 : Systolic_Symmetric_FIR.vhd(94) | Bit 43 of signal P_0 is floating -- simulation mismatch possible.
    @END

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 20:34:14 2014

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Linked File: DSP
    Printing clock  summary report in "D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Parallel FIR\Systolic_Symmetric_FIR\synthesis\Systolic_Symmetric_FIR_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB)

    syn_allowed_resources : blockrams=69  set on top level netlist Systolic_Symmetric_FIR

    Clock Summary
    **************

    Start                          Requested     Requested     Clock        Clock
    Clock                          Frequency     Period        Type         Group
    ---------------------------------------------------------------------------------------------
    System                         1.0 MHz       1000.000      system       system_clkgroup
    Systolic_Symmetric_FIR|Clk     475.3 MHz     2.104         inferred     Autoconstr_clkgroup_0
    =============================================================================================

    @W:MT530 : multadd_0_multadd_0_0_hard_mult_addsub.vhd(108) | Found inferred clock Systolic_Symmetric_FIR|Clk which controls 432 sequential elements including MUL1.multadd_0_0.U0. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Parallel FIR\Systolic_Symmetric_FIR\synthesis\Systolic_Symmetric_FIR.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 134MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 20:34:15 2014

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		    -6.75ns		 145 /       432
    ------------------------------------------------------------

    @N:FX271 : systolic_symmetric_fir.vhd(135) | Instance "Xreg_15[0]" with 8 loads replicated 1 times to improve timing
    @N:FX271 : systolic_symmetric_fir.vhd(135) | Instance "Xreg_15[1]" with 8 loads replicated 1 times to improve timing
    Timing driven replication report
    Added 2 Registers via timing driven replication
    Added 0 LUTs via timing driven replication

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		    -6.63ns		 145 /       434
    ------------------------------------------------------------

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		    -6.63ns		 145 /       434
    ------------------------------------------------------------

    @N:FP130 :  | Promoting Net Clk_c on CLKINT  I_1
    @N:FP130 :  | Promoting Net resetn_c on CLKINT  I_2

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    1 non-gated/non-generated clock tree(s) driving 450 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId0001        Clk                 port                   450        Xreg_10[0]
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Writing Analyst data base D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Parallel FIR\Systolic_Symmetric_FIR\synthesis\Systolic_Symmetric_FIR.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 132MB peak: 134MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    I-2013.09M-SP1

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 132MB peak: 134MB)

    @W:MT420 :  | Found inferred clock Systolic_Symmetric_FIR|Clk with period 2.13ns. Please declare a user-defined clock on object "p:Clk"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed May 21 20:34:17 2014
    #

    Top view:               Systolic_Symmetric_FIR
    Requested Frequency:    469.7 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: -0.376

                                   Requested      Estimated      Requested     Estimated                Clock        Clock
    Starting Clock                 Frequency      Frequency      Period        Period        Slack      Type         Group
    --------------------------------------------------------------------------------------------------------------------------------------
    Systolic_Symmetric_FIR|Clk     469.7 MHz      399.3 MHz      2.129         2.505         -0.376     inferred     Autoconstr_clkgroup_0
    System                         1211.1 MHz     1029.4 MHz     0.826         0.971         -0.146     system       system_clkgroup
    ======================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                  |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -----------------------------------------------------------------------------------------------------------------------------------------------
    Starting                    Ending                      |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    -----------------------------------------------------------------------------------------------------------------------------------------------
    System                      System                      |  0.826       -0.146  |  No paths    -      |  No paths    -      |  No paths    -
    Systolic_Symmetric_FIR|Clk  System                      |  2.129       1.063   |  No paths    -      |  No paths    -      |  No paths    -
    Systolic_Symmetric_FIR|Clk  Systolic_Symmetric_FIR|Clk  |  2.129       -0.376  |  No paths    -      |  No paths    -      |  No paths    -
    ===============================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: Systolic_Symmetric_FIR|Clk
    ====================================

    Starting Points with Worst Slack
    ********************************

                        Starting                                                            Arrival
    Instance            Reference                      Type     Pin     Net                 Time        Slack
                        Clock
    ----------------------------------------------------------------------------------------------------------
    Xreg_15[2]          Systolic_Symmetric_FIR|Clk     SLE      Q       Xreg_15[2]          0.094       -0.376
    Xreg_15[3]          Systolic_Symmetric_FIR|Clk     SLE      Q       Xreg_15[3]          0.094       -0.361
    Xreg_15[4]          Systolic_Symmetric_FIR|Clk     SLE      Q       Xreg_15[4]          0.094       -0.347
    Xreg_15[5]          Systolic_Symmetric_FIR|Clk     SLE      Q       Xreg_15[5]          0.094       -0.333
    Xreg_15[6]          Systolic_Symmetric_FIR|Clk     SLE      Q       Xreg_15[6]          0.094       -0.319
    Xreg_15[7]          Systolic_Symmetric_FIR|Clk     SLE      Q       Xreg_15[7]          0.094       -0.305
    Xreg_15[0]          Systolic_Symmetric_FIR|Clk     SLE      Q       un48_sum            0.094       -0.300
    Xreg_15_fast[0]     Systolic_Symmetric_FIR|Clk     SLE      Q       Xreg_15_fast[0]     0.094       -0.300
    Xreg_14[0]          Systolic_Symmetric_FIR|Clk     SLE      Q       Xreg_14[0]          0.094       -0.300
    Xreg_15[8]          Systolic_Symmetric_FIR|Clk     SLE      Q       Xreg_15[8]          0.094       -0.290
    ==========================================================================================================

    Ending Points with Worst Slack
    ******************************

                  Starting                                                              Required
    Instance      Reference                      Type     Pin     Net                   Time         Slack
                  Clock
    -------------------------------------------------------------------------------------------------------
    sum_0[17]     Systolic_Symmetric_FIR|Clk     SLE      D       un12_sum_s_17_S       1.907        -0.376
    sum_1[17]     Systolic_Symmetric_FIR|Clk     SLE      D       un20_sum_s_17_S       1.907        -0.376
    sum_2[17]     Systolic_Symmetric_FIR|Clk     SLE      D       un27_sum_s_17_S       1.907        -0.376
    sum_3[17]     Systolic_Symmetric_FIR|Clk     SLE      D       un34_sum_s_17_S       1.907        -0.376
    sum_4[17]     Systolic_Symmetric_FIR|Clk     SLE      D       un41_sum_s_17_S       1.907        -0.376
    sum_5[17]     Systolic_Symmetric_FIR|Clk     SLE      D       un48_sum_s_17_S       1.907        -0.376
    sum_6[17]     Systolic_Symmetric_FIR|Clk     SLE      D       un55_sum_s_17_S       1.907        -0.376
    sum_7[17]     Systolic_Symmetric_FIR|Clk     SLE      D       un62_sum_s_17_S       1.907        -0.376
    sum_0[16]     Systolic_Symmetric_FIR|Clk     SLE      D       un12_sum_cry_16_S     1.907        -0.361
    sum_1[16]     Systolic_Symmetric_FIR|Clk     SLE      D       un20_sum_cry_16_S     1.907        -0.361
    =======================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      2.129
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         1.907

        - Propagation time:                      2.283
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.376

        Number of logic level(s):                16
        Starting point:                          Xreg_15[2] / Q
        Ending point:                            sum_0[17] / D
        The start point is clocked by            Systolic_Symmetric_FIR|Clk [rising] on pin CLK
        The end   point is clocked by            Systolic_Symmetric_FIR|Clk [rising] on pin CLK

    Instance / Net               Pin      Pin               Arrival     No. of
    Name                Type     Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------
    Xreg_15[2]          SLE      Q        Out     0.094     0.094       -
    Xreg_15[2]          Net      -        -       0.780     -           8
    un12_sum_cry_2      ARI1     B        In      -         0.874       -
    un12_sum_cry_2      ARI1     FCO      Out     0.174     1.049       -
    un12_sum_cry_2      Net      -        -       0.000     -           1
    un12_sum_cry_3      ARI1     FCI      In      -         1.049       -
    un12_sum_cry_3      ARI1     FCO      Out     0.014     1.063       -
    un12_sum_cry_3      Net      -        -       0.000     -           1
    un12_sum_cry_4      ARI1     FCI      In      -         1.063       -
    un12_sum_cry_4      ARI1     FCO      Out     0.014     1.077       -
    un12_sum_cry_4      Net      -        -       0.000     -           1
    un12_sum_cry_5      ARI1     FCI      In      -         1.077       -
    un12_sum_cry_5      ARI1     FCO      Out     0.014     1.091       -
    un12_sum_cry_5      Net      -        -       0.000     -           1
    un12_sum_cry_6      ARI1     FCI      In      -         1.091       -
    un12_sum_cry_6      ARI1     FCO      Out     0.014     1.106       -
    un12_sum_cry_6      Net      -        -       0.000     -           1
    un12_sum_cry_7      ARI1     FCI      In      -         1.106       -
    un12_sum_cry_7      ARI1     FCO      Out     0.014     1.120       -
    un12_sum_cry_7      Net      -        -       0.000     -           1
    un12_sum_cry_8      ARI1     FCI      In      -         1.120       -
    un12_sum_cry_8      ARI1     FCO      Out     0.014     1.134       -
    un12_sum_cry_8      Net      -        -       0.000     -           1
    un12_sum_cry_9      ARI1     FCI      In      -         1.134       -
    un12_sum_cry_9      ARI1     FCO      Out     0.014     1.148       -
    un12_sum_cry_9      Net      -        -       0.000     -           1
    un12_sum_cry_10     ARI1     FCI      In      -         1.148       -
    un12_sum_cry_10     ARI1     FCO      Out     0.014     1.163       -
    un12_sum_cry_10     Net      -        -       0.000     -           1
    un12_sum_cry_11     ARI1     FCI      In      -         1.163       -
    un12_sum_cry_11     ARI1     FCO      Out     0.014     1.177       -
    un12_sum_cry_11     Net      -        -       0.000     -           1
    un12_sum_cry_12     ARI1     FCI      In      -         1.177       -
    un12_sum_cry_12     ARI1     FCO      Out     0.014     1.191       -
    un12_sum_cry_12     Net      -        -       0.000     -           1
    un12_sum_cry_13     ARI1     FCI      In      -         1.191       -
    un12_sum_cry_13     ARI1     FCO      Out     0.014     1.205       -
    un12_sum_cry_13     Net      -        -       0.000     -           1
    un12_sum_cry_14     ARI1     FCI      In      -         1.205       -
    un12_sum_cry_14     ARI1     FCO      Out     0.014     1.219       -
    un12_sum_cry_14     Net      -        -       0.000     -           1
    un12_sum_cry_15     ARI1     FCI      In      -         1.219       -
    un12_sum_cry_15     ARI1     FCO      Out     0.014     1.234       -
    un12_sum_cry_15     Net      -        -       0.000     -           1
    un12_sum_cry_16     ARI1     FCI      In      -         1.234       -
    un12_sum_cry_16     ARI1     FCO      Out     0.014     1.248       -
    un12_sum_cry_16     Net      -        -       0.000     -           1
    un12_sum_s_17       ARI1     FCI      In      -         1.248       -
    un12_sum_s_17       ARI1     S        Out     0.063     1.311       -
    un12_sum_s_17_S     Net      -        -       0.971     -           1
    sum_0[17]           SLE      D        In      -         2.283       -
    ==============================================================================
    Total path delay (propagation time + setup) of 2.505 is 0.753(30.1%) logic and 1.752(69.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      2.129
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         1.907

        - Propagation time:                      2.283
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.376

        Number of logic level(s):                16
        Starting point:                          Xreg_15[2] / Q
        Ending point:                            sum_5[17] / D
        The start point is clocked by            Systolic_Symmetric_FIR|Clk [rising] on pin CLK
        The end   point is clocked by            Systolic_Symmetric_FIR|Clk [rising] on pin CLK

    Instance / Net               Pin      Pin               Arrival     No. of
    Name                Type     Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------
    Xreg_15[2]          SLE      Q        Out     0.094     0.094       -
    Xreg_15[2]          Net      -        -       0.780     -           8
    un48_sum_cry_2      ARI1     B        In      -         0.874       -
    un48_sum_cry_2      ARI1     FCO      Out     0.174     1.049       -
    un48_sum_cry_2      Net      -        -       0.000     -           1
    un48_sum_cry_3      ARI1     FCI      In      -         1.049       -
    un48_sum_cry_3      ARI1     FCO      Out     0.014     1.063       -
    un48_sum_cry_3      Net      -        -       0.000     -           1
    un48_sum_cry_4      ARI1     FCI      In      -         1.063       -
    un48_sum_cry_4      ARI1     FCO      Out     0.014     1.077       -
    un48_sum_cry_4      Net      -        -       0.000     -           1
    un48_sum_cry_5      ARI1     FCI      In      -         1.077       -
    un48_sum_cry_5      ARI1     FCO      Out     0.014     1.091       -
    un48_sum_cry_5      Net      -        -       0.000     -           1
    un48_sum_cry_6      ARI1     FCI      In      -         1.091       -
    un48_sum_cry_6      ARI1     FCO      Out     0.014     1.106       -
    un48_sum_cry_6      Net      -        -       0.000     -           1
    un48_sum_cry_7      ARI1     FCI      In      -         1.106       -
    un48_sum_cry_7      ARI1     FCO      Out     0.014     1.120       -
    un48_sum_cry_7      Net      -        -       0.000     -           1
    un48_sum_cry_8      ARI1     FCI      In      -         1.120       -
    un48_sum_cry_8      ARI1     FCO      Out     0.014     1.134       -
    un48_sum_cry_8      Net      -        -       0.000     -           1
    un48_sum_cry_9      ARI1     FCI      In      -         1.134       -
    un48_sum_cry_9      ARI1     FCO      Out     0.014     1.148       -
    un48_sum_cry_9      Net      -        -       0.000     -           1
    un48_sum_cry_10     ARI1     FCI      In      -         1.148       -
    un48_sum_cry_10     ARI1     FCO      Out     0.014     1.163       -
    un48_sum_cry_10     Net      -        -       0.000     -           1
    un48_sum_cry_11     ARI1     FCI      In      -         1.163       -
    un48_sum_cry_11     ARI1     FCO      Out     0.014     1.177       -
    un48_sum_cry_11     Net      -        -       0.000     -           1
    un48_sum_cry_12     ARI1     FCI      In      -         1.177       -
    un48_sum_cry_12     ARI1     FCO      Out     0.014     1.191       -
    un48_sum_cry_12     Net      -        -       0.000     -           1
    un48_sum_cry_13     ARI1     FCI      In      -         1.191       -
    un48_sum_cry_13     ARI1     FCO      Out     0.014     1.205       -
    un48_sum_cry_13     Net      -        -       0.000     -           1
    un48_sum_cry_14     ARI1     FCI      In      -         1.205       -
    un48_sum_cry_14     ARI1     FCO      Out     0.014     1.219       -
    un48_sum_cry_14     Net      -        -       0.000     -           1
    un48_sum_cry_15     ARI1     FCI      In      -         1.219       -
    un48_sum_cry_15     ARI1     FCO      Out     0.014     1.234       -
    un48_sum_cry_15     Net      -        -       0.000     -           1
    un48_sum_cry_16     ARI1     FCI      In      -         1.234       -
    un48_sum_cry_16     ARI1     FCO      Out     0.014     1.248       -
    un48_sum_cry_16     Net      -        -       0.000     -           1
    un48_sum_s_17       ARI1     FCI      In      -         1.248       -
    un48_sum_s_17       ARI1     S        Out     0.063     1.311       -
    un48_sum_s_17_S     Net      -        -       0.971     -           1
    sum_5[17]           SLE      D        In      -         2.283       -
    ==============================================================================
    Total path delay (propagation time + setup) of 2.505 is 0.753(30.1%) logic and 1.752(69.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      2.129
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         1.907

        - Propagation time:                      2.283
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.376

        Number of logic level(s):                16
        Starting point:                          Xreg_15[2] / Q
        Ending point:                            sum_6[17] / D
        The start point is clocked by            Systolic_Symmetric_FIR|Clk [rising] on pin CLK
        The end   point is clocked by            Systolic_Symmetric_FIR|Clk [rising] on pin CLK

    Instance / Net               Pin      Pin               Arrival     No. of
    Name                Type     Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------
    Xreg_15[2]          SLE      Q        Out     0.094     0.094       -
    Xreg_15[2]          Net      -        -       0.780     -           8
    un55_sum_cry_2      ARI1     B        In      -         0.874       -
    un55_sum_cry_2      ARI1     FCO      Out     0.174     1.049       -
    un55_sum_cry_2      Net      -        -       0.000     -           1
    un55_sum_cry_3      ARI1     FCI      In      -         1.049       -
    un55_sum_cry_3      ARI1     FCO      Out     0.014     1.063       -
    un55_sum_cry_3      Net      -        -       0.000     -           1
    un55_sum_cry_4      ARI1     FCI      In      -         1.063       -
    un55_sum_cry_4      ARI1     FCO      Out     0.014     1.077       -
    un55_sum_cry_4      Net      -        -       0.000     -           1
    un55_sum_cry_5      ARI1     FCI      In      -         1.077       -
    un55_sum_cry_5      ARI1     FCO      Out     0.014     1.091       -
    un55_sum_cry_5      Net      -        -       0.000     -           1
    un55_sum_cry_6      ARI1     FCI      In      -         1.091       -
    un55_sum_cry_6      ARI1     FCO      Out     0.014     1.106       -
    un55_sum_cry_6      Net      -        -       0.000     -           1
    un55_sum_cry_7      ARI1     FCI      In      -         1.106       -
    un55_sum_cry_7      ARI1     FCO      Out     0.014     1.120       -
    un55_sum_cry_7      Net      -        -       0.000     -           1
    un55_sum_cry_8      ARI1     FCI      In      -         1.120       -
    un55_sum_cry_8      ARI1     FCO      Out     0.014     1.134       -
    un55_sum_cry_8      Net      -        -       0.000     -           1
    un55_sum_cry_9      ARI1     FCI      In      -         1.134       -
    un55_sum_cry_9      ARI1     FCO      Out     0.014     1.148       -
    un55_sum_cry_9      Net      -        -       0.000     -           1
    un55_sum_cry_10     ARI1     FCI      In      -         1.148       -
    un55_sum_cry_10     ARI1     FCO      Out     0.014     1.163       -
    un55_sum_cry_10     Net      -        -       0.000     -           1
    un55_sum_cry_11     ARI1     FCI      In      -         1.163       -
    un55_sum_cry_11     ARI1     FCO      Out     0.014     1.177       -
    un55_sum_cry_11     Net      -        -       0.000     -           1
    un55_sum_cry_12     ARI1     FCI      In      -         1.177       -
    un55_sum_cry_12     ARI1     FCO      Out     0.014     1.191       -
    un55_sum_cry_12     Net      -        -       0.000     -           1
    un55_sum_cry_13     ARI1     FCI      In      -         1.191       -
    un55_sum_cry_13     ARI1     FCO      Out     0.014     1.205       -
    un55_sum_cry_13     Net      -        -       0.000     -           1
    un55_sum_cry_14     ARI1     FCI      In      -         1.205       -
    un55_sum_cry_14     ARI1     FCO      Out     0.014     1.219       -
    un55_sum_cry_14     Net      -        -       0.000     -           1
    un55_sum_cry_15     ARI1     FCI      In      -         1.219       -
    un55_sum_cry_15     ARI1     FCO      Out     0.014     1.234       -
    un55_sum_cry_15     Net      -        -       0.000     -           1
    un55_sum_cry_16     ARI1     FCI      In      -         1.234       -
    un55_sum_cry_16     ARI1     FCO      Out     0.014     1.248       -
    un55_sum_cry_16     Net      -        -       0.000     -           1
    un55_sum_s_17       ARI1     FCI      In      -         1.248       -
    un55_sum_s_17       ARI1     S        Out     0.063     1.311       -
    un55_sum_s_17_S     Net      -        -       0.971     -           1
    sum_6[17]           SLE      D        In      -         2.283       -
    ==============================================================================
    Total path delay (propagation time + setup) of 2.505 is 0.753(30.1%) logic and 1.752(69.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      2.129
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         1.907

        - Propagation time:                      2.283
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.376

        Number of logic level(s):                16
        Starting point:                          Xreg_15[2] / Q
        Ending point:                            sum_7[17] / D
        The start point is clocked by            Systolic_Symmetric_FIR|Clk [rising] on pin CLK
        The end   point is clocked by            Systolic_Symmetric_FIR|Clk [rising] on pin CLK

    Instance / Net               Pin      Pin               Arrival     No. of
    Name                Type     Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------
    Xreg_15[2]          SLE      Q        Out     0.094     0.094       -
    Xreg_15[2]          Net      -        -       0.780     -           8
    un62_sum_cry_2      ARI1     B        In      -         0.874       -
    un62_sum_cry_2      ARI1     FCO      Out     0.174     1.049       -
    un62_sum_cry_2      Net      -        -       0.000     -           1
    un62_sum_cry_3      ARI1     FCI      In      -         1.049       -
    un62_sum_cry_3      ARI1     FCO      Out     0.014     1.063       -
    un62_sum_cry_3      Net      -        -       0.000     -           1
    un62_sum_cry_4      ARI1     FCI      In      -         1.063       -
    un62_sum_cry_4      ARI1     FCO      Out     0.014     1.077       -
    un62_sum_cry_4      Net      -        -       0.000     -           1
    un62_sum_cry_5      ARI1     FCI      In      -         1.077       -
    un62_sum_cry_5      ARI1     FCO      Out     0.014     1.091       -
    un62_sum_cry_5      Net      -        -       0.000     -           1
    un62_sum_cry_6      ARI1     FCI      In      -         1.091       -
    un62_sum_cry_6      ARI1     FCO      Out     0.014     1.106       -
    un62_sum_cry_6      Net      -        -       0.000     -           1
    un62_sum_cry_7      ARI1     FCI      In      -         1.106       -
    un62_sum_cry_7      ARI1     FCO      Out     0.014     1.120       -
    un62_sum_cry_7      Net      -        -       0.000     -           1
    un62_sum_cry_8      ARI1     FCI      In      -         1.120       -
    un62_sum_cry_8      ARI1     FCO      Out     0.014     1.134       -
    un62_sum_cry_8      Net      -        -       0.000     -           1
    un62_sum_cry_9      ARI1     FCI      In      -         1.134       -
    un62_sum_cry_9      ARI1     FCO      Out     0.014     1.148       -
    un62_sum_cry_9      Net      -        -       0.000     -           1
    un62_sum_cry_10     ARI1     FCI      In      -         1.148       -
    un62_sum_cry_10     ARI1     FCO      Out     0.014     1.163       -
    un62_sum_cry_10     Net      -        -       0.000     -           1
    un62_sum_cry_11     ARI1     FCI      In      -         1.163       -
    un62_sum_cry_11     ARI1     FCO      Out     0.014     1.177       -
    un62_sum_cry_11     Net      -        -       0.000     -           1
    un62_sum_cry_12     ARI1     FCI      In      -         1.177       -
    un62_sum_cry_12     ARI1     FCO      Out     0.014     1.191       -
    un62_sum_cry_12     Net      -        -       0.000     -           1
    un62_sum_cry_13     ARI1     FCI      In      -         1.191       -
    un62_sum_cry_13     ARI1     FCO      Out     0.014     1.205       -
    un62_sum_cry_13     Net      -        -       0.000     -           1
    un62_sum_cry_14     ARI1     FCI      In      -         1.205       -
    un62_sum_cry_14     ARI1     FCO      Out     0.014     1.219       -
    un62_sum_cry_14     Net      -        -       0.000     -           1
    un62_sum_cry_15     ARI1     FCI      In      -         1.219       -
    un62_sum_cry_15     ARI1     FCO      Out     0.014     1.234       -
    un62_sum_cry_15     Net      -        -       0.000     -           1
    un62_sum_cry_16     ARI1     FCI      In      -         1.234       -
    un62_sum_cry_16     ARI1     FCO      Out     0.014     1.248       -
    un62_sum_cry_16     Net      -        -       0.000     -           1
    un62_sum_s_17       ARI1     FCI      In      -         1.248       -
    un62_sum_s_17       ARI1     S        Out     0.063     1.311       -
    un62_sum_s_17_S     Net      -        -       0.971     -           1
    sum_7[17]           SLE      D        In      -         2.283       -
    ==============================================================================
    Total path delay (propagation time + setup) of 2.505 is 0.753(30.1%) logic and 1.752(69.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      2.129
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         1.907

        - Propagation time:                      2.283
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.376

        Number of logic level(s):                16
        Starting point:                          Xreg_15[2] / Q
        Ending point:                            sum_1[17] / D
        The start point is clocked by            Systolic_Symmetric_FIR|Clk [rising] on pin CLK
        The end   point is clocked by            Systolic_Symmetric_FIR|Clk [rising] on pin CLK

    Instance / Net               Pin      Pin               Arrival     No. of
    Name                Type     Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------
    Xreg_15[2]          SLE      Q        Out     0.094     0.094       -
    Xreg_15[2]          Net      -        -       0.780     -           8
    un20_sum_cry_2      ARI1     B        In      -         0.874       -
    un20_sum_cry_2      ARI1     FCO      Out     0.174     1.049       -
    un20_sum_cry_2      Net      -        -       0.000     -           1
    un20_sum_cry_3      ARI1     FCI      In      -         1.049       -
    un20_sum_cry_3      ARI1     FCO      Out     0.014     1.063       -
    un20_sum_cry_3      Net      -        -       0.000     -           1
    un20_sum_cry_4      ARI1     FCI      In      -         1.063       -
    un20_sum_cry_4      ARI1     FCO      Out     0.014     1.077       -
    un20_sum_cry_4      Net      -        -       0.000     -           1
    un20_sum_cry_5      ARI1     FCI      In      -         1.077       -
    un20_sum_cry_5      ARI1     FCO      Out     0.014     1.091       -
    un20_sum_cry_5      Net      -        -       0.000     -           1
    un20_sum_cry_6      ARI1     FCI      In      -         1.091       -
    un20_sum_cry_6      ARI1     FCO      Out     0.014     1.106       -
    un20_sum_cry_6      Net      -        -       0.000     -           1
    un20_sum_cry_7      ARI1     FCI      In      -         1.106       -
    un20_sum_cry_7      ARI1     FCO      Out     0.014     1.120       -
    un20_sum_cry_7      Net      -        -       0.000     -           1
    un20_sum_cry_8      ARI1     FCI      In      -         1.120       -
    un20_sum_cry_8      ARI1     FCO      Out     0.014     1.134       -
    un20_sum_cry_8      Net      -        -       0.000     -           1
    un20_sum_cry_9      ARI1     FCI      In      -         1.134       -
    un20_sum_cry_9      ARI1     FCO      Out     0.014     1.148       -
    un20_sum_cry_9      Net      -        -       0.000     -           1
    un20_sum_cry_10     ARI1     FCI      In      -         1.148       -
    un20_sum_cry_10     ARI1     FCO      Out     0.014     1.163       -
    un20_sum_cry_10     Net      -        -       0.000     -           1
    un20_sum_cry_11     ARI1     FCI      In      -         1.163       -
    un20_sum_cry_11     ARI1     FCO      Out     0.014     1.177       -
    un20_sum_cry_11     Net      -        -       0.000     -           1
    un20_sum_cry_12     ARI1     FCI      In      -         1.177       -
    un20_sum_cry_12     ARI1     FCO      Out     0.014     1.191       -
    un20_sum_cry_12     Net      -        -       0.000     -           1
    un20_sum_cry_13     ARI1     FCI      In      -         1.191       -
    un20_sum_cry_13     ARI1     FCO      Out     0.014     1.205       -
    un20_sum_cry_13     Net      -        -       0.000     -           1
    un20_sum_cry_14     ARI1     FCI      In      -         1.205       -
    un20_sum_cry_14     ARI1     FCO      Out     0.014     1.219       -
    un20_sum_cry_14     Net      -        -       0.000     -           1
    un20_sum_cry_15     ARI1     FCI      In      -         1.219       -
    un20_sum_cry_15     ARI1     FCO      Out     0.014     1.234       -
    un20_sum_cry_15     Net      -        -       0.000     -           1
    un20_sum_cry_16     ARI1     FCI      In      -         1.234       -
    un20_sum_cry_16     ARI1     FCO      Out     0.014     1.248       -
    un20_sum_cry_16     Net      -        -       0.000     -           1
    un20_sum_s_17       ARI1     FCI      In      -         1.248       -
    un20_sum_s_17       ARI1     S        Out     0.063     1.311       -
    un20_sum_s_17_S     Net      -        -       0.971     -           1
    sum_1[17]           SLE      D        In      -         2.283       -
    ==============================================================================
    Total path delay (propagation time + setup) of 2.505 is 0.753(30.1%) logic and 1.752(69.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                       Starting                                           Arrival
    Instance                           Reference     Type     Pin          Net            Time        Slack
                                       Clock
    --------------------------------------------------------------------------------------------------------
    U3\.4\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDOUT[0]     CDOUT_4[0]     0.000       -0.146
    U3\.6\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDOUT[0]     CDOUT_6[0]     0.000       -0.146
    U3\.6\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDOUT[0]     CDOUT_6[0]     0.000       -0.146
    U3\.2\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDOUT[0]     CDOUT_2[0]     0.000       -0.146
    U3\.1\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDOUT[0]     CDOUT_1[0]     0.000       -0.146
    U3\.5\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDOUT[0]     CDOUT_5[0]     0.000       -0.146
    U3\.5\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDOUT[0]     CDOUT_5[0]     0.000       -0.146
    U3\.3\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDOUT[0]     CDOUT_3[0]     0.000       -0.146
    U3\.2\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDOUT[0]     CDOUT_2[0]     0.000       -0.146
    MUL1.multadd_0_0.U0                System        MACC     CDOUT[0]     CDOUT_0[0]     0.000       -0.146
    ========================================================================================================

    Ending Points with Worst Slack
    ******************************

                                       Starting                                          Required
    Instance                           Reference     Type     Pin         Net            Time         Slack
                                       Clock
    --------------------------------------------------------------------------------------------------------
    U3\.4\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDIN[0]     CDOUT_3[0]     0.826        -0.146
    U3\.3\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDIN[0]     CDOUT_2[0]     0.826        -0.146
    U3\.3\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDIN[0]     CDOUT_2[0]     0.826        -0.146
    U3\.2\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDIN[0]     CDOUT_1[0]     0.826        -0.146
    U3\.1\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDIN[0]     CDOUT_0[0]     0.826        -0.146
    U3\.6\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDIN[0]     CDOUT_5[0]     0.826        -0.146
    U3\.6\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDIN[0]     CDOUT_5[0]     0.826        -0.146
    U3\.7\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDIN[0]     CDOUT_6[0]     0.826        -0.146
    U3\.2\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDIN[0]     CDOUT_1[0]     0.826        -0.146
    U3\.5\.L1\.MUL3.multadd_0_0.U0     System        MACC     CDIN[0]     CDOUT_4[0]     0.826        -0.146
    ========================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.146

        Number of logic level(s):                0
        Starting point:                          U3\.4\.L1\.MUL3.multadd_0_0.U0 / CDOUT[0]
        Ending point:                            U3\.5\.L1\.MUL3.multadd_0_0.U0 / CDIN[0]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                              Pin          Pin               Arrival     No. of
    Name                               Type     Name         Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------
    U3\.4\.L1\.MUL3.multadd_0_0.U0     MACC     CDOUT[0]     Out     0.000     0.000       -
    CDOUT_4[0]                         Net      -            -       0.971     -           1
    U3\.5\.L1\.MUL3.multadd_0_0.U0     MACC     CDIN[0]      In      -         0.971       -
    =================================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.146

        Number of logic level(s):                0
        Starting point:                          U3\.6\.L1\.MUL3.multadd_0_0.U0 / CDOUT[0]
        Ending point:                            U3\.7\.L1\.MUL3.multadd_0_0.U0 / CDIN[0]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                              Pin          Pin               Arrival     No. of
    Name                               Type     Name         Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------
    U3\.6\.L1\.MUL3.multadd_0_0.U0     MACC     CDOUT[0]     Out     0.000     0.000       -
    CDOUT_6[0]                         Net      -            -       0.971     -           1
    U3\.7\.L1\.MUL3.multadd_0_0.U0     MACC     CDIN[0]      In      -         0.971       -
    =================================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.146

        Number of logic level(s):                0
        Starting point:                          U3\.6\.L1\.MUL3.multadd_0_0.U0 / CDOUT[0]
        Ending point:                            U3\.7\.L1\.MUL3.multadd_0_0.U0 / CDIN[0]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                              Pin          Pin               Arrival     No. of
    Name                               Type     Name         Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------
    U3\.6\.L1\.MUL3.multadd_0_0.U0     MACC     CDOUT[0]     Out     0.000     0.000       -
    CDOUT_6[0]                         Net      -            -       0.971     -           1
    U3\.7\.L1\.MUL3.multadd_0_0.U0     MACC     CDIN[0]      In      -         0.971       -
    =================================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.146

        Number of logic level(s):                0
        Starting point:                          U3\.2\.L1\.MUL3.multadd_0_0.U0 / CDOUT[0]
        Ending point:                            U3\.3\.L1\.MUL3.multadd_0_0.U0 / CDIN[0]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                              Pin          Pin               Arrival     No. of
    Name                               Type     Name         Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------
    U3\.2\.L1\.MUL3.multadd_0_0.U0     MACC     CDOUT[0]     Out     0.000     0.000       -
    CDOUT_2[0]                         Net      -            -       0.971     -           1
    U3\.3\.L1\.MUL3.multadd_0_0.U0     MACC     CDIN[0]      In      -         0.971       -
    =================================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      0.826
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.826

        - Propagation time:                      0.971
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.146

        Number of logic level(s):                0
        Starting point:                          U3\.1\.L1\.MUL3.multadd_0_0.U0 / CDOUT[0]
        Ending point:                            U3\.2\.L1\.MUL3.multadd_0_0.U0 / CDIN[0]
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                              Pin          Pin               Arrival     No. of
    Name                               Type     Name         Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------
    U3\.1\.L1\.MUL3.multadd_0_0.U0     MACC     CDOUT[0]     Out     0.000     0.000       -
    CDOUT_1[0]                         Net      -            -       0.971     -           1
    U3\.2\.L1\.MUL3.multadd_0_0.U0     MACC     CDIN[0]      In      -         0.971       -
    =================================================================================================
    Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    ---------------------------------------
    Resource Usage Report for Systolic_Symmetric_FIR

    Mapping to part: m2s050fbga896-1
    Cell usage:
    CLKINT          2 uses

    Carry primitives used for arithmetic functions:
    ARI1           144 uses

    Sequential Cells:
    SLE            434 uses

    DSP Blocks:    8
     MACC:         8 Mults

    I/O ports: 64
    I/O primitives: 64
    INBUF          20 uses
    OUTBUF         44 uses

    Global Clock Buffers: 2

    Total LUTs:    144

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 49MB peak: 135MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed May 21 20:34:17 2014

    ###########################################################]

`