Project Settings Project Name Top_level_syn Implementation Name synthesis Top Module Top_level Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time Compile Input out-of-date 68 3215 0 - 0m:03s - 6/19/2014 2:24:11 PM Pre-mapping out-of-date 62 5 0 0m:01s 0m:02s 162MB 6/19/2014 2:24:15 PM Map & Optimize out-of-date 199 6607 0 0m:05s 0m:06s 162MB 6/19/2014 2:24:22 PM Area Summary Carry Cells 58 Sequential Cells 1124 DSP Blocks (MACC) (dsp_used) 0 I/O Cells 5 Global Clock Buffers 8 Block Rams (RAM1K18) (v_ram) 8 LUTs (total_luts) 738 Timing Summary Clock Name Req Freq Est Freq Slack PCIe_Demo_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 121.4 MHz 1.763 PCIe_Demo_CCC_0_FCCC|GL3_net_inferred_clock 100.0 MHz 282.5 MHz 6.461 PCIe_Demo_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock 100.0 MHz 362.9 MHz 7.244 PCIe_Demo_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 114.1 MHz 0.617 System 100.0 MHz 574.6 MHz 8.260 Optimizations Summary Combined Clock Conversion 3 / 1