@W: BN132 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance SERDESIF_INIT_BLK_0.PCIe_Demo_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance SERDESIF_INIT_BLK_0.PCIe_Demo_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@W: MT530 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\work\fabric_ram\fabric_ram_0\fabric_ram_fabric_ram_0_tpsram.v":30:12:30:46|Found inferred clock PCIe_Demo_CCC_0_FCCC|GL0_net_inferred_clock which controls 1276 sequential elements including AXI_SLAVE_IF_FAB_RAM_0.U000.fabric_ram_0.fabric_ram_fabric_ram_0_TPSRAM_R0C0. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":447:4:447:9|Found inferred clock PCIe_Demo_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 110 sequential elements including SERDESIF_INIT_BLK_0.PCIe_Demo_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Found inferred clock PCIe_Demo_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock which controls 30 sequential elements including SERDESIF_INIT_BLK_0.PCIe_Demo_0.CORERESETP_0.count_sdif1[12:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v":179:4:179:9|Found inferred clock PCIe_Demo_CCC_0_FCCC|GL3_net_inferred_clock which controls 37 sequential elements including SERDESIF_INIT_BLK_0.PCIe_Demo_0.CORERESETP_0.genblk3\.sdif1_phr.state[3:0]. This clock has no specified timing constraint which may adversely impact design performance. 
