@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: FA239 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":1744:6:1744:9|ROM SLAVE_SELECT_WADDRCH_M_cnst[15:0] mapped in logic.
@N: FA239 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":1744:6:1744:9|ROM SLAVE_SELECT_WADDRCH_M_cnst[15:0] mapped in logic.
@N: MO106 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":1744:6:1744:9|Found ROM, 'SLAVE_SELECT_WADDRCH_M_cnst[15:0]', 16 words by 16 bits 
@N: FA239 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":1785:6:1785:9|ROM SLAVE_SELECT_RADDRCH_M_cnst[15:0] mapped in logic.
@N: FA239 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":1785:6:1785:9|ROM SLAVE_SELECT_RADDRCH_M_cnst[15:0] mapped in logic.
@N: MO106 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":1785:6:1785:9|Found ROM, 'SLAVE_SELECT_RADDRCH_M_cnst[15:0]', 16 words by 16 bits 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":1942:3:1942:8|Removing sequential instance SLAVE_SELECT_WADDRCH_M_r[15:0] of view:PrimLib.dffr(prim) in hierarchy view:work.axi_wrmatrix_4Mto1S_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":470:3:470:8|Removing sequential instance rd_wdcntr[3:0] of view:PrimLib.dffr(prim) in hierarchy view:work.axi_rdmatrix_4Mto1S_Z14(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":492:3:492:8|Removing sequential instance rd_rdcntr[3:0] of view:PrimLib.dffr(prim) in hierarchy view:work.axi_rdmatrix_4Mto1S_Z14(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":1984:3:1984:8|Removing sequential instance SLAVE_SELECT_RADDRCH_M_r[15:0] of view:PrimLib.dffr(prim) in hierarchy view:work.axi_rdmatrix_4Mto1S_Z14(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWID_S[4] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWID_S[5] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[12] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[13] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[14] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[15] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[16] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[17] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[18] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[19] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[20] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[21] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[22] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[23] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[24] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[25] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[26] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[27] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[28] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[29] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[30] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWADDR_S[31] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARID_S[4] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARID_S[5] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[12] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[13] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[14] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[15] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[16] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[17] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[18] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[19] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[20] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[21] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[22] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[23] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[24] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[25] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[26] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[27] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[28] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[29] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[30] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARADDR_S[31] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWSIZE_M_INPFF1[2] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARSIZE_M_INPFF1[2] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: FX404 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\hdl\axi_slave_if_fab_ram.v":121:3:121:6|Found addmux in view:work.AXI_SLAVE_IF_FAB_RAM_Z1(verilog) inst mem_waddr_9[11:0] from un1_mem_waddr[11:0] 
@N: FX404 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\hdl\axi_slave_if_fab_ram.v":255:3:255:6|Found addmux in view:work.AXI_SLAVE_IF_FAB_RAM_Z1(verilog) inst mem_raddr_10[11:0] from un1_mem_raddr[11:0] 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_16sto1m.v":586:3:586:8|Removing sequential instance RID_IM[4] of view:PrimLib.dffr(prim) in hierarchy view:work.axi_rdmatrix_16Sto1M_Z3(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_16sto1m.v":586:3:586:8|Removing sequential instance RID_IM[5] of view:PrimLib.dffr(prim) in hierarchy view:work.axi_rdmatrix_16Sto1M_Z3(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_ra_arbiter.v":568:3:568:8|Removing sequential instance m0_lock_clear_read of view:PrimLib.dffre(prim) in hierarchy view:work.axi_RA_ARBITER_Z13(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance paddr[16] in hierarchy view:work.CoreConfigP_Z18(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWID_IS[4] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWID_IS[5] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[12] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[13] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[14] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[15] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[16] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[17] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[18] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[19] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[20] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[21] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[22] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[23] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[24] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[25] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[26] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[27] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARID_IS[4] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARID_IS[5] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[12] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[13] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[14] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[15] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[16] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[17] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[18] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[19] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[20] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[21] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[22] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[23] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[24] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[25] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[26] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[27] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARADDR_IS[28] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWID_IS_int[4] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWID_IS_int[5] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[12] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[13] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[14] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[15] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[16] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[17] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[18] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[19] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[20] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[21] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[22] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[23] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[24] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[25] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[26] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":553:9:553:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.genblk1\.AWADDR_IS_int[27] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARID_IS_int[4] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARID_IS_int[5] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[12] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[13] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[14] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[15] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[16] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[17] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[18] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[19] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[20] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[21] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[22] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[23] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[24] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[25] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[26] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARADDR_IS_int[27] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[12] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[13] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[14] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[15] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[16] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[17] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[18] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[19] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[20] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[21] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[22] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[23] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[24] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[25] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[26] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWADDR_M_INPFF1[27] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARID_M_INPFF1[4] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARID_M_INPFF1[5] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[12] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[13] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[14] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[15] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[16] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[17] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[18] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[19] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[20] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[21] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[22] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[23] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[24] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[25] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[26] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.ARADDR_M_INPFF1[27] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWID_M_INPFF1[4] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Removing sequential instance COREAXI_0.genblk3\.master_stage0.genblk4\.AWID_M_INPFF1[5] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_wrmatrix_4mto1s.v":506:3:506:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_wa_channel.genblk1\.inst_wrmatrix_4Mto1S.AWADDR_IS[28] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":589:9:589:14|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.genblk1\.ARSIZE_IS_int[2] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWID_S[2] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARID_S[2] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\hdl\axi_slave_if_fab_ram.v":239:0:239:5|Removing sequential instance AXI_SLAVE_IF_FAB_RAM_0.RID[2] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\hdl\axi_slave_if_fab_ram.v":104:0:104:5|Removing sequential instance AXI_SLAVE_IF_FAB_RAM_0.AWID_INT[2] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_4mto1s.v":524:3:524:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.genblk4\.inst_matrix_S0.inst_ra_channel.genblk1\.inst_rdmatrix_4Mto1S.ARSIZE_IS[2] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\hdl\axi_slave_if_fab_ram.v":104:0:104:5|Removing sequential instance AXI_SLAVE_IF_FAB_RAM_0.BID[2] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_16sto1m.v":586:3:586:8|Removing sequential instance COREAXI_0.genblk2\.u_interconnect_ntom.inst_matrix_m0.inst_rd_channel.inst_rdmatrix_16Sto1M.RID_IM[2] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.AWSIZE_S[2] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: BN362 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_slave_stage.v":497:9:497:14|Removing sequential instance COREAXI_0.genblk7\.slave_stage0.genblk1\.ARSIZE_S[2] in hierarchy view:work.Top_level(verilog) because there are no references to its outputs 
@N: FX271 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\hdl\axi_slave_if_fab_ram.v":239:0:239:5|Instance "AXI_SLAVE_IF_FAB_RAM_0.axi_fsm_read_state[0]" with 14 loads replicated 1 times to improve timing 
@N: FX271 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_master_stage.v":2127:9:2127:14|Instance "COREAXI_0.genblk3\.master_stage0.genblk8\.RVALID_M" with 148 loads replicated 2 times to improve timing 
@N: FX271 :"d:\appsnotes\2014\axi__update\design_file\libero\pcie_with_axi_slave\component\actel\directcore\coreaxi\3.0.112\rtl\vlog\core\axi_rdmatrix_16sto1m.v":604:3:604:8|Instance "COREAXI_0.genblk2\.u_interconnect_ntom.inst_matrix_m0.inst_rd_channel.inst_rdmatrix_16Sto1M.curr_state[1]" with 76 loads replicated 1 times to improve timing 
@N: FP130 |Promoting Net SERDESIF_INIT_BLK_0.PCIe_Demo_0_INIT_APB_S_PRESET_N on CLKINT  I_101 
@N: FP130 |Promoting Net SERDESIF_INIT_BLK_0.PCIe_Demo_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT  I_102 
@N: FP130 |Promoting Net SERDESIF_INIT_BLK_0.PCIe_Demo_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_103 
@N: FP130 |Promoting Net SERDESIF_INIT_BLK_0_USER_FAB_RESET_N on CLKINT  I_104 
@N: FP130 |Promoting Net SERDESIF_INIT_BLK_0.PCIe_Demo_0_INIT_APB_S_PCLK on CLKINT  I_105 
@N: FP130 |Promoting Net SERDESIF_INIT_BLK_0.PCIe_Demo_0.CORERESETP_0.genblk3\.sdif1_phr.reset_n_clk_ltssm on CLKINT  I_106 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
