@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":84:12:84:20|No assignment to AWLEN_INT
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":86:12:86:22|No assignment to AWBURST_INT
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":92:12:92:22|No assignment to ARVALID_INT
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":93:12:93:21|No assignment to RREADY_INT
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":239:0:239:5|Pruning register w_tr_length[3:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":239:0:239:5|Pruning register ARBURST_INT[1:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":104:0:104:5|Pruning register w_tr_length[3:0] 
@W: CL265 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":239:0:239:5|Pruning bit 2 of ARSIZE_INT[2:0] -- not in use ...
@W: CL265 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":104:0:104:5|Pruning bit 2 of AWSIZE_INT[2:0] -- not in use ...
@W: CL113 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":239:0:239:5|Feedback mux created for signal RRESP[1:0].
@W: CL250 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":239:0:239:5|All reachable assignments to RRESP[1:0] assign 0, register removed by optimization
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":104:0:104:5|Optimizing register bit BRESP[0] to a constant 0
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":104:0:104:5|Optimizing register bit BRESP[1] to a constant 0
@W: CL189 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":239:0:239:5|Register bit mem_read is always 1, optimizing ...
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":104:0:104:5|Pruning register BRESP[1:0] 
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_16Sto1M.v":552:38:552:48|No assignment to curr_slv_rd
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_16Sto1M.v":562:3:562:8|Pruning register RID_IM_r[5:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_16Sto1M.v":562:3:562:8|Pruning register RDATA_IM_r[63:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_16Sto1M.v":562:3:562:8|Pruning register RLAST_IM_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_16Sto1M.v":562:3:562:8|Pruning register RRESP_IM_r[1:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_16Sto1M.v":562:3:562:8|Pruning register prev_slv_rd[4:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_16Sto1M.v":562:3:562:8|Pruning register rd_inprog_r 
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wresp_channel.v":459:3:459:8|Optimizing register bit BID_IM[2] to a constant 0
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wresp_channel.v":459:3:459:8|Optimizing register bit BID_IM[3] to a constant 0
@W: CL279 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wresp_channel.v":459:3:459:8|Pruning register bits 3 to 2 of BID_IM[5:0] 
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_m.v":724:41:724:50|No assignment to RID_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_m.v":725:41:725:52|No assignment to RDATA_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_m.v":726:41:726:52|No assignment to RLAST_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_m.v":727:41:727:53|No assignment to RVALID_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_m.v":728:41:728:52|No assignment to RRESP_IM_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_m.v":730:41:730:49|No assignment to wire RREADY_IS
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_m.v":731:41:731:48|No assignment to wire RRESP_IC
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_m.v":732:41:732:48|No assignment to wire RDATA_IC
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_arbiter.v":169:35:169:43|No assignment to wrid_flag
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_arbiter.v":542:3:542:8|Pruning register m3_req_inprog 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_arbiter.v":529:3:529:8|Pruning register m2_req_inprog 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_arbiter.v":516:3:516:8|Pruning register m1_req_inprog 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_arbiter.v":503:3:503:8|Pruning register m0_req_inprog 
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":402:38:402:48|No assignment to AWREADY_IM1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":403:38:403:48|No assignment to AWREADY_IM2
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":404:38:404:48|No assignment to AWREADY_IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":394:38:394:51|No assignment to wire AWREADY_SI_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":395:38:395:46|No assignment to wr_rdcntr
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":396:38:396:46|No assignment to wr_wdcntr
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":398:38:398:48|No assignment to wire wr_wen_flag
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":399:38:399:48|No assignment to wire wr_ren_flag
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":406:38:406:46|No assignment to wire AW_REQ_MI
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":413:38:413:48|No assignment to mst0_wr_end
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":414:38:414:55|No assignment to mst0_outstd_wrcntr
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":415:38:415:51|No assignment to mst0_wr_end_d1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":417:38:417:48|No assignment to mst1_wr_end
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":418:38:418:55|No assignment to mst1_outstd_wrcntr
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":419:38:419:51|No assignment to mst1_wr_end_d1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":421:38:421:48|No assignment to mst2_wr_end
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":422:38:422:55|No assignment to mst2_outstd_wrcntr
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":423:38:423:51|No assignment to mst2_wr_end_d1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":425:38:425:48|No assignment to mst3_wr_end
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":426:38:426:55|No assignment to mst3_outstd_wrcntr
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":427:38:427:51|No assignment to mst3_wr_end_d1
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":1942:3:1942:8|Optimizing register bit SLAVE_SELECT_WADDRCH_M_r[16] to a constant 0
@W: CL260 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":1942:3:1942:8|Pruning register bit 16 of SLAVE_SELECT_WADDRCH_M_r[16:0] 
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_channel.v":377:39:377:45|No assignment to wire AWID_IC
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_channel.v":378:29:378:37|No assignment to wire AWADDR_IC
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_channel.v":379:39:379:46|No assignment to wire AWLEN_IC
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_channel.v":380:39:380:47|No assignment to wire AWSIZE_IC
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_channel.v":381:39:381:48|No assignment to wire AWBURST_IC
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_channel.v":382:39:382:47|No assignment to wire AWLOCK_IC
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_channel.v":383:39:383:48|No assignment to wire AWCACHE_IC
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_channel.v":384:39:384:47|No assignment to wire AWPROT_IC
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_channel.v":385:39:385:48|No assignment to wire AWVALID_IC
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":295:41:295:54|No assignment to WREADY_IM1_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":296:41:296:54|No assignment to WREADY_IM2_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":297:41:297:54|No assignment to WREADY_IM3_int
@W: CL207 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":320:3:320:8|All reachable assignments to genblk1.WREADY_IM3 assign 0, register removed by optimization.
@W: CL207 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":320:3:320:8|All reachable assignments to genblk1.WREADY_IM2 assign 0, register removed by optimization.
@W: CL207 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":320:3:320:8|All reachable assignments to genblk1.WREADY_IM1 assign 0, register removed by optimization.
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":402:38:402:63|No assignment to SLAVE_SELECT_RADDRCH_M_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":409:38:409:46|No assignment to wr_rdcntr
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":410:38:410:46|No assignment to wr_wdcntr
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":413:38:413:48|No assignment to wire wr_wen_flag
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":414:38:414:48|No assignment to wire wr_ren_flag
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":422:38:422:52|No assignment to ARREADY_IM1_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":423:38:423:52|No assignment to ARREADY_IM2_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":424:38:424:52|No assignment to ARREADY_IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":426:38:426:46|No assignment to wire AR_REQ_MI
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":433:38:433:48|No assignment to mst0_rd_end
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":434:38:434:55|No assignment to mst0_outstd_rdcntr
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":435:38:435:51|No assignment to mst0_rd_end_d1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":437:38:437:48|No assignment to mst1_rd_end
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":438:38:438:55|No assignment to mst1_outstd_rdcntr
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":439:38:439:51|No assignment to mst1_rd_end_d1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":441:38:441:48|No assignment to mst2_rd_end
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":442:38:442:55|No assignment to mst2_outstd_rdcntr
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":443:38:443:51|No assignment to mst2_rd_end_d1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":445:38:445:48|No assignment to mst3_rd_end
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":446:38:446:55|No assignment to mst3_outstd_rdcntr
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":447:38:447:51|No assignment to mst3_rd_end_d1
@W: CL207 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":524:3:524:8|All reachable assignments to ARREADY_IM3 assign 0, register removed by optimization.
@W: CL207 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":524:3:524:8|All reachable assignments to ARREADY_IM2 assign 0, register removed by optimization.
@W: CL207 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":524:3:524:8|All reachable assignments to ARREADY_IM1 assign 0, register removed by optimization.
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":1984:3:1984:8|Optimizing register bit SLAVE_SELECT_RADDRCH_M_r[16] to a constant 0
@W: CL260 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":1984:3:1984:8|Pruning register bit 16 of SLAVE_SELECT_RADDRCH_M_r[16:0] 
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":587:34:587:55|No assignment to wire SLAVE_SELECT_WADDRCH_M
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":593:34:593:55|No assignment to wire SLAVE_SELECT_RADDRCH_M
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":594:34:594:52|No assignment to wire SLAVE_SELECT_WDCH_M
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":595:34:595:55|No assignment to wire SLAVE_SELECT_WRESPCH_M
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":596:34:596:52|No assignment to wire SLAVE_SELECT_RDCH_M
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":597:34:597:43|No assignment to AWREADY_IM
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":598:34:598:43|No assignment to ARREADY_IM
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":599:34:599:42|No assignment to WREADY_IM
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":600:34:600:46|No assignment to WREADY_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":601:38:601:47|No assignment to BID_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":602:38:602:50|No assignment to BVALID_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":603:38:603:49|No assignment to BRESP_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":605:38:605:45|No assignment to BRESP_IM
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":606:38:606:46|No assignment to BVALID_IM
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":607:38:607:43|No assignment to BID_IM
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":609:39:609:47|No assignment to wire BREADY_IS
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":619:29:619:42|No assignment to wire ARADDR_IS_int1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":640:39:640:50|No assignment to wire AR_MASGNT_IC
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2096:34:2096:43|No assignment to AWREADY_IM
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2097:34:2097:43|No assignment to ARREADY_IM
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2098:34:2098:42|No assignment to WREADY_IM
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2099:34:2099:46|No assignment to WREADY_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2100:38:2100:47|No assignment to BID_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2101:38:2101:50|No assignment to BVALID_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2102:38:2102:49|No assignment to BRESP_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2103:38:2103:47|No assignment to RID_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2104:38:2104:49|No assignment to RDATA_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2105:38:2105:49|No assignment to RLAST_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2106:38:2106:50|No assignment to RVALID_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2107:38:2107:49|No assignment to RRESP_IM_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2110:38:2110:45|No assignment to BRESP_IM
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2111:38:2111:46|No assignment to BVALID_IM
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2112:38:2112:43|No assignment to BID_IM
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2168:39:2168:50|No assignment to wire RREADY_M1IS0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2169:39:2169:50|No assignment to wire RREADY_M1IS1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2170:39:2170:50|No assignment to wire RREADY_M1IS2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2171:39:2171:50|No assignment to wire RREADY_M1IS3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2172:39:2172:50|No assignment to wire RREADY_M1IS4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2173:39:2173:50|No assignment to wire RREADY_M1IS5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2174:39:2174:50|No assignment to wire RREADY_M1IS6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2175:39:2175:50|No assignment to wire RREADY_M1IS7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2176:39:2176:50|No assignment to wire RREADY_M1IS8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2177:39:2177:50|No assignment to wire RREADY_M1IS9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2178:39:2178:51|No assignment to wire RREADY_M1IS10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2179:39:2179:51|No assignment to wire RREADY_M1IS11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2180:39:2180:51|No assignment to wire RREADY_M1IS12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2181:39:2181:51|No assignment to wire RREADY_M1IS13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2182:39:2182:51|No assignment to wire RREADY_M1IS14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2183:39:2183:51|No assignment to wire RREADY_M1IS15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2184:39:2184:51|No assignment to wire RREADY_M1IS16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2186:39:2186:50|No assignment to wire RREADY_M2IS0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2187:39:2187:50|No assignment to wire RREADY_M2IS1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2188:39:2188:50|No assignment to wire RREADY_M2IS2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2189:39:2189:50|No assignment to wire RREADY_M2IS3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2190:39:2190:50|No assignment to wire RREADY_M2IS4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2191:39:2191:50|No assignment to wire RREADY_M2IS5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2192:39:2192:50|No assignment to wire RREADY_M2IS6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2193:39:2193:50|No assignment to wire RREADY_M2IS7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2194:39:2194:50|No assignment to wire RREADY_M2IS8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2195:39:2195:50|No assignment to wire RREADY_M2IS9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2196:39:2196:51|No assignment to wire RREADY_M2IS10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2197:39:2197:51|No assignment to wire RREADY_M2IS11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2198:39:2198:51|No assignment to wire RREADY_M2IS12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2199:39:2199:51|No assignment to wire RREADY_M2IS13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2200:39:2200:51|No assignment to wire RREADY_M2IS14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2201:39:2201:51|No assignment to wire RREADY_M2IS15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2202:39:2202:51|No assignment to wire RREADY_M2IS16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2204:39:2204:50|No assignment to wire RREADY_M3IS0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2205:39:2205:50|No assignment to wire RREADY_M3IS1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2206:39:2206:50|No assignment to wire RREADY_M3IS2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2207:39:2207:50|No assignment to wire RREADY_M3IS3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2208:39:2208:50|No assignment to wire RREADY_M3IS4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2209:39:2209:50|No assignment to wire RREADY_M3IS5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2210:39:2210:50|No assignment to wire RREADY_M3IS6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2211:39:2211:50|No assignment to wire RREADY_M3IS7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2212:39:2212:50|No assignment to wire RREADY_M3IS8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2213:39:2213:50|No assignment to wire RREADY_M3IS9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2214:39:2214:51|No assignment to wire RREADY_M3IS10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2215:39:2215:51|No assignment to wire RREADY_M3IS11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2216:39:2216:51|No assignment to wire RREADY_M3IS12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2217:39:2217:51|No assignment to wire RREADY_M3IS13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2218:39:2218:51|No assignment to wire RREADY_M3IS14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2219:39:2219:51|No assignment to wire RREADY_M3IS15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2220:39:2220:51|No assignment to wire RREADY_M3IS16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2241:39:2241:50|No assignment to wire BREADY_M1IS0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2242:39:2242:50|No assignment to wire BREADY_M1IS1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2243:39:2243:50|No assignment to wire BREADY_M1IS2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2244:39:2244:50|No assignment to wire BREADY_M1IS3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2245:39:2245:50|No assignment to wire BREADY_M1IS4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2246:39:2246:50|No assignment to wire BREADY_M1IS5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2247:39:2247:50|No assignment to wire BREADY_M1IS6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2248:39:2248:50|No assignment to wire BREADY_M1IS7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2249:39:2249:50|No assignment to wire BREADY_M1IS8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2250:39:2250:50|No assignment to wire BREADY_M1IS9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2251:39:2251:51|No assignment to wire BREADY_M1IS10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2252:39:2252:51|No assignment to wire BREADY_M1IS11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2253:39:2253:51|No assignment to wire BREADY_M1IS12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2254:39:2254:51|No assignment to wire BREADY_M1IS13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2255:39:2255:51|No assignment to wire BREADY_M1IS14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2256:39:2256:51|No assignment to wire BREADY_M1IS15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2257:39:2257:51|No assignment to wire BREADY_M1IS16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2259:39:2259:50|No assignment to wire BREADY_M2IS0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2260:39:2260:50|No assignment to wire BREADY_M2IS1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2261:39:2261:50|No assignment to wire BREADY_M2IS2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2262:39:2262:50|No assignment to wire BREADY_M2IS3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2263:39:2263:50|No assignment to wire BREADY_M2IS4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2264:39:2264:50|No assignment to wire BREADY_M2IS5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2265:39:2265:50|No assignment to wire BREADY_M2IS6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2266:39:2266:50|No assignment to wire BREADY_M2IS7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2267:39:2267:50|No assignment to wire BREADY_M2IS8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2268:39:2268:50|No assignment to wire BREADY_M2IS9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2269:39:2269:51|No assignment to wire BREADY_M2IS10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2270:39:2270:51|No assignment to wire BREADY_M2IS11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2271:39:2271:51|No assignment to wire BREADY_M2IS12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2272:39:2272:51|No assignment to wire BREADY_M2IS13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2273:39:2273:51|No assignment to wire BREADY_M2IS14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2274:39:2274:51|No assignment to wire BREADY_M2IS15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2275:39:2275:51|No assignment to wire BREADY_M2IS16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2277:39:2277:50|No assignment to wire BREADY_M3IS0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2278:39:2278:50|No assignment to wire BREADY_M3IS1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2279:39:2279:50|No assignment to wire BREADY_M3IS2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2280:39:2280:50|No assignment to wire BREADY_M3IS3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2281:39:2281:50|No assignment to wire BREADY_M3IS4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2282:39:2282:50|No assignment to wire BREADY_M3IS5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2283:39:2283:50|No assignment to wire BREADY_M3IS6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2284:39:2284:50|No assignment to wire BREADY_M3IS7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2285:39:2285:50|No assignment to wire BREADY_M3IS8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2286:39:2286:50|No assignment to wire BREADY_M3IS9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2287:39:2287:51|No assignment to wire BREADY_M3IS10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2288:39:2288:51|No assignment to wire BREADY_M3IS11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2289:39:2289:51|No assignment to wire BREADY_M3IS12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2290:39:2290:51|No assignment to wire BREADY_M3IS13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2291:39:2291:51|No assignment to wire BREADY_M3IS14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2292:39:2292:51|No assignment to wire BREADY_M3IS15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2293:39:2293:51|No assignment to wire BREADY_M3IS16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2476:39:2476:52|No assignment to wire AWID_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2477:29:2477:44|No assignment to wire AWADDR_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2478:39:2478:53|No assignment to wire AWLEN_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2479:39:2479:54|No assignment to wire AWSIZE_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2480:39:2480:55|No assignment to wire AWBURST_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2481:39:2481:54|No assignment to wire AWLOCK_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2482:39:2482:55|No assignment to wire AWCACHE_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2483:39:2483:54|No assignment to wire AWPROT_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2484:39:2484:55|No assignment to wire AWVALID_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2486:39:2486:52|No assignment to wire AWID_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2487:29:2487:44|No assignment to wire AWADDR_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2488:39:2488:53|No assignment to wire AWLEN_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2489:39:2489:54|No assignment to wire AWSIZE_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2490:39:2490:55|No assignment to wire AWBURST_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2491:39:2491:54|No assignment to wire AWLOCK_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2492:39:2492:55|No assignment to wire AWCACHE_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2493:39:2493:54|No assignment to wire AWPROT_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2494:39:2494:55|No assignment to wire AWVALID_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2496:39:2496:52|No assignment to wire AWID_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2497:29:2497:44|No assignment to wire AWADDR_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2498:39:2498:53|No assignment to wire AWLEN_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2499:39:2499:54|No assignment to wire AWSIZE_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2500:39:2500:55|No assignment to wire AWBURST_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2501:39:2501:54|No assignment to wire AWLOCK_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2502:39:2502:55|No assignment to wire AWCACHE_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2503:39:2503:54|No assignment to wire AWPROT_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2504:39:2504:55|No assignment to wire AWVALID_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2506:39:2506:52|No assignment to wire AWID_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2507:29:2507:44|No assignment to wire AWADDR_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2508:39:2508:53|No assignment to wire AWLEN_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2509:39:2509:54|No assignment to wire AWSIZE_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2510:39:2510:55|No assignment to wire AWBURST_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2511:39:2511:54|No assignment to wire AWLOCK_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2512:39:2512:55|No assignment to wire AWCACHE_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2513:39:2513:54|No assignment to wire AWPROT_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2514:39:2514:55|No assignment to wire AWVALID_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2516:39:2516:52|No assignment to wire AWID_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2517:29:2517:44|No assignment to wire AWADDR_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2518:39:2518:53|No assignment to wire AWLEN_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2519:39:2519:54|No assignment to wire AWSIZE_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2520:39:2520:55|No assignment to wire AWBURST_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2521:39:2521:54|No assignment to wire AWLOCK_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2522:39:2522:55|No assignment to wire AWCACHE_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2523:39:2523:54|No assignment to wire AWPROT_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2524:39:2524:55|No assignment to wire AWVALID_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2526:39:2526:52|No assignment to wire AWID_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2527:29:2527:44|No assignment to wire AWADDR_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2528:39:2528:53|No assignment to wire AWLEN_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2529:39:2529:54|No assignment to wire AWSIZE_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2530:39:2530:55|No assignment to wire AWBURST_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2531:39:2531:54|No assignment to wire AWLOCK_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2532:39:2532:55|No assignment to wire AWCACHE_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2533:39:2533:54|No assignment to wire AWPROT_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2534:39:2534:55|No assignment to wire AWVALID_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2536:39:2536:52|No assignment to wire AWID_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2537:29:2537:44|No assignment to wire AWADDR_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2538:39:2538:53|No assignment to wire AWLEN_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2539:39:2539:54|No assignment to wire AWSIZE_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2540:39:2540:55|No assignment to wire AWBURST_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2541:39:2541:54|No assignment to wire AWLOCK_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2542:39:2542:55|No assignment to wire AWCACHE_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2543:39:2543:54|No assignment to wire AWPROT_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2544:39:2544:55|No assignment to wire AWVALID_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2546:39:2546:52|No assignment to wire AWID_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2547:29:2547:44|No assignment to wire AWADDR_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2548:39:2548:53|No assignment to wire AWLEN_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2549:39:2549:54|No assignment to wire AWSIZE_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2550:39:2550:55|No assignment to wire AWBURST_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2551:39:2551:54|No assignment to wire AWLOCK_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2552:39:2552:55|No assignment to wire AWCACHE_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2553:39:2553:54|No assignment to wire AWPROT_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2554:39:2554:55|No assignment to wire AWVALID_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2556:39:2556:52|No assignment to wire AWID_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2557:29:2557:44|No assignment to wire AWADDR_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2558:39:2558:53|No assignment to wire AWLEN_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2559:39:2559:54|No assignment to wire AWSIZE_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2560:39:2560:55|No assignment to wire AWBURST_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2561:39:2561:54|No assignment to wire AWLOCK_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2562:39:2562:55|No assignment to wire AWCACHE_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2563:39:2563:54|No assignment to wire AWPROT_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2564:39:2564:55|No assignment to wire AWVALID_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2566:39:2566:53|No assignment to wire AWID_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2567:29:2567:45|No assignment to wire AWADDR_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2568:39:2568:54|No assignment to wire AWLEN_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2569:39:2569:55|No assignment to wire AWSIZE_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2570:39:2570:56|No assignment to wire AWBURST_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2571:39:2571:55|No assignment to wire AWLOCK_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2572:39:2572:56|No assignment to wire AWCACHE_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2573:39:2573:55|No assignment to wire AWPROT_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2574:39:2574:56|No assignment to wire AWVALID_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2576:39:2576:53|No assignment to wire AWID_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2577:29:2577:45|No assignment to wire AWADDR_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2578:39:2578:54|No assignment to wire AWLEN_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2579:39:2579:55|No assignment to wire AWSIZE_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2580:39:2580:56|No assignment to wire AWBURST_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2581:39:2581:55|No assignment to wire AWLOCK_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2582:39:2582:56|No assignment to wire AWCACHE_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2583:39:2583:55|No assignment to wire AWPROT_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2584:39:2584:56|No assignment to wire AWVALID_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2586:39:2586:53|No assignment to wire AWID_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2587:29:2587:45|No assignment to wire AWADDR_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2588:39:2588:54|No assignment to wire AWLEN_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2589:39:2589:55|No assignment to wire AWSIZE_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2590:39:2590:56|No assignment to wire AWBURST_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2591:39:2591:55|No assignment to wire AWLOCK_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2592:39:2592:56|No assignment to wire AWCACHE_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2593:39:2593:55|No assignment to wire AWPROT_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2594:39:2594:56|No assignment to wire AWVALID_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2596:39:2596:53|No assignment to wire AWID_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2597:29:2597:45|No assignment to wire AWADDR_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2598:39:2598:54|No assignment to wire AWLEN_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2599:39:2599:55|No assignment to wire AWSIZE_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2600:39:2600:56|No assignment to wire AWBURST_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2601:39:2601:55|No assignment to wire AWLOCK_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2602:39:2602:56|No assignment to wire AWCACHE_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2603:39:2603:55|No assignment to wire AWPROT_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2604:39:2604:56|No assignment to wire AWVALID_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2606:39:2606:53|No assignment to wire AWID_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2607:29:2607:45|No assignment to wire AWADDR_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2608:39:2608:54|No assignment to wire AWLEN_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2609:39:2609:55|No assignment to wire AWSIZE_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2610:39:2610:56|No assignment to wire AWBURST_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2611:39:2611:55|No assignment to wire AWLOCK_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2612:39:2612:56|No assignment to wire AWCACHE_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2613:39:2613:55|No assignment to wire AWPROT_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2614:39:2614:56|No assignment to wire AWVALID_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2616:39:2616:53|No assignment to wire AWID_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2617:29:2617:45|No assignment to wire AWADDR_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2618:39:2618:54|No assignment to wire AWLEN_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2619:39:2619:55|No assignment to wire AWSIZE_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2620:39:2620:56|No assignment to wire AWBURST_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2621:39:2621:55|No assignment to wire AWLOCK_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2622:39:2622:56|No assignment to wire AWCACHE_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2623:39:2623:55|No assignment to wire AWPROT_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2624:39:2624:56|No assignment to wire AWVALID_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2626:39:2626:53|No assignment to wire AWID_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2627:29:2627:45|No assignment to wire AWADDR_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2628:39:2628:54|No assignment to wire AWLEN_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2629:39:2629:55|No assignment to wire AWSIZE_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2630:39:2630:56|No assignment to wire AWBURST_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2631:39:2631:55|No assignment to wire AWLOCK_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2632:39:2632:56|No assignment to wire AWCACHE_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2633:39:2633:55|No assignment to wire AWPROT_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2634:39:2634:56|No assignment to wire AWVALID_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2744:39:2744:51|No assignment to wire WID_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2745:39:2745:54|No assignment to wire WVALID_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2746:39:2746:53|No assignment to wire WDATA_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2747:39:2747:53|No assignment to wire WSTRB_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2748:39:2748:53|No assignment to wire WLAST_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2750:39:2750:51|No assignment to wire WID_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2751:39:2751:54|No assignment to wire WVALID_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2752:39:2752:53|No assignment to wire WDATA_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2753:39:2753:53|No assignment to wire WSTRB_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2754:39:2754:53|No assignment to wire WLAST_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2756:39:2756:51|No assignment to wire WID_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2757:39:2757:54|No assignment to wire WVALID_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2758:39:2758:53|No assignment to wire WDATA_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2759:39:2759:53|No assignment to wire WSTRB_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2760:39:2760:53|No assignment to wire WLAST_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2762:39:2762:51|No assignment to wire WID_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2763:39:2763:54|No assignment to wire WVALID_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2764:39:2764:53|No assignment to wire WDATA_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2765:39:2765:53|No assignment to wire WSTRB_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2766:39:2766:53|No assignment to wire WLAST_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2768:39:2768:51|No assignment to wire WID_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2769:39:2769:54|No assignment to wire WVALID_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2770:39:2770:53|No assignment to wire WDATA_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2771:39:2771:53|No assignment to wire WSTRB_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2772:39:2772:53|No assignment to wire WLAST_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2774:39:2774:51|No assignment to wire WID_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2775:39:2775:54|No assignment to wire WVALID_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2776:39:2776:53|No assignment to wire WDATA_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2777:39:2777:53|No assignment to wire WSTRB_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2778:39:2778:53|No assignment to wire WLAST_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2780:39:2780:51|No assignment to wire WID_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2781:39:2781:54|No assignment to wire WVALID_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2782:39:2782:53|No assignment to wire WDATA_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2783:39:2783:53|No assignment to wire WSTRB_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2784:39:2784:53|No assignment to wire WLAST_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2786:39:2786:51|No assignment to wire WID_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2787:39:2787:54|No assignment to wire WVALID_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2788:39:2788:53|No assignment to wire WDATA_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2789:39:2789:53|No assignment to wire WSTRB_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2790:39:2790:53|No assignment to wire WLAST_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2792:39:2792:51|No assignment to wire WID_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2793:39:2793:54|No assignment to wire WVALID_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2794:39:2794:53|No assignment to wire WDATA_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2795:39:2795:53|No assignment to wire WSTRB_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2796:39:2796:53|No assignment to wire WLAST_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2798:39:2798:52|No assignment to wire WID_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2799:39:2799:55|No assignment to wire WVALID_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2800:39:2800:54|No assignment to wire WDATA_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2801:39:2801:54|No assignment to wire WSTRB_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2802:39:2802:54|No assignment to wire WLAST_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2804:39:2804:52|No assignment to wire WID_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2805:39:2805:55|No assignment to wire WVALID_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2806:39:2806:54|No assignment to wire WDATA_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2807:39:2807:54|No assignment to wire WSTRB_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2808:39:2808:54|No assignment to wire WLAST_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2810:39:2810:52|No assignment to wire WID_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2811:39:2811:55|No assignment to wire WVALID_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2812:39:2812:54|No assignment to wire WDATA_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2813:39:2813:54|No assignment to wire WSTRB_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2814:39:2814:54|No assignment to wire WLAST_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2816:39:2816:52|No assignment to wire WID_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2817:39:2817:55|No assignment to wire WVALID_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2818:39:2818:54|No assignment to wire WDATA_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2819:39:2819:54|No assignment to wire WSTRB_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2820:39:2820:54|No assignment to wire WLAST_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2822:39:2822:52|No assignment to wire WID_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2823:39:2823:55|No assignment to wire WVALID_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2824:39:2824:54|No assignment to wire WDATA_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2825:39:2825:54|No assignment to wire WSTRB_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2826:39:2826:54|No assignment to wire WLAST_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2828:39:2828:52|No assignment to wire WID_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2829:39:2829:55|No assignment to wire WVALID_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2830:39:2830:54|No assignment to wire WDATA_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2831:39:2831:54|No assignment to wire WSTRB_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2832:39:2832:54|No assignment to wire WLAST_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2834:39:2834:52|No assignment to wire WID_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2835:39:2835:55|No assignment to wire WVALID_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2836:39:2836:54|No assignment to wire WDATA_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2837:39:2837:54|No assignment to wire WSTRB_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2838:39:2838:54|No assignment to wire WLAST_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3021:39:3021:52|No assignment to wire ARID_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3022:29:3022:44|No assignment to wire ARADDR_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3023:39:3023:53|No assignment to wire ARLEN_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3024:39:3024:54|No assignment to wire ARSIZE_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3025:39:3025:55|No assignment to wire ARBURST_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3026:39:3026:54|No assignment to wire ARLOCK_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3027:39:3027:55|No assignment to wire ARCACHE_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3028:39:3028:54|No assignment to wire ARPROT_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3029:39:3029:55|No assignment to wire ARVALID_IS1_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3031:39:3031:52|No assignment to wire ARID_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3032:29:3032:44|No assignment to wire ARADDR_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3033:39:3033:53|No assignment to wire ARLEN_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3034:39:3034:54|No assignment to wire ARSIZE_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3035:39:3035:55|No assignment to wire ARBURST_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3036:39:3036:54|No assignment to wire ARLOCK_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3037:39:3037:55|No assignment to wire ARCACHE_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3038:39:3038:54|No assignment to wire ARPROT_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3039:39:3039:55|No assignment to wire ARVALID_IS2_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3041:39:3041:52|No assignment to wire ARID_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3042:29:3042:44|No assignment to wire ARADDR_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3043:39:3043:53|No assignment to wire ARLEN_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3044:39:3044:54|No assignment to wire ARSIZE_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3045:39:3045:55|No assignment to wire ARBURST_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3046:39:3046:54|No assignment to wire ARLOCK_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3047:39:3047:55|No assignment to wire ARCACHE_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3048:39:3048:54|No assignment to wire ARPROT_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3049:39:3049:55|No assignment to wire ARVALID_IS3_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3051:39:3051:52|No assignment to wire ARID_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3052:29:3052:44|No assignment to wire ARADDR_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3053:39:3053:53|No assignment to wire ARLEN_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3054:39:3054:54|No assignment to wire ARSIZE_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3055:39:3055:55|No assignment to wire ARBURST_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3056:39:3056:54|No assignment to wire ARLOCK_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3057:39:3057:55|No assignment to wire ARCACHE_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3058:39:3058:54|No assignment to wire ARPROT_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3059:39:3059:55|No assignment to wire ARVALID_IS4_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3061:39:3061:52|No assignment to wire ARID_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3062:29:3062:44|No assignment to wire ARADDR_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3063:39:3063:53|No assignment to wire ARLEN_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3064:39:3064:54|No assignment to wire ARSIZE_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3065:39:3065:55|No assignment to wire ARBURST_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3066:39:3066:54|No assignment to wire ARLOCK_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3067:39:3067:55|No assignment to wire ARCACHE_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3068:39:3068:54|No assignment to wire ARPROT_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3069:39:3069:55|No assignment to wire ARVALID_IS5_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3071:39:3071:52|No assignment to wire ARID_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3072:29:3072:44|No assignment to wire ARADDR_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3073:39:3073:53|No assignment to wire ARLEN_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3074:39:3074:54|No assignment to wire ARSIZE_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3075:39:3075:55|No assignment to wire ARBURST_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3076:39:3076:54|No assignment to wire ARLOCK_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3077:39:3077:55|No assignment to wire ARCACHE_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3078:39:3078:54|No assignment to wire ARPROT_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3079:39:3079:55|No assignment to wire ARVALID_IS6_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3081:39:3081:52|No assignment to wire ARID_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3082:29:3082:44|No assignment to wire ARADDR_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3083:39:3083:53|No assignment to wire ARLEN_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3084:39:3084:54|No assignment to wire ARSIZE_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3085:39:3085:55|No assignment to wire ARBURST_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3086:39:3086:54|No assignment to wire ARLOCK_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3087:39:3087:55|No assignment to wire ARCACHE_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3088:39:3088:54|No assignment to wire ARPROT_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3089:39:3089:55|No assignment to wire ARVALID_IS7_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3091:39:3091:52|No assignment to wire ARID_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3092:29:3092:44|No assignment to wire ARADDR_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3093:39:3093:53|No assignment to wire ARLEN_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3094:39:3094:54|No assignment to wire ARSIZE_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3095:39:3095:55|No assignment to wire ARBURST_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3096:39:3096:54|No assignment to wire ARLOCK_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3097:39:3097:55|No assignment to wire ARCACHE_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3098:39:3098:54|No assignment to wire ARPROT_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3099:39:3099:55|No assignment to wire ARVALID_IS8_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3101:39:3101:52|No assignment to wire ARID_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3102:29:3102:44|No assignment to wire ARADDR_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3103:39:3103:53|No assignment to wire ARLEN_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3104:39:3104:54|No assignment to wire ARSIZE_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3105:39:3105:55|No assignment to wire ARBURST_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3106:39:3106:54|No assignment to wire ARLOCK_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3107:39:3107:55|No assignment to wire ARCACHE_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3108:39:3108:54|No assignment to wire ARPROT_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3109:39:3109:55|No assignment to wire ARVALID_IS9_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3111:39:3111:53|No assignment to wire ARID_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3112:29:3112:45|No assignment to wire ARADDR_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3113:39:3113:54|No assignment to wire ARLEN_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3114:39:3114:55|No assignment to wire ARSIZE_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3115:39:3115:56|No assignment to wire ARBURST_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3116:39:3116:55|No assignment to wire ARLOCK_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3117:39:3117:56|No assignment to wire ARCACHE_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3118:39:3118:55|No assignment to wire ARPROT_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3119:39:3119:56|No assignment to wire ARVALID_IS10_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3121:39:3121:53|No assignment to wire ARID_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3122:29:3122:45|No assignment to wire ARADDR_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3123:39:3123:54|No assignment to wire ARLEN_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3124:39:3124:55|No assignment to wire ARSIZE_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3125:39:3125:56|No assignment to wire ARBURST_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3126:39:3126:55|No assignment to wire ARLOCK_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3127:39:3127:56|No assignment to wire ARCACHE_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3128:39:3128:55|No assignment to wire ARPROT_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3129:39:3129:56|No assignment to wire ARVALID_IS11_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3131:39:3131:53|No assignment to wire ARID_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3132:29:3132:45|No assignment to wire ARADDR_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3133:39:3133:54|No assignment to wire ARLEN_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3134:39:3134:55|No assignment to wire ARSIZE_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3135:39:3135:56|No assignment to wire ARBURST_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3136:39:3136:55|No assignment to wire ARLOCK_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3137:39:3137:56|No assignment to wire ARCACHE_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3138:39:3138:55|No assignment to wire ARPROT_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3139:39:3139:56|No assignment to wire ARVALID_IS12_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3141:39:3141:53|No assignment to wire ARID_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3142:29:3142:45|No assignment to wire ARADDR_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3143:39:3143:54|No assignment to wire ARLEN_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3144:39:3144:55|No assignment to wire ARSIZE_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3145:39:3145:56|No assignment to wire ARBURST_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3146:39:3146:55|No assignment to wire ARLOCK_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3147:39:3147:56|No assignment to wire ARCACHE_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3148:39:3148:55|No assignment to wire ARPROT_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3149:39:3149:56|No assignment to wire ARVALID_IS13_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3151:39:3151:53|No assignment to wire ARID_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3152:29:3152:45|No assignment to wire ARADDR_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3153:39:3153:54|No assignment to wire ARLEN_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3154:39:3154:55|No assignment to wire ARSIZE_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3155:39:3155:56|No assignment to wire ARBURST_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3156:39:3156:55|No assignment to wire ARLOCK_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3157:39:3157:56|No assignment to wire ARCACHE_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3158:39:3158:55|No assignment to wire ARPROT_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3159:39:3159:56|No assignment to wire ARVALID_IS14_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3161:39:3161:53|No assignment to wire ARID_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3162:29:3162:45|No assignment to wire ARADDR_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3163:39:3163:54|No assignment to wire ARLEN_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3164:39:3164:55|No assignment to wire ARSIZE_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3165:39:3165:56|No assignment to wire ARBURST_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3166:39:3166:55|No assignment to wire ARLOCK_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3167:39:3167:56|No assignment to wire ARCACHE_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3168:39:3168:55|No assignment to wire ARPROT_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3169:39:3169:56|No assignment to wire ARVALID_IS15_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3171:39:3171:53|No assignment to wire ARID_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3172:29:3172:45|No assignment to wire ARADDR_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3173:39:3173:54|No assignment to wire ARLEN_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3174:39:3174:55|No assignment to wire ARSIZE_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3175:39:3175:56|No assignment to wire ARBURST_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3176:39:3176:55|No assignment to wire ARLOCK_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3177:39:3177:56|No assignment to wire ARCACHE_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3178:39:3178:55|No assignment to wire ARPROT_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3179:39:3179:56|No assignment to wire ARVALID_IS16_gated
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3213:39:3213:50|No assignment to wire AW_MASGNT_IC
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3214:39:3214:50|No assignment to wire AR_MASGNT_IC
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3216:39:3216:47|No assignment to wire wr_rdcntr
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3217:39:3217:47|No assignment to wire wr_wdcntr
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3219:39:3219:47|No assignment to wire wd_rdcntr
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3220:39:3220:47|No assignment to wire wd_wdcntr
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3222:39:3222:51|No assignment to wire MST_RDGNT_NUM
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3223:39:3223:47|No assignment to wire rd_rdcntr
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3224:39:3224:47|No assignment to wire rd_wdcntr
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3235:39:3235:46|No assignment to wire RRESP_IC
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3236:39:3236:46|No assignment to wire RDATA_IC
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3242:39:3242:51|No assignment to wire AWREADY_S1IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3243:39:3243:51|No assignment to wire AWREADY_S1IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3244:39:3244:51|No assignment to wire AWREADY_S1IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3245:39:3245:51|No assignment to wire AWREADY_S1IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3246:39:3246:51|No assignment to wire AWREADY_S2IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3247:39:3247:51|No assignment to wire AWREADY_S2IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3248:39:3248:51|No assignment to wire AWREADY_S2IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3249:39:3249:51|No assignment to wire AWREADY_S2IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3250:39:3250:51|No assignment to wire AWREADY_S3IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3251:39:3251:51|No assignment to wire AWREADY_S3IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3252:39:3252:51|No assignment to wire AWREADY_S3IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3253:39:3253:51|No assignment to wire AWREADY_S3IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3254:39:3254:51|No assignment to wire AWREADY_S4IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3255:39:3255:51|No assignment to wire AWREADY_S4IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3256:39:3256:51|No assignment to wire AWREADY_S4IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3257:39:3257:51|No assignment to wire AWREADY_S4IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3258:39:3258:51|No assignment to wire AWREADY_S5IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3259:39:3259:51|No assignment to wire AWREADY_S5IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3260:39:3260:51|No assignment to wire AWREADY_S5IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3261:39:3261:51|No assignment to wire AWREADY_S5IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3262:39:3262:51|No assignment to wire AWREADY_S6IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3263:39:3263:51|No assignment to wire AWREADY_S6IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3264:39:3264:51|No assignment to wire AWREADY_S6IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3265:39:3265:51|No assignment to wire AWREADY_S6IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3266:39:3266:51|No assignment to wire AWREADY_S7IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3267:39:3267:51|No assignment to wire AWREADY_S7IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3268:39:3268:51|No assignment to wire AWREADY_S7IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3269:39:3269:51|No assignment to wire AWREADY_S7IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3270:39:3270:51|No assignment to wire AWREADY_S8IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3271:39:3271:51|No assignment to wire AWREADY_S8IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3272:39:3272:51|No assignment to wire AWREADY_S8IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3273:39:3273:51|No assignment to wire AWREADY_S8IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3274:39:3274:51|No assignment to wire AWREADY_S9IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3275:39:3275:51|No assignment to wire AWREADY_S9IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3276:39:3276:51|No assignment to wire AWREADY_S9IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3277:39:3277:51|No assignment to wire AWREADY_S9IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3278:39:3278:52|No assignment to wire AWREADY_S10IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3279:39:3279:52|No assignment to wire AWREADY_S10IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3280:39:3280:52|No assignment to wire AWREADY_S10IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3281:39:3281:52|No assignment to wire AWREADY_S10IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3282:39:3282:52|No assignment to wire AWREADY_S11IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3283:39:3283:52|No assignment to wire AWREADY_S11IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3284:39:3284:52|No assignment to wire AWREADY_S11IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3285:39:3285:52|No assignment to wire AWREADY_S11IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3286:39:3286:52|No assignment to wire AWREADY_S12IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3287:39:3287:52|No assignment to wire AWREADY_S12IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3288:39:3288:52|No assignment to wire AWREADY_S12IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3289:39:3289:52|No assignment to wire AWREADY_S12IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3290:39:3290:52|No assignment to wire AWREADY_S13IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3291:39:3291:52|No assignment to wire AWREADY_S13IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3292:39:3292:52|No assignment to wire AWREADY_S13IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3293:39:3293:52|No assignment to wire AWREADY_S13IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3294:39:3294:52|No assignment to wire AWREADY_S14IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3295:39:3295:52|No assignment to wire AWREADY_S14IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3296:39:3296:52|No assignment to wire AWREADY_S14IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3297:39:3297:52|No assignment to wire AWREADY_S14IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3298:39:3298:52|No assignment to wire AWREADY_S15IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3299:39:3299:52|No assignment to wire AWREADY_S15IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3300:39:3300:52|No assignment to wire AWREADY_S15IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3301:39:3301:52|No assignment to wire AWREADY_S15IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3302:39:3302:52|No assignment to wire AWREADY_S16IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3303:39:3303:52|No assignment to wire AWREADY_S16IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3304:39:3304:52|No assignment to wire AWREADY_S16IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3305:39:3305:52|No assignment to wire AWREADY_S16IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3311:39:3311:51|No assignment to wire ARREADY_S1IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3312:39:3312:51|No assignment to wire ARREADY_S1IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3313:39:3313:51|No assignment to wire ARREADY_S1IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3314:39:3314:51|No assignment to wire ARREADY_S1IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3315:39:3315:51|No assignment to wire ARREADY_S2IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3316:39:3316:51|No assignment to wire ARREADY_S2IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3317:39:3317:51|No assignment to wire ARREADY_S2IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3318:39:3318:51|No assignment to wire ARREADY_S2IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3319:39:3319:51|No assignment to wire ARREADY_S3IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3320:39:3320:51|No assignment to wire ARREADY_S3IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3321:39:3321:51|No assignment to wire ARREADY_S3IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3322:39:3322:51|No assignment to wire ARREADY_S3IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3323:39:3323:51|No assignment to wire ARREADY_S4IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3324:39:3324:51|No assignment to wire ARREADY_S4IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3325:39:3325:51|No assignment to wire ARREADY_S4IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3326:39:3326:51|No assignment to wire ARREADY_S4IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3327:39:3327:51|No assignment to wire ARREADY_S5IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3328:39:3328:51|No assignment to wire ARREADY_S5IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3329:39:3329:51|No assignment to wire ARREADY_S5IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3330:39:3330:51|No assignment to wire ARREADY_S5IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3331:39:3331:51|No assignment to wire ARREADY_S6IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3332:39:3332:51|No assignment to wire ARREADY_S6IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3333:39:3333:51|No assignment to wire ARREADY_S6IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3334:39:3334:51|No assignment to wire ARREADY_S6IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3335:39:3335:51|No assignment to wire ARREADY_S7IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3336:39:3336:51|No assignment to wire ARREADY_S7IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3337:39:3337:51|No assignment to wire ARREADY_S7IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3338:39:3338:51|No assignment to wire ARREADY_S7IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3339:39:3339:51|No assignment to wire ARREADY_S8IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3340:39:3340:51|No assignment to wire ARREADY_S8IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3341:39:3341:51|No assignment to wire ARREADY_S8IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3342:39:3342:51|No assignment to wire ARREADY_S8IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3343:39:3343:51|No assignment to wire ARREADY_S9IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3344:39:3344:51|No assignment to wire ARREADY_S9IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3345:39:3345:51|No assignment to wire ARREADY_S9IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3346:39:3346:51|No assignment to wire ARREADY_S9IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3347:39:3347:52|No assignment to wire ARREADY_S10IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3348:39:3348:52|No assignment to wire ARREADY_S10IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3349:39:3349:52|No assignment to wire ARREADY_S10IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3350:39:3350:52|No assignment to wire ARREADY_S10IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3351:39:3351:52|No assignment to wire ARREADY_S11IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3352:39:3352:52|No assignment to wire ARREADY_S11IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3353:39:3353:52|No assignment to wire ARREADY_S11IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3354:39:3354:52|No assignment to wire ARREADY_S11IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3355:39:3355:52|No assignment to wire ARREADY_S12IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3356:39:3356:52|No assignment to wire ARREADY_S12IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3357:39:3357:52|No assignment to wire ARREADY_S12IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3358:39:3358:52|No assignment to wire ARREADY_S12IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3359:39:3359:52|No assignment to wire ARREADY_S13IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3360:39:3360:52|No assignment to wire ARREADY_S13IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3361:39:3361:52|No assignment to wire ARREADY_S13IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3362:39:3362:52|No assignment to wire ARREADY_S13IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3363:39:3363:52|No assignment to wire ARREADY_S14IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3364:39:3364:52|No assignment to wire ARREADY_S14IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3365:39:3365:52|No assignment to wire ARREADY_S14IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3366:39:3366:52|No assignment to wire ARREADY_S14IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3367:39:3367:52|No assignment to wire ARREADY_S15IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3368:39:3368:52|No assignment to wire ARREADY_S15IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3369:39:3369:52|No assignment to wire ARREADY_S15IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3370:39:3370:52|No assignment to wire ARREADY_S15IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3371:39:3371:52|No assignment to wire ARREADY_S16IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3372:39:3372:52|No assignment to wire ARREADY_S16IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3373:39:3373:52|No assignment to wire ARREADY_S16IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3374:39:3374:52|No assignment to wire ARREADY_S16IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3376:39:3376:55|No assignment to wire ARREADY_S0IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3377:39:3377:55|No assignment to wire ARREADY_S0IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3378:39:3378:55|No assignment to wire ARREADY_S0IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3379:39:3379:55|No assignment to wire ARREADY_S0IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3380:39:3380:55|No assignment to wire ARREADY_S1IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3381:39:3381:55|No assignment to wire ARREADY_S1IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3382:39:3382:55|No assignment to wire ARREADY_S1IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3383:39:3383:55|No assignment to wire ARREADY_S1IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3384:39:3384:55|No assignment to wire ARREADY_S2IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3385:39:3385:55|No assignment to wire ARREADY_S2IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3386:39:3386:55|No assignment to wire ARREADY_S2IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3387:39:3387:55|No assignment to wire ARREADY_S2IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3388:39:3388:55|No assignment to wire ARREADY_S3IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3389:39:3389:55|No assignment to wire ARREADY_S3IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3390:39:3390:55|No assignment to wire ARREADY_S3IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3391:39:3391:55|No assignment to wire ARREADY_S3IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3392:39:3392:55|No assignment to wire ARREADY_S4IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3393:39:3393:55|No assignment to wire ARREADY_S4IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3394:39:3394:55|No assignment to wire ARREADY_S4IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3395:39:3395:55|No assignment to wire ARREADY_S4IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3396:39:3396:55|No assignment to wire ARREADY_S5IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3397:39:3397:55|No assignment to wire ARREADY_S5IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3398:39:3398:55|No assignment to wire ARREADY_S5IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3399:39:3399:55|No assignment to wire ARREADY_S5IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3400:39:3400:55|No assignment to wire ARREADY_S6IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3401:39:3401:55|No assignment to wire ARREADY_S6IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3402:39:3402:55|No assignment to wire ARREADY_S6IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3403:39:3403:55|No assignment to wire ARREADY_S6IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3404:39:3404:55|No assignment to wire ARREADY_S7IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3405:39:3405:55|No assignment to wire ARREADY_S7IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3406:39:3406:55|No assignment to wire ARREADY_S7IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3407:39:3407:55|No assignment to wire ARREADY_S7IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3408:39:3408:55|No assignment to wire ARREADY_S8IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3409:39:3409:55|No assignment to wire ARREADY_S8IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3410:39:3410:55|No assignment to wire ARREADY_S8IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3411:39:3411:55|No assignment to wire ARREADY_S8IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3412:39:3412:55|No assignment to wire ARREADY_S9IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3413:39:3413:55|No assignment to wire ARREADY_S9IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3414:39:3414:55|No assignment to wire ARREADY_S9IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3415:39:3415:55|No assignment to wire ARREADY_S9IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3416:39:3416:56|No assignment to wire ARREADY_S10IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3417:39:3417:56|No assignment to wire ARREADY_S10IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3418:39:3418:56|No assignment to wire ARREADY_S10IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3419:39:3419:56|No assignment to wire ARREADY_S10IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3420:39:3420:56|No assignment to wire ARREADY_S11IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3421:39:3421:56|No assignment to wire ARREADY_S11IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3422:39:3422:56|No assignment to wire ARREADY_S11IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3423:39:3423:56|No assignment to wire ARREADY_S11IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3424:39:3424:56|No assignment to wire ARREADY_S12IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3425:39:3425:56|No assignment to wire ARREADY_S12IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3426:39:3426:56|No assignment to wire ARREADY_S12IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3427:39:3427:56|No assignment to wire ARREADY_S12IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3428:39:3428:56|No assignment to wire ARREADY_S13IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3429:39:3429:56|No assignment to wire ARREADY_S13IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3430:39:3430:56|No assignment to wire ARREADY_S13IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3431:39:3431:56|No assignment to wire ARREADY_S13IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3432:39:3432:56|No assignment to wire ARREADY_S14IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3433:39:3433:56|No assignment to wire ARREADY_S14IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3434:39:3434:56|No assignment to wire ARREADY_S14IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3435:39:3435:56|No assignment to wire ARREADY_S14IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3436:39:3436:56|No assignment to wire ARREADY_S15IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3437:39:3437:56|No assignment to wire ARREADY_S15IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3438:39:3438:56|No assignment to wire ARREADY_S15IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3439:39:3439:56|No assignment to wire ARREADY_S15IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3440:39:3440:56|No assignment to wire ARREADY_S16IM0_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3441:39:3441:56|No assignment to wire ARREADY_S16IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3442:39:3442:56|No assignment to wire ARREADY_S16IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3443:39:3443:56|No assignment to wire ARREADY_S16IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3449:39:3449:50|No assignment to wire WREADY_S1IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3450:39:3450:50|No assignment to wire WREADY_S1IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3451:39:3451:50|No assignment to wire WREADY_S1IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3452:39:3452:50|No assignment to wire WREADY_S1IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3453:39:3453:50|No assignment to wire WREADY_S2IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3454:39:3454:50|No assignment to wire WREADY_S2IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3455:39:3455:50|No assignment to wire WREADY_S2IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3456:39:3456:50|No assignment to wire WREADY_S2IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3457:39:3457:50|No assignment to wire WREADY_S3IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3458:39:3458:50|No assignment to wire WREADY_S3IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3459:39:3459:50|No assignment to wire WREADY_S3IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3460:39:3460:50|No assignment to wire WREADY_S3IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3461:39:3461:50|No assignment to wire WREADY_S4IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3462:39:3462:50|No assignment to wire WREADY_S4IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3463:39:3463:50|No assignment to wire WREADY_S4IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3464:39:3464:50|No assignment to wire WREADY_S4IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3465:39:3465:50|No assignment to wire WREADY_S5IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3466:39:3466:50|No assignment to wire WREADY_S5IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3467:39:3467:50|No assignment to wire WREADY_S5IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3468:39:3468:50|No assignment to wire WREADY_S5IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3469:39:3469:50|No assignment to wire WREADY_S6IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3470:39:3470:50|No assignment to wire WREADY_S6IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3471:39:3471:50|No assignment to wire WREADY_S6IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3472:39:3472:50|No assignment to wire WREADY_S6IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3473:39:3473:50|No assignment to wire WREADY_S7IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3474:39:3474:50|No assignment to wire WREADY_S7IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3475:39:3475:50|No assignment to wire WREADY_S7IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3476:39:3476:50|No assignment to wire WREADY_S7IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3477:39:3477:50|No assignment to wire WREADY_S8IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3478:39:3478:50|No assignment to wire WREADY_S8IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3479:39:3479:50|No assignment to wire WREADY_S8IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3480:39:3480:50|No assignment to wire WREADY_S8IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3481:39:3481:50|No assignment to wire WREADY_S9IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3482:39:3482:50|No assignment to wire WREADY_S9IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3483:39:3483:50|No assignment to wire WREADY_S9IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3484:39:3484:50|No assignment to wire WREADY_S9IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3485:39:3485:51|No assignment to wire WREADY_S10IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3486:39:3486:51|No assignment to wire WREADY_S10IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3487:39:3487:51|No assignment to wire WREADY_S10IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3488:39:3488:51|No assignment to wire WREADY_S10IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3489:39:3489:51|No assignment to wire WREADY_S11IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3490:39:3490:51|No assignment to wire WREADY_S11IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3491:39:3491:51|No assignment to wire WREADY_S11IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3492:39:3492:51|No assignment to wire WREADY_S11IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3493:39:3493:51|No assignment to wire WREADY_S12IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3494:39:3494:51|No assignment to wire WREADY_S12IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3495:39:3495:51|No assignment to wire WREADY_S12IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3496:39:3496:51|No assignment to wire WREADY_S12IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3497:39:3497:51|No assignment to wire WREADY_S13IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3498:39:3498:51|No assignment to wire WREADY_S13IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3499:39:3499:51|No assignment to wire WREADY_S13IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3500:39:3500:51|No assignment to wire WREADY_S13IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3501:39:3501:51|No assignment to wire WREADY_S14IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3502:39:3502:51|No assignment to wire WREADY_S14IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3503:39:3503:51|No assignment to wire WREADY_S14IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3504:39:3504:51|No assignment to wire WREADY_S14IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3505:39:3505:51|No assignment to wire WREADY_S15IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3506:39:3506:51|No assignment to wire WREADY_S15IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3507:39:3507:51|No assignment to wire WREADY_S15IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3508:39:3508:51|No assignment to wire WREADY_S15IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3509:39:3509:51|No assignment to wire WREADY_S16IM0
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3510:39:3510:51|No assignment to wire WREADY_S16IM1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3511:39:3511:51|No assignment to wire WREADY_S16IM2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3512:39:3512:51|No assignment to wire WREADY_S16IM3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3533:39:3533:49|No assignment to wire BID_IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3534:39:3534:51|No assignment to wire BRESP_IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3535:39:3535:52|No assignment to wire BVALID_IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3537:39:3537:49|No assignment to wire BID_IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3538:39:3538:51|No assignment to wire BRESP_IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3539:39:3539:52|No assignment to wire BVALID_IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3541:39:3541:49|No assignment to wire BID_IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3542:39:3542:51|No assignment to wire BRESP_IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3543:39:3543:52|No assignment to wire BVALID_IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3551:39:3551:49|No assignment to wire RID_IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3552:39:3552:51|No assignment to wire RRESP_IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3553:39:3553:52|No assignment to wire RVALID_IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3554:39:3554:51|No assignment to wire RLAST_IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3555:39:3555:51|No assignment to wire RDATA_IM1_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3557:39:3557:49|No assignment to wire RID_IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3558:39:3558:51|No assignment to wire RRESP_IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3559:39:3559:52|No assignment to wire RVALID_IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3560:39:3560:51|No assignment to wire RLAST_IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3561:39:3561:51|No assignment to wire RDATA_IM2_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3563:39:3563:49|No assignment to wire RID_IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3564:39:3564:51|No assignment to wire RRESP_IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3565:39:3565:52|No assignment to wire RVALID_IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3566:39:3566:51|No assignment to wire RLAST_IM3_int
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3567:39:3567:51|No assignment to wire RDATA_IM3_int
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":11753:3:11753:8|Pruning register AWVALID_M0_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":11753:3:11753:8|Pruning register AWADDR_M0_r[31:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":11753:3:11753:8|Pruning register AWVALID_M1_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":11753:3:11753:8|Pruning register AWADDR_M1_r[31:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":11753:3:11753:8|Pruning register AWVALID_M2_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":11753:3:11753:8|Pruning register AWADDR_M2_r[31:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":11753:3:11753:8|Pruning register AWVALID_M3_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":11753:3:11753:8|Pruning register AWADDR_M3_r[31:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":5855:3:5855:8|Pruning register ARADDR_IS16_gated_r[31:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":5855:3:5855:8|Pruning register ARVALID_IS16_gated_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":5842:3:5842:8|Pruning register AWADDR_IS16_gated_r[31:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":5842:3:5842:8|Pruning register AWVALID_IS16_gated_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":5842:3:5842:8|Pruning register WVALID_IS16_gated_r 
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":391:38:391:47|No assignment to AWID_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":392:19:392:30|No assignment to AWADDR_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":393:29:393:39|No assignment to AWLEN_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":394:29:394:40|No assignment to AWSIZE_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":395:29:395:41|No assignment to AWBURST_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":396:29:396:40|No assignment to AWLOCK_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":397:29:397:41|No assignment to AWCACHE_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":398:29:398:40|No assignment to AWPROT_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":401:38:401:47|No assignment to ARID_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":402:19:402:30|No assignment to ARADDR_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":403:29:403:39|No assignment to ARLEN_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":404:29:404:40|No assignment to ARSIZE_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":405:29:405:41|No assignment to ARBURST_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":406:29:406:40|No assignment to ARLOCK_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":407:29:407:41|No assignment to ARCACHE_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":408:29:408:40|No assignment to ARPROT_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":413:38:413:46|No assignment to WID_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":414:29:414:39|No assignment to WDATA_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":416:29:416:39|No assignment to WLAST_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":417:29:417:39|No assignment to WSTRB_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":448:38:448:49|No assignment to AWID_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":449:19:449:32|No assignment to AWADDR_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":450:29:450:41|No assignment to AWLEN_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":451:29:451:42|No assignment to AWSIZE_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":452:29:452:43|No assignment to AWBURST_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":453:29:453:42|No assignment to AWLOCK_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":454:29:454:43|No assignment to AWCACHE_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":455:29:455:42|No assignment to AWPROT_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":458:38:458:49|No assignment to ARID_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":459:19:459:32|No assignment to ARADDR_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":460:29:460:41|No assignment to ARLEN_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":461:29:461:42|No assignment to ARSIZE_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":462:29:462:43|No assignment to ARBURST_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":463:29:463:42|No assignment to ARLOCK_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":464:29:464:43|No assignment to ARCACHE_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":465:29:465:42|No assignment to ARPROT_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":471:38:471:48|No assignment to WID_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":472:29:472:41|No assignment to WDATA_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":474:29:474:41|No assignment to WLAST_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":475:29:475:41|No assignment to WSTRB_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":532:39:532:39|No assignment to k
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":533:39:533:39|No assignment to p
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":553:39:553:52|No assignment to wire gated_WREADY_M
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":554:39:554:58|No assignment to wire gated_AWVALID_M_flag
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":555:39:555:50|No assignment to WREADY_M_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":569:39:569:52|No assignment to ARREADY_M_int1
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2384:3:2384:8|Pruning register rdtrans_inprog_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2363:3:2363:8|Pruning register rd_wen_flag 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2331:3:2331:8|Pruning register rd_ren_flag 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2278:3:2278:8|Pruning register BID_M_r[3:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2278:3:2278:8|Pruning register BVALID_M_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2278:3:2278:8|Pruning register BRESP_M_r[1:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2117:9:2117:14|Pruning register genblk8.RVALID_M_pulse_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2041:3:2041:8|Pruning register gatedWA_Rdy 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2014:3:2014:8|Pruning register AWREADY_M_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2014:3:2014:8|Pruning register ARREADY_M_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2014:3:2014:8|Pruning register WREADY_M_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1967:3:1967:8|Pruning register WVALID_MI_r1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1967:3:1967:8|Pruning register WVALID_MI_r2 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1943:3:1943:8|Pruning register WREADY_IM_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1926:3:1926:8|Pruning register RVALID_IM_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1926:3:1926:8|Pruning register RVALID_M_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1926:3:1926:8|Pruning register RREADY_M_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1576:9:1576:14|Pruning register genblk4.RVALID_M_pulse 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1576:9:1576:14|Pruning register genblk4.RID_M_pulse[5:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1576:9:1576:14|Pruning register genblk4.RRESP_M_pulse[1:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1576:9:1576:14|Pruning register genblk4.RDATA_M_pulse[63:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1576:9:1576:14|Pruning register genblk4.RLAST_M_pulse 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1549:9:1549:14|Pruning register genblk4.BID_M_FF1[5:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1549:9:1549:14|Pruning register genblk4.BRESP_M_FF1[1:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1549:9:1549:14|Pruning register genblk4.RID_M_FF1[5:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1549:9:1549:14|Pruning register genblk4.RDATA_M_FF1[63:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1549:9:1549:14|Pruning register genblk4.RRESP_M_FF1[1:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1549:9:1549:14|Pruning register genblk4.RLAST_M_FF1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1549:9:1549:14|Pruning register genblk4.RVALID_M_FF1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1505:9:1505:14|Pruning register genblk4.RID_M_INPFF1[5:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1505:9:1505:14|Pruning register genblk4.RDATA_M_INPFF1[63:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1505:9:1505:14|Pruning register genblk4.RRESP_M_INPFF1[1:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1505:9:1505:14|Pruning register genblk4.RLAST_M_INPFF1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1505:9:1505:14|Pruning register genblk4.RVALID_M_INPFF1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1483:9:1483:14|Pruning register genblk4.next_rvalid_sample 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1483:9:1483:14|Pruning register genblk4.next_rvalid_sample_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1483:9:1483:14|Pruning register genblk4.RLAST_IM_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1461:9:1461:14|Pruning register genblk4.next_valid_sample 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1461:9:1461:14|Pruning register genblk4.next_valid_sample_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1461:9:1461:14|Pruning register genblk4.WLAST_M_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1461:9:1461:14|Pruning register genblk4.AWVALID_M_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1461:9:1461:14|Pruning register genblk4.ARVALID_M_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1426:9:1426:14|Pruning register genblk4.BREADY_M_FF1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1426:9:1426:14|Pruning register genblk4.RREADY_M_FF1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1395:9:1395:14|Pruning register genblk4.BREADY_M_INPFF1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1395:9:1395:14|Pruning register genblk4.RREADY_M_INPFF1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Pruning register genblk4.prev_ARID[3:0] 
@W: CL271 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2157:9:2157:14|Pruning bits 5 to 4 of genblk8.RID_M_int[5:0] -- not in use ...
@W: CL271 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1603:9:1603:14|Pruning bits 5 to 2 of genblk4.BID_M_pulse[5:0] -- not in use ...
@W: CL271 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1505:9:1505:14|Pruning bits 5 to 2 of genblk4.BID_M_INPFF1[5:0] -- not in use ...
@W: CL271 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Pruning bits 27 to 0 of genblk4.prev_ARADDR[31:0] -- not in use ...
@W: CL207 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2331:3:2331:8|All reachable assignments to rd_rdcntr[3:0] assign 0, register removed by optimization.
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Optimizing register bit genblk4.ARID_M_INPFF1[2] to a constant 0
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Optimizing register bit genblk4.ARID_M_INPFF1[3] to a constant 0
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Optimizing register bit genblk4.AWID_M_INPFF1[2] to a constant 0
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Optimizing register bit genblk4.AWID_M_INPFF1[3] to a constant 0
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1395:9:1395:14|Optimizing register bit genblk4.WID_M_INPFF1[2] to a constant 0
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1395:9:1395:14|Optimizing register bit genblk4.WID_M_INPFF1[3] to a constant 0
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2157:9:2157:14|Optimizing register bit genblk8.RID_M_int[2] to a constant 0
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2157:9:2157:14|Optimizing register bit genblk8.RID_M_int[3] to a constant 0
@W: CL279 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2157:9:2157:14|Pruning register bits 3 to 2 of genblk8.RID_M_int[3:0] 
@W: CL279 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Pruning register bits 3 to 2 of genblk4.ARID_M_INPFF1[5:0] 
@W: CL279 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1255:9:1255:14|Pruning register bits 3 to 2 of genblk4.AWID_M_INPFF1[5:0] 
@W: CL279 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":1395:9:1395:14|Pruning register bits 3 to 2 of genblk4.WID_M_INPFF1[5:0] 
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":400:43:400:51|No assignment to RID_S_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":401:29:401:39|No assignment to RDATA_S_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":402:29:402:39|No assignment to RRESP_S_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":403:29:403:39|No assignment to RLAST_S_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":404:29:404:40|No assignment to RVALID_S_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":405:43:405:54|No assignment to RID_S_INPFF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":406:29:406:42|No assignment to RDATA_S_INPFF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":407:29:407:42|No assignment to RRESP_S_INPFF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":408:29:408:42|No assignment to RLAST_S_INPFF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":409:29:409:43|No assignment to RVALID_S_INPFF1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":410:44:410:54|No assignment to wire RID_S_pulse
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":411:30:411:42|No assignment to wire RDATA_S_pulse
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":412:30:412:42|No assignment to wire RRESP_S_pulse
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":413:30:413:42|No assignment to wire RLAST_S_pulse
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":414:30:414:43|No assignment to wire RVALID_S_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":416:43:416:51|No assignment to BID_S_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":417:29:417:39|No assignment to BRESP_S_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":418:29:418:40|No assignment to BVALID_S_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":419:43:419:54|No assignment to BID_S_INPFF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":420:29:420:42|No assignment to BRESP_S_INPFF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":421:29:421:43|No assignment to BVALID_S_INPFF1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":422:44:422:54|No assignment to wire BID_S_pulse
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":423:30:423:42|No assignment to wire BRESP_S_pulse
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":424:30:424:43|No assignment to wire BVALID_S_pulse
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":426:30:426:43|No assignment to wire gated_WVALID_S
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":427:30:427:47|No assignment to wire gated_AWVALID_flag
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":428:30:428:40|No assignment to WLAST_S_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":429:30:429:41|No assignment to WVALID_S_int
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":435:36:435:44|No assignment to RID_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":436:29:436:39|No assignment to RDATA_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":437:29:437:39|No assignment to RRESP_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":438:29:438:39|No assignment to RLAST_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":439:29:439:40|No assignment to RVALID_M_FF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":440:43:440:54|No assignment to RID_M_INPFF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":441:29:441:42|No assignment to RDATA_M_INPFF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":442:29:442:42|No assignment to RRESP_M_INPFF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":443:29:443:42|No assignment to RLAST_M_INPFF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":444:29:444:43|No assignment to RVALID_M_INPFF1
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":446:43:446:53|No assignment to RID_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":447:29:447:41|No assignment to RDATA_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":448:29:448:41|No assignment to RRESP_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":449:29:449:41|No assignment to RLAST_M_pulse
@W: CG133 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":450:29:450:42|No assignment to RVALID_M_pulse
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":762:3:762:8|Pruning register ARVALID_S_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":762:3:762:8|Pruning register AWVALID_S_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":762:3:762:8|Pruning register WVALID_S_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":762:3:762:8|Pruning register ARVALID_S_r1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":762:3:762:8|Pruning register AWVALID_S_r1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":762:3:762:8|Pruning register WVALID_S_r1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":762:3:762:8|Pruning register AWREADY_S_r 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":762:3:762:8|Pruning register ARREADY_S_r 
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1307:58:1307:64|No assignment to wire AWID_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1308:23:1308:31|No assignment to wire AWADDR_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1309:33:1309:40|No assignment to wire AWLEN_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1310:33:1310:41|No assignment to wire AWSIZE_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1311:33:1311:42|No assignment to wire AWBURST_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1312:33:1312:41|No assignment to wire AWLOCK_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1313:33:1313:42|No assignment to wire AWCACHE_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1314:33:1314:41|No assignment to wire AWPROT_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1315:33:1315:42|No assignment to wire AWVALID_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1318:58:1318:63|No assignment to wire WID_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1319:33:1319:40|No assignment to wire WDATA_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1320:33:1320:40|No assignment to wire WSTRB_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1321:33:1321:40|No assignment to wire WLAST_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1322:33:1322:41|No assignment to wire WVALID_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1328:33:1328:41|No assignment to wire BREADY_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1330:58:1330:64|No assignment to wire ARID_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1331:23:1331:31|No assignment to wire ARADDR_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1332:33:1332:40|No assignment to wire ARLEN_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|No assignment to wire ARSIZE_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1334:33:1334:42|No assignment to wire ARBURST_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1335:33:1335:41|No assignment to wire ARLOCK_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1336:33:1336:42|No assignment to wire ARCACHE_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1337:33:1337:41|No assignment to wire ARPROT_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1338:33:1338:42|No assignment to wire ARVALID_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1346:33:1346:41|No assignment to wire RREADY_S1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1350:58:1350:64|No assignment to wire AWID_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1351:23:1351:31|No assignment to wire AWADDR_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1352:33:1352:40|No assignment to wire AWLEN_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1353:33:1353:41|No assignment to wire AWSIZE_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1354:33:1354:42|No assignment to wire AWBURST_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1355:33:1355:41|No assignment to wire AWLOCK_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1356:33:1356:42|No assignment to wire AWCACHE_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1357:33:1357:41|No assignment to wire AWPROT_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1358:33:1358:42|No assignment to wire AWVALID_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1361:58:1361:63|No assignment to wire WID_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1362:33:1362:40|No assignment to wire WDATA_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1363:33:1363:40|No assignment to wire WSTRB_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1364:33:1364:40|No assignment to wire WLAST_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1365:33:1365:41|No assignment to wire WVALID_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1371:33:1371:41|No assignment to wire BREADY_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1373:58:1373:64|No assignment to wire ARID_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1374:23:1374:31|No assignment to wire ARADDR_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1375:33:1375:40|No assignment to wire ARLEN_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|No assignment to wire ARSIZE_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1377:33:1377:42|No assignment to wire ARBURST_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1378:33:1378:41|No assignment to wire ARLOCK_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1379:33:1379:42|No assignment to wire ARCACHE_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1380:33:1380:41|No assignment to wire ARPROT_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1381:33:1381:42|No assignment to wire ARVALID_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1389:33:1389:41|No assignment to wire RREADY_S2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1393:58:1393:64|No assignment to wire AWID_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1394:23:1394:31|No assignment to wire AWADDR_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1395:33:1395:40|No assignment to wire AWLEN_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1396:33:1396:41|No assignment to wire AWSIZE_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1397:33:1397:42|No assignment to wire AWBURST_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1398:33:1398:41|No assignment to wire AWLOCK_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1399:33:1399:42|No assignment to wire AWCACHE_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1400:33:1400:41|No assignment to wire AWPROT_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1401:33:1401:42|No assignment to wire AWVALID_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1404:58:1404:63|No assignment to wire WID_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1405:33:1405:40|No assignment to wire WDATA_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1406:33:1406:40|No assignment to wire WSTRB_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1407:33:1407:40|No assignment to wire WLAST_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1408:33:1408:41|No assignment to wire WVALID_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1414:33:1414:41|No assignment to wire BREADY_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1416:58:1416:64|No assignment to wire ARID_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1417:23:1417:31|No assignment to wire ARADDR_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1418:33:1418:40|No assignment to wire ARLEN_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|No assignment to wire ARSIZE_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1420:33:1420:42|No assignment to wire ARBURST_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1421:33:1421:41|No assignment to wire ARLOCK_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1422:33:1422:42|No assignment to wire ARCACHE_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1423:33:1423:41|No assignment to wire ARPROT_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1424:33:1424:42|No assignment to wire ARVALID_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1432:33:1432:41|No assignment to wire RREADY_S3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1436:58:1436:64|No assignment to wire AWID_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1437:23:1437:31|No assignment to wire AWADDR_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1438:33:1438:40|No assignment to wire AWLEN_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1439:33:1439:41|No assignment to wire AWSIZE_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1440:33:1440:42|No assignment to wire AWBURST_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1441:33:1441:41|No assignment to wire AWLOCK_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1442:33:1442:42|No assignment to wire AWCACHE_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1443:33:1443:41|No assignment to wire AWPROT_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1444:33:1444:42|No assignment to wire AWVALID_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1447:58:1447:63|No assignment to wire WID_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1448:33:1448:40|No assignment to wire WDATA_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1449:33:1449:40|No assignment to wire WSTRB_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1450:33:1450:40|No assignment to wire WLAST_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1451:33:1451:41|No assignment to wire WVALID_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1457:33:1457:41|No assignment to wire BREADY_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1459:58:1459:64|No assignment to wire ARID_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1460:23:1460:31|No assignment to wire ARADDR_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1461:33:1461:40|No assignment to wire ARLEN_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|No assignment to wire ARSIZE_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1463:33:1463:42|No assignment to wire ARBURST_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1464:33:1464:41|No assignment to wire ARLOCK_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1465:33:1465:42|No assignment to wire ARCACHE_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1466:33:1466:41|No assignment to wire ARPROT_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1467:33:1467:42|No assignment to wire ARVALID_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1475:33:1475:41|No assignment to wire RREADY_S4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1479:58:1479:64|No assignment to wire AWID_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1480:23:1480:31|No assignment to wire AWADDR_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1481:33:1481:40|No assignment to wire AWLEN_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1482:33:1482:41|No assignment to wire AWSIZE_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1483:33:1483:42|No assignment to wire AWBURST_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1484:33:1484:41|No assignment to wire AWLOCK_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1485:33:1485:42|No assignment to wire AWCACHE_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1486:33:1486:41|No assignment to wire AWPROT_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1487:33:1487:42|No assignment to wire AWVALID_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1490:58:1490:63|No assignment to wire WID_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1491:33:1491:40|No assignment to wire WDATA_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1492:33:1492:40|No assignment to wire WSTRB_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1493:33:1493:40|No assignment to wire WLAST_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1494:33:1494:41|No assignment to wire WVALID_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1500:33:1500:41|No assignment to wire BREADY_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1502:58:1502:64|No assignment to wire ARID_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1503:23:1503:31|No assignment to wire ARADDR_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1504:33:1504:40|No assignment to wire ARLEN_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|No assignment to wire ARSIZE_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1506:33:1506:42|No assignment to wire ARBURST_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1507:33:1507:41|No assignment to wire ARLOCK_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1508:33:1508:42|No assignment to wire ARCACHE_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1509:33:1509:41|No assignment to wire ARPROT_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1510:33:1510:42|No assignment to wire ARVALID_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1518:33:1518:41|No assignment to wire RREADY_S5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1522:58:1522:64|No assignment to wire AWID_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1523:23:1523:31|No assignment to wire AWADDR_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1524:33:1524:40|No assignment to wire AWLEN_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1525:33:1525:41|No assignment to wire AWSIZE_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1526:33:1526:42|No assignment to wire AWBURST_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1527:33:1527:41|No assignment to wire AWLOCK_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1528:33:1528:42|No assignment to wire AWCACHE_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1529:33:1529:41|No assignment to wire AWPROT_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1530:33:1530:42|No assignment to wire AWVALID_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1533:58:1533:63|No assignment to wire WID_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1534:33:1534:40|No assignment to wire WDATA_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1535:33:1535:40|No assignment to wire WSTRB_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1536:33:1536:40|No assignment to wire WLAST_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1537:33:1537:41|No assignment to wire WVALID_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1543:33:1543:41|No assignment to wire BREADY_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1545:58:1545:64|No assignment to wire ARID_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1546:23:1546:31|No assignment to wire ARADDR_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1547:33:1547:40|No assignment to wire ARLEN_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1548:33:1548:41|No assignment to wire ARSIZE_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1549:33:1549:42|No assignment to wire ARBURST_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1550:33:1550:41|No assignment to wire ARLOCK_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1551:33:1551:42|No assignment to wire ARCACHE_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1552:33:1552:41|No assignment to wire ARPROT_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1553:33:1553:42|No assignment to wire ARVALID_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1561:33:1561:41|No assignment to wire RREADY_S6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1565:58:1565:64|No assignment to wire AWID_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1566:23:1566:31|No assignment to wire AWADDR_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1567:33:1567:40|No assignment to wire AWLEN_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1568:33:1568:41|No assignment to wire AWSIZE_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1569:33:1569:42|No assignment to wire AWBURST_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1570:33:1570:41|No assignment to wire AWLOCK_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1571:33:1571:42|No assignment to wire AWCACHE_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1572:33:1572:41|No assignment to wire AWPROT_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1573:33:1573:42|No assignment to wire AWVALID_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1576:58:1576:63|No assignment to wire WID_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1577:33:1577:40|No assignment to wire WDATA_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1578:33:1578:40|No assignment to wire WSTRB_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1579:33:1579:40|No assignment to wire WLAST_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1580:33:1580:41|No assignment to wire WVALID_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1586:33:1586:41|No assignment to wire BREADY_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1588:58:1588:64|No assignment to wire ARID_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1589:23:1589:31|No assignment to wire ARADDR_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1590:33:1590:40|No assignment to wire ARLEN_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1591:33:1591:41|No assignment to wire ARSIZE_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1592:33:1592:42|No assignment to wire ARBURST_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1593:33:1593:41|No assignment to wire ARLOCK_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1594:33:1594:42|No assignment to wire ARCACHE_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1595:33:1595:41|No assignment to wire ARPROT_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1596:33:1596:42|No assignment to wire ARVALID_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1604:33:1604:41|No assignment to wire RREADY_S7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1608:58:1608:64|No assignment to wire AWID_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1609:23:1609:31|No assignment to wire AWADDR_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1610:33:1610:40|No assignment to wire AWLEN_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1611:33:1611:41|No assignment to wire AWSIZE_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1612:33:1612:42|No assignment to wire AWBURST_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1613:33:1613:41|No assignment to wire AWLOCK_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1614:33:1614:42|No assignment to wire AWCACHE_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1615:33:1615:41|No assignment to wire AWPROT_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1616:33:1616:42|No assignment to wire AWVALID_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1619:58:1619:63|No assignment to wire WID_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1620:33:1620:40|No assignment to wire WDATA_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1621:33:1621:40|No assignment to wire WSTRB_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1622:33:1622:40|No assignment to wire WLAST_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1623:33:1623:41|No assignment to wire WVALID_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1629:33:1629:41|No assignment to wire BREADY_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1631:58:1631:64|No assignment to wire ARID_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1632:23:1632:31|No assignment to wire ARADDR_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1633:33:1633:40|No assignment to wire ARLEN_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1634:33:1634:41|No assignment to wire ARSIZE_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1635:33:1635:42|No assignment to wire ARBURST_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1636:33:1636:41|No assignment to wire ARLOCK_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1637:33:1637:42|No assignment to wire ARCACHE_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1638:33:1638:41|No assignment to wire ARPROT_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1639:33:1639:42|No assignment to wire ARVALID_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1647:33:1647:41|No assignment to wire RREADY_S8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1651:58:1651:64|No assignment to wire AWID_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1652:23:1652:31|No assignment to wire AWADDR_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1653:33:1653:40|No assignment to wire AWLEN_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1654:33:1654:41|No assignment to wire AWSIZE_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1655:33:1655:42|No assignment to wire AWBURST_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1656:33:1656:41|No assignment to wire AWLOCK_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1657:33:1657:42|No assignment to wire AWCACHE_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1658:33:1658:41|No assignment to wire AWPROT_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1659:33:1659:42|No assignment to wire AWVALID_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1662:58:1662:63|No assignment to wire WID_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1663:33:1663:40|No assignment to wire WDATA_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1664:33:1664:40|No assignment to wire WSTRB_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1665:33:1665:40|No assignment to wire WLAST_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1666:33:1666:41|No assignment to wire WVALID_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1672:33:1672:41|No assignment to wire BREADY_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1674:58:1674:64|No assignment to wire ARID_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1675:23:1675:31|No assignment to wire ARADDR_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1676:33:1676:40|No assignment to wire ARLEN_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1677:33:1677:41|No assignment to wire ARSIZE_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1678:33:1678:42|No assignment to wire ARBURST_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1679:33:1679:41|No assignment to wire ARLOCK_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1680:33:1680:42|No assignment to wire ARCACHE_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1681:33:1681:41|No assignment to wire ARPROT_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1682:33:1682:42|No assignment to wire ARVALID_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1690:33:1690:41|No assignment to wire RREADY_S9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1694:58:1694:65|No assignment to wire AWID_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1695:23:1695:32|No assignment to wire AWADDR_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1696:33:1696:41|No assignment to wire AWLEN_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1697:33:1697:42|No assignment to wire AWSIZE_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1698:33:1698:43|No assignment to wire AWBURST_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1699:33:1699:42|No assignment to wire AWLOCK_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1700:33:1700:43|No assignment to wire AWCACHE_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1701:33:1701:42|No assignment to wire AWPROT_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1702:33:1702:43|No assignment to wire AWVALID_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1705:58:1705:64|No assignment to wire WID_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1706:33:1706:41|No assignment to wire WDATA_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1707:33:1707:41|No assignment to wire WSTRB_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1708:33:1708:41|No assignment to wire WLAST_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1709:33:1709:42|No assignment to wire WVALID_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1715:33:1715:42|No assignment to wire BREADY_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1717:58:1717:65|No assignment to wire ARID_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1718:23:1718:32|No assignment to wire ARADDR_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1719:33:1719:41|No assignment to wire ARLEN_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1720:33:1720:42|No assignment to wire ARSIZE_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1721:33:1721:43|No assignment to wire ARBURST_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1722:33:1722:42|No assignment to wire ARLOCK_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1723:33:1723:43|No assignment to wire ARCACHE_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1724:33:1724:42|No assignment to wire ARPROT_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1725:33:1725:43|No assignment to wire ARVALID_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1733:33:1733:42|No assignment to wire RREADY_S10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1737:58:1737:65|No assignment to wire AWID_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1738:23:1738:32|No assignment to wire AWADDR_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1739:33:1739:41|No assignment to wire AWLEN_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1740:33:1740:42|No assignment to wire AWSIZE_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1741:33:1741:43|No assignment to wire AWBURST_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1742:33:1742:42|No assignment to wire AWLOCK_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1743:33:1743:43|No assignment to wire AWCACHE_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1744:33:1744:42|No assignment to wire AWPROT_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1745:33:1745:43|No assignment to wire AWVALID_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1748:58:1748:64|No assignment to wire WID_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1749:33:1749:41|No assignment to wire WDATA_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1750:33:1750:41|No assignment to wire WSTRB_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1751:33:1751:41|No assignment to wire WLAST_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1752:33:1752:42|No assignment to wire WVALID_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1758:33:1758:42|No assignment to wire BREADY_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1760:58:1760:65|No assignment to wire ARID_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1761:23:1761:32|No assignment to wire ARADDR_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1762:33:1762:41|No assignment to wire ARLEN_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1763:33:1763:42|No assignment to wire ARSIZE_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1764:33:1764:43|No assignment to wire ARBURST_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1765:33:1765:42|No assignment to wire ARLOCK_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1766:33:1766:43|No assignment to wire ARCACHE_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1767:33:1767:42|No assignment to wire ARPROT_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1768:33:1768:43|No assignment to wire ARVALID_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1776:33:1776:42|No assignment to wire RREADY_S11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1780:58:1780:65|No assignment to wire AWID_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1781:23:1781:32|No assignment to wire AWADDR_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1782:33:1782:41|No assignment to wire AWLEN_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1783:33:1783:42|No assignment to wire AWSIZE_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1784:33:1784:43|No assignment to wire AWBURST_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1785:33:1785:42|No assignment to wire AWLOCK_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1786:33:1786:43|No assignment to wire AWCACHE_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1787:33:1787:42|No assignment to wire AWPROT_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1788:33:1788:43|No assignment to wire AWVALID_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1791:58:1791:64|No assignment to wire WID_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1792:33:1792:41|No assignment to wire WDATA_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1793:33:1793:41|No assignment to wire WSTRB_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1794:33:1794:41|No assignment to wire WLAST_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1795:33:1795:42|No assignment to wire WVALID_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1801:33:1801:42|No assignment to wire BREADY_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1803:58:1803:65|No assignment to wire ARID_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1804:23:1804:32|No assignment to wire ARADDR_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1805:33:1805:41|No assignment to wire ARLEN_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1806:33:1806:42|No assignment to wire ARSIZE_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1807:33:1807:43|No assignment to wire ARBURST_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1808:33:1808:42|No assignment to wire ARLOCK_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1809:33:1809:43|No assignment to wire ARCACHE_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1810:33:1810:42|No assignment to wire ARPROT_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1811:33:1811:43|No assignment to wire ARVALID_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1819:33:1819:42|No assignment to wire RREADY_S12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1823:58:1823:65|No assignment to wire AWID_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1824:23:1824:32|No assignment to wire AWADDR_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1825:33:1825:41|No assignment to wire AWLEN_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1826:33:1826:42|No assignment to wire AWSIZE_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1827:33:1827:43|No assignment to wire AWBURST_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1828:33:1828:42|No assignment to wire AWLOCK_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1829:33:1829:43|No assignment to wire AWCACHE_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1830:33:1830:42|No assignment to wire AWPROT_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1831:33:1831:43|No assignment to wire AWVALID_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1834:58:1834:64|No assignment to wire WID_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1835:33:1835:41|No assignment to wire WDATA_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1836:33:1836:41|No assignment to wire WSTRB_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1837:33:1837:41|No assignment to wire WLAST_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1838:33:1838:42|No assignment to wire WVALID_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1844:33:1844:42|No assignment to wire BREADY_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1846:58:1846:65|No assignment to wire ARID_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1847:23:1847:32|No assignment to wire ARADDR_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1848:33:1848:41|No assignment to wire ARLEN_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1849:33:1849:42|No assignment to wire ARSIZE_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1850:33:1850:43|No assignment to wire ARBURST_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1851:33:1851:42|No assignment to wire ARLOCK_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1852:33:1852:43|No assignment to wire ARCACHE_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1853:33:1853:42|No assignment to wire ARPROT_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1854:33:1854:43|No assignment to wire ARVALID_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1862:33:1862:42|No assignment to wire RREADY_S13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1866:58:1866:65|No assignment to wire AWID_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1867:23:1867:32|No assignment to wire AWADDR_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1868:33:1868:41|No assignment to wire AWLEN_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1869:33:1869:42|No assignment to wire AWSIZE_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1870:33:1870:43|No assignment to wire AWBURST_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1871:33:1871:42|No assignment to wire AWLOCK_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1872:33:1872:43|No assignment to wire AWCACHE_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1873:33:1873:42|No assignment to wire AWPROT_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1874:33:1874:43|No assignment to wire AWVALID_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1877:58:1877:64|No assignment to wire WID_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1878:33:1878:41|No assignment to wire WDATA_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1879:33:1879:41|No assignment to wire WSTRB_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1880:33:1880:41|No assignment to wire WLAST_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1881:33:1881:42|No assignment to wire WVALID_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1887:33:1887:42|No assignment to wire BREADY_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1889:58:1889:65|No assignment to wire ARID_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1890:23:1890:32|No assignment to wire ARADDR_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1891:33:1891:41|No assignment to wire ARLEN_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1892:33:1892:42|No assignment to wire ARSIZE_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1893:33:1893:43|No assignment to wire ARBURST_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1894:33:1894:42|No assignment to wire ARLOCK_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1895:33:1895:43|No assignment to wire ARCACHE_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1896:33:1896:42|No assignment to wire ARPROT_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1897:33:1897:43|No assignment to wire ARVALID_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1905:33:1905:42|No assignment to wire RREADY_S14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1909:58:1909:65|No assignment to wire AWID_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1910:23:1910:32|No assignment to wire AWADDR_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1911:33:1911:41|No assignment to wire AWLEN_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1912:33:1912:42|No assignment to wire AWSIZE_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1913:33:1913:43|No assignment to wire AWBURST_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1914:33:1914:42|No assignment to wire AWLOCK_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1915:33:1915:43|No assignment to wire AWCACHE_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1916:33:1916:42|No assignment to wire AWPROT_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1917:33:1917:43|No assignment to wire AWVALID_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1920:58:1920:64|No assignment to wire WID_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1921:33:1921:41|No assignment to wire WDATA_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1922:33:1922:41|No assignment to wire WSTRB_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1923:33:1923:41|No assignment to wire WLAST_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1924:33:1924:42|No assignment to wire WVALID_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1930:33:1930:42|No assignment to wire BREADY_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1932:58:1932:65|No assignment to wire ARID_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1933:23:1933:32|No assignment to wire ARADDR_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1934:33:1934:41|No assignment to wire ARLEN_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1935:33:1935:42|No assignment to wire ARSIZE_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1936:33:1936:43|No assignment to wire ARBURST_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1937:33:1937:42|No assignment to wire ARLOCK_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1938:33:1938:43|No assignment to wire ARCACHE_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1939:33:1939:42|No assignment to wire ARPROT_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1940:33:1940:43|No assignment to wire ARVALID_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1948:33:1948:42|No assignment to wire RREADY_S15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1952:58:1952:65|No assignment to wire AWID_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1953:23:1953:32|No assignment to wire AWADDR_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1954:33:1954:41|No assignment to wire AWLEN_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1955:33:1955:42|No assignment to wire AWSIZE_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1956:33:1956:43|No assignment to wire AWBURST_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1957:33:1957:42|No assignment to wire AWLOCK_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1958:33:1958:43|No assignment to wire AWCACHE_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1959:33:1959:42|No assignment to wire AWPROT_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1960:33:1960:43|No assignment to wire AWVALID_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1963:58:1963:64|No assignment to wire WID_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1964:33:1964:41|No assignment to wire WDATA_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1965:33:1965:41|No assignment to wire WSTRB_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1966:33:1966:41|No assignment to wire WLAST_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1967:33:1967:42|No assignment to wire WVALID_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1973:33:1973:42|No assignment to wire BREADY_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1975:58:1975:65|No assignment to wire ARID_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1976:23:1976:32|No assignment to wire ARADDR_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1977:33:1977:41|No assignment to wire ARLEN_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1978:33:1978:42|No assignment to wire ARSIZE_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1979:33:1979:43|No assignment to wire ARBURST_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1980:33:1980:42|No assignment to wire ARLOCK_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1981:33:1981:43|No assignment to wire ARCACHE_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1982:33:1982:42|No assignment to wire ARPROT_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1983:33:1983:43|No assignment to wire ARVALID_S16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2010:33:2010:42|No assignment to wire BREADY_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2011:33:2011:42|No assignment to wire BREADY_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2012:33:2012:42|No assignment to wire BREADY_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2014:33:2014:42|No assignment to wire RREADY_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2015:33:2015:42|No assignment to wire RREADY_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2016:33:2016:42|No assignment to wire RREADY_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2610:39:2610:46|No assignment to wire AWID_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2611:22:2611:31|No assignment to wire AWADDR_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2612:32:2612:40|No assignment to wire AWLEN_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2613:32:2613:41|No assignment to wire AWSIZE_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2614:32:2614:42|No assignment to wire AWBURST_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2615:32:2615:41|No assignment to wire AWLOCK_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2616:32:2616:42|No assignment to wire AWCACHE_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2617:32:2617:41|No assignment to wire AWPROT_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2618:32:2618:42|No assignment to wire AWVALID_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2620:39:2620:45|No assignment to wire WID_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2621:32:2621:40|No assignment to wire WDATA_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2622:32:2622:40|No assignment to wire WSTRB_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2623:32:2623:40|No assignment to wire WLAST_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2624:32:2624:41|No assignment to wire WVALID_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2626:39:2626:46|No assignment to wire ARID_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2627:21:2627:30|No assignment to wire ARADDR_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2628:31:2628:39|No assignment to wire ARLEN_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2629:31:2629:40|No assignment to wire ARSIZE_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2630:31:2630:41|No assignment to wire ARBURST_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2631:31:2631:40|No assignment to wire ARLOCK_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2632:31:2632:41|No assignment to wire ARCACHE_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2633:31:2633:40|No assignment to wire ARPROT_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2634:31:2634:41|No assignment to wire ARVALID_MI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2647:39:2647:46|No assignment to wire AWID_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2648:22:2648:31|No assignment to wire AWADDR_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2649:32:2649:40|No assignment to wire AWLEN_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2650:32:2650:41|No assignment to wire AWSIZE_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2651:32:2651:42|No assignment to wire AWBURST_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2652:32:2652:41|No assignment to wire AWLOCK_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2653:32:2653:42|No assignment to wire AWCACHE_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2654:32:2654:41|No assignment to wire AWPROT_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2655:32:2655:42|No assignment to wire AWVALID_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2657:39:2657:45|No assignment to wire WID_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2658:32:2658:40|No assignment to wire WDATA_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2659:32:2659:40|No assignment to wire WSTRB_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2660:32:2660:40|No assignment to wire WLAST_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2661:32:2661:41|No assignment to wire WVALID_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2663:39:2663:46|No assignment to wire ARID_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2664:21:2664:30|No assignment to wire ARADDR_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2665:31:2665:39|No assignment to wire ARLEN_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2666:31:2666:40|No assignment to wire ARSIZE_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2667:31:2667:41|No assignment to wire ARBURST_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2668:31:2668:40|No assignment to wire ARLOCK_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2669:31:2669:41|No assignment to wire ARCACHE_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2670:31:2670:40|No assignment to wire ARPROT_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2671:31:2671:41|No assignment to wire ARVALID_MI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2684:39:2684:46|No assignment to wire AWID_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2685:22:2685:31|No assignment to wire AWADDR_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2686:32:2686:40|No assignment to wire AWLEN_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2687:32:2687:41|No assignment to wire AWSIZE_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2688:32:2688:42|No assignment to wire AWBURST_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2689:32:2689:41|No assignment to wire AWLOCK_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2690:32:2690:42|No assignment to wire AWCACHE_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2691:32:2691:41|No assignment to wire AWPROT_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2692:32:2692:42|No assignment to wire AWVALID_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2694:39:2694:45|No assignment to wire WID_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2695:32:2695:40|No assignment to wire WDATA_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2696:32:2696:40|No assignment to wire WSTRB_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2697:32:2697:40|No assignment to wire WLAST_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2698:32:2698:41|No assignment to wire WVALID_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2700:39:2700:46|No assignment to wire ARID_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2701:21:2701:30|No assignment to wire ARADDR_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2702:31:2702:39|No assignment to wire ARLEN_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2703:31:2703:40|No assignment to wire ARSIZE_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2704:31:2704:41|No assignment to wire ARBURST_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2705:31:2705:40|No assignment to wire ARLOCK_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2706:31:2706:41|No assignment to wire ARCACHE_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2707:31:2707:40|No assignment to wire ARPROT_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2708:31:2708:41|No assignment to wire ARVALID_MI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3264:31:3264:41|No assignment to wire AWREADY_SI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3265:31:3265:41|No assignment to wire AWREADY_SI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3266:31:3266:41|No assignment to wire AWREADY_SI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3267:31:3267:41|No assignment to wire AWREADY_SI4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3268:31:3268:41|No assignment to wire AWREADY_SI5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3269:31:3269:41|No assignment to wire AWREADY_SI6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3270:31:3270:41|No assignment to wire AWREADY_SI7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3271:31:3271:41|No assignment to wire AWREADY_SI8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3272:31:3272:41|No assignment to wire AWREADY_SI9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3273:31:3273:42|No assignment to wire AWREADY_SI10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3274:31:3274:42|No assignment to wire AWREADY_SI11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3275:31:3275:42|No assignment to wire AWREADY_SI12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3276:31:3276:42|No assignment to wire AWREADY_SI13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3277:31:3277:42|No assignment to wire AWREADY_SI14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3278:31:3278:42|No assignment to wire AWREADY_SI15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3279:31:3279:42|No assignment to wire AWREADY_SI16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3282:31:3282:40|No assignment to wire WREADY_SI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3283:31:3283:40|No assignment to wire WREADY_SI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3284:31:3284:40|No assignment to wire WREADY_SI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3285:31:3285:40|No assignment to wire WREADY_SI4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3286:31:3286:40|No assignment to wire WREADY_SI5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3287:31:3287:40|No assignment to wire WREADY_SI6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3288:31:3288:40|No assignment to wire WREADY_SI7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3289:31:3289:40|No assignment to wire WREADY_SI8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3290:31:3290:40|No assignment to wire WREADY_SI9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3291:31:3291:41|No assignment to wire WREADY_SI10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3292:31:3292:41|No assignment to wire WREADY_SI11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3293:31:3293:41|No assignment to wire WREADY_SI12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3294:31:3294:41|No assignment to wire WREADY_SI13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3295:31:3295:41|No assignment to wire WREADY_SI14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3296:31:3296:41|No assignment to wire WREADY_SI15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3297:31:3297:41|No assignment to wire WREADY_SI16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3300:31:3300:41|No assignment to wire ARREADY_SI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3301:31:3301:41|No assignment to wire ARREADY_SI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3302:31:3302:41|No assignment to wire ARREADY_SI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3303:31:3303:41|No assignment to wire ARREADY_SI4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3304:31:3304:41|No assignment to wire ARREADY_SI5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3305:31:3305:41|No assignment to wire ARREADY_SI6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3306:31:3306:41|No assignment to wire ARREADY_SI7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3307:31:3307:41|No assignment to wire ARREADY_SI8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3308:31:3308:41|No assignment to wire ARREADY_SI9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3309:31:3309:42|No assignment to wire ARREADY_SI10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3310:31:3310:42|No assignment to wire ARREADY_SI11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3311:31:3311:42|No assignment to wire ARREADY_SI12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3312:31:3312:42|No assignment to wire ARREADY_SI13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3313:31:3313:42|No assignment to wire ARREADY_SI14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3314:31:3314:42|No assignment to wire ARREADY_SI15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3315:31:3315:42|No assignment to wire ARREADY_SI16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3397:55:3397:61|No assignment to wire BID_SI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3398:30:3398:38|No assignment to wire BRESP_SI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3399:30:3399:39|No assignment to wire BVALID_SI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3400:55:3400:61|No assignment to wire RID_SI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3401:30:3401:38|No assignment to wire RDATA_SI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3402:30:3402:38|No assignment to wire RRESP_SI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3403:30:3403:38|No assignment to wire RLAST_SI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3404:30:3404:39|No assignment to wire RVALID_SI1
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3406:55:3406:61|No assignment to wire BID_SI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3407:30:3407:38|No assignment to wire BRESP_SI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3408:30:3408:39|No assignment to wire BVALID_SI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3409:55:3409:61|No assignment to wire RID_SI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3410:30:3410:38|No assignment to wire RDATA_SI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3411:30:3411:38|No assignment to wire RRESP_SI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3412:30:3412:38|No assignment to wire RLAST_SI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3413:30:3413:39|No assignment to wire RVALID_SI2
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3415:55:3415:61|No assignment to wire BID_SI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3416:30:3416:38|No assignment to wire BRESP_SI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3417:30:3417:39|No assignment to wire BVALID_SI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3418:55:3418:61|No assignment to wire RID_SI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3419:30:3419:38|No assignment to wire RDATA_SI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3420:30:3420:38|No assignment to wire RRESP_SI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3421:30:3421:38|No assignment to wire RLAST_SI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3422:30:3422:39|No assignment to wire RVALID_SI3
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3424:55:3424:61|No assignment to wire BID_SI4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3425:30:3425:38|No assignment to wire BRESP_SI4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3426:30:3426:39|No assignment to wire BVALID_SI4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3427:55:3427:61|No assignment to wire RID_SI4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3428:30:3428:38|No assignment to wire RDATA_SI4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3429:30:3429:38|No assignment to wire RRESP_SI4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3430:30:3430:38|No assignment to wire RLAST_SI4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3431:30:3431:39|No assignment to wire RVALID_SI4
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3433:55:3433:61|No assignment to wire BID_SI5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3434:30:3434:38|No assignment to wire BRESP_SI5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3435:30:3435:39|No assignment to wire BVALID_SI5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3436:55:3436:61|No assignment to wire RID_SI5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3437:30:3437:38|No assignment to wire RDATA_SI5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3438:30:3438:38|No assignment to wire RRESP_SI5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3439:30:3439:38|No assignment to wire RLAST_SI5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3440:30:3440:39|No assignment to wire RVALID_SI5
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3442:55:3442:61|No assignment to wire BID_SI6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3443:30:3443:38|No assignment to wire BRESP_SI6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3444:30:3444:39|No assignment to wire BVALID_SI6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3445:55:3445:61|No assignment to wire RID_SI6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3446:30:3446:38|No assignment to wire RDATA_SI6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3447:30:3447:38|No assignment to wire RRESP_SI6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3448:30:3448:38|No assignment to wire RLAST_SI6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3449:30:3449:39|No assignment to wire RVALID_SI6
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3451:55:3451:61|No assignment to wire BID_SI7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3452:30:3452:38|No assignment to wire BRESP_SI7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3453:30:3453:39|No assignment to wire BVALID_SI7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3454:55:3454:61|No assignment to wire RID_SI7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3455:30:3455:38|No assignment to wire RDATA_SI7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3456:30:3456:38|No assignment to wire RRESP_SI7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3457:30:3457:38|No assignment to wire RLAST_SI7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3458:30:3458:39|No assignment to wire RVALID_SI7
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3460:55:3460:61|No assignment to wire BID_SI8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3461:30:3461:38|No assignment to wire BRESP_SI8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3462:30:3462:39|No assignment to wire BVALID_SI8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3463:55:3463:61|No assignment to wire RID_SI8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3464:30:3464:38|No assignment to wire RDATA_SI8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3465:30:3465:38|No assignment to wire RRESP_SI8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3466:30:3466:38|No assignment to wire RLAST_SI8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3467:30:3467:39|No assignment to wire RVALID_SI8
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3469:55:3469:61|No assignment to wire BID_SI9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3470:30:3470:38|No assignment to wire BRESP_SI9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3471:30:3471:39|No assignment to wire BVALID_SI9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3472:55:3472:61|No assignment to wire RID_SI9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3473:30:3473:38|No assignment to wire RDATA_SI9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3474:30:3474:38|No assignment to wire RRESP_SI9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3475:30:3475:38|No assignment to wire RLAST_SI9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3476:30:3476:39|No assignment to wire RVALID_SI9
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3478:55:3478:62|No assignment to wire BID_SI10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3479:30:3479:39|No assignment to wire BRESP_SI10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3480:30:3480:40|No assignment to wire BVALID_SI10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3481:55:3481:62|No assignment to wire RID_SI10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3482:30:3482:39|No assignment to wire RDATA_SI10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3483:30:3483:39|No assignment to wire RRESP_SI10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3484:30:3484:39|No assignment to wire RLAST_SI10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3485:30:3485:40|No assignment to wire RVALID_SI10
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3487:55:3487:62|No assignment to wire BID_SI11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3488:30:3488:39|No assignment to wire BRESP_SI11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3489:30:3489:40|No assignment to wire BVALID_SI11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3490:55:3490:62|No assignment to wire RID_SI11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3491:30:3491:39|No assignment to wire RDATA_SI11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3492:30:3492:39|No assignment to wire RRESP_SI11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3493:30:3493:39|No assignment to wire RLAST_SI11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3494:30:3494:40|No assignment to wire RVALID_SI11
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3496:55:3496:62|No assignment to wire BID_SI12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3497:30:3497:39|No assignment to wire BRESP_SI12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3498:30:3498:40|No assignment to wire BVALID_SI12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3499:55:3499:62|No assignment to wire RID_SI12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3500:30:3500:39|No assignment to wire RDATA_SI12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3501:30:3501:39|No assignment to wire RRESP_SI12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3502:30:3502:39|No assignment to wire RLAST_SI12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3503:30:3503:40|No assignment to wire RVALID_SI12
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3505:55:3505:62|No assignment to wire BID_SI13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3506:30:3506:39|No assignment to wire BRESP_SI13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3507:30:3507:40|No assignment to wire BVALID_SI13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3508:55:3508:62|No assignment to wire RID_SI13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3509:30:3509:39|No assignment to wire RDATA_SI13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3510:30:3510:39|No assignment to wire RRESP_SI13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3511:30:3511:39|No assignment to wire RLAST_SI13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3512:30:3512:40|No assignment to wire RVALID_SI13
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3514:55:3514:62|No assignment to wire BID_SI14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3515:30:3515:39|No assignment to wire BRESP_SI14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3516:30:3516:40|No assignment to wire BVALID_SI14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3517:55:3517:62|No assignment to wire RID_SI14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3518:30:3518:39|No assignment to wire RDATA_SI14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3519:30:3519:39|No assignment to wire RRESP_SI14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3520:30:3520:39|No assignment to wire RLAST_SI14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3521:30:3521:40|No assignment to wire RVALID_SI14
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3523:55:3523:62|No assignment to wire BID_SI15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3524:30:3524:39|No assignment to wire BRESP_SI15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3525:30:3525:40|No assignment to wire BVALID_SI15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3526:55:3526:62|No assignment to wire RID_SI15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3527:30:3527:39|No assignment to wire RDATA_SI15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3528:30:3528:39|No assignment to wire RRESP_SI15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3529:30:3529:39|No assignment to wire RLAST_SI15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3530:30:3530:40|No assignment to wire RVALID_SI15
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3532:55:3532:62|No assignment to wire BID_SI16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3533:30:3533:39|No assignment to wire BRESP_SI16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3534:30:3534:40|No assignment to wire BVALID_SI16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3535:55:3535:62|No assignment to wire RID_SI16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3536:30:3536:39|No assignment to wire RDATA_SI16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3537:30:3537:39|No assignment to wire RRESP_SI16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3538:30:3538:39|No assignment to wire RLAST_SI16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3539:30:3539:40|No assignment to wire RVALID_SI16
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3542:55:3542:60|No assignment to wire BID_IM
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3543:30:3543:37|No assignment to wire BRESP_IM
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3544:30:3544:38|No assignment to wire BVALID_IM
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3545:55:3545:60|No assignment to wire RID_IM
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3546:30:3546:37|No assignment to wire RDATA_IM
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3547:30:3547:37|No assignment to wire RRESP_IM
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3548:30:3548:37|No assignment to wire RLAST_IM
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3549:30:3549:38|No assignment to wire RVALID_IM
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3552:30:3552:38|No assignment to wire m1_rd_end
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3553:30:3553:38|No assignment to wire m2_rd_end
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3554:30:3554:38|No assignment to wire m3_rd_end
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3556:30:3556:38|No assignment to wire m1_wr_end
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3557:30:3557:38|No assignment to wire m2_wr_end
@W: CG360 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3558:30:3558:38|No assignment to wire m3_wr_end
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning register count_ddr[13:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning register count_sdif3[12:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning register count_sdif2[12:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Pruning register count_sdif0[12:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif0_enable_q1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_q1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_q1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif0_enable_rcosc 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_rcosc 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_rcosc 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_ddr_enable_q1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_ddr_enable_rcosc 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning register count_sdif3_enable 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning register count_sdif2_enable 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Pruning register count_sdif0_enable 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning register count_ddr_enable 
@W: CL190 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning register release_ext_reset 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register EXT_RESET_OUT_int 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register sm2_state[2:0] 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_q1 
@W: CL169 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_clk_base 
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\PCIe_Demo\FABOSC_0\PCIe_Demo_FABOSC_0_OSC.v":15:7:15:24|*Output RCOSC_25_50MHZ_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\PCIe_Demo\FABOSC_0\PCIe_Demo_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\PCIe_Demo\FABOSC_0\PCIe_Demo_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\PCIe_Demo\FABOSC_0\PCIe_Demo_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\PCIe_Demo\FABOSC_0\PCIe_Demo_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\PCIe_Demo\FABOSC_0\PCIe_Demo_FABOSC_0_OSC.v":14:7:14:9|Input XTL is unused
@W: CL247 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v":36:24:36:29|Input port bit 31 of prdata[31:0] is unused
@W: CL246 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v":36:24:36:29|Input port bits 25 to 0 of prdata[31:0] are unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":59:20:59:34|Input SDIF0_SPLL_LOCK is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":72:20:72:34|Input SDIF2_SPLL_LOCK is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":76:20:76:34|Input SDIF3_SPLL_LOCK is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":90:20:90:29|Input SDIF0_PSEL is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":91:20:91:31|Input SDIF0_PWRITE is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":92:20:92:31|Input SDIF0_PRDATA is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":96:20:96:29|Input SDIF2_PSEL is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":97:20:97:31|Input SDIF2_PWRITE is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":98:20:98:31|Input SDIF2_PRDATA is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":99:20:99:29|Input SDIF3_PSEL is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":100:20:100:31|Input SDIF3_PWRITE is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":101:20:101:31|Input SDIF3_PRDATA is unused
@W: CL260 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2086:3:2086:8|Pruning register bit 3 of WID_MI[5:0] 
@W: CL189 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2086:3:2086:8|Register bit WID_MI[2] is always 0, optimizing ...
@W: CL260 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2086:3:2086:8|Pruning register bit 2 of WID_MI[2:0] 
@W: CL246 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":331:42:331:47|Input port bits 5 to 2 of BID_IM[5:0] are unused
@W: CL246 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":347:40:347:45|Input port bits 5 to 4 of RID_IM[5:0] are unused
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":790:32:790:40|*Input BVALID_SI to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":609:39:609:47|*Input BREADY_IS to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL279 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":589:9:589:14|Pruning register bits 3 to 2 of genblk1.MST_RDGNT_NUM[3:0] 
@W: CL189 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":589:9:589:14|Register bit genblk1.MST_RDGNT_NUM[1] is always 0, optimizing ...
@W: CL260 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":589:9:589:14|Pruning register bit 1 of genblk1.MST_RDGNT_NUM[1:0] 
@W: CL246 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":282:23:282:31|Input port bits 27 to 0 of ARADDR_M0[31:0] are unused
@W: CL246 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":285:23:285:31|Input port bits 27 to 0 of ARADDR_M1[31:0] are unused
@W: CL246 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":288:23:288:31|Input port bits 27 to 0 of ARADDR_M2[31:0] are unused
@W: CL246 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":291:23:291:31|Input port bits 27 to 0 of ARADDR_M3[31:0] are unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":319:40:319:47|Input ARID_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":320:23:320:32|Input ARADDR_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":321:33:321:41|Input ARLEN_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":322:33:322:42|Input ARSIZE_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":323:33:323:43|Input ARBURST_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":325:33:325:43|Input ARCACHE_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":326:33:326:42|Input ARPROT_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":327:33:327:43|Input ARVALID_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":332:40:332:47|Input ARID_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":333:23:333:32|Input ARADDR_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":334:33:334:41|Input ARLEN_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":335:33:335:42|Input ARSIZE_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":336:33:336:43|Input ARBURST_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":338:33:338:43|Input ARCACHE_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":339:33:339:42|Input ARPROT_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":340:33:340:43|Input ARVALID_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":345:40:345:47|Input ARID_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":346:23:346:32|Input ARADDR_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":347:33:347:41|Input ARLEN_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":348:33:348:42|Input ARSIZE_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":349:33:349:43|Input ARBURST_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":351:33:351:43|Input ARCACHE_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":352:33:352:42|Input ARPROT_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":353:33:353:43|Input ARVALID_MI3 is unused
@W: CL246 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":281:31:281:43|Input port bits 27 to 0 of AWADDR_IS_int[31:0] are unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":243:40:243:46|Input WID_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":244:33:244:41|Input WDATA_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":245:33:245:41|Input WSTRB_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":246:33:246:41|Input WLAST_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":247:33:247:42|Input WVALID_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":252:40:252:46|Input WID_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":253:33:253:41|Input WDATA_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":254:33:254:41|Input WSTRB_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":255:33:255:41|Input WLAST_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":256:33:256:42|Input WVALID_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":261:40:261:46|Input WID_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":262:33:262:41|Input WDATA_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":263:33:263:41|Input WSTRB_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":264:33:264:41|Input WLAST_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":265:33:265:42|Input WVALID_MI3 is unused
@W: CL279 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":553:9:553:14|Pruning register bits 3 to 2 of genblk1.MST_WRGNT_NUM[3:0] 
@W: CL189 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":553:9:553:14|Register bit genblk1.MST_WRGNT_NUM[1] is always 0, optimizing ...
@W: CL260 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":553:9:553:14|Pruning register bit 1 of genblk1.MST_WRGNT_NUM[1:0] 
@W: CL246 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":272:22:272:30|Input port bits 27 to 0 of AWADDR_M0[31:0] are unused
@W: CL246 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":275:22:275:30|Input port bits 27 to 0 of AWADDR_M1[31:0] are unused
@W: CL246 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":278:22:278:30|Input port bits 27 to 0 of AWADDR_M2[31:0] are unused
@W: CL246 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":281:22:281:30|Input port bits 27 to 0 of AWADDR_M3[31:0] are unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":287:15:287:23|Input BVALID_SI is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":288:15:288:23|Input BREADY_IS is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":312:40:312:47|Input AWID_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":313:23:313:32|Input AWADDR_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":314:33:314:41|Input AWLEN_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":315:33:315:42|Input AWSIZE_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":316:33:316:43|Input AWBURST_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":318:33:318:43|Input AWCACHE_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":319:33:319:42|Input AWPROT_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":320:33:320:43|Input AWVALID_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":325:40:325:47|Input AWID_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":326:23:326:32|Input AWADDR_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":327:33:327:41|Input AWLEN_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":328:33:328:42|Input AWSIZE_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":329:33:329:43|Input AWBURST_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":331:33:331:43|Input AWCACHE_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":332:33:332:42|Input AWPROT_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":333:33:333:43|Input AWVALID_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":338:40:338:47|Input AWID_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":339:23:339:32|Input AWADDR_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":340:33:340:41|Input AWLEN_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":341:33:341:42|Input AWSIZE_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":342:33:342:43|Input AWBURST_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":344:33:344:43|Input AWCACHE_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":345:33:345:42|Input AWPROT_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":346:33:346:43|Input AWVALID_MI3 is unused
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":3541:39:3541:49|*Input BID_IM3_int[3] to expression [buf] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1247:41:1247:47|*Output RID_IM1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1248:32:1248:40|*Output RDATA_IM1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1249:32:1249:40|*Output RRESP_IM1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1250:32:1250:40|*Output RLAST_IM1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1251:32:1251:41|*Output RVALID_IM1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1290:41:1290:47|*Output RID_IM2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1291:32:1291:40|*Output RDATA_IM2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1292:32:1292:40|*Output RRESP_IM2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1293:32:1293:40|*Output RLAST_IM2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1294:32:1294:41|*Output RVALID_IM2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1318:41:1318:47|*Output BID_IM3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1319:32:1319:40|*Output BRESP_IM3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1320:32:1320:41|*Output BVALID_IM3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1334:41:1334:47|*Output RID_IM3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1335:32:1335:40|*Output RDATA_IM3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1336:32:1336:40|*Output RRESP_IM3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1337:32:1337:40|*Output RLAST_IM3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1338:32:1338:41|*Output RVALID_IM3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2306:38:2306:45|*Output AWID_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2307:28:2307:37|*Output AWADDR_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2308:38:2308:46|*Output AWLEN_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2309:38:2309:47|*Output AWSIZE_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2310:38:2310:48|*Output AWBURST_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2311:38:2311:47|*Output AWLOCK_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2312:38:2312:48|*Output AWCACHE_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2313:38:2313:47|*Output AWPROT_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2314:38:2314:48|*Output AWVALID_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2642:38:2642:44|*Output WID_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2644:38:2644:46|*Output WDATA_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2645:38:2645:46|*Output WSTRB_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2646:38:2646:46|*Output WLAST_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2643:38:2643:47|*Output WVALID_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2850:38:2850:45|*Output ARID_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2851:28:2851:37|*Output ARADDR_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2852:38:2852:46|*Output ARLEN_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2853:38:2853:47|*Output ARSIZE_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2854:38:2854:48|*Output ARBURST_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2855:38:2855:47|*Output ARLOCK_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2856:38:2856:48|*Output ARCACHE_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2857:38:2857:47|*Output ARPROT_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2858:38:2858:48|*Output ARVALID_IS1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2316:38:2316:45|*Output AWID_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2317:28:2317:37|*Output AWADDR_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2318:38:2318:46|*Output AWLEN_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2319:38:2319:47|*Output AWSIZE_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2320:38:2320:48|*Output AWBURST_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2321:38:2321:47|*Output AWLOCK_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2322:38:2322:48|*Output AWCACHE_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2323:38:2323:47|*Output AWPROT_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2324:38:2324:48|*Output AWVALID_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2648:38:2648:44|*Output WID_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2650:38:2650:46|*Output WDATA_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2651:38:2651:46|*Output WSTRB_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2652:38:2652:46|*Output WLAST_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2649:38:2649:47|*Output WVALID_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2860:38:2860:45|*Output ARID_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2861:28:2861:37|*Output ARADDR_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2862:38:2862:46|*Output ARLEN_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2863:38:2863:47|*Output ARSIZE_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2864:38:2864:48|*Output ARBURST_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2865:38:2865:47|*Output ARLOCK_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2866:38:2866:48|*Output ARCACHE_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2867:38:2867:47|*Output ARPROT_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2868:38:2868:48|*Output ARVALID_IS2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2326:38:2326:45|*Output AWID_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2327:28:2327:37|*Output AWADDR_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2328:38:2328:46|*Output AWLEN_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2329:38:2329:47|*Output AWSIZE_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2330:38:2330:48|*Output AWBURST_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2331:38:2331:47|*Output AWLOCK_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2332:38:2332:48|*Output AWCACHE_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2333:38:2333:47|*Output AWPROT_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2334:38:2334:48|*Output AWVALID_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2654:38:2654:44|*Output WID_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2656:38:2656:46|*Output WDATA_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2657:38:2657:46|*Output WSTRB_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2658:38:2658:46|*Output WLAST_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2655:38:2655:47|*Output WVALID_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2870:38:2870:45|*Output ARID_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2871:28:2871:37|*Output ARADDR_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2872:38:2872:46|*Output ARLEN_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2873:38:2873:47|*Output ARSIZE_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2874:38:2874:48|*Output ARBURST_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2875:38:2875:47|*Output ARLOCK_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2876:38:2876:48|*Output ARCACHE_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2877:38:2877:47|*Output ARPROT_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2878:38:2878:48|*Output ARVALID_IS3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2336:38:2336:45|*Output AWID_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2337:28:2337:37|*Output AWADDR_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2338:38:2338:46|*Output AWLEN_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2339:38:2339:47|*Output AWSIZE_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2340:38:2340:48|*Output AWBURST_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2341:38:2341:47|*Output AWLOCK_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2342:38:2342:48|*Output AWCACHE_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2343:38:2343:47|*Output AWPROT_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2344:38:2344:48|*Output AWVALID_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2660:38:2660:44|*Output WID_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2662:38:2662:46|*Output WDATA_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2663:38:2663:46|*Output WSTRB_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2664:38:2664:46|*Output WLAST_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2661:38:2661:47|*Output WVALID_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2880:38:2880:45|*Output ARID_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2881:28:2881:37|*Output ARADDR_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2882:38:2882:46|*Output ARLEN_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2883:38:2883:47|*Output ARSIZE_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2884:38:2884:48|*Output ARBURST_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2885:38:2885:47|*Output ARLOCK_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2886:38:2886:48|*Output ARCACHE_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2887:38:2887:47|*Output ARPROT_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2888:38:2888:48|*Output ARVALID_IS4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2346:38:2346:45|*Output AWID_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2347:28:2347:37|*Output AWADDR_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2348:38:2348:46|*Output AWLEN_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2349:38:2349:47|*Output AWSIZE_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2350:38:2350:48|*Output AWBURST_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2351:38:2351:47|*Output AWLOCK_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2352:38:2352:48|*Output AWCACHE_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2353:38:2353:47|*Output AWPROT_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2354:38:2354:48|*Output AWVALID_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2666:38:2666:44|*Output WID_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2668:38:2668:46|*Output WDATA_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2669:38:2669:46|*Output WSTRB_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2670:38:2670:46|*Output WLAST_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2667:38:2667:47|*Output WVALID_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2890:38:2890:45|*Output ARID_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2891:28:2891:37|*Output ARADDR_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2892:38:2892:46|*Output ARLEN_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2893:38:2893:47|*Output ARSIZE_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2894:38:2894:48|*Output ARBURST_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2895:38:2895:47|*Output ARLOCK_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2896:38:2896:48|*Output ARCACHE_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2897:38:2897:47|*Output ARPROT_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2898:38:2898:48|*Output ARVALID_IS5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2356:38:2356:45|*Output AWID_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2357:28:2357:37|*Output AWADDR_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2358:38:2358:46|*Output AWLEN_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2359:38:2359:47|*Output AWSIZE_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2360:38:2360:48|*Output AWBURST_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2361:38:2361:47|*Output AWLOCK_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2362:38:2362:48|*Output AWCACHE_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2363:38:2363:47|*Output AWPROT_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2364:38:2364:48|*Output AWVALID_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2672:38:2672:44|*Output WID_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2674:38:2674:46|*Output WDATA_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2675:38:2675:46|*Output WSTRB_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2676:38:2676:46|*Output WLAST_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2673:38:2673:47|*Output WVALID_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2900:38:2900:45|*Output ARID_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2901:28:2901:37|*Output ARADDR_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2902:38:2902:46|*Output ARLEN_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2903:38:2903:47|*Output ARSIZE_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2904:38:2904:48|*Output ARBURST_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2905:38:2905:47|*Output ARLOCK_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2906:38:2906:48|*Output ARCACHE_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2907:38:2907:47|*Output ARPROT_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2908:38:2908:48|*Output ARVALID_IS6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2366:38:2366:45|*Output AWID_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2367:28:2367:37|*Output AWADDR_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2368:38:2368:46|*Output AWLEN_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2369:38:2369:47|*Output AWSIZE_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2370:38:2370:48|*Output AWBURST_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2371:38:2371:47|*Output AWLOCK_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2372:38:2372:48|*Output AWCACHE_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2373:38:2373:47|*Output AWPROT_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2374:38:2374:48|*Output AWVALID_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2678:38:2678:44|*Output WID_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2680:38:2680:46|*Output WDATA_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2681:38:2681:46|*Output WSTRB_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2682:38:2682:46|*Output WLAST_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2679:38:2679:47|*Output WVALID_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2910:38:2910:45|*Output ARID_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2911:28:2911:37|*Output ARADDR_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2912:38:2912:46|*Output ARLEN_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2913:38:2913:47|*Output ARSIZE_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2914:38:2914:48|*Output ARBURST_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2915:38:2915:47|*Output ARLOCK_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2916:38:2916:48|*Output ARCACHE_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2917:38:2917:47|*Output ARPROT_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2918:38:2918:48|*Output ARVALID_IS7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2376:38:2376:45|*Output AWID_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2377:28:2377:37|*Output AWADDR_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2378:38:2378:46|*Output AWLEN_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2379:38:2379:47|*Output AWSIZE_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2380:38:2380:48|*Output AWBURST_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2381:38:2381:47|*Output AWLOCK_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2382:38:2382:48|*Output AWCACHE_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2383:38:2383:47|*Output AWPROT_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2384:38:2384:48|*Output AWVALID_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2684:38:2684:44|*Output WID_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2686:38:2686:46|*Output WDATA_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2687:38:2687:46|*Output WSTRB_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2688:38:2688:46|*Output WLAST_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2685:38:2685:47|*Output WVALID_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2920:38:2920:45|*Output ARID_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2921:28:2921:37|*Output ARADDR_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2922:38:2922:46|*Output ARLEN_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2923:38:2923:47|*Output ARSIZE_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2924:38:2924:48|*Output ARBURST_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2925:38:2925:47|*Output ARLOCK_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2926:38:2926:48|*Output ARCACHE_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2927:38:2927:47|*Output ARPROT_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2928:38:2928:48|*Output ARVALID_IS8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2386:38:2386:45|*Output AWID_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2387:28:2387:37|*Output AWADDR_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2388:38:2388:46|*Output AWLEN_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2389:38:2389:47|*Output AWSIZE_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2390:38:2390:48|*Output AWBURST_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2391:38:2391:47|*Output AWLOCK_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2392:38:2392:48|*Output AWCACHE_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2393:38:2393:47|*Output AWPROT_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2394:38:2394:48|*Output AWVALID_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2690:38:2690:44|*Output WID_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2692:38:2692:46|*Output WDATA_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2693:38:2693:46|*Output WSTRB_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2694:38:2694:46|*Output WLAST_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2691:38:2691:47|*Output WVALID_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2930:38:2930:45|*Output ARID_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2931:28:2931:37|*Output ARADDR_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2932:38:2932:46|*Output ARLEN_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2933:38:2933:47|*Output ARSIZE_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2934:38:2934:48|*Output ARBURST_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2935:38:2935:47|*Output ARLOCK_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2936:38:2936:48|*Output ARCACHE_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2937:38:2937:47|*Output ARPROT_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2938:38:2938:48|*Output ARVALID_IS9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2396:38:2396:46|*Output AWID_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2397:28:2397:38|*Output AWADDR_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2398:38:2398:47|*Output AWLEN_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2399:38:2399:48|*Output AWSIZE_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2400:38:2400:49|*Output AWBURST_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2401:38:2401:48|*Output AWLOCK_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2402:38:2402:49|*Output AWCACHE_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2403:38:2403:48|*Output AWPROT_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2404:38:2404:49|*Output AWVALID_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2696:38:2696:45|*Output WID_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2698:38:2698:47|*Output WDATA_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2699:38:2699:47|*Output WSTRB_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2700:38:2700:47|*Output WLAST_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2697:38:2697:48|*Output WVALID_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2940:38:2940:46|*Output ARID_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2941:28:2941:38|*Output ARADDR_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2942:38:2942:47|*Output ARLEN_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2943:38:2943:48|*Output ARSIZE_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2944:38:2944:49|*Output ARBURST_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2945:38:2945:48|*Output ARLOCK_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2946:38:2946:49|*Output ARCACHE_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2947:38:2947:48|*Output ARPROT_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2948:38:2948:49|*Output ARVALID_IS10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2406:38:2406:46|*Output AWID_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2407:28:2407:38|*Output AWADDR_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2408:38:2408:47|*Output AWLEN_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2409:38:2409:48|*Output AWSIZE_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2410:38:2410:49|*Output AWBURST_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2411:38:2411:48|*Output AWLOCK_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2412:38:2412:49|*Output AWCACHE_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2413:38:2413:48|*Output AWPROT_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2414:38:2414:49|*Output AWVALID_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2702:38:2702:45|*Output WID_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2704:38:2704:47|*Output WDATA_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2705:38:2705:47|*Output WSTRB_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2706:38:2706:47|*Output WLAST_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2703:38:2703:48|*Output WVALID_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2950:38:2950:46|*Output ARID_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2951:28:2951:38|*Output ARADDR_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2952:38:2952:47|*Output ARLEN_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2953:38:2953:48|*Output ARSIZE_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2954:38:2954:49|*Output ARBURST_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2955:38:2955:48|*Output ARLOCK_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2956:38:2956:49|*Output ARCACHE_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2957:38:2957:48|*Output ARPROT_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2958:38:2958:49|*Output ARVALID_IS11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2416:38:2416:46|*Output AWID_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2417:28:2417:38|*Output AWADDR_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2418:38:2418:47|*Output AWLEN_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2419:38:2419:48|*Output AWSIZE_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2420:38:2420:49|*Output AWBURST_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2421:38:2421:48|*Output AWLOCK_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2422:38:2422:49|*Output AWCACHE_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2423:38:2423:48|*Output AWPROT_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2424:38:2424:49|*Output AWVALID_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2708:38:2708:45|*Output WID_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2710:38:2710:47|*Output WDATA_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2711:38:2711:47|*Output WSTRB_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2712:38:2712:47|*Output WLAST_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2709:38:2709:48|*Output WVALID_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2960:38:2960:46|*Output ARID_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2961:28:2961:38|*Output ARADDR_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2962:38:2962:47|*Output ARLEN_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2963:38:2963:48|*Output ARSIZE_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2964:38:2964:49|*Output ARBURST_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2965:38:2965:48|*Output ARLOCK_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2966:38:2966:49|*Output ARCACHE_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2967:38:2967:48|*Output ARPROT_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2968:38:2968:49|*Output ARVALID_IS12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2426:38:2426:46|*Output AWID_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2427:28:2427:38|*Output AWADDR_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2428:38:2428:47|*Output AWLEN_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2429:38:2429:48|*Output AWSIZE_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2430:38:2430:49|*Output AWBURST_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2431:38:2431:48|*Output AWLOCK_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2432:38:2432:49|*Output AWCACHE_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2433:38:2433:48|*Output AWPROT_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2434:38:2434:49|*Output AWVALID_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2714:38:2714:45|*Output WID_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2716:38:2716:47|*Output WDATA_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2717:38:2717:47|*Output WSTRB_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2718:38:2718:47|*Output WLAST_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2715:38:2715:48|*Output WVALID_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2970:38:2970:46|*Output ARID_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2971:28:2971:38|*Output ARADDR_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2972:38:2972:47|*Output ARLEN_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2973:38:2973:48|*Output ARSIZE_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2974:38:2974:49|*Output ARBURST_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2975:38:2975:48|*Output ARLOCK_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2976:38:2976:49|*Output ARCACHE_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2977:38:2977:48|*Output ARPROT_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2978:38:2978:49|*Output ARVALID_IS13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2436:38:2436:46|*Output AWID_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2437:28:2437:38|*Output AWADDR_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2438:38:2438:47|*Output AWLEN_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2439:38:2439:48|*Output AWSIZE_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2440:38:2440:49|*Output AWBURST_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2441:38:2441:48|*Output AWLOCK_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2442:38:2442:49|*Output AWCACHE_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2443:38:2443:48|*Output AWPROT_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2444:38:2444:49|*Output AWVALID_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2720:38:2720:45|*Output WID_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2722:38:2722:47|*Output WDATA_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2723:38:2723:47|*Output WSTRB_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2724:38:2724:47|*Output WLAST_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2721:38:2721:48|*Output WVALID_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2980:38:2980:46|*Output ARID_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2981:28:2981:38|*Output ARADDR_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2982:38:2982:47|*Output ARLEN_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2983:38:2983:48|*Output ARSIZE_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2984:38:2984:49|*Output ARBURST_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2985:38:2985:48|*Output ARLOCK_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2986:38:2986:49|*Output ARCACHE_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2987:38:2987:48|*Output ARPROT_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2988:38:2988:49|*Output ARVALID_IS14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2446:38:2446:46|*Output AWID_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2447:28:2447:38|*Output AWADDR_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2448:38:2448:47|*Output AWLEN_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2449:38:2449:48|*Output AWSIZE_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2450:38:2450:49|*Output AWBURST_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2451:38:2451:48|*Output AWLOCK_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2452:38:2452:49|*Output AWCACHE_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2453:38:2453:48|*Output AWPROT_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2454:38:2454:49|*Output AWVALID_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2726:38:2726:45|*Output WID_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2728:38:2728:47|*Output WDATA_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2729:38:2729:47|*Output WSTRB_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2730:38:2730:47|*Output WLAST_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2727:38:2727:48|*Output WVALID_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2990:38:2990:46|*Output ARID_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2991:28:2991:38|*Output ARADDR_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2992:38:2992:47|*Output ARLEN_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2993:38:2993:48|*Output ARSIZE_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2994:38:2994:49|*Output ARBURST_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2995:38:2995:48|*Output ARLOCK_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2996:38:2996:49|*Output ARCACHE_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2997:38:2997:48|*Output ARPROT_IS15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2998:38:2998:49|*Output ARVALID_IS15 has undriven bits -- simulation mismatch possible.
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1234:32:1234:41|Input BREADY_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1252:32:1252:41|Input RREADY_MI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1277:32:1277:41|Input BREADY_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1295:32:1295:41|Input RREADY_MI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1321:32:1321:41|Input BREADY_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1339:32:1339:41|Input RREADY_MI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1396:32:1396:42|Input AWREADY_SI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1403:32:1403:41|Input WREADY_SI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1419:32:1419:42|Input ARREADY_SI1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1439:32:1439:42|Input AWREADY_SI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1446:32:1446:41|Input WREADY_SI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1462:32:1462:42|Input ARREADY_SI2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1482:32:1482:42|Input AWREADY_SI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1489:32:1489:41|Input WREADY_SI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1505:32:1505:42|Input ARREADY_SI3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1525:32:1525:42|Input AWREADY_SI4 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1532:32:1532:41|Input WREADY_SI4 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1548:32:1548:42|Input ARREADY_SI4 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1568:32:1568:42|Input AWREADY_SI5 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1575:32:1575:41|Input WREADY_SI5 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1591:32:1591:42|Input ARREADY_SI5 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1611:32:1611:42|Input AWREADY_SI6 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1618:32:1618:41|Input WREADY_SI6 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1634:32:1634:42|Input ARREADY_SI6 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1654:32:1654:42|Input AWREADY_SI7 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1661:32:1661:41|Input WREADY_SI7 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1677:32:1677:42|Input ARREADY_SI7 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1697:32:1697:42|Input AWREADY_SI8 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1704:32:1704:41|Input WREADY_SI8 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1720:32:1720:42|Input ARREADY_SI8 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1740:32:1740:42|Input AWREADY_SI9 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1747:32:1747:41|Input WREADY_SI9 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1763:32:1763:42|Input ARREADY_SI9 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1783:32:1783:43|Input AWREADY_SI10 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1790:32:1790:42|Input WREADY_SI10 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1806:32:1806:43|Input ARREADY_SI10 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1826:32:1826:43|Input AWREADY_SI11 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1833:32:1833:42|Input WREADY_SI11 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1849:32:1849:43|Input ARREADY_SI11 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1869:32:1869:43|Input AWREADY_SI12 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1876:32:1876:42|Input WREADY_SI12 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1892:32:1892:43|Input ARREADY_SI12 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1912:32:1912:43|Input AWREADY_SI13 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1919:32:1919:42|Input WREADY_SI13 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1935:32:1935:43|Input ARREADY_SI13 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1955:32:1955:43|Input AWREADY_SI14 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1962:32:1962:42|Input WREADY_SI14 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1978:32:1978:43|Input ARREADY_SI14 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":1998:32:1998:43|Input AWREADY_SI15 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2005:32:2005:42|Input WREADY_SI15 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2021:32:2021:43|Input ARREADY_SI15 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2041:32:2041:43|Input AWREADY_SI16 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2048:32:2048:42|Input WREADY_SI16 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":2064:32:2064:43|Input ARREADY_SI16 is unused
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2610:39:2610:46|*Input AWID_MI1[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2611:22:2611:31|*Input AWADDR_MI1[31:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2612:32:2612:40|*Input AWLEN_MI1[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2613:32:2613:41|*Input AWSIZE_MI1[2:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2614:32:2614:42|*Input AWBURST_MI1[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2615:32:2615:41|*Input AWLOCK_MI1[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2616:32:2616:42|*Input AWCACHE_MI1[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2617:32:2617:41|*Input AWPROT_MI1[2:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2618:32:2618:42|*Input AWVALID_MI1 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2620:39:2620:45|*Input WID_MI1[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2621:32:2621:40|*Input WDATA_MI1[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2622:32:2622:40|*Input WSTRB_MI1[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2623:32:2623:40|*Input WLAST_MI1 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2624:32:2624:41|*Input WVALID_MI1 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2010:33:2010:42|*Input BREADY_MI1 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2626:39:2626:46|*Input ARID_MI1[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2627:21:2627:30|*Input ARADDR_MI1[31:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2628:31:2628:39|*Input ARLEN_MI1[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2629:31:2629:40|*Input ARSIZE_MI1[2:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2630:31:2630:41|*Input ARBURST_MI1[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2631:31:2631:40|*Input ARLOCK_MI1[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2632:31:2632:41|*Input ARCACHE_MI1[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2633:31:2633:40|*Input ARPROT_MI1[2:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2634:31:2634:41|*Input ARVALID_MI1 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2014:33:2014:42|*Input RREADY_MI1 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2647:39:2647:46|*Input AWID_MI2[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2648:22:2648:31|*Input AWADDR_MI2[31:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2649:32:2649:40|*Input AWLEN_MI2[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2650:32:2650:41|*Input AWSIZE_MI2[2:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2651:32:2651:42|*Input AWBURST_MI2[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2652:32:2652:41|*Input AWLOCK_MI2[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2653:32:2653:42|*Input AWCACHE_MI2[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2654:32:2654:41|*Input AWPROT_MI2[2:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2655:32:2655:42|*Input AWVALID_MI2 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2657:39:2657:45|*Input WID_MI2[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2658:32:2658:40|*Input WDATA_MI2[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2659:32:2659:40|*Input WSTRB_MI2[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2660:32:2660:40|*Input WLAST_MI2 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2661:32:2661:41|*Input WVALID_MI2 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2011:33:2011:42|*Input BREADY_MI2 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2663:39:2663:46|*Input ARID_MI2[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2664:21:2664:30|*Input ARADDR_MI2[31:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2665:31:2665:39|*Input ARLEN_MI2[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2666:31:2666:40|*Input ARSIZE_MI2[2:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2667:31:2667:41|*Input ARBURST_MI2[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2668:31:2668:40|*Input ARLOCK_MI2[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2669:31:2669:41|*Input ARCACHE_MI2[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2670:31:2670:40|*Input ARPROT_MI2[2:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2671:31:2671:41|*Input ARVALID_MI2 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2015:33:2015:42|*Input RREADY_MI2 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2684:39:2684:46|*Input AWID_MI3[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2685:22:2685:31|*Input AWADDR_MI3[31:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2686:32:2686:40|*Input AWLEN_MI3[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2687:32:2687:41|*Input AWSIZE_MI3[2:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2688:32:2688:42|*Input AWBURST_MI3[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2689:32:2689:41|*Input AWLOCK_MI3[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2690:32:2690:42|*Input AWCACHE_MI3[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2691:32:2691:41|*Input AWPROT_MI3[2:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2692:32:2692:42|*Input AWVALID_MI3 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2694:39:2694:45|*Input WID_MI3[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2695:32:2695:40|*Input WDATA_MI3[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2696:32:2696:40|*Input WSTRB_MI3[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2697:32:2697:40|*Input WLAST_MI3 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2698:32:2698:41|*Input WVALID_MI3 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2012:33:2012:42|*Input BREADY_MI3 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2700:39:2700:46|*Input ARID_MI3[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2701:21:2701:30|*Input ARADDR_MI3[31:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2702:31:2702:39|*Input ARLEN_MI3[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2703:31:2703:40|*Input ARSIZE_MI3[2:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2704:31:2704:41|*Input ARBURST_MI3[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2705:31:2705:40|*Input ARLOCK_MI3[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2706:31:2706:41|*Input ARCACHE_MI3[3:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2707:31:2707:40|*Input ARPROT_MI3[2:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2708:31:2708:41|*Input ARVALID_MI3 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":2016:33:2016:42|*Input RREADY_MI3 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3264:31:3264:41|*Input AWREADY_SI1 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3282:31:3282:40|*Input WREADY_SI1 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3397:55:3397:61|*Input BID_SI1[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3398:30:3398:38|*Input BRESP_SI1[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3399:30:3399:39|*Input BVALID_SI1 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3300:31:3300:41|*Input ARREADY_SI1 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3400:55:3400:61|*Input RID_SI1[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3401:30:3401:38|*Input RDATA_SI1[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3402:30:3402:38|*Input RRESP_SI1[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3403:30:3403:38|*Input RLAST_SI1 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3404:30:3404:39|*Input RVALID_SI1 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3265:31:3265:41|*Input AWREADY_SI2 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3283:31:3283:40|*Input WREADY_SI2 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3406:55:3406:61|*Input BID_SI2[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3407:30:3407:38|*Input BRESP_SI2[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3408:30:3408:39|*Input BVALID_SI2 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3301:31:3301:41|*Input ARREADY_SI2 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3409:55:3409:61|*Input RID_SI2[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3410:30:3410:38|*Input RDATA_SI2[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3411:30:3411:38|*Input RRESP_SI2[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3412:30:3412:38|*Input RLAST_SI2 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3413:30:3413:39|*Input RVALID_SI2 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3266:31:3266:41|*Input AWREADY_SI3 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3284:31:3284:40|*Input WREADY_SI3 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3415:55:3415:61|*Input BID_SI3[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3416:30:3416:38|*Input BRESP_SI3[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3417:30:3417:39|*Input BVALID_SI3 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3302:31:3302:41|*Input ARREADY_SI3 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3418:55:3418:61|*Input RID_SI3[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3419:30:3419:38|*Input RDATA_SI3[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3420:30:3420:38|*Input RRESP_SI3[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3421:30:3421:38|*Input RLAST_SI3 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3422:30:3422:39|*Input RVALID_SI3 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3267:31:3267:41|*Input AWREADY_SI4 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3285:31:3285:40|*Input WREADY_SI4 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3424:55:3424:61|*Input BID_SI4[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3425:30:3425:38|*Input BRESP_SI4[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3426:30:3426:39|*Input BVALID_SI4 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3303:31:3303:41|*Input ARREADY_SI4 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3427:55:3427:61|*Input RID_SI4[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3428:30:3428:38|*Input RDATA_SI4[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3429:30:3429:38|*Input RRESP_SI4[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3430:30:3430:38|*Input RLAST_SI4 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3431:30:3431:39|*Input RVALID_SI4 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3268:31:3268:41|*Input AWREADY_SI5 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3286:31:3286:40|*Input WREADY_SI5 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3433:55:3433:61|*Input BID_SI5[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3434:30:3434:38|*Input BRESP_SI5[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3435:30:3435:39|*Input BVALID_SI5 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3304:31:3304:41|*Input ARREADY_SI5 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3436:55:3436:61|*Input RID_SI5[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3437:30:3437:38|*Input RDATA_SI5[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3438:30:3438:38|*Input RRESP_SI5[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3439:30:3439:38|*Input RLAST_SI5 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3440:30:3440:39|*Input RVALID_SI5 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3269:31:3269:41|*Input AWREADY_SI6 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3287:31:3287:40|*Input WREADY_SI6 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3442:55:3442:61|*Input BID_SI6[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3443:30:3443:38|*Input BRESP_SI6[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3444:30:3444:39|*Input BVALID_SI6 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3305:31:3305:41|*Input ARREADY_SI6 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3445:55:3445:61|*Input RID_SI6[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3446:30:3446:38|*Input RDATA_SI6[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3447:30:3447:38|*Input RRESP_SI6[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3448:30:3448:38|*Input RLAST_SI6 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3449:30:3449:39|*Input RVALID_SI6 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3270:31:3270:41|*Input AWREADY_SI7 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3288:31:3288:40|*Input WREADY_SI7 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3451:55:3451:61|*Input BID_SI7[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3452:30:3452:38|*Input BRESP_SI7[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3453:30:3453:39|*Input BVALID_SI7 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3306:31:3306:41|*Input ARREADY_SI7 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3454:55:3454:61|*Input RID_SI7[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3455:30:3455:38|*Input RDATA_SI7[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3456:30:3456:38|*Input RRESP_SI7[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3457:30:3457:38|*Input RLAST_SI7 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3458:30:3458:39|*Input RVALID_SI7 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3271:31:3271:41|*Input AWREADY_SI8 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3289:31:3289:40|*Input WREADY_SI8 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3460:55:3460:61|*Input BID_SI8[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3461:30:3461:38|*Input BRESP_SI8[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3462:30:3462:39|*Input BVALID_SI8 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3307:31:3307:41|*Input ARREADY_SI8 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3463:55:3463:61|*Input RID_SI8[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3464:30:3464:38|*Input RDATA_SI8[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3465:30:3465:38|*Input RRESP_SI8[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3466:30:3466:38|*Input RLAST_SI8 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3467:30:3467:39|*Input RVALID_SI8 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3272:31:3272:41|*Input AWREADY_SI9 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3290:31:3290:40|*Input WREADY_SI9 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3469:55:3469:61|*Input BID_SI9[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3470:30:3470:38|*Input BRESP_SI9[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3471:30:3471:39|*Input BVALID_SI9 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3308:31:3308:41|*Input ARREADY_SI9 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3472:55:3472:61|*Input RID_SI9[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3473:30:3473:38|*Input RDATA_SI9[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3474:30:3474:38|*Input RRESP_SI9[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3475:30:3475:38|*Input RLAST_SI9 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3476:30:3476:39|*Input RVALID_SI9 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3273:31:3273:42|*Input AWREADY_SI10 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3291:31:3291:41|*Input WREADY_SI10 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3478:55:3478:62|*Input BID_SI10[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3479:30:3479:39|*Input BRESP_SI10[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3480:30:3480:40|*Input BVALID_SI10 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3309:31:3309:42|*Input ARREADY_SI10 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3481:55:3481:62|*Input RID_SI10[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3482:30:3482:39|*Input RDATA_SI10[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3483:30:3483:39|*Input RRESP_SI10[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3484:30:3484:39|*Input RLAST_SI10 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3485:30:3485:40|*Input RVALID_SI10 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3274:31:3274:42|*Input AWREADY_SI11 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3292:31:3292:41|*Input WREADY_SI11 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3487:55:3487:62|*Input BID_SI11[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3488:30:3488:39|*Input BRESP_SI11[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3489:30:3489:40|*Input BVALID_SI11 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3310:31:3310:42|*Input ARREADY_SI11 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3490:55:3490:62|*Input RID_SI11[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3491:30:3491:39|*Input RDATA_SI11[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3492:30:3492:39|*Input RRESP_SI11[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3493:30:3493:39|*Input RLAST_SI11 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3494:30:3494:40|*Input RVALID_SI11 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3275:31:3275:42|*Input AWREADY_SI12 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3293:31:3293:41|*Input WREADY_SI12 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3496:55:3496:62|*Input BID_SI12[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3497:30:3497:39|*Input BRESP_SI12[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3498:30:3498:40|*Input BVALID_SI12 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3311:31:3311:42|*Input ARREADY_SI12 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3499:55:3499:62|*Input RID_SI12[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3500:30:3500:39|*Input RDATA_SI12[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3501:30:3501:39|*Input RRESP_SI12[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3502:30:3502:39|*Input RLAST_SI12 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3503:30:3503:40|*Input RVALID_SI12 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3276:31:3276:42|*Input AWREADY_SI13 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3294:31:3294:41|*Input WREADY_SI13 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3505:55:3505:62|*Input BID_SI13[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3506:30:3506:39|*Input BRESP_SI13[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3507:30:3507:40|*Input BVALID_SI13 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3312:31:3312:42|*Input ARREADY_SI13 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3508:55:3508:62|*Input RID_SI13[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3509:30:3509:39|*Input RDATA_SI13[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3510:30:3510:39|*Input RRESP_SI13[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3511:30:3511:39|*Input RLAST_SI13 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3512:30:3512:40|*Input RVALID_SI13 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3277:31:3277:42|*Input AWREADY_SI14 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3295:31:3295:41|*Input WREADY_SI14 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3514:55:3514:62|*Input BID_SI14[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3515:30:3515:39|*Input BRESP_SI14[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3516:30:3516:40|*Input BVALID_SI14 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3313:31:3313:42|*Input ARREADY_SI14 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3517:55:3517:62|*Input RID_SI14[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3518:30:3518:39|*Input RDATA_SI14[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3519:30:3519:39|*Input RRESP_SI14[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3520:30:3520:39|*Input RLAST_SI14 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3521:30:3521:40|*Input RVALID_SI14 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3278:31:3278:42|*Input AWREADY_SI15 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3296:31:3296:41|*Input WREADY_SI15 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3523:55:3523:62|*Input BID_SI15[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3524:30:3524:39|*Input BRESP_SI15[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3525:30:3525:40|*Input BVALID_SI15 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3314:31:3314:42|*Input ARREADY_SI15 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3526:55:3526:62|*Input RID_SI15[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3527:30:3527:39|*Input RDATA_SI15[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3528:30:3528:39|*Input RRESP_SI15[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3529:30:3529:39|*Input RLAST_SI15 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3530:30:3530:40|*Input RVALID_SI15 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3279:31:3279:42|*Input AWREADY_SI16 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3297:31:3297:41|*Input WREADY_SI16 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3532:55:3532:62|*Input BID_SI16[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3533:30:3533:39|*Input BRESP_SI16[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3534:30:3534:40|*Input BVALID_SI16 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3315:31:3315:42|*Input ARREADY_SI16 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3535:55:3535:62|*Input RID_SI16[5:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3536:30:3536:39|*Input RDATA_SI16[63:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3537:30:3537:39|*Input RRESP_SI16[1:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3538:30:3538:39|*Input RLAST_SI16 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3539:30:3539:40|*Input RVALID_SI16 to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3552:30:3552:38|*Input m1_rd_end to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3553:30:3553:38|*Input m2_rd_end to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3554:30:3554:38|*Input m3_rd_end to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3556:30:3556:38|*Input m1_wr_end to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3557:30:3557:38|*Input m2_wr_end to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL156 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":3558:30:3558:38|*Input m3_wr_end to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1144:33:1144:42|*Output AWREADY_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1151:33:1151:41|*Output WREADY_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1153:33:1153:38|*Output BID_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1154:33:1154:40|*Output BRESP_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1155:33:1155:41|*Output BVALID_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1167:33:1167:42|*Output ARREADY_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1169:33:1169:38|*Output RID_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1170:33:1170:40|*Output RDATA_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1171:33:1171:40|*Output RRESP_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1172:33:1172:40|*Output RLAST_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1173:33:1173:41|*Output RVALID_M1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1187:33:1187:42|*Output AWREADY_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1194:33:1194:41|*Output WREADY_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1196:33:1196:38|*Output BID_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1197:33:1197:40|*Output BRESP_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1198:33:1198:41|*Output BVALID_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1210:33:1210:42|*Output ARREADY_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1212:33:1212:38|*Output RID_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1213:33:1213:40|*Output RDATA_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1214:33:1214:40|*Output RRESP_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1215:33:1215:40|*Output RLAST_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1216:33:1216:41|*Output RVALID_M2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1230:33:1230:42|*Output AWREADY_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1237:33:1237:41|*Output WREADY_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1239:33:1239:38|*Output BID_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1240:33:1240:40|*Output BRESP_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1241:33:1241:41|*Output BVALID_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1253:33:1253:42|*Output ARREADY_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1255:33:1255:38|*Output RID_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1256:33:1256:40|*Output RDATA_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1257:33:1257:40|*Output RRESP_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1258:33:1258:40|*Output RLAST_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1259:33:1259:41|*Output RVALID_M3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1307:58:1307:64|*Output AWID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1308:23:1308:31|*Output AWADDR_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1309:33:1309:40|*Output AWLEN_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1310:33:1310:41|*Output AWSIZE_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1311:33:1311:42|*Output AWBURST_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1312:33:1312:41|*Output AWLOCK_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1313:33:1313:42|*Output AWCACHE_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1314:33:1314:41|*Output AWPROT_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1315:33:1315:42|*Output AWVALID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1318:58:1318:63|*Output WID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1319:33:1319:40|*Output WDATA_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1320:33:1320:40|*Output WSTRB_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1321:33:1321:40|*Output WLAST_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1322:33:1322:41|*Output WVALID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1328:33:1328:41|*Output BREADY_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1330:58:1330:64|*Output ARID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1331:23:1331:31|*Output ARADDR_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1332:33:1332:40|*Output ARLEN_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|*Output ARSIZE_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1334:33:1334:42|*Output ARBURST_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1335:33:1335:41|*Output ARLOCK_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1336:33:1336:42|*Output ARCACHE_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1337:33:1337:41|*Output ARPROT_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1338:33:1338:42|*Output ARVALID_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1346:33:1346:41|*Output RREADY_S1 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1350:58:1350:64|*Output AWID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1351:23:1351:31|*Output AWADDR_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1352:33:1352:40|*Output AWLEN_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1353:33:1353:41|*Output AWSIZE_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1354:33:1354:42|*Output AWBURST_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1355:33:1355:41|*Output AWLOCK_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1356:33:1356:42|*Output AWCACHE_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1357:33:1357:41|*Output AWPROT_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1358:33:1358:42|*Output AWVALID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1361:58:1361:63|*Output WID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1362:33:1362:40|*Output WDATA_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1363:33:1363:40|*Output WSTRB_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1364:33:1364:40|*Output WLAST_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1365:33:1365:41|*Output WVALID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1371:33:1371:41|*Output BREADY_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1373:58:1373:64|*Output ARID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1374:23:1374:31|*Output ARADDR_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1375:33:1375:40|*Output ARLEN_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|*Output ARSIZE_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1377:33:1377:42|*Output ARBURST_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1378:33:1378:41|*Output ARLOCK_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1379:33:1379:42|*Output ARCACHE_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1380:33:1380:41|*Output ARPROT_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1381:33:1381:42|*Output ARVALID_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1389:33:1389:41|*Output RREADY_S2 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1393:58:1393:64|*Output AWID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1394:23:1394:31|*Output AWADDR_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1395:33:1395:40|*Output AWLEN_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1396:33:1396:41|*Output AWSIZE_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1397:33:1397:42|*Output AWBURST_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1398:33:1398:41|*Output AWLOCK_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1399:33:1399:42|*Output AWCACHE_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1400:33:1400:41|*Output AWPROT_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1401:33:1401:42|*Output AWVALID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1404:58:1404:63|*Output WID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1405:33:1405:40|*Output WDATA_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1406:33:1406:40|*Output WSTRB_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1407:33:1407:40|*Output WLAST_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1408:33:1408:41|*Output WVALID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1414:33:1414:41|*Output BREADY_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1416:58:1416:64|*Output ARID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1417:23:1417:31|*Output ARADDR_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1418:33:1418:40|*Output ARLEN_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|*Output ARSIZE_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1420:33:1420:42|*Output ARBURST_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1421:33:1421:41|*Output ARLOCK_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1422:33:1422:42|*Output ARCACHE_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1423:33:1423:41|*Output ARPROT_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1424:33:1424:42|*Output ARVALID_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1432:33:1432:41|*Output RREADY_S3 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1436:58:1436:64|*Output AWID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1437:23:1437:31|*Output AWADDR_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1438:33:1438:40|*Output AWLEN_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1439:33:1439:41|*Output AWSIZE_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1440:33:1440:42|*Output AWBURST_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1441:33:1441:41|*Output AWLOCK_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1442:33:1442:42|*Output AWCACHE_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1443:33:1443:41|*Output AWPROT_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1444:33:1444:42|*Output AWVALID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1447:58:1447:63|*Output WID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1448:33:1448:40|*Output WDATA_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1449:33:1449:40|*Output WSTRB_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1450:33:1450:40|*Output WLAST_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1451:33:1451:41|*Output WVALID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1457:33:1457:41|*Output BREADY_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1459:58:1459:64|*Output ARID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1460:23:1460:31|*Output ARADDR_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1461:33:1461:40|*Output ARLEN_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|*Output ARSIZE_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1463:33:1463:42|*Output ARBURST_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1464:33:1464:41|*Output ARLOCK_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1465:33:1465:42|*Output ARCACHE_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1466:33:1466:41|*Output ARPROT_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1467:33:1467:42|*Output ARVALID_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1475:33:1475:41|*Output RREADY_S4 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1479:58:1479:64|*Output AWID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1480:23:1480:31|*Output AWADDR_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1481:33:1481:40|*Output AWLEN_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1482:33:1482:41|*Output AWSIZE_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1483:33:1483:42|*Output AWBURST_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1484:33:1484:41|*Output AWLOCK_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1485:33:1485:42|*Output AWCACHE_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1486:33:1486:41|*Output AWPROT_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1487:33:1487:42|*Output AWVALID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1490:58:1490:63|*Output WID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1491:33:1491:40|*Output WDATA_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1492:33:1492:40|*Output WSTRB_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1493:33:1493:40|*Output WLAST_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1494:33:1494:41|*Output WVALID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1500:33:1500:41|*Output BREADY_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1502:58:1502:64|*Output ARID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1503:23:1503:31|*Output ARADDR_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1504:33:1504:40|*Output ARLEN_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|*Output ARSIZE_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1506:33:1506:42|*Output ARBURST_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1507:33:1507:41|*Output ARLOCK_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1508:33:1508:42|*Output ARCACHE_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1509:33:1509:41|*Output ARPROT_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1510:33:1510:42|*Output ARVALID_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1518:33:1518:41|*Output RREADY_S5 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1522:58:1522:64|*Output AWID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1523:23:1523:31|*Output AWADDR_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1524:33:1524:40|*Output AWLEN_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1525:33:1525:41|*Output AWSIZE_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1526:33:1526:42|*Output AWBURST_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1527:33:1527:41|*Output AWLOCK_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1528:33:1528:42|*Output AWCACHE_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1529:33:1529:41|*Output AWPROT_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1530:33:1530:42|*Output AWVALID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1533:58:1533:63|*Output WID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1534:33:1534:40|*Output WDATA_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1535:33:1535:40|*Output WSTRB_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1536:33:1536:40|*Output WLAST_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1537:33:1537:41|*Output WVALID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1543:33:1543:41|*Output BREADY_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1545:58:1545:64|*Output ARID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1546:23:1546:31|*Output ARADDR_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1547:33:1547:40|*Output ARLEN_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1548:33:1548:41|*Output ARSIZE_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1549:33:1549:42|*Output ARBURST_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1550:33:1550:41|*Output ARLOCK_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1551:33:1551:42|*Output ARCACHE_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1552:33:1552:41|*Output ARPROT_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1553:33:1553:42|*Output ARVALID_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1561:33:1561:41|*Output RREADY_S6 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1565:58:1565:64|*Output AWID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1566:23:1566:31|*Output AWADDR_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1567:33:1567:40|*Output AWLEN_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1568:33:1568:41|*Output AWSIZE_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1569:33:1569:42|*Output AWBURST_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1570:33:1570:41|*Output AWLOCK_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1571:33:1571:42|*Output AWCACHE_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1572:33:1572:41|*Output AWPROT_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1573:33:1573:42|*Output AWVALID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1576:58:1576:63|*Output WID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1577:33:1577:40|*Output WDATA_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1578:33:1578:40|*Output WSTRB_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1579:33:1579:40|*Output WLAST_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1580:33:1580:41|*Output WVALID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1586:33:1586:41|*Output BREADY_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1588:58:1588:64|*Output ARID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1589:23:1589:31|*Output ARADDR_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1590:33:1590:40|*Output ARLEN_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1591:33:1591:41|*Output ARSIZE_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1592:33:1592:42|*Output ARBURST_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1593:33:1593:41|*Output ARLOCK_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1594:33:1594:42|*Output ARCACHE_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1595:33:1595:41|*Output ARPROT_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1596:33:1596:42|*Output ARVALID_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1604:33:1604:41|*Output RREADY_S7 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1608:58:1608:64|*Output AWID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1609:23:1609:31|*Output AWADDR_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1610:33:1610:40|*Output AWLEN_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1611:33:1611:41|*Output AWSIZE_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1612:33:1612:42|*Output AWBURST_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1613:33:1613:41|*Output AWLOCK_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1614:33:1614:42|*Output AWCACHE_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1615:33:1615:41|*Output AWPROT_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1616:33:1616:42|*Output AWVALID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1619:58:1619:63|*Output WID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1620:33:1620:40|*Output WDATA_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1621:33:1621:40|*Output WSTRB_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1622:33:1622:40|*Output WLAST_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1623:33:1623:41|*Output WVALID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1629:33:1629:41|*Output BREADY_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1631:58:1631:64|*Output ARID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1632:23:1632:31|*Output ARADDR_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1633:33:1633:40|*Output ARLEN_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1634:33:1634:41|*Output ARSIZE_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1635:33:1635:42|*Output ARBURST_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1636:33:1636:41|*Output ARLOCK_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1637:33:1637:42|*Output ARCACHE_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1638:33:1638:41|*Output ARPROT_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1639:33:1639:42|*Output ARVALID_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1647:33:1647:41|*Output RREADY_S8 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1651:58:1651:64|*Output AWID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1652:23:1652:31|*Output AWADDR_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1653:33:1653:40|*Output AWLEN_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1654:33:1654:41|*Output AWSIZE_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1655:33:1655:42|*Output AWBURST_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1656:33:1656:41|*Output AWLOCK_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1657:33:1657:42|*Output AWCACHE_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1658:33:1658:41|*Output AWPROT_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1659:33:1659:42|*Output AWVALID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1662:58:1662:63|*Output WID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1663:33:1663:40|*Output WDATA_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1664:33:1664:40|*Output WSTRB_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1665:33:1665:40|*Output WLAST_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1666:33:1666:41|*Output WVALID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1672:33:1672:41|*Output BREADY_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1674:58:1674:64|*Output ARID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1675:23:1675:31|*Output ARADDR_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1676:33:1676:40|*Output ARLEN_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1677:33:1677:41|*Output ARSIZE_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1678:33:1678:42|*Output ARBURST_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1679:33:1679:41|*Output ARLOCK_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1680:33:1680:42|*Output ARCACHE_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1681:33:1681:41|*Output ARPROT_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1682:33:1682:42|*Output ARVALID_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1690:33:1690:41|*Output RREADY_S9 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1694:58:1694:65|*Output AWID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1695:23:1695:32|*Output AWADDR_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1696:33:1696:41|*Output AWLEN_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1697:33:1697:42|*Output AWSIZE_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1698:33:1698:43|*Output AWBURST_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1699:33:1699:42|*Output AWLOCK_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1700:33:1700:43|*Output AWCACHE_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1701:33:1701:42|*Output AWPROT_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1702:33:1702:43|*Output AWVALID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1705:58:1705:64|*Output WID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1706:33:1706:41|*Output WDATA_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1707:33:1707:41|*Output WSTRB_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1708:33:1708:41|*Output WLAST_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1709:33:1709:42|*Output WVALID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1715:33:1715:42|*Output BREADY_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1717:58:1717:65|*Output ARID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1718:23:1718:32|*Output ARADDR_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1719:33:1719:41|*Output ARLEN_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1720:33:1720:42|*Output ARSIZE_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1721:33:1721:43|*Output ARBURST_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1722:33:1722:42|*Output ARLOCK_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1723:33:1723:43|*Output ARCACHE_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1724:33:1724:42|*Output ARPROT_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1725:33:1725:43|*Output ARVALID_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1733:33:1733:42|*Output RREADY_S10 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1737:58:1737:65|*Output AWID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1738:23:1738:32|*Output AWADDR_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1739:33:1739:41|*Output AWLEN_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1740:33:1740:42|*Output AWSIZE_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1741:33:1741:43|*Output AWBURST_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1742:33:1742:42|*Output AWLOCK_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1743:33:1743:43|*Output AWCACHE_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1744:33:1744:42|*Output AWPROT_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1745:33:1745:43|*Output AWVALID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1748:58:1748:64|*Output WID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1749:33:1749:41|*Output WDATA_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1750:33:1750:41|*Output WSTRB_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1751:33:1751:41|*Output WLAST_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1752:33:1752:42|*Output WVALID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1758:33:1758:42|*Output BREADY_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1760:58:1760:65|*Output ARID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1761:23:1761:32|*Output ARADDR_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1762:33:1762:41|*Output ARLEN_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1763:33:1763:42|*Output ARSIZE_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1764:33:1764:43|*Output ARBURST_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1765:33:1765:42|*Output ARLOCK_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1766:33:1766:43|*Output ARCACHE_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1767:33:1767:42|*Output ARPROT_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1768:33:1768:43|*Output ARVALID_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1776:33:1776:42|*Output RREADY_S11 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1780:58:1780:65|*Output AWID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1781:23:1781:32|*Output AWADDR_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1782:33:1782:41|*Output AWLEN_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1783:33:1783:42|*Output AWSIZE_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1784:33:1784:43|*Output AWBURST_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1785:33:1785:42|*Output AWLOCK_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1786:33:1786:43|*Output AWCACHE_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1787:33:1787:42|*Output AWPROT_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1788:33:1788:43|*Output AWVALID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1791:58:1791:64|*Output WID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1792:33:1792:41|*Output WDATA_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1793:33:1793:41|*Output WSTRB_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1794:33:1794:41|*Output WLAST_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1795:33:1795:42|*Output WVALID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1801:33:1801:42|*Output BREADY_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1803:58:1803:65|*Output ARID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1804:23:1804:32|*Output ARADDR_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1805:33:1805:41|*Output ARLEN_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1806:33:1806:42|*Output ARSIZE_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1807:33:1807:43|*Output ARBURST_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1808:33:1808:42|*Output ARLOCK_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1809:33:1809:43|*Output ARCACHE_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1810:33:1810:42|*Output ARPROT_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1811:33:1811:43|*Output ARVALID_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1819:33:1819:42|*Output RREADY_S12 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1823:58:1823:65|*Output AWID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1824:23:1824:32|*Output AWADDR_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1825:33:1825:41|*Output AWLEN_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1826:33:1826:42|*Output AWSIZE_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1827:33:1827:43|*Output AWBURST_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1828:33:1828:42|*Output AWLOCK_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1829:33:1829:43|*Output AWCACHE_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1830:33:1830:42|*Output AWPROT_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1831:33:1831:43|*Output AWVALID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1834:58:1834:64|*Output WID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1835:33:1835:41|*Output WDATA_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1836:33:1836:41|*Output WSTRB_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1837:33:1837:41|*Output WLAST_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1838:33:1838:42|*Output WVALID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1844:33:1844:42|*Output BREADY_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1846:58:1846:65|*Output ARID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1847:23:1847:32|*Output ARADDR_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1848:33:1848:41|*Output ARLEN_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1849:33:1849:42|*Output ARSIZE_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1850:33:1850:43|*Output ARBURST_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1851:33:1851:42|*Output ARLOCK_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1852:33:1852:43|*Output ARCACHE_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1853:33:1853:42|*Output ARPROT_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1854:33:1854:43|*Output ARVALID_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1862:33:1862:42|*Output RREADY_S13 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1866:58:1866:65|*Output AWID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1867:23:1867:32|*Output AWADDR_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1868:33:1868:41|*Output AWLEN_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1869:33:1869:42|*Output AWSIZE_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1870:33:1870:43|*Output AWBURST_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1871:33:1871:42|*Output AWLOCK_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1872:33:1872:43|*Output AWCACHE_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1873:33:1873:42|*Output AWPROT_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1874:33:1874:43|*Output AWVALID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1877:58:1877:64|*Output WID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1878:33:1878:41|*Output WDATA_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1879:33:1879:41|*Output WSTRB_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1880:33:1880:41|*Output WLAST_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1881:33:1881:42|*Output WVALID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1887:33:1887:42|*Output BREADY_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1889:58:1889:65|*Output ARID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1890:23:1890:32|*Output ARADDR_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1891:33:1891:41|*Output ARLEN_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1892:33:1892:42|*Output ARSIZE_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1893:33:1893:43|*Output ARBURST_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1894:33:1894:42|*Output ARLOCK_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1895:33:1895:43|*Output ARCACHE_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1896:33:1896:42|*Output ARPROT_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1897:33:1897:43|*Output ARVALID_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1905:33:1905:42|*Output RREADY_S14 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1909:58:1909:65|*Output AWID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1910:23:1910:32|*Output AWADDR_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1911:33:1911:41|*Output AWLEN_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1912:33:1912:42|*Output AWSIZE_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1913:33:1913:43|*Output AWBURST_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1914:33:1914:42|*Output AWLOCK_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1915:33:1915:43|*Output AWCACHE_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1916:33:1916:42|*Output AWPROT_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1917:33:1917:43|*Output AWVALID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1920:58:1920:64|*Output WID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1921:33:1921:41|*Output WDATA_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1922:33:1922:41|*Output WSTRB_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1923:33:1923:41|*Output WLAST_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1924:33:1924:42|*Output WVALID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1930:33:1930:42|*Output BREADY_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1932:58:1932:65|*Output ARID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1933:23:1933:32|*Output ARADDR_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1934:33:1934:41|*Output ARLEN_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1935:33:1935:42|*Output ARSIZE_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1936:33:1936:43|*Output ARBURST_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1937:33:1937:42|*Output ARLOCK_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1938:33:1938:43|*Output ARCACHE_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1939:33:1939:42|*Output ARPROT_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1940:33:1940:43|*Output ARVALID_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1948:33:1948:42|*Output RREADY_S15 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1952:58:1952:65|*Output AWID_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1953:23:1953:32|*Output AWADDR_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1954:33:1954:41|*Output AWLEN_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1955:33:1955:42|*Output AWSIZE_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1956:33:1956:43|*Output AWBURST_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1957:33:1957:42|*Output AWLOCK_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1958:33:1958:43|*Output AWCACHE_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1959:33:1959:42|*Output AWPROT_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1960:33:1960:43|*Output AWVALID_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1963:58:1963:64|*Output WID_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1964:33:1964:41|*Output WDATA_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1965:33:1965:41|*Output WSTRB_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1966:33:1966:41|*Output WLAST_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1967:33:1967:42|*Output WVALID_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1973:33:1973:42|*Output BREADY_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1975:58:1975:65|*Output ARID_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1976:23:1976:32|*Output ARADDR_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1977:33:1977:41|*Output ARLEN_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1978:33:1978:42|*Output ARSIZE_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1979:33:1979:43|*Output ARBURST_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1980:33:1980:42|*Output ARLOCK_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1981:33:1981:43|*Output ARCACHE_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1982:33:1982:42|*Output ARPROT_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1983:33:1983:43|*Output ARVALID_S16 has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1991:33:1991:42|*Output RREADY_S16 has undriven bits -- simulation mismatch possible.
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1135:33:1135:39|Input AWID_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1137:33:1137:40|Input AWLEN_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1138:33:1138:41|Input AWSIZE_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1139:33:1139:42|Input AWBURST_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1141:33:1141:42|Input AWCACHE_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1142:33:1142:41|Input AWPROT_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1146:33:1146:38|Input WID_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1147:33:1147:40|Input WDATA_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1148:33:1148:40|Input WSTRB_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1149:33:1149:40|Input WLAST_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1150:33:1150:41|Input WVALID_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1156:33:1156:41|Input BREADY_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1158:33:1158:39|Input ARID_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Input ARLEN_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1161:33:1161:41|Input ARSIZE_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1162:33:1162:42|Input ARBURST_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1164:33:1164:42|Input ARCACHE_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1165:33:1165:41|Input ARPROT_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1174:33:1174:41|Input RREADY_M1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1178:33:1178:39|Input AWID_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1180:33:1180:40|Input AWLEN_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1181:33:1181:41|Input AWSIZE_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1182:33:1182:42|Input AWBURST_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1184:33:1184:42|Input AWCACHE_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1185:33:1185:41|Input AWPROT_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1189:33:1189:38|Input WID_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1190:33:1190:40|Input WDATA_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1191:33:1191:40|Input WSTRB_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1192:33:1192:40|Input WLAST_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1193:33:1193:41|Input WVALID_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1199:33:1199:41|Input BREADY_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1201:33:1201:39|Input ARID_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Input ARLEN_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1204:33:1204:41|Input ARSIZE_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1205:33:1205:42|Input ARBURST_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1207:33:1207:42|Input ARCACHE_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1208:33:1208:41|Input ARPROT_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1217:33:1217:41|Input RREADY_M2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1221:33:1221:39|Input AWID_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1223:33:1223:40|Input AWLEN_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1224:33:1224:41|Input AWSIZE_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1225:33:1225:42|Input AWBURST_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1227:33:1227:42|Input AWCACHE_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1228:33:1228:41|Input AWPROT_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1232:33:1232:38|Input WID_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1233:33:1233:40|Input WDATA_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1234:33:1234:40|Input WSTRB_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1235:33:1235:40|Input WLAST_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1236:33:1236:41|Input WVALID_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1242:33:1242:41|Input BREADY_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1244:33:1244:39|Input ARID_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Input ARLEN_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1247:33:1247:41|Input ARSIZE_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1248:33:1248:42|Input ARBURST_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1250:33:1250:42|Input ARCACHE_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1251:33:1251:41|Input ARPROT_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1260:33:1260:41|Input RREADY_M3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1316:33:1316:42|Input AWREADY_S1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1323:33:1323:41|Input WREADY_S1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1325:58:1325:63|Input BID_S1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1326:33:1326:40|Input BRESP_S1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1327:33:1327:41|Input BVALID_S1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1339:33:1339:42|Input ARREADY_S1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1341:58:1341:63|Input RID_S1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1342:33:1342:40|Input RDATA_S1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1343:33:1343:40|Input RRESP_S1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1344:33:1344:40|Input RLAST_S1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1345:33:1345:41|Input RVALID_S1 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1359:33:1359:42|Input AWREADY_S2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1366:33:1366:41|Input WREADY_S2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1368:58:1368:63|Input BID_S2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1369:33:1369:40|Input BRESP_S2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1370:33:1370:41|Input BVALID_S2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1382:33:1382:42|Input ARREADY_S2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1384:58:1384:63|Input RID_S2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1385:33:1385:40|Input RDATA_S2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1386:33:1386:40|Input RRESP_S2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1387:33:1387:40|Input RLAST_S2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1388:33:1388:41|Input RVALID_S2 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1402:33:1402:42|Input AWREADY_S3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1409:33:1409:41|Input WREADY_S3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1411:58:1411:63|Input BID_S3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1412:33:1412:40|Input BRESP_S3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1413:33:1413:41|Input BVALID_S3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1425:33:1425:42|Input ARREADY_S3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1427:58:1427:63|Input RID_S3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1428:33:1428:40|Input RDATA_S3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1429:33:1429:40|Input RRESP_S3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1430:33:1430:40|Input RLAST_S3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1431:33:1431:41|Input RVALID_S3 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1445:33:1445:42|Input AWREADY_S4 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1452:33:1452:41|Input WREADY_S4 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1454:58:1454:63|Input BID_S4 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1455:33:1455:40|Input BRESP_S4 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1456:33:1456:41|Input BVALID_S4 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1468:33:1468:42|Input ARREADY_S4 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1470:58:1470:63|Input RID_S4 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1471:33:1471:40|Input RDATA_S4 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1472:33:1472:40|Input RRESP_S4 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1473:33:1473:40|Input RLAST_S4 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1474:33:1474:41|Input RVALID_S4 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1488:33:1488:42|Input AWREADY_S5 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1495:33:1495:41|Input WREADY_S5 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1497:58:1497:63|Input BID_S5 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1498:33:1498:40|Input BRESP_S5 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1499:33:1499:41|Input BVALID_S5 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1511:33:1511:42|Input ARREADY_S5 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1513:58:1513:63|Input RID_S5 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1514:33:1514:40|Input RDATA_S5 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1515:33:1515:40|Input RRESP_S5 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1516:33:1516:40|Input RLAST_S5 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1517:33:1517:41|Input RVALID_S5 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1531:33:1531:42|Input AWREADY_S6 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1538:33:1538:41|Input WREADY_S6 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1540:58:1540:63|Input BID_S6 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1541:33:1541:40|Input BRESP_S6 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1542:33:1542:41|Input BVALID_S6 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1554:33:1554:42|Input ARREADY_S6 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1556:58:1556:63|Input RID_S6 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1557:33:1557:40|Input RDATA_S6 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1558:33:1558:40|Input RRESP_S6 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1559:33:1559:40|Input RLAST_S6 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1560:33:1560:41|Input RVALID_S6 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1574:33:1574:42|Input AWREADY_S7 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1581:33:1581:41|Input WREADY_S7 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1583:58:1583:63|Input BID_S7 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1584:33:1584:40|Input BRESP_S7 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1585:33:1585:41|Input BVALID_S7 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1597:33:1597:42|Input ARREADY_S7 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1599:58:1599:63|Input RID_S7 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1600:33:1600:40|Input RDATA_S7 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1601:33:1601:40|Input RRESP_S7 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1602:33:1602:40|Input RLAST_S7 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1603:33:1603:41|Input RVALID_S7 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1617:33:1617:42|Input AWREADY_S8 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1624:33:1624:41|Input WREADY_S8 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1626:58:1626:63|Input BID_S8 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1627:33:1627:40|Input BRESP_S8 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1628:33:1628:41|Input BVALID_S8 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1640:33:1640:42|Input ARREADY_S8 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1642:58:1642:63|Input RID_S8 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1643:33:1643:40|Input RDATA_S8 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1644:33:1644:40|Input RRESP_S8 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1645:33:1645:40|Input RLAST_S8 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1646:33:1646:41|Input RVALID_S8 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1660:33:1660:42|Input AWREADY_S9 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1667:33:1667:41|Input WREADY_S9 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1669:58:1669:63|Input BID_S9 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1670:33:1670:40|Input BRESP_S9 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1671:33:1671:41|Input BVALID_S9 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1683:33:1683:42|Input ARREADY_S9 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1685:58:1685:63|Input RID_S9 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1686:33:1686:40|Input RDATA_S9 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1687:33:1687:40|Input RRESP_S9 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1688:33:1688:40|Input RLAST_S9 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1689:33:1689:41|Input RVALID_S9 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1703:33:1703:43|Input AWREADY_S10 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1710:33:1710:42|Input WREADY_S10 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1712:58:1712:64|Input BID_S10 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1713:33:1713:41|Input BRESP_S10 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1714:33:1714:42|Input BVALID_S10 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1726:33:1726:43|Input ARREADY_S10 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1728:58:1728:64|Input RID_S10 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1729:33:1729:41|Input RDATA_S10 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1730:33:1730:41|Input RRESP_S10 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1731:33:1731:41|Input RLAST_S10 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1732:33:1732:42|Input RVALID_S10 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1746:33:1746:43|Input AWREADY_S11 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1753:33:1753:42|Input WREADY_S11 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1755:58:1755:64|Input BID_S11 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1756:33:1756:41|Input BRESP_S11 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1757:33:1757:42|Input BVALID_S11 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1769:33:1769:43|Input ARREADY_S11 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1771:58:1771:64|Input RID_S11 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1772:33:1772:41|Input RDATA_S11 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1773:33:1773:41|Input RRESP_S11 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1774:33:1774:41|Input RLAST_S11 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1775:33:1775:42|Input RVALID_S11 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1789:33:1789:43|Input AWREADY_S12 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1796:33:1796:42|Input WREADY_S12 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1798:58:1798:64|Input BID_S12 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1799:33:1799:41|Input BRESP_S12 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1800:33:1800:42|Input BVALID_S12 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1812:33:1812:43|Input ARREADY_S12 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1814:58:1814:64|Input RID_S12 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1815:33:1815:41|Input RDATA_S12 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1816:33:1816:41|Input RRESP_S12 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1817:33:1817:41|Input RLAST_S12 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1818:33:1818:42|Input RVALID_S12 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1832:33:1832:43|Input AWREADY_S13 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1839:33:1839:42|Input WREADY_S13 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1841:58:1841:64|Input BID_S13 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1842:33:1842:41|Input BRESP_S13 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1843:33:1843:42|Input BVALID_S13 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1855:33:1855:43|Input ARREADY_S13 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1857:58:1857:64|Input RID_S13 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1858:33:1858:41|Input RDATA_S13 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1859:33:1859:41|Input RRESP_S13 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1860:33:1860:41|Input RLAST_S13 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1861:33:1861:42|Input RVALID_S13 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1875:33:1875:43|Input AWREADY_S14 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1882:33:1882:42|Input WREADY_S14 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1884:58:1884:64|Input BID_S14 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1885:33:1885:41|Input BRESP_S14 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1886:33:1886:42|Input BVALID_S14 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1898:33:1898:43|Input ARREADY_S14 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1900:58:1900:64|Input RID_S14 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1901:33:1901:41|Input RDATA_S14 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1902:33:1902:41|Input RRESP_S14 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1903:33:1903:41|Input RLAST_S14 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1904:33:1904:42|Input RVALID_S14 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1918:33:1918:43|Input AWREADY_S15 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1925:33:1925:42|Input WREADY_S15 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1927:58:1927:64|Input BID_S15 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1928:33:1928:41|Input BRESP_S15 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1929:33:1929:42|Input BVALID_S15 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1941:33:1941:43|Input ARREADY_S15 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1943:58:1943:64|Input RID_S15 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1944:33:1944:41|Input RDATA_S15 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1945:33:1945:41|Input RRESP_S15 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1946:33:1946:41|Input RLAST_S15 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1947:33:1947:42|Input RVALID_S15 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1961:33:1961:43|Input AWREADY_S16 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1968:33:1968:42|Input WREADY_S16 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1970:58:1970:64|Input BID_S16 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1971:33:1971:41|Input BRESP_S16 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1972:33:1972:42|Input BVALID_S16 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1984:33:1984:43|Input ARREADY_S16 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1986:58:1986:64|Input RID_S16 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1987:33:1987:41|Input RDATA_S16 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1988:33:1988:41|Input RRESP_S16 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1989:33:1989:41|Input RLAST_S16 is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":1990:33:1990:42|Input RVALID_S16 is unused
@W: CL246 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":32:17:32:22|Input port bits 31 to 12 of AWADDR[31:0] are unused
@W: CL246 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":53:18:53:23|Input port bits 31 to 12 of ARADDR[31:0] are unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":33:20:33:24|Input AWLEN is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":35:19:35:24|Input AWLOCK is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":40:20:40:22|Input WID is unused
@W: CL159 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":56:20:56:25|Input ARLOCK is unused

