@N|Running in 64-bit mode
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":377:7:377:13|Synthesizing module RAM1K18
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":367:7:367:9|Synthesizing module GND
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":371:7:371:9|Synthesizing module VCC
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\fabric_ram\fabric_ram_0\fabric_ram_fabric_ram_0_TPSRAM.v":5:7:5:36|Synthesizing module fabric_ram_fabric_ram_0_TPSRAM
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\fabric_ram\fabric_ram.v":9:7:9:16|Synthesizing module fabric_ram
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":21:7:21:26|Synthesizing module AXI_SLAVE_IF_FAB_RAM
@N: CG179 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":186:45:186:53|Removing redundant assignment
@N: CG179 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":317:47:317:55|Removing redundant assignment
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\COREAXI_0\rtl\vlog\core\coreaxi.v":29:7:29:33|Synthesizing module Top_level_COREAXI_0_COREAXI
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_16Sto1M.v":33:7:33:26|Synthesizing module axi_rdmatrix_16Sto1M
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rd_channel.v":33:7:33:20|Synthesizing module axi_rd_channel
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wresp_channel.v":33:7:33:23|Synthesizing module axi_wresp_channel
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_m.v":33:7:33:18|Synthesizing module axi_matrix_m
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":38:7:38:27|Synthesizing module axi_interconnect_ntom
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_channel.v":33:7:33:20|Synthesizing module axi_wa_channel
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_arbiter.v":28:7:28:20|Synthesizing module axi_WA_ARBITER
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":33:7:33:25|Synthesizing module axi_wrmatrix_4Mto1S
@N: CG179 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":531:26:531:34|Removing redundant assignment
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":33:7:33:20|Synthesizing module axi_wd_channel
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_ra_channel.v":33:7:33:20|Synthesizing module axi_ra_channel
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_ra_arbiter.v":28:7:28:20|Synthesizing module axi_RA_ARBITER
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":32:7:32:25|Synthesizing module axi_rdmatrix_4Mto1S
@N: CG179 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":561:26:561:34|Removing redundant assignment
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":34:7:34:18|Synthesizing module axi_matrix_s
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":28:7:28:22|Synthesizing module axi_master_stage
@N: CG179 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2370:25:2370:33|Removing redundant assignment
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":29:7:29:21|Synthesizing module axi_slave_stage
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\Debounce.v":2:8:2:15|Synthesizing module DEBOUNCE
@N: CG179 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\Debounce.v":57:18:57:26|Removing redundant assignment
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":362:7:362:12|Synthesizing module CLKINT
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":722:7:722:9|Synthesizing module CCC
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":268:7:268:11|Synthesizing module INBUF
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\PCIe_Demo\CCC_0\PCIe_Demo_CCC_0_FCCC.v":5:7:5:26|Synthesizing module PCIe_Demo_CCC_0_FCCC
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v":31:7:31:30|Synthesizing module coreresetp_pcie_hotreset
@N: CL177 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CL177 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1.
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\SgCore\OSC\1.0.101\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\SgCore\OSC\1.0.101\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\PCIe_Demo\FABOSC_0\PCIe_Demo_FABOSC_0_OSC.v":5:7:5:28|Synthesizing module PCIe_Demo_FABOSC_0_OSC
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\PCIe_Demo_MSS\PCIe_Demo_MSS_syn.v":5:7:5:13|Synthesizing module MSS_050
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\PCIe_Demo_MSS\PCIe_Demo_MSS.v":9:7:9:19|Synthesizing module PCIe_Demo_MSS
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":713:7:713:14|Synthesizing module SYSRESET
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\PCIe_Demo\PCIe_Demo.v":9:7:9:15|Synthesizing module PCIe_Demo
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":320:7:320:16|Synthesizing module INBUF_DIFF
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\SERDESIF_INIT_BLK\SERDES_IF_0\SERDESIF_INIT_BLK_SERDES_IF_0_SERDES_IF_syn.v":5:7:5:16|Synthesizing module SERDESIF_1
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\SERDESIF_INIT_BLK\SERDES_IF_0\SERDESIF_INIT_BLK_SERDES_IF_0_SERDES_IF.v":5:7:5:45|Synthesizing module SERDESIF_INIT_BLK_SERDES_IF_0_SERDES_IF
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\SERDESIF_INIT_BLK\SERDESIF_INIT_BLK.v":9:7:9:23|Synthesizing module SERDESIF_INIT_BLK
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\work\Top_level\Top_level.v":9:7:9:15|Synthesizing module Top_level
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v":179:4:179:9|Trying to extract state machine for register state
@N: CL177 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL177 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2.
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v":447:4:447:9|Trying to extract state machine for register state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_ra_arbiter.v":217:3:217:8|Trying to extract state machine for register rd_curr_state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_arbiter.v":209:3:209:8|Trying to extract state machine for register wr_curr_state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_16Sto1M.v":604:3:604:8|Trying to extract state machine for register curr_state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":239:0:239:5|Trying to extract state machine for register axi_fsm_read_state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\hdl\AXI_SLAVE_IF_FAB_RAM.v":104:0:104:5|Trying to extract state machine for register axi_fsm_write_state

