#--  Synopsys, Inc.
#--  Version I-2013.09M-SP1-1 
#--  Project file D:\Appsnotes\2014\AXI__update\design_file\Libero\PCIe_with_AXI_SLAVE\synthesis\run_options.txt
#--  Written on Thu Jun 19 14:24:08 2014


#project files
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_feedthrough.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_rdmatrix_16Sto1M.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_rd_channel.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_wresp_channel.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_matrix_m.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_wa_arbiter.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_wrmatrix_4Mto1S.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_low.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_high.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_wa_channel.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_wd_channel.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_ra_arbiter.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_rdmatrix_4Mto1S.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_low.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_high.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_ra_channel.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_matrix_s.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_interconnect_ntom.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_master_stage.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/COREAXI/3.0.112/rtl/vlog/core/axi_slave_stage.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/work/Top_level/COREAXI_0/rtl/vlog/core/coreaxi.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/hdl/Debounce.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/work/PCIe_Demo/CCC_0/PCIe_Demo_CCC_0_FCCC.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vlog/core/coreconfigp.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/Actel/SgCore/OSC/1.0.101/osc_comps.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/work/PCIe_Demo/FABOSC_0/PCIe_Demo_FABOSC_0_OSC.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/work/PCIe_Demo_MSS/PCIe_Demo_MSS_syn.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/work/PCIe_Demo_MSS/PCIe_Demo_MSS.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/work/PCIe_Demo/PCIe_Demo.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/work/SERDESIF_INIT_BLK/SERDES_IF_0/SERDESIF_INIT_BLK_SERDES_IF_0_SERDES_IF_syn.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/work/SERDESIF_INIT_BLK/SERDES_IF_0/SERDESIF_INIT_BLK_SERDES_IF_0_SERDES_IF.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/work/SERDESIF_INIT_BLK/SERDESIF_INIT_BLK.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/work/fabric_ram/fabric_ram_0/fabric_ram_fabric_ram_0_TPSRAM.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/work/fabric_ram/fabric_ram.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/hdl/AXI_SLAVE_IF_FAB_RAM.v"
add_file -verilog "D:/Appsnotes/2014/AXI__update/design_file/Libero/PCIe_with_AXI_SLAVE/component/work/Top_level/Top_level.v"



#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion2
set_option -part M2S050T
set_option -package FBGA896
set_option -speed_grade STD
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "Top_level"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# actel_options
set_option -RWCheckOnRam 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -opcond COMWC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./Top_level.edn"
impl -active "synthesis"
