
*******************************************
       Libero SoC, MSS and IP Core VERSIONS
*******************************************

This design was tested with the following: 
	Libero SoC Version: 11.4 
	MSS Version: 1.1.209


******************************************
     DESIGN FILE DIRECTORY STRUCTURE
******************************************


sf2_axi_appsnote_df
    |
    |    
    |   
    |      
    |      
    |----libero
    |      |
    |      |
    |      |     
    |      |-----FABRIC_AXI_master.zip
    |      |     
    |      |-----PCIe_with_AXI_SLAVE.zip 
    |      
    |
    |
    |	        
    |
    |
    |
    |
    |---readme.txt
    

libero
==================================
LiberoProject files

For reference, the Libero SoC Verilog project of appsnote is provided under this folder. 
The designs are created for SmartFusion2 device.
FABRIC_AXI_master: Fabric AXI master block communicate with FDDR
PCIe_with_AXI_SLAVE: Fabric AXI slave communicate with SERDESIF in PCIe mode









