Project Settings Project Name SF2_AXI_master_top_syn Implementation Name synthesis Top Module SF2_AXI_master_top Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time Compile Input out-of-date 57 3213 0 - 0m:03s - 6/17/2014 4:11:14 PM Pre-mapping out-of-date 45 10 0 0m:01s 0m:02s 161MB 6/17/2014 4:11:18 PM Map & Optimize out-of-date 68 6697 0 0m:04s 0m:05s 162MB 6/17/2014 4:11:24 PM Area Summary Carry Cells 16 Sequential Cells 1157 DSP Blocks (MACC) (dsp_used) 0 I/O Cells 263 Global Clock Buffers 5 LUTs (total_luts) 602 Timing Summary Clock Name Req Freq Est Freq Slack SF2_AXI_master_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 127.2 MHz 1.070 SF2_FDDR_INIT_BLK_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 152.6 MHz 3.445 SF2_FDDR_INIT_BLK_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 394.1 MHz 7.462 System 100.0 MHz NA NA Optimizations Summary Combined Clock Conversion 2 / 1