Synopsys Generic Technology Pre-mapping, Version mapact, Build 976R, Built May 23 2013 12:46:43 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version H-2013.03M-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Linked File: SF2_AXI_master_top_scck.rpt Printing clock summary report in "D:\Appsnotes\2013\AXI_master\Apps_design_final\FABRIC_AXI_master\synthesis\SF2_AXI_master_top_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 115MB peak: 118MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 118MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 118MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB) @W:BN132 : coresf2reset.v(550) | Removing sequential instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF3_PHY_RESET_N, because it is equivalent to instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF2_PHY_RESET_N @W:BN132 : coresf2reset.v(550) | Removing sequential instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF2_PHY_RESET_N, because it is equivalent to instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF1_PHY_RESET_N @W:BN132 : coresf2reset.v(550) | Removing sequential instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF1_PHY_RESET_N, because it is equivalent to instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF0_PHY_RESET_N @W:BN132 : coresf2reset.v(550) | Removing sequential instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF3_CORE_RESET_N, because it is equivalent to instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF2_CORE_RESET_N @W:BN132 : coresf2reset.v(550) | Removing sequential instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF2_CORE_RESET_N, because it is equivalent to instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF1_CORE_RESET_N @W:BN132 : coresf2reset.v(550) | Removing sequential instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF1_CORE_RESET_N, because it is equivalent to instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF0_CORE_RESET_N @W:BN132 : coresf2reset.v(550) | Removing sequential instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.MDDR_DDR_AXI_S_CORE_RESET_N, because it is equivalent to instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.FDDR_CORE_RESET_N @N:BN362 : coresf2config.v(337) | Removing sequential instance MDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(337) | Removing sequential instance SDIF0_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(337) | Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(337) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(337) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2reset.v(550) | Removing sequential instance SDIF0_PHY_RESET_N of view:PrimLib.dffre(prim) in hierarchy view:work.CoreSF2Reset_Z4(verilog) because there are no references to its outputs @N:BN362 : coresf2reset.v(550) | Removing sequential instance SDIF0_CORE_RESET_N of view:PrimLib.dffre(prim) in hierarchy view:work.CoreSF2Reset_Z4(verilog) because there are no references to its outputs syn_allowed_resources : blockrams=69 set on top level netlist SF2_AXI_master_top Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group --------------------------------------------------------------------------------------------------------------------------------- System 1.0 MHz 1000.000 system system_clkgroup SF2_FDDR_INIT_BLK_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 SF2_AXI_master_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 SF2_FDDR_INIT_BLK_FABOSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 ================================================================================================================================= @W:MT530 : axi_master_if.v(98) | Found inferred clock SF2_FDDR_INIT_BLK_CCC_0_FCCC|GL0_net_inferred_clock which controls 698 sequential elements including AXI_MASTER_IF_0.w_tr_length[3:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coresf2config.v(323) | Found inferred clock SF2_AXI_master_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 92 sequential elements including SF2_FDDR_INIT_BLK_0.CORESF2CONFIG_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coresf2reset.v(722) | Found inferred clock SF2_FDDR_INIT_BLK_FABOSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock which controls 40 sequential elements including SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.count[13:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase.@N: BN225 |Writing default property annotation file D:\Appsnotes\2013\AXI_master\Apps_design_final\FABRIC_AXI_master\synthesis\SF2_AXI_master_top.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 84MB peak: 149MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Aug 21 16:29:06 2013 ###########################################################]