@W: BN132 :"d:\appsnotes\2014\axi__update\design_file\libero\fabric_axi_master\component\actel\directcore\coresf2reset\3.0.100\rtl\vlog\core\coresf2reset.v":550:4:550:9|Removing sequential instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF3_PHY_RESET_N,  because it is equivalent to instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF2_PHY_RESET_N
@W: BN132 :"d:\appsnotes\2014\axi__update\design_file\libero\fabric_axi_master\component\actel\directcore\coresf2reset\3.0.100\rtl\vlog\core\coresf2reset.v":550:4:550:9|Removing sequential instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF2_PHY_RESET_N,  because it is equivalent to instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF1_PHY_RESET_N
@W: BN132 :"d:\appsnotes\2014\axi__update\design_file\libero\fabric_axi_master\component\actel\directcore\coresf2reset\3.0.100\rtl\vlog\core\coresf2reset.v":550:4:550:9|Removing sequential instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF1_PHY_RESET_N,  because it is equivalent to instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF0_PHY_RESET_N
@W: BN132 :"d:\appsnotes\2014\axi__update\design_file\libero\fabric_axi_master\component\actel\directcore\coresf2reset\3.0.100\rtl\vlog\core\coresf2reset.v":550:4:550:9|Removing sequential instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF3_CORE_RESET_N,  because it is equivalent to instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF2_CORE_RESET_N
@W: BN132 :"d:\appsnotes\2014\axi__update\design_file\libero\fabric_axi_master\component\actel\directcore\coresf2reset\3.0.100\rtl\vlog\core\coresf2reset.v":550:4:550:9|Removing sequential instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF2_CORE_RESET_N,  because it is equivalent to instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF1_CORE_RESET_N
@W: BN132 :"d:\appsnotes\2014\axi__update\design_file\libero\fabric_axi_master\component\actel\directcore\coresf2reset\3.0.100\rtl\vlog\core\coresf2reset.v":550:4:550:9|Removing sequential instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF1_CORE_RESET_N,  because it is equivalent to instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.SDIF0_CORE_RESET_N
@W: BN132 :"d:\appsnotes\2014\axi__update\design_file\libero\fabric_axi_master\component\actel\directcore\coresf2reset\3.0.100\rtl\vlog\core\coresf2reset.v":550:4:550:9|Removing sequential instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.MDDR_DDR_AXI_S_CORE_RESET_N,  because it is equivalent to instance SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.FDDR_CORE_RESET_N
@W: MT530 :"d:\appsnotes\2014\axi__update\design_file\libero\fabric_axi_master\hdl\axi_master_if.v":98:0:98:5|Found inferred clock SF2_FDDR_INIT_BLK_CCC_0_FCCC|GL0_net_inferred_clock which controls 1297 sequential elements including AXI_MASTER_IF_0.w_tr_length[3:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\appsnotes\2014\axi__update\design_file\libero\fabric_axi_master\component\actel\directcore\coresf2config\3.0.100\rtl\vlog\core\coresf2config.v":323:4:323:9|Found inferred clock SF2_AXI_master_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 92 sequential elements including SF2_FDDR_INIT_BLK_0.CORESF2CONFIG_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\appsnotes\2014\axi__update\design_file\libero\fabric_axi_master\component\actel\directcore\coresf2reset\3.0.100\rtl\vlog\core\coresf2reset.v":722:4:722:9|Found inferred clock SF2_FDDR_INIT_BLK_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 40 sequential elements including SF2_FDDR_INIT_BLK_0.CORESF2RESET_0.count[13:0]. This clock has no specified timing constraint which may adversely impact design performance. 
