@N|Running in 64-bit mode
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\hdl\AXI_MASTER_IF.v":21:7:21:19|Synthesizing module AXI_MASTER_IF
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\work\SF2_AXI_master_top\COREAXI_0\rtl\vlog\core\coreaxi.v":29:7:29:42|Synthesizing module SF2_AXI_master_top_COREAXI_0_COREAXI
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_16Sto1M.v":33:7:33:26|Synthesizing module axi_rdmatrix_16Sto1M
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rd_channel.v":33:7:33:20|Synthesizing module axi_rd_channel
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wresp_channel.v":33:7:33:23|Synthesizing module axi_wresp_channel
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_m.v":33:7:33:18|Synthesizing module axi_matrix_m
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_interconnect_ntom.v":38:7:38:27|Synthesizing module axi_interconnect_ntom
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_channel.v":33:7:33:20|Synthesizing module axi_wa_channel
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_arbiter.v":28:7:28:20|Synthesizing module axi_WA_ARBITER
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":33:7:33:25|Synthesizing module axi_wrmatrix_4Mto1S
@N: CG179 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wrmatrix_4Mto1S.v":531:26:531:34|Removing redundant assignment
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wd_channel.v":33:7:33:20|Synthesizing module axi_wd_channel
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_ra_channel.v":33:7:33:20|Synthesizing module axi_ra_channel
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_ra_arbiter.v":28:7:28:20|Synthesizing module axi_RA_ARBITER
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":32:7:32:25|Synthesizing module axi_rdmatrix_4Mto1S
@N: CG179 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_4Mto1S.v":561:26:561:34|Removing redundant assignment
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_matrix_s.v":34:7:34:18|Synthesizing module axi_matrix_s
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":28:7:28:22|Synthesizing module axi_master_stage
@N: CG179 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_master_stage.v":2370:25:2370:33|Removing redundant assignment
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_slave_stage.v":29:7:29:21|Synthesizing module axi_slave_stage
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":362:7:362:12|Synthesizing module CLKINT
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":371:7:371:9|Synthesizing module VCC
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":367:7:367:9|Synthesizing module GND
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":722:7:722:9|Synthesizing module CCC
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\work\SF2_FDDR_INIT_BLK\CCC_0\SF2_FDDR_INIT_BLK_CCC_0_FCCC.v":5:7:5:34|Synthesizing module SF2_FDDR_INIT_BLK_CCC_0_FCCC
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\CoreSF2Config\3.0.100\rtl\vlog\core\coresf2config.v":21:7:21:19|Synthesizing module CoreSF2Config
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\CoreSF2Reset\3.0.100\rtl\vlog\core\coresf2reset.v":22:7:22:18|Synthesizing module CoreSF2Reset
@N: CL177 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\CoreSF2Reset\3.0.100\rtl\vlog\core\coresf2reset.v":659:4:659:9|Sharing sequential element M3_RESET_N.
@N: CL177 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\CoreSF2Reset\3.0.100\rtl\vlog\core\coresf2reset.v":421:4:421:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\CoreSF2Reset\3.0.100\rtl\vlog\core\coresf2reset.v":421:4:421:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\CoreSF2Reset\3.0.100\rtl\vlog\core\coresf2reset.v":421:4:421:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\work\SF2_FDDR_INIT_BLK\FABDDR_0\SF2_FDDR_INIT_BLK_FABDDR_0_FDDRC_syn.v":5:7:5:10|Synthesizing module FDDR
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":274:7:274:12|Synthesizing module OUTBUF
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":286:7:286:11|Synthesizing module BIBUF
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":326:7:326:17|Synthesizing module OUTBUF_DIFF
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":338:7:338:16|Synthesizing module BIBUF_DIFF
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":268:7:268:11|Synthesizing module INBUF
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\work\SF2_FDDR_INIT_BLK\FABDDR_0\SF2_FDDR_INIT_BLK_FABDDR_0_FDDRC.v":5:7:5:38|Synthesizing module SF2_FDDR_INIT_BLK_FABDDR_0_FDDRC
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\SgCore\OSC\1.0.101\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\SgCore\OSC\1.0.101\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\work\SF2_FDDR_INIT_BLK\FABOSC_0\SF2_FDDR_INIT_BLK_FABOSC_0_OSC.v":5:7:5:36|Synthesizing module SF2_FDDR_INIT_BLK_FABOSC_0_OSC
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\work\SF2_AXI_master_MSS\SF2_AXI_master_MSS_syn.v":5:7:5:13|Synthesizing module MSS_050
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\work\SF2_AXI_master_MSS\SF2_AXI_master_MSS.v":9:7:9:24|Synthesizing module SF2_AXI_master_MSS
@N: CG364 :"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v":713:7:713:14|Synthesizing module SYSRESET
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\work\SF2_FDDR_INIT_BLK\SF2_FDDR_INIT_BLK.v":9:7:9:23|Synthesizing module SF2_FDDR_INIT_BLK
@N: CG364 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\work\SF2_AXI_master_top\SF2_AXI_master_top.v":9:7:9:24|Synthesizing module SF2_AXI_master_top
@N: CL177 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\CoreSF2Reset\3.0.100\rtl\vlog\core\coresf2reset.v":421:4:421:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\CoreSF2Reset\3.0.100\rtl\vlog\core\coresf2reset.v":421:4:421:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\CoreSF2Reset\3.0.100\rtl\vlog\core\coresf2reset.v":421:4:421:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\CoreSF2Reset\3.0.100\rtl\vlog\core\coresf2reset.v":550:4:550:9|Trying to extract state machine for register sm0_state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\CoreSF2Config\3.0.100\rtl\vlog\core\coresf2config.v":323:4:323:9|Trying to extract state machine for register state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_ra_arbiter.v":217:3:217:8|Trying to extract state machine for register rd_curr_state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_wa_arbiter.v":209:3:209:8|Trying to extract state machine for register wr_curr_state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\component\Actel\DirectCore\COREAXI\3.0.112\rtl\vlog\core\axi_rdmatrix_16Sto1M.v":604:3:604:8|Trying to extract state machine for register curr_state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\hdl\AXI_MASTER_IF.v":223:0:223:5|Trying to extract state machine for register axi_fsm_read_state
@N: CL201 :"D:\Appsnotes\2014\AXI__update\design_file\Libero\FABRIC_AXI_master\hdl\AXI_MASTER_IF.v":98:0:98:5|Trying to extract state machine for register axi_fsm_write_state

