***************************************************************************
                               Status Report
                          Sat Jul 21 01:25:25 2012 ***************************************************************************

Product: Designer
Release: v10.0 SP2
Version: 10.0.20.2
File Name: C:\Actelprj\A2F_Webserver_uIPRTOS_SoftConsole_DF\Webserver_uIPRTOS_SC_DF\EVAL_KIT\SF_Webserver_Demo\designer\impl2\TOP.adb
Design Name: TOP  Design State: layout
Last Saved: Sat Jul 21 01:24:52 2012

***** Device Data **************************************************

Family: SmartFusion  Die: A2F200M3F  Package: 484 FBGA
Speed: -1  Voltage: 1.5

Restrict JTAG Pins: YES
Restrict Probe Pins: YES

Junction Temperature Range:   COM
Voltage Range:   COM

***** Import Variables *********************************************

Source File(s) Imported on Sat Jul 21 01:24:31 2012:
        C:\Actelprj\A2F_Webserver_uIPRTOS_SoftConsole_DF\Webserver_uIPRTOS_SC_DF\EVAL_KIT\SF_Webserver_Demo\synthesis\TOP.edn
        C:\Actelprj\A2F_Webserver_uIPRTOS_SoftConsole_DF\Webserver_uIPRTOS_SC_DF\EVAL_KIT\SF_Webserver_Demo\component\work\TOP\TOP.pdc


***** CAE Variables ************************************************

Back Annotation File: N/A


***** Bitstream Variables ******************************************

Bitstream File: N/A
     Lock Mode: OFF


***** Compile Variables ********************************************

Netlist PIN properties overwrite existing properties: 0

Compile Output:
=====================================================================
Parameters used to run compile:
===============================

Family      : SmartFusion
Device      : A2F200M3F
Package     : 484 FBGA
Source      :
C:\Actelprj\A2F_Webserver_uIPRTOS_SoftConsole_DF\Webserver_uIPRTOS_SC_DF\EVAL_KIT\SF_Webserver_\
Demo\synthesis\TOP.edn

C:\Actelprj\A2F_Webserver_uIPRTOS_SoftConsole_DF\Webserver_uIPRTOS_SC_DF\EVAL_KIT\SF_Webserver_\
Demo\component\work\TOP\TOP.pdc
Format      : EDIF
Topcell     : TOP
Speed grade : -1
Temp        : 0:25:85
Voltage     : 1.58:1.50:1.42

Keep Existing Physical Constraints : Yes
Keep Existing Timing Constraints   : Yes

pdc_abort_on_error                 : Yes
pdc_eco_display_unmatched_objects  : No
pdc_eco_max_warnings               : 10000

demote_globals                     : No
promote_globals                    : No
localclock_max_shared_instances    : 12
localclock_buffer_tree_max_fanout  : 12

combine_register                   : No
delete_buffer_tree                 : No

report_high_fanout_nets_limit      : 10

=====================================================================
Compile starts ...

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Warning: CMP201: Net Webserver_0/TXEV drives no load.
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Warning: CMP201: Net Webserver_0/VAREFOUT drives no load.
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Warning: CMP201: Net Webserver_0/MSS_CCC_0/I_MSSCCC_GLA drives no load.
Warning: CMP201: Net Webserver_0/MSS_CCC_0/I_MSSCCC_GLB drives no load.
Warning: CMP201: Net Webserver_0/MSS_CCC_0/I_MSSCCC_LOCK drives no load.
Warning: CMP201: Net Webserver_0/MSS_CCC_0/I_MSSCCC_YB drives no load.
Warning: CMP201: Net Webserver_0/MSS_CCC_0/I_MSSCCC_YC drives no load.

Netlist Optimization Report
===========================

Optimized macros:
  - Dangling net drivers:   0
  - Buffers:                11
  - Inverters:              0
  - Tieoff:                 0
  - Logic combining:        0

    Total macros optimized  11

There were 0 error(s) and 312 warning(s) in this design.
=====================================================================

Reading previous post-compile physical placement constraints.


There were 0 error(s) and 0 warning(s).

=====================================================================

Reading user pdc (Physical Design Constraints) file(s) postcompile


There were 0 error(s) and 0 warning(s) in reading the user pdc.

=====================================================================
Compile report:
===============

    Microcontroller Subsystem  Used:      1  Total:      1   (100.00%)
    Fabric                     Used:      0  Total:   4608   (0.00%)
    Fabric IO (W/ clocks)      Used:     12  Total:     94   (12.77%)
    Fabric Differential IO     Used:      0  Total:     47   (0.00%)
    Dedicated Analog IO        Used:      5  Total:     32   (15.63%)
    Dedicated MSS IO           Used:     18  Total:     43   (41.86%)
    GLOBAL (Chip+Quadrant)     Used:      0  Total:     15   (0.00%)
    MSS GLOBAL                 Used:      3  Total:      3   (100.00%)
    On-chip RC oscillator      Used:      0  Total:      1   (0.00%)
    Main Crystal oscillator    Used:      1  Total:      1   (100.00%)
    32 KHz Crystal oscillator  Used:      0  Total:      1   (0.00%)
    RAM/FIFO                   Used:      0  Total:      8   (0.00%)
    User JTAG                  Used:      0  Total:      1   (0.00%)

Global Information:

    Type            | Used   | Total
    ----------------|--------|--------------
    Chip global     | 0      | 3  (0.00%)*
    Quadrant global | 0      | 12 (0.00%)
    MSS global      | 3      | 3  (100.00%)

    (*) Chip globals may be assigned to Quadrant globals using the Multi-View Navigator (MVN)
        or Physical Design Constraints (PDC).
        They may also be assigned to Quadrant globals automatically during Layout.

Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 0            | 0
    SEQ     | 0            | 0

I/O Function:

    Type                          | w/o register  | w/ register  | w/ DDR register
    ------------------------------|---------------|--------------|----------------
    Input I/O                     | 2             | 0            | 0
    Output I/O                    | 10            | 0            | 0
    Bidirectional I/O             | 0             | 0            | 0
    Differential Input I/O Pairs  | 0             | 0            | 0
    Differential Output I/O Pairs | 0             | 0            | 0

I/O Technology:

                                    |   Voltages    |             I/Os
    --------------------------------|-------|-------|-------|--------|--------------
    I/O Standard(s)                 | Vcci  | Vref  | Input | Output | Bidirectional
    --------------------------------|-------|-------|-------|--------|--------------
    LVTTL                           | 3.30v | N/A   | 2     | 10     | 0

I/O Placement:

    Locked  :  12 ( 100.00% )
    Placed  :   0
    UnPlaced:   0

Net information report:
=======================

The following nets have been assigned to a chip global resource:
    Fanout  Type          Name
    --------------------------
    1       INT_NET       Net   : GLC_c
                          Driver: Webserver_0/MSS_CCC_0/I_MSSCCC
                          Source: ESSENTIAL

High fanout nets in the post compile netlist:
    Fanout  Type          Name
    --------------------------
    1       INT_NET       Net   : F2M_GPI_8_c
                          Driver: F2M_GPI_8_pad
    1       INT_NET       Net   : F2M_GPI_9_c
                          Driver: F2M_GPI_9_pad
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_4_A
                          Driver: Webserver_0/MSS_ADLIB_INST
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_3_A
                          Driver: Webserver_0/MSS_ADLIB_INST
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_0_A
                          Driver: Webserver_0/MSS_ADLIB_INST
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_1_A
                          Driver: Webserver_0/MSS_ADLIB_INST
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_2_A
                          Driver: Webserver_0/MSS_ADLIB_INST
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_5_A
                          Driver: Webserver_0/MSS_ADLIB_INST
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_6_A
                          Driver: Webserver_0/MSS_ADLIB_INST
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_7_A
                          Driver: Webserver_0/MSS_ADLIB_INST

Nets that are candidates for clock assignment and the resulting fanout:
    Fanout  Type          Name
    --------------------------
    1       INT_NET       Net   : F2M_GPI_8_c
                          Driver: F2M_GPI_8_pad
    1       INT_NET       Net   : F2M_GPI_9_c
                          Driver: F2M_GPI_9_pad
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_4_A
                          Driver: Webserver_0/MSS_ADLIB_INST
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_3_A
                          Driver: Webserver_0/MSS_ADLIB_INST
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_0_A
                          Driver: Webserver_0/MSS_ADLIB_INST
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_1_A
                          Driver: Webserver_0/MSS_ADLIB_INST
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_2_A
                          Driver: Webserver_0/MSS_ADLIB_INST
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_5_A
                          Driver: Webserver_0/MSS_ADLIB_INST
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_6_A
                          Driver: Webserver_0/MSS_ADLIB_INST
    1       INT_NET       Net   : Webserver_0/MSSINT_GPO_7_A
                          Driver: Webserver_0/MSS_ADLIB_INST


Layout Output:
***** Layout Variables *********************************************

Mode: TIMING_DRIVEN
Power-driven Layout: OFF
Incremental Placement: OFF
Incremental Route: OFF


Info: I/O Bank Assigner detected (1) out of (6) I/O Bank(s) with locked I/O technologies.

Running I/O Bank Assigner.

I/O Bank Assigner completed successfully.


Planning global net placement...


Global net placement completed successfully.


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Timing-driven Placer Started: Sat Jul 21 01:25:06 2012



Placer Finished: Sat Jul 21 01:25:08 2012

Total Placer CPU Time:     00:00:02



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Timing-driven Router 

Design: TOP                             Started: Sat Jul 21 01:25:13 2012



 



Timing-driven Router completed successfully.



Design: TOP                             

Finished: Sat Jul 21 01:25:19 2012

Total CPU Time:     00:00:06            Total Elapsed Time: 00:00:06

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