@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
@N: MF547 |Generated clock conversion disabled 
@N: MF239 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corei2c\7.0.102\rtl\vhdl\core_obfuscated\corei2c.vhd":158:10:158:17|Found 13-bit decrementor, 'un7_ci2co0[12:0]'
@N: MO106 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corei2c\7.0.102\rtl\vhdl\core_obfuscated\corei2creal.vhd":498:0:498:3|Found ROM, 'CI2Co00I\.CI2COi1l_31[4:0]', 29 words by 5 bits 
@N: MF176 |Default generator successful 
@N: MF179 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":245:5:245:33|Found 16 bit by 16 bit '<' comparator, 'CPWMi0ll\.1\.un1_period_cnt'
@N: MF179 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":245:5:245:33|Found 16 bit by 16 bit '<' comparator, 'CPWMi0ll\.1\.un1_period_cnt'
@N: BN115 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":245:5:245:33|Removing instance CPWMi0ll\.1\.un1_period_cnt_2 of view:VhdlGenLib.CMP_LT__w16(fcomp) because there are no references to its outputs 
@N: MF179 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\timebase.vhd":48:5:48:26|Found 16 bit by 16 bit '<' comparator, 'un1_CPWMoooi'
@N: MF179 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\timebase.vhd":56:23:56:46|Found 16 bit by 16 bit '<' comparator, 'sync_pulse'
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: BN362 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":49:0:49:1|Removing sequential instance MPM_PWM_Trimming_Outputs.CPWMLLOL\.CPWMilol.CPWMLIOL\.3\.CPWMiiol\.CPWMi[3] of view:PrimLib.dffr(prim) in hierarchy view:work.SmartFusion_MPM_Reference_Design(def_arch) because there are no references to its outputs 
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
