@W: CD434 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":909:17:909:21|Signal paddr in the sensitivity list is not used in the process
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.31.CGPIOI1I.CGPIOOLL_127(31)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.31.CGPIOI1I.CGPIOlll_127(31)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.31.CGPIOI1I.CGPIOIOL_127(31)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.30.CGPIOI1I.CGPIOOLL_123(30)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.30.CGPIOI1I.CGPIOlll_123(30)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.30.CGPIOI1I.CGPIOIOL_123(30)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.29.CGPIOI1I.CGPIOOLL_119(29)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.29.CGPIOI1I.CGPIOlll_119(29)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.29.CGPIOI1I.CGPIOIOL_119(29)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.28.CGPIOI1I.CGPIOOLL_115(28)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.28.CGPIOI1I.CGPIOlll_115(28)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.28.CGPIOI1I.CGPIOIOL_115(28)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.27.CGPIOI1I.CGPIOOLL_111(27)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.27.CGPIOI1I.CGPIOlll_111(27)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.27.CGPIOI1I.CGPIOIOL_111(27)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.26.CGPIOI1I.CGPIOOLL_107(26)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.26.CGPIOI1I.CGPIOlll_107(26)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.26.CGPIOI1I.CGPIOIOL_107(26)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.25.CGPIOI1I.CGPIOOLL_103(25)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.25.CGPIOI1I.CGPIOlll_103(25)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.25.CGPIOI1I.CGPIOIOL_103(25)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.24.CGPIOI1I.CGPIOOLL_99(24)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.24.CGPIOI1I.CGPIOlll_99(24)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.24.CGPIOI1I.CGPIOIOL_99(24)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.23.CGPIOI1I.CGPIOOLL_95(23)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.23.CGPIOI1I.CGPIOlll_95(23)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.23.CGPIOI1I.CGPIOIOL_95(23)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.22.CGPIOI1I.CGPIOOLL_91(22)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.22.CGPIOI1I.CGPIOlll_91(22)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.22.CGPIOI1I.CGPIOIOL_91(22)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.21.CGPIOI1I.CGPIOOLL_87(21)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.21.CGPIOI1I.CGPIOlll_87(21)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.21.CGPIOI1I.CGPIOIOL_87(21)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.20.CGPIOI1I.CGPIOOLL_83(20)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.20.CGPIOI1I.CGPIOlll_83(20)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.20.CGPIOI1I.CGPIOIOL_83(20)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.19.CGPIOI1I.CGPIOOLL_79(19)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.19.CGPIOI1I.CGPIOlll_79(19)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.19.CGPIOI1I.CGPIOIOL_79(19)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.18.CGPIOI1I.CGPIOOLL_75(18)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.18.CGPIOI1I.CGPIOlll_75(18)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.18.CGPIOI1I.CGPIOIOL_75(18)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.17.CGPIOI1I.CGPIOOLL_71(17)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.17.CGPIOI1I.CGPIOlll_71(17)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.17.CGPIOI1I.CGPIOIOL_71(17)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.16.CGPIOI1I.CGPIOOLL_67(16)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.16.CGPIOI1I.CGPIOlll_67(16)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.16.CGPIOI1I.CGPIOIOL_67(16)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.15.CGPIOI1I.CGPIOOLL_63(15)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.15.CGPIOI1I.CGPIOlll_63(15)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.15.CGPIOI1I.CGPIOIOL_63(15)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.14.CGPIOI1I.CGPIOOLL_59(14)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.14.CGPIOI1I.CGPIOlll_59(14)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.14.CGPIOI1I.CGPIOIOL_59(14)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.13.CGPIOI1I.CGPIOOLL_55(13)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.13.CGPIOI1I.CGPIOlll_55(13)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.13.CGPIOI1I.CGPIOIOL_55(13)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.12.CGPIOI1I.CGPIOOLL_51(12)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.12.CGPIOI1I.CGPIOlll_51(12)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.12.CGPIOI1I.CGPIOIOL_51(12)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.11.CGPIOI1I.CGPIOOLL_47(11)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.11.CGPIOI1I.CGPIOlll_47(11)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.11.CGPIOI1I.CGPIOIOL_47(11)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.10.CGPIOI1I.CGPIOOLL_43(10)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.10.CGPIOI1I.CGPIOlll_43(10)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.10.CGPIOI1I.CGPIOIOL_43(10)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.9.CGPIOI1I.CGPIOOLL_39(9)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.9.CGPIOI1I.CGPIOlll_39(9)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.9.CGPIOI1I.CGPIOIOL_39(9)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.8.CGPIOI1I.CGPIOOLL_35(8)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.8.CGPIOI1I.CGPIOlll_35(8)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.8.CGPIOI1I.CGPIOIOL_35(8)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.7.CGPIOI1I.CGPIOOLL_31(7)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.7.CGPIOI1I.CGPIOlll_31(7)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.7.CGPIOI1I.CGPIOIOL_31(7)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.6.CGPIOI1I.CGPIOOLL_27(6)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.6.CGPIOI1I.CGPIOlll_27(6)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.6.CGPIOI1I.CGPIOIOL_27(6)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.5.CGPIOI1I.CGPIOOLL_23(5)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.5.CGPIOI1I.CGPIOlll_23(5)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.5.CGPIOI1I.CGPIOIOL_23(5)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.4.CGPIOI1I.CGPIOOLL_19(4)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.4.CGPIOI1I.CGPIOlll_19(4)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.4.CGPIOI1I.CGPIOIOL_19(4)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.3.CGPIOI1I.CGPIOOLL_15(3)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.3.CGPIOI1I.CGPIOlll_15(3)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.3.CGPIOI1I.CGPIOIOL_15(3)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.2.CGPIOI1I.CGPIOOLL_11(2)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.2.CGPIOI1I.CGPIOlll_11(2)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.2.CGPIOI1I.CGPIOIOL_11(2)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.1.CGPIOI1I.CGPIOOLL_7(1)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.1.CGPIOI1I.CGPIOlll_7(1)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.1.CGPIOI1I.CGPIOIOL_7(1)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":327:7:327:14|Pruning register CGPIOiOI.0.CGPIOI1I.CGPIOOLL_3(0)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":329:7:329:14|Pruning register CGPIOiOI.0.CGPIOI1I.CGPIOlll_3(0)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":325:7:325:14|Pruning register CGPIOiOI.0.CGPIOI1I.CGPIOIOL_3(0)  
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.0.CGPIOI1I.CGPIOii(0) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.1.CGPIOI1I.CGPIOii(1) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.2.CGPIOI1I.CGPIOii(2) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.3.CGPIOI1I.CGPIOii(3) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.4.CGPIOI1I.CGPIOii(4) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.5.CGPIOI1I.CGPIOii(5) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.6.CGPIOI1I.CGPIOii(6) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.7.CGPIOI1I.CGPIOii(7) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.8.CGPIOI1I.CGPIOii(8) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.9.CGPIOI1I.CGPIOii(9) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.10.CGPIOI1I.CGPIOii(10) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.11.CGPIOI1I.CGPIOii(11) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.12.CGPIOI1I.CGPIOii(12) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.13.CGPIOI1I.CGPIOii(13) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.14.CGPIOI1I.CGPIOii(14) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.15.CGPIOI1I.CGPIOii(15) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.16.CGPIOI1I.CGPIOii(16) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.17.CGPIOI1I.CGPIOii(17) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.18.CGPIOI1I.CGPIOii(18) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.19.CGPIOI1I.CGPIOii(19) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.20.CGPIOI1I.CGPIOii(20) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.21.CGPIOI1I.CGPIOii(21) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.22.CGPIOI1I.CGPIOii(22) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.23.CGPIOI1I.CGPIOii(23) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.24.CGPIOI1I.CGPIOii(24) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.25.CGPIOI1I.CGPIOii(25) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.26.CGPIOI1I.CGPIOii(26) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.27.CGPIOI1I.CGPIOii(27) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.28.CGPIOI1I.CGPIOii(28) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.29.CGPIOI1I.CGPIOii(29) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.30.CGPIOI1I.CGPIOii(30) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.31.CGPIOI1I.CGPIOii(31) to a constant 0
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(0)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(1)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(2)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(3)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(4)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(5)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(6)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(7)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(8)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(9)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(10)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(11)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(12)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(13)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(14)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(15)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(16)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(17)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(18)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(19)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(20)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(21)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(22)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(23)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(24)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(25)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(26)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(27)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(28)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(29)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(30)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(31)  
@W: CD434 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":909:17:909:21|Signal paddr in the sensitivity list is not used in the process
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.31.CGPIOI1I.CGPIOOLL_127(31)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.31.CGPIOI1I.CGPIOlll_127(31)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.31.CGPIOI1I.CGPIOIOL_127(31)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.30.CGPIOI1I.CGPIOOLL_123(30)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.30.CGPIOI1I.CGPIOlll_123(30)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.30.CGPIOI1I.CGPIOIOL_123(30)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.29.CGPIOI1I.CGPIOOLL_119(29)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.29.CGPIOI1I.CGPIOlll_119(29)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.29.CGPIOI1I.CGPIOIOL_119(29)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.28.CGPIOI1I.CGPIOOLL_115(28)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.28.CGPIOI1I.CGPIOlll_115(28)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.28.CGPIOI1I.CGPIOIOL_115(28)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.27.CGPIOI1I.CGPIOOLL_111(27)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.27.CGPIOI1I.CGPIOlll_111(27)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.27.CGPIOI1I.CGPIOIOL_111(27)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.26.CGPIOI1I.CGPIOOLL_107(26)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.26.CGPIOI1I.CGPIOlll_107(26)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.26.CGPIOI1I.CGPIOIOL_107(26)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.25.CGPIOI1I.CGPIOOLL_103(25)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.25.CGPIOI1I.CGPIOlll_103(25)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.25.CGPIOI1I.CGPIOIOL_103(25)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.24.CGPIOI1I.CGPIOOLL_99(24)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.24.CGPIOI1I.CGPIOlll_99(24)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.24.CGPIOI1I.CGPIOIOL_99(24)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.23.CGPIOI1I.CGPIOOLL_95(23)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.23.CGPIOI1I.CGPIOlll_95(23)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.23.CGPIOI1I.CGPIOIOL_95(23)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.22.CGPIOI1I.CGPIOOLL_91(22)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.22.CGPIOI1I.CGPIOlll_91(22)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.22.CGPIOI1I.CGPIOIOL_91(22)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.21.CGPIOI1I.CGPIOOLL_87(21)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.21.CGPIOI1I.CGPIOlll_87(21)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.21.CGPIOI1I.CGPIOIOL_87(21)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.20.CGPIOI1I.CGPIOOLL_83(20)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.20.CGPIOI1I.CGPIOlll_83(20)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.20.CGPIOI1I.CGPIOIOL_83(20)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.19.CGPIOI1I.CGPIOOLL_79(19)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.19.CGPIOI1I.CGPIOlll_79(19)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.19.CGPIOI1I.CGPIOIOL_79(19)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.18.CGPIOI1I.CGPIOOLL_75(18)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.18.CGPIOI1I.CGPIOlll_75(18)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.18.CGPIOI1I.CGPIOIOL_75(18)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.17.CGPIOI1I.CGPIOOLL_71(17)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.17.CGPIOI1I.CGPIOlll_71(17)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.17.CGPIOI1I.CGPIOIOL_71(17)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.16.CGPIOI1I.CGPIOOLL_67(16)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.16.CGPIOI1I.CGPIOlll_67(16)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.16.CGPIOI1I.CGPIOIOL_67(16)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.15.CGPIOI1I.CGPIOOLL_63(15)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.15.CGPIOI1I.CGPIOlll_63(15)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.15.CGPIOI1I.CGPIOIOL_63(15)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.14.CGPIOI1I.CGPIOOLL_59(14)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.14.CGPIOI1I.CGPIOlll_59(14)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.14.CGPIOI1I.CGPIOIOL_59(14)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.13.CGPIOI1I.CGPIOOLL_55(13)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.13.CGPIOI1I.CGPIOlll_55(13)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.13.CGPIOI1I.CGPIOIOL_55(13)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.12.CGPIOI1I.CGPIOOLL_51(12)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.12.CGPIOI1I.CGPIOlll_51(12)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.12.CGPIOI1I.CGPIOIOL_51(12)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.11.CGPIOI1I.CGPIOOLL_47(11)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.11.CGPIOI1I.CGPIOlll_47(11)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.11.CGPIOI1I.CGPIOIOL_47(11)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.10.CGPIOI1I.CGPIOOLL_43(10)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.10.CGPIOI1I.CGPIOlll_43(10)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.10.CGPIOI1I.CGPIOIOL_43(10)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.9.CGPIOI1I.CGPIOOLL_39(9)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.9.CGPIOI1I.CGPIOlll_39(9)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.9.CGPIOI1I.CGPIOIOL_39(9)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.8.CGPIOI1I.CGPIOOLL_35(8)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.8.CGPIOI1I.CGPIOlll_35(8)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.8.CGPIOI1I.CGPIOIOL_35(8)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.7.CGPIOI1I.CGPIOOLL_31(7)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.7.CGPIOI1I.CGPIOlll_31(7)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.7.CGPIOI1I.CGPIOIOL_31(7)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.6.CGPIOI1I.CGPIOOLL_27(6)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.6.CGPIOI1I.CGPIOlll_27(6)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.6.CGPIOI1I.CGPIOIOL_27(6)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.5.CGPIOI1I.CGPIOOLL_23(5)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.5.CGPIOI1I.CGPIOlll_23(5)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.5.CGPIOI1I.CGPIOIOL_23(5)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.4.CGPIOI1I.CGPIOOLL_19(4)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.4.CGPIOI1I.CGPIOlll_19(4)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.4.CGPIOI1I.CGPIOIOL_19(4)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.3.CGPIOI1I.CGPIOOLL_15(3)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.3.CGPIOI1I.CGPIOlll_15(3)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.3.CGPIOI1I.CGPIOIOL_15(3)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.2.CGPIOI1I.CGPIOOLL_11(2)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.2.CGPIOI1I.CGPIOlll_11(2)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.2.CGPIOI1I.CGPIOIOL_11(2)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":546:0:546:17|Pruning register CGPIOiOI.1.CGPIOI1I.CGPIOOLL_7(1)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":526:0:526:17|Pruning register CGPIOiOI.1.CGPIOI1I.CGPIOlll_7(1)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":506:0:506:17|Pruning register CGPIOiOI.1.CGPIOI1I.CGPIOIOL_7(1)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":327:7:327:14|Pruning register CGPIOiOI.0.CGPIOI1I.CGPIOOLL_3(0)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":329:7:329:14|Pruning register CGPIOiOI.0.CGPIOI1I.CGPIOlll_3(0)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":325:7:325:14|Pruning register CGPIOiOI.0.CGPIOI1I.CGPIOIOL_3(0)  
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.0.CGPIOI1I.CGPIOii(0) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.1.CGPIOI1I.CGPIOii(1) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.2.CGPIOI1I.CGPIOii(2) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.3.CGPIOI1I.CGPIOii(3) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.4.CGPIOI1I.CGPIOii(4) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.5.CGPIOI1I.CGPIOii(5) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.6.CGPIOI1I.CGPIOii(6) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.7.CGPIOI1I.CGPIOii(7) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.8.CGPIOI1I.CGPIOii(8) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.9.CGPIOI1I.CGPIOii(9) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.10.CGPIOI1I.CGPIOii(10) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.11.CGPIOI1I.CGPIOii(11) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.12.CGPIOI1I.CGPIOii(12) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.13.CGPIOI1I.CGPIOii(13) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.14.CGPIOI1I.CGPIOii(14) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.15.CGPIOI1I.CGPIOii(15) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.16.CGPIOI1I.CGPIOii(16) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.17.CGPIOI1I.CGPIOii(17) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.18.CGPIOI1I.CGPIOii(18) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.19.CGPIOI1I.CGPIOii(19) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.20.CGPIOI1I.CGPIOii(20) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.21.CGPIOI1I.CGPIOii(21) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.22.CGPIOI1I.CGPIOii(22) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.23.CGPIOI1I.CGPIOii(23) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.24.CGPIOI1I.CGPIOii(24) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.25.CGPIOI1I.CGPIOii(25) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.26.CGPIOI1I.CGPIOii(26) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.27.CGPIOI1I.CGPIOii(27) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.28.CGPIOI1I.CGPIOii(28) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.29.CGPIOI1I.CGPIOii(29) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.30.CGPIOI1I.CGPIOii(30) to a constant 0
@W: CL190 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Optimizing register bit CGPIOiOI.31.CGPIOI1I.CGPIOii(31) to a constant 0
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(0)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(1)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(2)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(3)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(4)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(5)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(6)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(7)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(8)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(9)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(10)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(11)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(12)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(13)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(14)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(15)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(16)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(17)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(18)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(19)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(20)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(21)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(22)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(23)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(24)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(25)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(26)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(27)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(28)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(29)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(30)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":568:0:568:1|Pruning register CGPIOii(31)  
@W: CD638 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Signal cpwmol is undriven 
@W: CD638 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":260:7:260:12|Signal cpwmll is undriven 
@W: CD638 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":262:7:262:15|Signal tach_edge is undriven 
@W: CD638 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":264:7:264:12|Signal cpwmil is undriven 
@W: CD638 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":266:7:266:12|Signal cpwmoi is undriven 
@W: CD638 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":270:7:270:12|Signal cpwmli is undriven 
@W: CD638 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":272:7:272:14|Signal tachmode is undriven 
@W: CD638 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":276:7:276:12|Signal cpwmii is undriven 
@W: CD638 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":278:7:278:12|Signal cpwmo0 is undriven 
@W: CD638 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":280:7:280:12|Signal cpwml0 is undriven 
@W: CD638 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":282:7:282:18|Signal tach_cnt_clk is undriven 
@W: CD638 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":284:7:284:18|Signal tachpulsedur is undriven 
@W: CD638 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":286:7:286:19|Signal update_status is undriven 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 34 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 35 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 36 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 37 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 38 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 39 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 40 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 41 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 42 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 43 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 44 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 45 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 46 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 47 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 48 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 49 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":34:7:34:14|Bit 50 of signal cpwmoiol is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CG296 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":355:0:355:6|Incomplete sensitivity list - assuming completeness
@W: CG290 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":371:22:371:32|Referenced variable pwm_stretch is not in sensitivity list
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":90:7:90:25|Bit 3 of signal pwm_enable_out_wire is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":90:7:90:25|Bit 4 of signal pwm_enable_out_wire is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":90:7:90:25|Bit 5 of signal pwm_enable_out_wire is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":90:7:90:25|Bit 6 of signal pwm_enable_out_wire is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":90:7:90:25|Bit 7 of signal pwm_enable_out_wire is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":90:7:90:25|Bit 8 of signal pwm_enable_out_wire is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":90:7:90:25|Bit 9 of signal pwm_enable_out_wire is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":90:7:90:25|Bit 10 of signal pwm_enable_out_wire is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":90:7:90:25|Bit 11 of signal pwm_enable_out_wire is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":90:7:90:25|Bit 12 of signal pwm_enable_out_wire is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":90:7:90:25|Bit 13 of signal pwm_enable_out_wire is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":90:7:90:25|Bit 14 of signal pwm_enable_out_wire is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":90:7:90:25|Bit 15 of signal pwm_enable_out_wire is undriven.  Possible simulation mismatch as initial value or default value is ignored.  To avoid simulation mismatches, explicitly drive this bit. 
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":238:0:238:1|Pruning register pwm_enable_reg(16 downto 1)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":184:0:184:1|Pruning register CPWMi0ll.3.pwm_negedge_rEG_20(48 downto 33)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":184:0:184:1|Pruning register CPWMi0ll.3.pwm_posedgE_REG_20(48 downto 33)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":184:0:184:1|Pruning register CPWMi0ll.2.pwm_negedge_rEG_13(32 downto 17)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":184:0:184:1|Pruning register CPWMi0ll.2.pwm_posedgE_REG_13(32 downto 17)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":184:0:184:1|Pruning register CPWMi0ll.1.pwm_negedge_rEG_6(16 downto 1)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":184:0:184:1|Pruning register CPWMi0ll.1.pwm_posedgE_REG_6(16 downto 1)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":111:0:111:1|Pruning register CPWMolll(16 downto 9)  
@W: CL271 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":111:0:111:1|Pruning bits 8 to 4 of CPWMIOll(8 downto 1) -- not in use ... 
@W: CL240 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":286:7:286:19|UPDATE_STATUS is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 0 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 1 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 2 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 3 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 4 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 5 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 6 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 7 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 8 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 9 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 10 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 11 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 12 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 13 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 14 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL252 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":258:7:258:12|Bit 15 of signal CPWMol is floating -- simulation mismatch possible.
@W: CL240 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":165:0:165:6|TAchint is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":510:0:510:1|Pruning register STATUS_CLEAR(0)  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":510:0:510:1|Pruning register taCHSTATUS(0)  
@W: CD638 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vhdl\core_obfuscated\corei2c.vhd":132:7:132:12|Signal ci2cl1 is undriven 
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vhdl\core_obfuscated\corei2c.vhd":168:0:168:1|Pruning register CI2CI0  
@W: CL169 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vhdl\core_obfuscated\corei2c.vhd":168:0:168:1|Pruning register CI2CL0  
@W: CD604 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":439:0:439:13|OTHERS clause is not synthesized 
@W: CD604 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3_muxptob3.vhd":152:0:152:13|OTHERS clause is not synthesized 
@W: CD604 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3_muxptob3.vhd":195:0:195:13|OTHERS clause is not synthesized 
@W: CD604 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3_muxptob3.vhd":238:0:238:13|OTHERS clause is not synthesized 
@W: CL240 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":38:10:38:21|LPXIN_CLKOUT is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL240 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":37:10:37:23|MAINXIN_CLKOUT is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL240 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":36:10:36:21|RCOSC_CLKOUT is not assigned a value (floating) -- simulation mismatch possible. 
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":10:10:10:13|Input CLKA is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":11:10:11:17|Input CLKA_PAD is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":12:10:12:18|Input CLKA_PADP is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":13:10:13:18|Input CLKA_PADN is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":14:10:14:13|Input CLKB is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":15:10:15:17|Input CLKB_PAD is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":16:10:16:18|Input CLKB_PADP is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":17:10:17:18|Input CLKB_PADN is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":18:10:18:13|Input CLKC is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":19:10:19:17|Input CLKC_PAD is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":20:10:20:18|Input CLKC_PADP is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":21:10:21:18|Input CLKC_PADN is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":22:10:22:16|Input MAINXIN is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":23:10:23:14|Input LPXIN is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SF_MPM_RefDesign_MSS\MSS_CCC_0\SF_MPM_RefDesign_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd":24:10:24:16|Input MAC_CLK is unused
@W: CL246 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":35:0:35:4|Input port bits 23 to 13 of paddr(23 downto 0) are unused 
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":33:52:33:58|Input presetn is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":34:0:34:3|Input pclk is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":68:0:68:7|Input PRDATAS4 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":69:0:69:7|Input PRDATAS5 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":70:0:70:7|Input PRDATAS6 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":71:0:71:7|Input PRDATAS7 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":72:0:72:7|Input PRDATAS8 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":73:0:73:7|Input PRDATAS9 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":74:0:74:8|Input PRDATAS10 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":75:0:75:8|Input PRDATAS11 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":76:0:76:8|Input PRDATAS12 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":77:0:77:8|Input PRDATAS13 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":78:0:78:8|Input PRDATAS14 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":79:0:79:8|Input PRDATAS15 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":84:0:84:7|Input preadys4 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":85:0:85:7|Input PREADYs5 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":86:0:86:7|Input preadyS6 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":87:0:87:7|Input PREadys7 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":88:0:88:7|Input pREADYS8 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":89:0:89:7|Input preADYS9 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":90:0:90:8|Input preadys10 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":91:0:91:8|Input preaDYS11 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":92:0:92:8|Input PREADYS12 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":93:0:93:8|Input PREadys13 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":94:0:94:8|Input preADYS14 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":95:0:95:8|Input PREAdys15 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":100:0:100:8|Input pSLVERRS4 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":101:0:101:8|Input PSLVERRS5 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":102:0:102:8|Input PSLVERRS6 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":103:0:103:8|Input pslvERRS7 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":104:0:104:8|Input pslverrs8 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":105:0:105:8|Input PSLVERRS9 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":106:0:106:9|Input PSLVERRS10 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":107:0:107:9|Input pslverRS11 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":108:0:108:9|Input PSLverrs12 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":109:0:109:9|Input PSLVERRS13 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":110:0:110:9|Input pslverrs14 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd":111:0:111:9|Input pSLVERRS15 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vhdl\core_obfuscated\corei2creal.vhd":33:0:33:10|Input sERAdr1APb0 is unused
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vhdl\core_obfuscated\corei2c.vhd":30:0:30:3|Input bclk is unused
@W: CL246 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\pwm_gen.vhd":25:0:25:14|Input port bits 32 to 1 of pwm_posedge_reg(48 downto 1) are unused 
@W: CL246 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":159:0:159:4|Input port bits 1 to 0 of paddr(7 downto 0) are unused 
@W: CL159 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\corepwm.vhd":164:0:164:5|Input tACHIN is unused
@W: CL246 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":158:0:158:6|Input port bits 31 to 6 of gpio_in(31 downto 0) are unused 
@W: CL246 :"C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":158:0:158:6|Input port bits 4 to 0 of gpio_in(31 downto 0) are unused 

