Timing Report Min Delay Analysis

SmartTime Version v10.0 SP2
Actel Corporation - Actel Designer Software Release v10.0 SP2 (Version 10.0.20.2)
Copyright (c) 1989-2012
Date: Fri Jun 29 16:41:25 2012


Design: SmartFusion_MPM_Reference_Design
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.434
External Hold (ns):         4.176
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                27.354
Frequency (MHz):            36.558
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        0.163
External Hold (ns):         2.591
Min Clock-To-Out (ns):      5.908
Max Clock-To-Out (ns):      16.247

Clock Domain:               \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                25.925
Frequency (MHz):            38.573
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        1.437
External Hold (ns):         3.129
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.277
  Slack (ns):
  Arrival (ns):                0.277
  Required (ns):
  Hold (ns):                   1.358
  External Hold (ns):          4.176


Expanded Path 1
  From: MSS_RESET_N
  To: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.277
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        \\SF_MPM_RefDesign_MSS\\/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_RESET_0_MSS_RESET_N_Y
  0.277                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.277                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.371          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST_FCLK
  N/C                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.358          Library hold time: ADLIB:MSS_APB_IP
  N/C                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_glb to mss_ccc_gla0

Path 1
  From:                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cll1L[3]:CLK
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FABINT
  Delay (ns):                  1.054
  Slack (ns):                  0.856
  Arrival (ns):                5.192
  Required (ns):               4.336
  Hold (ns):                   1.241


Expanded Path 1
  From: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cll1L[3]:CLK
  To: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FABINT
  data arrival time                              5.192
  data required time                         -   4.336
  slack                                          0.856
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.451          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  4.138                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cll1L[3]:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.387                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cll1L[3]:Q (r)
               +     0.554          net: MPM_PMBus_I2C_INT
  4.941                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_60:PIN5 (r)
               +     0.037          cell: ADLIB:MSS_IF
  4.978                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_60:PIN5INT (r)
               +     0.214          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/FABINTINT_NET
  5.192                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FABINT (r)
                                    
  5.192                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.371          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST_FCLK
  3.095                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.241          Library hold time: ADLIB:MSS_APB_IP
  4.336                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FABINT
                                    
  4.336                        data required time


END SET mss_ccc_glb to mss_ccc_gla0

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cli1L/U1:CLK
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CioOI:D
  Delay (ns):                  0.399
  Slack (ns):                  0.356
  Arrival (ns):                4.520
  Required (ns):               4.164
  Hold (ns):                   0.000

Path 2
  From:                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CI0oi:CLK
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Co1OI:D
  Delay (ns):                  0.395
  Slack (ns):                  0.358
  Arrival (ns):                4.482
  Required (ns):               4.124
  Hold (ns):                   0.000

Path 3
  From:                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CioOI:CLK
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2COloI:D
  Delay (ns):                  0.399
  Slack (ns):                  0.396
  Arrival (ns):                4.520
  Required (ns):               4.124
  Hold (ns):                   0.000

Path 4
  From:                        MPM_PWM_Trimming_Outputs/CPWMI11.CPWMOOOL/CPWMi11l[11]:CLK
  To:                          MPM_PWM_Trimming_Outputs/CPWMI11.CPWMOOOL/CPWMi11l[11]:D
  Delay (ns):                  0.687
  Slack (ns):                  0.667
  Arrival (ns):                4.691
  Required (ns):               4.024
  Hold (ns):                   0.000

Path 5
  From:                        MPM_PWM_Trimming_Outputs/CPWMI11.CPWMOOOL/CPWMi11l[3]:CLK
  To:                          MPM_PWM_Trimming_Outputs/CPWMI11.CPWMOOOL/CPWMi11l[3]:D
  Delay (ns):                  0.693
  Slack (ns):                  0.677
  Arrival (ns):                4.674
  Required (ns):               3.997
  Hold (ns):                   0.000


Expanded Path 1
  From: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cli1L/U1:CLK
  To: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CioOI:D
  data arrival time                              4.520
  data required time                         -   4.164
  slack                                          0.356
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.434          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  4.121                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cli1L/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.370                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cli1L/U1:Q (r)
               +     0.150          net: MPM_PMBus_I2C/CI2CO0l_0_Ui2C/CI2Cli1L
  4.520                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CioOI:D (r)
                                    
  4.520                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.477          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  4.164                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CioOI:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.164                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CioOI:D
                                    
  4.164                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MPM_PMBus_SMBALERT
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CI0oi:D
  Delay (ns):                  1.576
  Slack (ns):
  Arrival (ns):                1.576
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          2.591

Path 2
  From:                        MPM_PMBus_SDA
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Ci1oI[0]:D
  Delay (ns):                  2.399
  Slack (ns):
  Arrival (ns):                2.399
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          1.833

Path 3
  From:                        MPM_PMBus_SCL
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CLOLi[0]:D
  Delay (ns):                  2.519
  Slack (ns):
  Arrival (ns):                2.519
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          1.671


Expanded Path 1
  From: MPM_PMBus_SMBALERT
  To: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CI0oi:D
  data arrival time                              1.576
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MPM_PMBus_SMBALERT (f)
               +     0.000          net: MPM_PMBus_SMBALERT
  0.000                        MPM_PMBus_SMBALERT_BIBUF/U0/U0:PAD (f)
               +     0.293          cell: ADLIB:IOPAD_BI
  0.293                        MPM_PMBus_SMBALERT_BIBUF/U0/U0:Y (f)
               +     0.000          net: MPM_PMBus_SMBALERT_BIBUF/U0/NET3
  0.293                        MPM_PMBus_SMBALERT_BIBUF/U0/U1:YIN (f)
               +     0.017          cell: ADLIB:IOBI_IB_OB_EB
  0.310                        MPM_PMBus_SMBALERT_BIBUF/U0/U1:Y (f)
               +     1.266          net: MPM_PMBus_SMBALERT_BIBUF_Y
  1.576                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CI0oi:D (f)
                                    
  1.576                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  N/C
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.480          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  N/C                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CI0oi:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1P0
  N/C                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CI0oi:D


END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        MPM_GPIO_Digital_IOs/CGPIOiOI.7.CGPIOI1I.CGPIOo0[7]/U1:CLK
  To:                          DMPM_DB_LED_D7_N
  Delay (ns):                  1.879
  Slack (ns):
  Arrival (ns):                5.908
  Required (ns):
  Clock to Out (ns):           5.908

Path 2
  From:                        MPM_GPIO_Digital_IOs/CGPIOiOI.4.CGPIOI1I.CGPIOo0[4]/U1:CLK
  To:                          DMPM_DB_LED_D4_N
  Delay (ns):                  1.888
  Slack (ns):
  Arrival (ns):                5.917
  Required (ns):
  Clock to Out (ns):           5.917

Path 3
  From:                        MPM_GPIO_Digital_IOs/CGPIOiOI.6.CGPIOI1I.CGPIOo0[6]/U1:CLK
  To:                          DMPM_DB_LED_D6_N
  Delay (ns):                  1.912
  Slack (ns):
  Arrival (ns):                5.941
  Required (ns):
  Clock to Out (ns):           5.941

Path 4
  From:                        MPM_GPIO_Regulator_Enables/CGPIOiOI.0.CGPIOI1I.CGPIOo0[0]/U1:CLK
  To:                          DMPM_DB_APOL1_EN
  Delay (ns):                  2.100
  Slack (ns):
  Arrival (ns):                6.077
  Required (ns):
  Clock to Out (ns):           6.077

Path 5
  From:                        MPM_GPIO_Digital_IOs/CGPIOiOI.5.CGPIOI1I.CGPIOo0[5]/U1:CLK
  To:                          DMPM_DB_LED_D5_N
  Delay (ns):                  2.283
  Slack (ns):
  Arrival (ns):                6.291
  Required (ns):
  Clock to Out (ns):           6.291


Expanded Path 1
  From: MPM_GPIO_Digital_IOs/CGPIOiOI.7.CGPIOI1I.CGPIOo0[7]/U1:CLK
  To: DMPM_DB_LED_D7_N
  data arrival time                              5.908
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.342          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  4.029                        MPM_GPIO_Digital_IOs/CGPIOiOI.7.CGPIOI1I.CGPIOo0[7]/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.278                        MPM_GPIO_Digital_IOs/CGPIOiOI.7.CGPIOI1I.CGPIOo0[7]/U1:Q (r)
               +     0.163          net: MPM_GPIO_Digital_IOs_GPIO_OUT7to7
  4.441                        _SF_MPM_RefDesign_MSS_/FIO_OUTBUF_7/U0/U1:PIN5 (r)
               +     0.037          cell: ADLIB:MSS_IF
  4.478                        _SF_MPM_RefDesign_MSS_/FIO_OUTBUF_7/U0/U1:PIN5INT (r)
               +     0.000          net: _SF_MPM_RefDesign_MSS_/FIO_OUTBUF_7/U0/D_INT
  4.478                        _SF_MPM_RefDesign_MSS_/FIO_OUTBUF_7/U0/U0:D (r)
               +     1.430          cell: ADLIB:IOPAD_TRI
  5.908                        _SF_MPM_RefDesign_MSS_/FIO_OUTBUF_7/U0/U0:PAD (r)
               +     0.000          net: DMPM_DB_LED_D7_N
  5.908                        DMPM_DB_LED_D7_N (r)
                                    
  5.908                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  N/C
                                    
  N/C                          DMPM_DB_LED_D7_N (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_glb

Path 1
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MPM_PMBus_I2C/CI2Co1[6]/U1:CLR
  Delay (ns):                  2.307
  Slack (ns):                  1.286
  Arrival (ns):                5.340
  Required (ns):               4.054
  Hold (ns):

Path 2
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CI0il[6]/U1:CLR
  Delay (ns):                  2.502
  Slack (ns):                  1.346
  Arrival (ns):                5.535
  Required (ns):               4.189
  Hold (ns):

Path 3
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MPM_GPIO_Digital_IOs/CGPIOiOI.9.CGPIOI1I.CGPIOo0[9]/U1:CLR
  Delay (ns):                  2.401
  Slack (ns):                  1.355
  Arrival (ns):                5.434
  Required (ns):               4.079
  Hold (ns):

Path 4
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/CPWMLIOL.1.CPWMo0ol.CPWMoiol[9]/U1:CLR
  Delay (ns):                  2.422
  Slack (ns):                  1.358
  Arrival (ns):                5.455
  Required (ns):               4.097
  Hold (ns):

Path 5
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CI0il[4]/U1:CLR
  Delay (ns):                  2.518
  Slack (ns):                  1.362
  Arrival (ns):                5.551
  Required (ns):               4.189
  Hold (ns):


Expanded Path 1
  From: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK
  To: MPM_PMBus_I2C/CI2Co1[6]/U1:CLR
  data arrival time                              5.340
  data required time                         -   4.054
  slack                                          1.286
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.309          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST_FCLK
  3.033                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.710          cell: ADLIB:MSS_APB_IP
  4.743                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.060          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/M2FRESETnINT_NET
  4.803                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.045          cell: ADLIB:MSS_IF
  4.848                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     0.492          net: SmartFusion_MPM_Reference_Design_MSS_0_M2F_RESET_N
  5.340                        MPM_PMBus_I2C/CI2Co1[6]/U1:CLR (r)
                                    
  5.340                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.367          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  4.054                        MPM_PMBus_I2C/CI2Co1[6]/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  4.054                        MPM_PMBus_I2C/CI2Co1[6]/U1:CLR
                                    
  4.054                        data required time


END SET mss_ccc_gla0 to mss_ccc_glb

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_glb

Path 1
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl01L/U1:D
  Delay (ns):                  2.699
  Slack (ns):                  1.565
  Arrival (ns):                5.732
  Required (ns):               4.167
  Hold (ns):                   0.000

Path 2
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMooll[3]/U1:D
  Delay (ns):                  2.636
  Slack (ns):                  1.584
  Arrival (ns):                5.669
  Required (ns):               4.085
  Hold (ns):                   0.000

Path 3
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.2.CPWMllLL[24]/U1:D
  Delay (ns):                  2.675
  Slack (ns):                  1.614
  Arrival (ns):                5.708
  Required (ns):               4.094
  Hold (ns):                   0.000

Path 4
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MPM_GPIO_Regulator_Enables/CGPIOiOI.23.CGPIOI1I.CGPIOo0[23]/U1:D
  Delay (ns):                  2.779
  Slack (ns):                  1.648
  Arrival (ns):                5.812
  Required (ns):               4.164
  Hold (ns):                   0.000

Path 5
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MPM_GPIO_Digital_IOs/CGPIOiOI.23.CGPIOI1I.CGPIOo0[23]/U1:D
  Delay (ns):                  2.779
  Slack (ns):                  1.648
  Arrival (ns):                5.812
  Required (ns):               4.164
  Hold (ns):                   0.000


Expanded Path 1
  From: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl01L/U1:D
  data arrival time                              5.732
  data required time                         -   4.167
  slack                                          1.565
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.641          cell: ADLIB:MSS_APB_IP
  4.674                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPWDATA[4] (f)
               +     0.078          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/MSSPWDATA[4]INT_NET
  4.752                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_38:PIN1INT (f)
               +     0.042          cell: ADLIB:MSS_IF
  4.794                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_38:PIN1 (f)
               +     0.538          net: _CoreAPB3_0_APBmslave0_PWDATA_[4]_
  5.332                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl01L/U0:A (f)
               +     0.252          cell: ADLIB:MX2
  5.584                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl01L/U0:Y (f)
               +     0.148          net: MPM_PMBus_I2C/CI2CO0l_0_Ui2C/CI2Cl01L/Y
  5.732                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl01L/U1:D (f)
                                    
  5.732                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.480          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  4.167                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl01L/U1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1P0
  4.167                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl01L/U1:D
                                    
  4.167                        data required time


END SET mss_fabric_interface_clock to mss_ccc_glb

----------------------------------------------------

Clock Domain \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  Delay (ns):                  4.124
  Slack (ns):                  2.724
  Arrival (ns):                7.157
  Required (ns):               4.433
  Hold (ns):                   1.400

Path 2
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[21]
  Delay (ns):                  4.268
  Slack (ns):                  2.868
  Arrival (ns):                7.301
  Required (ns):               4.433
  Hold (ns):                   1.400

Path 3
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[31]
  Delay (ns):                  4.589
  Slack (ns):                  3.193
  Arrival (ns):                7.622
  Required (ns):               4.429
  Hold (ns):                   1.396

Path 4
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[30]
  Delay (ns):                  4.777
  Slack (ns):                  3.376
  Arrival (ns):                7.810
  Required (ns):               4.434
  Hold (ns):                   1.401

Path 5
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[14]
  Delay (ns):                  4.785
  Slack (ns):                  3.387
  Arrival (ns):                7.818
  Required (ns):               4.431
  Hold (ns):                   1.398


Expanded Path 1
  From: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  data arrival time                              7.157
  data required time                         -   4.433
  slack                                          2.724
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.754          cell: ADLIB:MSS_APB_IP
  4.787                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPADDR[10] (f)
               +     0.077          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/MSSPADDR[10]INT_NET
  4.864                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_33:PIN2INT (f)
               +     0.045          cell: ADLIB:MSS_IF
  4.909                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_33:PIN2 (f)
               +     0.707          net: _SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[10]_
  5.616                        CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0_a2_3_1[8]:B (f)
               +     0.209          cell: ADLIB:NOR3A
  5.825                        CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0_a2_3_1[8]:Y (r)
               +     0.156          net: CoreAPB3_0/CAPB3O1II/N_30_0
  5.981                        CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0[15]:B (r)
               +     0.194          cell: ADLIB:AO1B
  6.175                        CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0[15]:Y (r)
               +     0.675          net: _SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[15]_
  6.850                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_41:PIN6 (r)
               +     0.090          cell: ADLIB:MSS_IF
  6.940                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_41:PIN6INT (r)
               +     0.217          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/MSSPRDATA[15]INT_NET
  7.157                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15] (r)
                                    
  7.157                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.400          Library hold time: ADLIB:MSS_APB_IP
  4.433                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
                                    
  4.433                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_glb to mss_fabric_interface_clock

Path 1
  From:                        MPM_GPIO_Digital_IOs/CGPIOiOI.22.CGPIOI1I.CGPIOo0[22]/U1:CLK
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[22]
  Delay (ns):                  1.418
  Slack (ns):                  0.995
  Arrival (ns):                5.427
  Required (ns):               4.432
  Hold (ns):                   1.399

Path 2
  From:                        MPM_GPIO_Digital_IOs/CGPIOiOI.21.CGPIOI1I.CGPIOo0[21]/U1:CLK
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[21]
  Delay (ns):                  1.439
  Slack (ns):                  1.032
  Arrival (ns):                5.465
  Required (ns):               4.433
  Hold (ns):                   1.400

Path 3
  From:                        MPM_GPIO_Digital_IOs/CGPIOiOI.20.CGPIOI1I.CGPIOo0[20]/U1:CLK
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[20]
  Delay (ns):                  1.533
  Slack (ns):                  1.082
  Arrival (ns):                5.514
  Required (ns):               4.432
  Hold (ns):                   1.399

Path 4
  From:                        MPM_GPIO_Digital_IOs/CGPIOiOI.29.CGPIOI1I.CGPIOo0[29]/U1:CLK
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[29]
  Delay (ns):                  1.465
  Slack (ns):                  1.123
  Arrival (ns):                5.552
  Required (ns):               4.429
  Hold (ns):                   1.396

Path 5
  From:                        MPM_GPIO_Digital_IOs/CGPIOiOI.27.CGPIOI1I.CGPIOo0[27]/U1:CLK
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[27]
  Delay (ns):                  1.583
  Slack (ns):                  1.140
  Arrival (ns):                5.573
  Required (ns):               4.433
  Hold (ns):                   1.400


Expanded Path 1
  From: MPM_GPIO_Digital_IOs/CGPIOiOI.22.CGPIOI1I.CGPIOo0[22]/U1:CLK
  To: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[22]
  data arrival time                              5.427
  data required time                         -   4.432
  slack                                          0.995
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     3.687          Clock generation
  3.687
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  3.687                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.687                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.322          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  4.009                        MPM_GPIO_Digital_IOs/CGPIOiOI.22.CGPIOI1I.CGPIOo0[22]/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.258                        MPM_GPIO_Digital_IOs/CGPIOiOI.22.CGPIOI1I.CGPIOo0[22]/U1:Q (r)
               +     0.174          net: CGPIOiOI_22_CGPIOI1I_CGPIOo0_0[22]
  4.432                        CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0[22]:A (r)
               +     0.201          cell: ADLIB:AO1B
  4.633                        CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0[22]:Y (r)
               +     0.475          net: _SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[22]_
  5.108                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_55:PIN5 (r)
               +     0.102          cell: ADLIB:MSS_IF
  5.210                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_55:PIN5INT (r)
               +     0.217          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/MSSPRDATA[22]INT_NET
  5.427                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[22] (r)
                                    
  5.427                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.399          Library hold time: ADLIB:MSS_APB_IP
  4.432                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[22]
                                    
  4.432                        data required time


END SET mss_ccc_glb to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MPM_Channel_4_DMPM_DB_DPOL2_PG
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[14]
  Delay (ns):                  0.865
  Slack (ns):
  Arrival (ns):                0.865
  Required (ns):
  Hold (ns):                   0.961
  External Hold (ns):          3.129

Path 2
  From:                        MPM_Channel_3_DMPM_DB_DPOL1_PG
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[13]
  Delay (ns):                  0.897
  Slack (ns):
  Arrival (ns):                0.897
  Required (ns):
  Hold (ns):                   0.960
  External Hold (ns):          3.096

Path 3
  From:                        MPM_Channel_5_DMPM_DB_DPOL3_PG
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[15]
  Delay (ns):                  0.918
  Slack (ns):
  Arrival (ns):                0.918
  Required (ns):
  Hold (ns):                   0.938
  External Hold (ns):          3.053

Path 4
  From:                        A2F_BOARD_SW2_N
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[29]
  Delay (ns):                  2.392
  Slack (ns):
  Arrival (ns):                2.392
  Required (ns):
  Hold (ns):                   0.808
  External Hold (ns):          1.449

Path 5
  From:                        A2F_BOARD_SW1_N
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[28]
  Delay (ns):                  2.668
  Slack (ns):
  Arrival (ns):                2.668
  Required (ns):
  Hold (ns):                   0.803
  External Hold (ns):          1.168


Expanded Path 1
  From: MPM_Channel_4_DMPM_DB_DPOL2_PG
  To: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[14]
  data arrival time                              0.865
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MPM_Channel_4_DMPM_DB_DPOL2_PG (f)
               +     0.000          net: MPM_Channel_4_DMPM_DB_DPOL2_PG
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_GPIO_0_GPIO_14_IN:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        \\SF_MPM_RefDesign_MSS\\/MSS_GPIO_0_GPIO_14_IN:Y (f)
               +     0.588          net: _SF_MPM_RefDesign_MSS_/MSS_GPIO_0_GPIO_14_IN_Y
  0.865                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[14] (f)
                                    
  0.865                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.033          Clock generation
  N/C
               +     0.961          Library hold time: ADLIB:MSS_APB_IP
  N/C                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[14]


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

