Timing Report Max Delay Analysis

SmartTime Version v10.0 SP2
Actel Corporation - Actel Designer Software Release v10.0 SP2 (Version 10.0.20.2)
Copyright (c) 1989-2012
Date: Fri Jun 29 16:41:25 2012


Design: SmartFusion_MPM_Reference_Design
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.434
External Hold (ns):         4.176
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                27.354
Frequency (MHz):            36.558
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        0.163
External Hold (ns):         2.591
Min Clock-To-Out (ns):      5.908
Max Clock-To-Out (ns):      16.247

Clock Domain:               \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                25.925
Frequency (MHz):            38.573
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        1.437
External Hold (ns):         3.129
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.196
  External Setup (ns):         -5.434


Expanded Path 1
  From: MSS_RESET_N
  To: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        \\SF_MPM_RefDesign_MSS\\/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.630          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST_FCLK
  N/C                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.196          Library setup time: ADLIB:MSS_APB_IP
  N/C                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_glb to mss_ccc_gla0

Path 1
  From:                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cll1L[3]:CLK
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FABINT
  Delay (ns):                  2.246
  Slack (ns):                  8.087
  Arrival (ns):                7.964
  Required (ns):               16.051
  Setup (ns):                  0.624


Expanded Path 1
  From: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cll1L[3]:CLK
  To: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FABINT
  data required time                             16.051
  data arrival time                          -   7.964
  slack                                          8.087
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  4.798
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  4.798                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.798                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.920          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  5.718                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cll1L[3]:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  6.389                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cll1L[3]:Q (f)
               +     1.070          net: MPM_PMBus_I2C_INT
  7.459                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_60:PIN5 (f)
               +     0.095          cell: ADLIB:MSS_IF
  7.554                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_60:PIN5INT (f)
               +     0.410          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/FABINTINT_NET
  7.964                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FABINT (f)
                                    
  7.964                        data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla0
               +     0.000          Clock source
  12.500                       \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  16.045
               +     0.630          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST_FCLK
  16.675                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -     0.624          Library setup time: ADLIB:MSS_APB_IP
  16.051                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FABINT
                                    
  16.051                       data required time


END SET mss_ccc_glb to mss_ccc_gla0

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.1.CPWMilll[1]/U1:CLK
  To:                          MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/CPWMLIOL.1.CPWMo0ol.CPWMoiol[17]/U1:D
  Delay (ns):                  26.987
  Slack (ns):                  22.646
  Arrival (ns):                32.477
  Required (ns):               55.123
  Setup (ns):                  0.490
  Minimum Period (ns):         27.354

Path 2
  From:                        MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/CPWMLIOL.1.CPWMo0ol.CPWMoiol[1]/U1:CLK
  To:                          MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/CPWMLIOL.1.CPWMo0ol.CPWMoiol[17]/U1:D
  Delay (ns):                  26.752
  Slack (ns):                  22.758
  Arrival (ns):                32.365
  Required (ns):               55.123
  Setup (ns):                  0.490
  Minimum Period (ns):         27.242

Path 3
  From:                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.1.CPWMilll[2]/U1:CLK
  To:                          MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/CPWMLIOL.1.CPWMo0ol.CPWMoiol[17]/U1:D
  Delay (ns):                  25.955
  Slack (ns):                  23.555
  Arrival (ns):                31.568
  Required (ns):               55.123
  Setup (ns):                  0.490
  Minimum Period (ns):         26.445

Path 4
  From:                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.1.CPWMilll[1]/U1:CLK
  To:                          MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/CPWMLIOL.1.CPWMo0ol.CPWMoiol[16]/U1:D
  Delay (ns):                  25.779
  Slack (ns):                  23.697
  Arrival (ns):                31.269
  Required (ns):               54.966
  Setup (ns):                  0.522
  Minimum Period (ns):         26.303

Path 5
  From:                        MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/CPWMLIOL.1.CPWMo0ol.CPWMoiol[1]/U1:CLK
  To:                          MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/CPWMLIOL.1.CPWMo0ol.CPWMoiol[16]/U1:D
  Delay (ns):                  25.544
  Slack (ns):                  23.809
  Arrival (ns):                31.157
  Required (ns):               54.966
  Setup (ns):                  0.522
  Minimum Period (ns):         26.191


Expanded Path 1
  From: MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.1.CPWMilll[1]/U1:CLK
  To: MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/CPWMLIOL.1.CPWMo0ol.CPWMoiol[17]/U1:D
  data required time                             55.123
  data arrival time                          -   32.477
  slack                                          22.646
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  4.798
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  4.798                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.798                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.692          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  5.490                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.1.CPWMilll[1]/U1:CLK (r)
               +     0.528          cell: ADLIB:DFN1C0
  6.018                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.1.CPWMilll[1]/U1:Q (r)
               +     1.470          net: MPM_PWM_Trimming_Outputs/PWM_negedge_reg[1]
  7.488                        MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I0_un1_CO1:A (r)
               +     0.445          cell: ADLIB:NOR2B
  7.933                        MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I0_un1_CO1:Y (r)
               +     0.390          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/I0_un1_CO1
  8.323                        MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I1_CO1:B (r)
               +     0.850          cell: ADLIB:MAJ3
  9.173                        MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I1_CO1:Y (r)
               +     0.370          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/N209
  9.543                        MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I2_un1_CO1:B (r)
               +     0.895          cell: ADLIB:MAJ3
  10.438                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I2_un1_CO1:Y (r)
               +     0.306          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/I2_un1_CO1_0
  10.744                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I3_CO1:B (r)
               +     0.895          cell: ADLIB:MAJ3
  11.639                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I3_CO1:Y (r)
               +     0.369          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/N213
  12.008                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I4_un1_CO1:B (r)
               +     0.895          cell: ADLIB:MAJ3
  12.903                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I4_un1_CO1:Y (r)
               +     0.369          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/I4_un1_CO1
  13.272                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I5_CO1:B (r)
               +     0.895          cell: ADLIB:MAJ3
  14.167                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I5_CO1:Y (r)
               +     1.093          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/N217
  15.260                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I6_un1_CO1:B (r)
               +     0.895          cell: ADLIB:MAJ3
  16.155                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I6_un1_CO1:Y (r)
               +     0.432          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/I6_un1_CO1
  16.587                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I7_CO1_0:B (r)
               +     0.554          cell: ADLIB:OAI1
  17.141                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I7_CO1_0:Y (f)
               +     0.306          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/ADD_16x16_slow_I7_CO1_0
  17.447                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I7_CO1:C (f)
               +     0.642          cell: ADLIB:AO1B
  18.089                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I7_CO1:Y (r)
               +     1.116          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/N221
  19.205                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I8_un1_CO1:B (r)
               +     0.850          cell: ADLIB:MAJ3
  20.055                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I8_un1_CO1:Y (r)
               +     0.398          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/I8_un1_CO1
  20.453                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I9_CO1:B (r)
               +     0.895          cell: ADLIB:MAJ3
  21.348                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I9_CO1:Y (r)
               +     0.405          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/N225
  21.753                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I10_un1_CO1:B (r)
               +     0.895          cell: ADLIB:MAJ3
  22.648                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I10_un1_CO1:Y (r)
               +     0.369          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/I10_un1_CO1
  23.017                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I11_CO1:B (r)
               +     0.895          cell: ADLIB:MAJ3
  23.912                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I11_CO1:Y (r)
               +     0.370          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/N229
  24.282                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I12_un1_CO1:B (r)
               +     0.895          cell: ADLIB:MAJ3
  25.177                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I12_un1_CO1:Y (r)
               +     1.555          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/I12_un1_CO1
  26.732                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I13_CO1:B (r)
               +     0.895          cell: ADLIB:MAJ3
  27.627                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I13_CO1:Y (r)
               +     0.369          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/N233
  27.996                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I14_un1_CO1:B (r)
               +     0.895          cell: ADLIB:MAJ3
  28.891                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I14_un1_CO1:Y (r)
               +     0.369          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/I14_un1_CO1
  29.260                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I15_CO1:B (r)
               +     0.895          cell: ADLIB:MAJ3
  30.155                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/un7_cpwmoiol_ADD_16x16_slow_I15_CO1:Y (r)
               +     0.306          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/un7_cpwmoiol[16]
  30.461                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/CPWMLIOL.1.CPWMo0ol.CPWMoiol[17]/U0:B (r)
               +     0.533          cell: ADLIB:MX2
  30.994                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/CPWMLIOL.1.CPWMo0ol.CPWMoiol[17]/U0:Y (r)
               +     1.483          net: MPM_PWM_Trimming_Outputs/CPWMLLOL_CPWMilol/CPWMLIOL_1_CPWMo0ol_CPWMoiol[17]/Y
  32.477                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/CPWMLIOL.1.CPWMo0ol.CPWMoiol[17]/U1:D (r)
                                    
  32.477                       data arrival time
  ________________________________________________________
  Data required time calculation
  50.000                       mss_ccc_glb
               +     0.000          Clock source
  50.000                       \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  54.798
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  54.798                       \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  54.798                       \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.815          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  55.613                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/CPWMLIOL.1.CPWMo0ol.CPWMoiol[17]/U1:CLK (r)
               -     0.490          Library setup time: ADLIB:DFN1C0
  55.123                       MPM_PWM_Trimming_Outputs/CPWMLLOL.CPWMilol/CPWMLIOL.1.CPWMo0ol.CPWMoiol[17]/U1:D
                                    
  55.123                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MPM_PMBus_SCL
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CLOLi[0]:D
  Delay (ns):                  5.294
  Slack (ns):
  Arrival (ns):                5.294
  Required (ns):
  Setup (ns):                  0.522
  External Setup (ns):         0.163

Path 2
  From:                        MPM_PMBus_SDA
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Ci1oI[0]:D
  Delay (ns):                  5.054
  Slack (ns):
  Arrival (ns):                5.054
  Required (ns):
  Setup (ns):                  0.522
  External Setup (ns):         -0.147

Path 3
  From:                        MPM_PMBus_SMBALERT
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CI0oi:D
  Delay (ns):                  3.426
  Slack (ns):
  Arrival (ns):                3.426
  Required (ns):
  Setup (ns):                  0.522
  External Setup (ns):         -1.665


Expanded Path 1
  From: MPM_PMBus_SCL
  To: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CLOLi[0]:D
  data required time                             N/C
  data arrival time                          -   5.294
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MPM_PMBus_SCL (r)
               +     0.000          net: MPM_PMBus_SCL
  0.000                        MPM_PMBus_SCL_BIBUF/U0/U0:PAD (r)
               +     0.967          cell: ADLIB:IOPAD_BI
  0.967                        MPM_PMBus_SCL_BIBUF/U0/U0:Y (r)
               +     0.000          net: MPM_PMBus_SCL_BIBUF/U0/NET3
  0.967                        MPM_PMBus_SCL_BIBUF/U0/U1:YIN (r)
               +     0.039          cell: ADLIB:IOBI_IB_OB_EB
  1.006                        MPM_PMBus_SCL_BIBUF/U0/U1:Y (r)
               +     1.892          net: MPM_PMBus_SCL_BIBUF_Y
  2.898                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CLOLi_RNO[0]:A (r)
               +     0.424          cell: ADLIB:OR2
  3.322                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CLOLi_RNO[0]:Y (r)
               +     1.972          net: MPM_PMBus_I2C/CI2CO0l_0_Ui2C/N_473
  5.294                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CLOLi[0]:D (r)
                                    
  5.294                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  N/C
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.855          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  N/C                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CLOLi[0]:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1P0
  N/C                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CLOLi[0]:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CoiiI:CLK
  To:                          MPM_PMBus_SCL
  Delay (ns):                  10.524
  Slack (ns):
  Arrival (ns):                16.247
  Required (ns):
  Clock to Out (ns):           16.247

Path 2
  From:                        MPM_GPIO_Digital_IOs/CGPIOiOI.9.CGPIOI1I.CGPIOo0[9]/U1:CLK
  To:                          A2F_BOARD_LED_D2_N
  Delay (ns):                  9.831
  Slack (ns):
  Arrival (ns):                15.369
  Required (ns):
  Clock to Out (ns):           15.369

Path 3
  From:                        MPM_GPIO_Regulator_Enables/CGPIOiOI.1.CGPIOI1I.CGPIOo0[1]/U1:CLK
  To:                          DMPM_DB_APOL2_EN
  Delay (ns):                  9.456
  Slack (ns):
  Arrival (ns):                15.142
  Required (ns):
  Clock to Out (ns):           15.142

Path 4
  From:                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cli1L/U1:CLK
  To:                          MPM_PMBus_SCL
  Delay (ns):                  9.245
  Slack (ns):
  Arrival (ns):                14.927
  Required (ns):
  Clock to Out (ns):           14.927

Path 5
  From:                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl01L/U1:CLK
  To:                          MPM_PMBus_SMBALERT
  Delay (ns):                  8.158
  Slack (ns):
  Arrival (ns):                13.844
  Required (ns):
  Clock to Out (ns):           13.844


Expanded Path 1
  From: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CoiiI:CLK
  To: MPM_PMBus_SCL
  data required time                             N/C
  data arrival time                          -   16.247
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  4.798
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  4.798                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.798                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.925          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  5.723                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CoiiI:CLK (r)
               +     0.671          cell: ADLIB:DFN1P0
  6.394                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CoiiI:Q (f)
               +     2.639          net: MPM_PMBus_I2C/CI2CO0l_0_Ui2C/CI2CoiiI
  9.033                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CoiiI_RNIUPLS:A (f)
               +     0.574          cell: ADLIB:NOR2A
  9.607                        MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CoiiI_RNIUPLS:Y (f)
               +     2.002          net: MPM_PMBus_I2C_SCLO
  11.609                       INV_5:A (f)
               +     0.489          cell: ADLIB:INV
  12.098                       INV_5:Y (r)
               +     0.291          net: INV_5_Y
  12.389                       MPM_PMBus_SCL_BIBUF/U0/U1:E (r)
               +     0.426          cell: ADLIB:IOBI_IB_OB_EB
  12.815                       MPM_PMBus_SCL_BIBUF/U0/U1:EOUT (r)
               +     0.000          net: MPM_PMBus_SCL_BIBUF/U0/NET2
  12.815                       MPM_PMBus_SCL_BIBUF/U0/U0:E (r)
               +     3.432          cell: ADLIB:IOPAD_BI
  16.247                       MPM_PMBus_SCL_BIBUF/U0/U0:PAD (f)
               +     0.000          net: MPM_PMBus_SCL
  16.247                       MPM_PMBus_SCL (f)
                                    
  16.247                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  N/C
                                    
  N/C                          MPM_PMBus_SCL (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_glb

Path 1
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MPM_GPIO_Digital_IOs/CGPIOiOI.26.CGPIOI1I.CGPIOo0[26]/U1:CLR
  Delay (ns):                  6.603
  Slack (ns):                  6.905
  Arrival (ns):                10.778
  Required (ns):               17.683
  Setup (ns):

Path 2
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CI11l/U1:CLR
  Delay (ns):                  6.378
  Slack (ns):                  7.086
  Arrival (ns):                10.553
  Required (ns):               17.639
  Setup (ns):

Path 3
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MPM_GPIO_Regulator_Enables/CGPIOiOI.26.CGPIOI1I.CGPIOo0[26]/U1:CLR
  Delay (ns):                  6.283
  Slack (ns):                  7.225
  Arrival (ns):                10.458
  Required (ns):               17.683
  Setup (ns):

Path 4
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MPM_GPIO_Digital_IOs/CGPIOiOI.27.CGPIOI1I.CGPIOo0[27]/U1:CLR
  Delay (ns):                  6.068
  Slack (ns):                  7.401
  Arrival (ns):                10.243
  Required (ns):               17.644
  Setup (ns):

Path 5
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MPM_PWM_Trimming_Outputs/CPWMI11.CPWMOOOL/CPWMoooi[5]/U1:CLR
  Delay (ns):                  6.128
  Slack (ns):                  7.419
  Arrival (ns):                10.303
  Required (ns):               17.722
  Setup (ns):


Expanded Path 1
  From: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK
  To: MPM_GPIO_Digital_IOs/CGPIOiOI.26.CGPIOI1I.CGPIOo0[26]/U1:CLR
  data required time                             17.683
  data arrival time                          -   10.778
  slack                                          6.905
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  3.545
               +     0.630          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST_FCLK
  4.175                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     3.632          cell: ADLIB:MSS_APB_IP
  7.807                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.122          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/M2FRESETnINT_NET
  7.929                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.095          cell: ADLIB:MSS_IF
  8.024                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     2.754          net: SmartFusion_MPM_Reference_Design_MSS_0_M2F_RESET_N
  10.778                       MPM_GPIO_Digital_IOs/CGPIOiOI.26.CGPIOI1I.CGPIOo0[26]/U1:CLR (r)
                                    
  10.778                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_glb
               +     0.000          Clock source
  12.500                       \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  17.298
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  17.298                       \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.298                       \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.656          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  17.954                       MPM_GPIO_Digital_IOs/CGPIOiOI.26.CGPIOI1I.CGPIOo0[26]/U1:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1C0
  17.683                       MPM_GPIO_Digital_IOs/CGPIOiOI.26.CGPIOI1I.CGPIOo0[26]/U1:CLR
                                    
  17.683                       data required time


END SET mss_ccc_gla0 to mss_ccc_glb

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_glb

Path 1
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2COL1l/U1:D
  Delay (ns):                  28.692
  Slack (ns):                  22.262
  Arrival (ns):                32.867
  Required (ns):               55.129
  Setup (ns):                  0.490

Path 2
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CIO1l/U1:D
  Delay (ns):                  28.253
  Slack (ns):                  22.768
  Arrival (ns):                32.428
  Required (ns):               55.196
  Setup (ns):                  0.490

Path 3
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/Ack/U1:D
  Delay (ns):                  27.896
  Slack (ns):                  23.052
  Arrival (ns):                32.071
  Required (ns):               55.123
  Setup (ns):                  0.490

Path 4
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cll1L[3]:D
  Delay (ns):                  27.872
  Slack (ns):                  23.181
  Arrival (ns):                32.047
  Required (ns):               55.228
  Setup (ns):                  0.490

Path 5
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cll1L_0[3]:D
  Delay (ns):                  27.503
  Slack (ns):                  23.514
  Arrival (ns):                31.678
  Required (ns):               55.192
  Setup (ns):                  0.490


Expanded Path 1
  From: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2COL1l/U1:D
  data required time                             55.129
  data arrival time                          -   32.867
  slack                                          22.262
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.175          Clock generation
  4.175
               +    15.481          cell: ADLIB:MSS_APB_IP
  19.656                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPSEL (r)
               +     0.123          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/MSSPSELINT_NET
  19.779                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_42:PIN1INT (r)
               +     0.089          cell: ADLIB:MSS_IF
  19.868                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_42:PIN1 (r)
               +     1.140          net: SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PSELx
  21.008                       CoreAPB3_0/CAPB3O1II/CAPB3O0L_0_a2_0[0]:A (r)
               +     0.478          cell: ADLIB:OR3A
  21.486                       CoreAPB3_0/CAPB3O1II/CAPB3O0L_0_a2_0[0]:Y (f)
               +     0.972          net: N_127
  22.458                       CoreAPB3_0/CAPB3iool_0_a2[3]:C (f)
               +     0.606          cell: ADLIB:OR3B
  23.064                       CoreAPB3_0/CAPB3iool_0_a2[3]:Y (f)
               +     1.173          net: CoreAPB3_0_APBmslave3_PSELx
  24.237                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cli0I.un3_penable:B (f)
               +     0.568          cell: ADLIB:AND3B
  24.805                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cli0I.un3_penable:Y (r)
               +     1.103          net: MPM_PMBus_I2C/CI2CO0l_0_Ui2C/un3_penable
  25.908                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CIi0i.un105_ci2cl10l_0_o3:B (r)
               +     0.470          cell: ADLIB:OR2B
  26.378                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CIi0i.un105_ci2cl10l_0_o3:Y (f)
               +     1.111          net: MPM_PMBus_I2C/CI2CO0l_0_Ui2C/N_1679
  27.489                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2COL1l_RNO_5:B (f)
               +     0.862          cell: ADLIB:AXOI5
  28.351                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2COL1l_RNO_5:Y (r)
               +     0.296          net: MPM_PMBus_I2C/CI2CO0l_0_Ui2C/N_422
  28.647                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2COL1l_RNO_2:B (r)
               +     0.666          cell: ADLIB:AOI1
  29.313                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2COL1l_RNO_2:Y (f)
               +     0.296          net: MPM_PMBus_I2C/CI2CO0l_0_Ui2C/N_509
  29.609                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2COL1l_RNO:C (f)
               +     0.683          cell: ADLIB:NOR3
  30.292                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2COL1l_RNO:Y (r)
               +     0.306          net: MPM_PMBus_I2C/CI2CO0l_0_Ui2C/N_1911
  30.598                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2COL1l/U0:A (r)
               +     0.517          cell: ADLIB:MX2
  31.115                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2COL1l/U0:Y (r)
               +     1.752          net: MPM_PMBus_I2C/CI2CO0l_0_Ui2C/CI2COL1l/Y
  32.867                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2COL1l/U1:D (r)
                                    
  32.867                       data arrival time
  ________________________________________________________
  Data required time calculation
  50.000                       mss_ccc_glb
               +     0.000          Clock source
  50.000                       \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  54.798
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  54.798                       \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  54.798                       \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.821          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  55.619                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2COL1l/U1:CLK (r)
               -     0.490          Library setup time: ADLIB:DFN1P0
  55.129                       MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2COL1l/U1:D
                                    
  55.129                       data required time


END SET mss_fabric_interface_clock to mss_ccc_glb

----------------------------------------------------

Clock Domain \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
  Delay (ns):                  28.159
  Slack (ns):                  24.075
  Arrival (ns):                32.334
  Required (ns):               56.409
  Setup (ns):                  -2.234
  Minimum Period (ns):         25.925

Path 2
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  Delay (ns):                  27.152
  Slack (ns):                  25.072
  Arrival (ns):                31.327
  Required (ns):               56.399
  Setup (ns):                  -2.224
  Minimum Period (ns):         24.928

Path 3
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]
  Delay (ns):                  27.023
  Slack (ns):                  25.197
  Arrival (ns):                31.198
  Required (ns):               56.395
  Setup (ns):                  -2.220
  Minimum Period (ns):         24.803

Path 4
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  26.876
  Slack (ns):                  25.339
  Arrival (ns):                31.051
  Required (ns):               56.390
  Setup (ns):                  -2.215
  Minimum Period (ns):         24.661

Path 5
  From:                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[7]
  Delay (ns):                  26.761
  Slack (ns):                  25.466
  Arrival (ns):                30.936
  Required (ns):               56.402
  Setup (ns):                  -2.227
  Minimum Period (ns):         24.534


Expanded Path 1
  From: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB
  To: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
  data required time                             56.409
  data arrival time                          -   32.334
  slack                                          24.075
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.175          Clock generation
  4.175
               +    15.481          cell: ADLIB:MSS_APB_IP
  19.656                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPSEL (r)
               +     0.123          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/MSSPSELINT_NET
  19.779                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_42:PIN1INT (r)
               +     0.089          cell: ADLIB:MSS_IF
  19.868                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_42:PIN1 (r)
               +     1.140          net: SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PSELx
  21.008                       CoreAPB3_0/CAPB3O1II/CAPB3O0L_0_a2_0[0]:A (r)
               +     0.478          cell: ADLIB:OR3A
  21.486                       CoreAPB3_0/CAPB3O1II/CAPB3O0L_0_a2_0[0]:Y (f)
               +     1.477          net: N_127
  22.963                       MPM_GPIO_Digital_IOs/CGPIOo0_0_sqmuxa_0_a2_0:A (f)
               +     0.489          cell: ADLIB:OR2
  23.452                       MPM_GPIO_Digital_IOs/CGPIOo0_0_sqmuxa_0_a2_0:Y (f)
               +     0.514          net: N_128
  23.966                       CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0_a2_2[8]:C (f)
               +     0.568          cell: ADLIB:NOR3A
  24.534                       CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0_a2_2[8]:Y (r)
               +     2.443          net: N_29
  26.977                       CoreAPB3_0/CAPB3O1II/PRDATA_iv_0_a2_2[6]:B (r)
               +     0.470          cell: ADLIB:OR2B
  27.447                       CoreAPB3_0/CAPB3O1II/PRDATA_iv_0_a2_2[6]:Y (f)
               +     0.285          net: CoreAPB3_0/CAPB3O1II/N_120
  27.732                       CoreAPB3_0/CAPB3O1II/PRDATA_iv_0_1[6]:C (f)
               +     0.369          cell: ADLIB:AOI1B
  28.101                       CoreAPB3_0/CAPB3O1II/PRDATA_iv_0_1[6]:Y (f)
               +     1.438          net: CoreAPB3_0/CAPB3O1II/PRDATA_iv_0_1[6]
  29.539                       CoreAPB3_0/CAPB3O1II/PRDATA_iv_0[6]:C (f)
               +     0.584          cell: ADLIB:OR3C
  30.123                       CoreAPB3_0/CAPB3O1II/PRDATA_iv_0[6]:Y (r)
               +     1.603          net: _SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[6]_
  31.726                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_38:PIN6 (r)
               +     0.190          cell: ADLIB:MSS_IF
  31.916                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_38:PIN6INT (r)
               +     0.418          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/MSSPRDATA[6]INT_NET
  32.334                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6] (r)
                                    
  32.334                       data arrival time
  ________________________________________________________
  Data required time calculation
  50.000                       mss_fabric_interface_clock
               +     0.000          Clock source
  50.000                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.175          Clock generation
  54.175
               -    -2.234          Library setup time: ADLIB:MSS_APB_IP
  56.409                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
                                    
  56.409                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_glb to mss_fabric_interface_clock

Path 1
  From:                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.1.CPWMilll[16]/U1:CLK
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  Delay (ns):                  12.119
  Slack (ns):                  38.628
  Arrival (ns):                17.801
  Required (ns):               56.429
  Setup (ns):                  -2.254

Path 2
  From:                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.2.CPWMilll[20]/U1:CLK
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]
  Delay (ns):                  11.961
  Slack (ns):                  38.738
  Arrival (ns):                17.679
  Required (ns):               56.417
  Setup (ns):                  -2.242

Path 3
  From:                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/period_reg[15]/U1:CLK
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  Delay (ns):                  11.967
  Slack (ns):                  38.895
  Arrival (ns):                17.534
  Required (ns):               56.429
  Setup (ns):                  -2.254

Path 4
  From:                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.2.CPWMilll[32]/U1:CLK
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  Delay (ns):                  11.644
  Slack (ns):                  39.067
  Arrival (ns):                17.362
  Required (ns):               56.429
  Setup (ns):                  -2.254

Path 5
  From:                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/period_reg[11]/U1:CLK
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[11]
  Delay (ns):                  11.780
  Slack (ns):                  39.105
  Arrival (ns):                17.318
  Required (ns):               56.423
  Setup (ns):                  -2.248


Expanded Path 1
  From: MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.1.CPWMilll[16]/U1:CLK
  To: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  data required time                             56.429
  data arrival time                          -   17.801
  slack                                          38.628
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     4.798          Clock generation
  4.798
               +     0.000          net: _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC/GLB_INT
  4.798                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.798                        \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.884          net: SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
  5.682                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.1.CPWMilll[16]/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  6.353                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.1.CPWMilll[16]/U1:Q (f)
               +     1.817          net: MPM_PWM_Trimming_Outputs/PWM_negedge_reg[16]
  8.170                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.1.CPWMilll_RNIKPKB2[16]:A (f)
               +     0.468          cell: ADLIB:OR2B
  8.638                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.1.CPWMilll_RNIKPKB2[16]:Y (r)
               +     0.306          net: MPM_PWM_Trimming_Outputs/CPWMi01_CPWMo11/CPWMilll_m_i[16]
  8.944                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.1.CPWMilll_RNIEDSF7[16]:B (r)
               +     0.568          cell: ADLIB:NOR3C
  9.512                        MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.1.CPWMilll_RNIEDSF7[16]:Y (r)
               +     1.046          net: MPM_PWM_Trimming_Outputs/CPWMi01_CPWMo11/pRDATA_REGIF_0_iv_1[15]
  10.558                       MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.2.CPWMllLL_RNIAQKU9[32]:C (r)
               +     0.362          cell: ADLIB:AOI1B
  10.920                       MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.2.CPWMllLL_RNIAQKU9[32]:Y (r)
               +     1.142          net: MPM_PWM_Trimming_Outputs/CPWMi01_CPWMo11/pRDATA_REGIF_0_iv_3[15]
  12.062                       MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.2.CPWMllLL_RNI5O2JH[32]:A (r)
               +     0.478          cell: ADLIB:OR3C
  12.540                       MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMl0ll.2.CPWMllLL_RNI5O2JH[32]:Y (f)
               +     0.306          net: _CoreAPB3_0_APBmslave2_PRDATA_[15]_
  12.846                       CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0_a2[15]:B (f)
               +     0.574          cell: ADLIB:OR2B
  13.420                       CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0_a2[15]:Y (r)
               +     1.055          net: CoreAPB3_0/CAPB3O1II/N_82
  14.475                       CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0_0[15]:C (r)
               +     0.362          cell: ADLIB:AOI1B
  14.837                       CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0_0[15]:Y (r)
               +     0.314          net: CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0_0[15]
  15.151                       CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0[15]:C (r)
               +     0.596          cell: ADLIB:AO1B
  15.747                       CoreAPB3_0/CAPB3O1II/PRDATA_0_iv_0[15]:Y (f)
               +     1.467          net: _SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[15]_
  17.214                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_41:PIN6 (f)
               +     0.174          cell: ADLIB:MSS_IF
  17.388                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_41:PIN6INT (f)
               +     0.413          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/MSSPRDATA[15]INT_NET
  17.801                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15] (f)
                                    
  17.801                       data arrival time
  ________________________________________________________
  Data required time calculation
  50.000                       mss_fabric_interface_clock
               +     0.000          Clock source
  50.000                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.175          Clock generation
  54.175
               -    -2.254          Library setup time: ADLIB:MSS_APB_IP
  56.429                       _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
                                    
  56.429                       data required time


END SET mss_ccc_glb to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        A2F_BOARD_SW1_N
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[28]
  Delay (ns):                  5.584
  Slack (ns):
  Arrival (ns):                5.584
  Required (ns):
  Setup (ns):                  0.028
  External Setup (ns):         1.437

Path 2
  From:                        A2F_BOARD_SW2_N
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[29]
  Delay (ns):                  5.022
  Slack (ns):
  Arrival (ns):                5.022
  Required (ns):
  Setup (ns):                  0.142
  External Setup (ns):         0.989

Path 3
  From:                        MPM_Channel_4_DMPM_DB_DPOL2_PG
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[14]
  Delay (ns):                  2.067
  Slack (ns):
  Arrival (ns):                2.067
  Required (ns):
  Setup (ns):                  0.232
  External Setup (ns):         -1.876

Path 4
  From:                        MPM_Channel_5_DMPM_DB_DPOL3_PG
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[15]
  Delay (ns):                  2.009
  Slack (ns):
  Arrival (ns):                2.009
  Required (ns):
  Setup (ns):                  0.155
  External Setup (ns):         -2.011

Path 5
  From:                        MPM_Channel_3_DMPM_DB_DPOL1_PG
  To:                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[13]
  Delay (ns):                  2.063
  Slack (ns):
  Arrival (ns):                2.063
  Required (ns):
  Setup (ns):                  0.041
  External Setup (ns):         -2.071


Expanded Path 1
  From: A2F_BOARD_SW1_N
  To: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[28]
  data required time                             N/C
  data arrival time                          -   5.584
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        A2F_BOARD_SW1_N (r)
               +     0.000          net: A2F_BOARD_SW1_N
  0.000                        A2F_BOARD_SW1_N_pad/U0/U0:PAD (r)
               +     0.935          cell: ADLIB:IOPAD_IN
  0.935                        A2F_BOARD_SW1_N_pad/U0/U0:Y (r)
               +     0.000          net: A2F_BOARD_SW1_N_pad/U0/NET1
  0.935                        A2F_BOARD_SW1_N_pad/U0/U1:YIN (r)
               +     0.039          cell: ADLIB:IOIN_IB
  0.974                        A2F_BOARD_SW1_N_pad/U0/U1:Y (r)
               +     4.275          net: A2F_BOARD_SW1_N_c
  5.249                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_6:PIN5 (r)
               +     0.216          cell: ADLIB:MSS_IF
  5.465                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_6:PIN5INT (r)
               +     0.119          net: _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/GPI[28]INT_NET
  5.584                        _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[28] (r)
                                    
  5.584                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.175          Clock generation
  N/C
               -     0.028          Library setup time: ADLIB:MSS_APB_IP
  N/C                          _SF_MPM_RefDesign_MSS_/MSS_ADLIB_INST/U_CORE:GPI[28]


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

