----------------------------------------------------------------------
-- Created by Actel SmartDesign Fri Jun 29 16:37:29 2012
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic 
-- clock and reset pins connected.  If your design has special
-- clock/reset or testbench driver requirements then you should 
-- copy this file and modify it. 
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

    constant SYSCLK_PERIOD : time := 100 ns;

    signal SYSCLK : std_logic := '0';
    signal NSYSRESET : std_logic := '0';

    component SF_MPM_RefDesign_MSS
        -- ports
        port( 
            -- Inputs
            MSSPREADY : in std_logic;
            MSSPSLVERR : in std_logic;
            FABINT : in std_logic;
            IO_12_D : in std_logic;
            IO_12_E : in std_logic;
            IO_11_D : in std_logic;
            IO_11_E : in std_logic;
            IO_10_D : in std_logic;
            IO_10_E : in std_logic;
            IO_9_D : in std_logic;
            IO_9_E : in std_logic;
            IO_8_D : in std_logic;
            IO_8_E : in std_logic;
            IO_7_D : in std_logic;
            IO_6_D : in std_logic;
            IO_5_D : in std_logic;
            IO_4_D : in std_logic;
            IO_3_D : in std_logic;
            IO_2_D : in std_logic;
            IO_1_D : in std_logic;
            IO_0_D : in std_logic;
            F2M_GPI_29 : in std_logic;
            F2M_GPI_28 : in std_logic;
            MSSPRDATA : in std_logic_vector(31 downto 0);
            UART_0_RXD : in std_logic;
            MPM_Channel_1_DMPM_DB_APOL1_3P3V : in std_logic;
            MPM_Channel_2_DMPM_DB_APOL2_1P5V : in std_logic;
            MPM_Channel_6_A2F_BOARD_RV1_POT_2P56V : in std_logic;
            VAREF0 : in std_logic;
            VAREF1 : in std_logic;
            GPIO_15_IN : in std_logic;
            GPIO_14_IN : in std_logic;
            GPIO_13_IN : in std_logic;
            MSS_RESET_N : in std_logic;

            -- Outputs
            MSSPSEL : out std_logic;
            MSSPENABLE : out std_logic;
            MSSPWRITE : out std_logic;
            FAB_CLK : out std_logic;
            M2F_RESET_N : out std_logic;
            MSSPADDR : out std_logic_vector(19 downto 0);
            MSSPWDATA : out std_logic_vector(31 downto 0);
            UART_0_TXD : out std_logic;
            SDD0 : out std_logic;
            SDD1 : out std_logic;
            IO_0_PADOUT : out std_logic;
            IO_1_PADOUT : out std_logic;
            IO_2_PADOUT : out std_logic;
            IO_3_PADOUT : out std_logic;
            IO_4_PADOUT : out std_logic;
            IO_5_PADOUT : out std_logic;
            IO_6_PADOUT : out std_logic;
            IO_7_PADOUT : out std_logic;
            IO_8_PADTRI : out std_logic;
            IO_9_PADTRI : out std_logic;
            IO_10_PADTRI : out std_logic;
            IO_11_PADTRI : out std_logic;
            IO_12_PADTRI : out std_logic;

            -- Inouts
            I2C_0_SDA : inout std_logic;
            I2C_0_SCL : inout std_logic;
            I2C_1_SDA : inout std_logic;
            I2C_1_SCL : inout std_logic

        );
    end component;

begin

    process
        variable vhdl_initial : BOOLEAN := TRUE;

    begin
        if ( vhdl_initial ) then
            -- Assert Reset
            NSYSRESET <= '0';
            wait for ( SYSCLK_PERIOD * 10 );
            
            NSYSRESET <= '1';
            wait;
        end if;
    end process;

    -- 10MHz Clock Driver
    SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );

    -- Instantiate Unit Under Test:  SF_MPM_RefDesign_MSS
    SF_MPM_RefDesign_MSS_0 : SF_MPM_RefDesign_MSS
        -- port map
        port map( 
            -- Inputs
            MSSPREADY => '0',
            MSSPSLVERR => '0',
            FABINT => '0',
            IO_12_D => '0',
            IO_12_E => '0',
            IO_11_D => '0',
            IO_11_E => '0',
            IO_10_D => '0',
            IO_10_E => '0',
            IO_9_D => '0',
            IO_9_E => '0',
            IO_8_D => '0',
            IO_8_E => '0',
            IO_7_D => '0',
            IO_6_D => '0',
            IO_5_D => '0',
            IO_4_D => '0',
            IO_3_D => '0',
            IO_2_D => '0',
            IO_1_D => '0',
            IO_0_D => '0',
            F2M_GPI_29 => '0',
            F2M_GPI_28 => '0',
            MSSPRDATA => (others=> '0'),
            UART_0_RXD => '0',
            MPM_Channel_1_DMPM_DB_APOL1_3P3V => '0',
            MPM_Channel_2_DMPM_DB_APOL2_1P5V => '0',
            MPM_Channel_6_A2F_BOARD_RV1_POT_2P56V => '0',
            VAREF0 => '0',
            VAREF1 => '0',
            GPIO_15_IN => '0',
            GPIO_14_IN => '0',
            GPIO_13_IN => '0',
            MSS_RESET_N => NSYSRESET,

            -- Outputs
            MSSPSEL =>  open,
            MSSPENABLE =>  open,
            MSSPWRITE =>  open,
            FAB_CLK =>  open,
            M2F_RESET_N =>  open,
            MSSPADDR => open,
            MSSPWDATA => open,
            UART_0_TXD =>  open,
            SDD0 =>  open,
            SDD1 =>  open,
            IO_0_PADOUT =>  open,
            IO_1_PADOUT =>  open,
            IO_2_PADOUT =>  open,
            IO_3_PADOUT =>  open,
            IO_4_PADOUT =>  open,
            IO_5_PADOUT =>  open,
            IO_6_PADOUT =>  open,
            IO_7_PADOUT =>  open,
            IO_8_PADTRI =>  open,
            IO_9_PADTRI =>  open,
            IO_10_PADTRI =>  open,
            IO_11_PADTRI =>  open,
            IO_12_PADTRI =>  open,

            -- Inouts
            I2C_0_SDA =>  open,
            I2C_0_SCL =>  open,
            I2C_1_SDA =>  open,
            I2C_1_SCL =>  open

        );

end behavioral;

