----------------------------------------------------------------------
-- Created by Actel SmartDesign Fri Jun 29 16:38:02 2012
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic 
-- clock and reset pins connected.  If your design has special
-- clock/reset or testbench driver requirements then you should 
-- copy this file and modify it. 
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

    constant SYSCLK_PERIOD : time := 100 ns;

    signal SYSCLK : std_logic := '0';
    signal NSYSRESET : std_logic := '0';

    component SmartFusion_MPM_Reference_Design
        -- ports
        port( 
            -- Inputs
            MSS_RESET_N : in std_logic;
            MPM_Channel_5_DMPM_DB_DPOL3_PG : in std_logic;
            MPM_Channel_4_DMPM_DB_DPOL2_PG : in std_logic;
            MPM_Channel_3_DMPM_DB_DPOL1_PG : in std_logic;
            MPM_Channel_1_DMPM_DB_APOL1_3P3V : in std_logic;
            MPM_Channel_2_DMPM_DB_APOL2_1P5V : in std_logic;
            MPM_Channel_6_A2F_BOARD_RV1_POT_2P56V : in std_logic;
            VAREF0 : in std_logic;
            VAREF1 : in std_logic;
            A2F_BOARD_SW2_N : in std_logic;
            A2F_BOARD_SW1_N : in std_logic;
            UART_0_RXD : in std_logic;

            -- Outputs
            DMPM_DB_DPOL3_EN : out std_logic;
            DMPM_DB_DPOL2_EN : out std_logic;
            DMPM_DB_DPOL1_EN : out std_logic;
            DMPM_DB_APOL2_EN : out std_logic;
            DMPM_DB_APOL1_EN : out std_logic;
            DMPM_DB_LED_D7_N : out std_logic;
            DMPM_DB_LED_D6_N : out std_logic;
            DMPM_DB_LED_D5_N : out std_logic;
            DMPM_DB_LED_D4_N : out std_logic;
            DMPM_DB_LED_D3_N : out std_logic;
            DMPM_DB_LED_D2_N : out std_logic;
            DMPM_DB_LED_D1_N : out std_logic;
            DMPM_DB_LED_D0_N : out std_logic;
            MPM_Channel_1_DMPM_DB_APOL1_SDD_TRIM : out std_logic;
            MPM_Channel_2_DMPM_DB_APOL2_SDD_TRIM : out std_logic;
            A2F_BOARD_LED_D1_N : out std_logic;
            A2F_BOARD_LED_D2_N : out std_logic;
            A2F_BOARD_LED_D3_N : out std_logic;
            A2F_BOARD_LED_D4_N : out std_logic;
            MPM_Channel_1_DMPM_DB_APOL1_PWM_TRIM : out std_logic;
            MPM_Channel_2_DMPM_DB_APOL2_PWM_TRIM : out std_logic;
            UART_0_TXD : out std_logic;

            -- Inouts
            I2C_0_SCL : inout std_logic;
            I2C_0_SDA : inout std_logic;
            I2C_1_SDA : inout std_logic;
            I2C_1_SCL : inout std_logic;
            MPM_PMBus_SCL : inout std_logic;
            MPM_PMBus_SDA : inout std_logic;
            MPM_PMBus_SMBALERT : inout std_logic

        );
    end component;

begin

    process
        variable vhdl_initial : BOOLEAN := TRUE;

    begin
        if ( vhdl_initial ) then
            -- Assert Reset
            NSYSRESET <= '0';
            wait for ( SYSCLK_PERIOD * 10 );
            
            NSYSRESET <= '1';
            wait;
        end if;
    end process;

    -- 10MHz Clock Driver
    SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );

    -- Instantiate Unit Under Test:  SmartFusion_MPM_Reference_Design
    SmartFusion_MPM_Reference_Design_0 : SmartFusion_MPM_Reference_Design
        -- port map
        port map( 
            -- Inputs
            MSS_RESET_N => NSYSRESET,
            MPM_Channel_5_DMPM_DB_DPOL3_PG => '0',
            MPM_Channel_4_DMPM_DB_DPOL2_PG => '0',
            MPM_Channel_3_DMPM_DB_DPOL1_PG => '0',
            MPM_Channel_1_DMPM_DB_APOL1_3P3V => '0',
            MPM_Channel_2_DMPM_DB_APOL2_1P5V => '0',
            MPM_Channel_6_A2F_BOARD_RV1_POT_2P56V => '0',
            VAREF0 => '0',
            VAREF1 => '0',
            A2F_BOARD_SW2_N => '0',
            A2F_BOARD_SW1_N => '0',
            UART_0_RXD => '0',

            -- Outputs
            DMPM_DB_DPOL3_EN =>  open,
            DMPM_DB_DPOL2_EN =>  open,
            DMPM_DB_DPOL1_EN =>  open,
            DMPM_DB_APOL2_EN =>  open,
            DMPM_DB_APOL1_EN =>  open,
            DMPM_DB_LED_D7_N =>  open,
            DMPM_DB_LED_D6_N =>  open,
            DMPM_DB_LED_D5_N =>  open,
            DMPM_DB_LED_D4_N =>  open,
            DMPM_DB_LED_D3_N =>  open,
            DMPM_DB_LED_D2_N =>  open,
            DMPM_DB_LED_D1_N =>  open,
            DMPM_DB_LED_D0_N =>  open,
            MPM_Channel_1_DMPM_DB_APOL1_SDD_TRIM =>  open,
            MPM_Channel_2_DMPM_DB_APOL2_SDD_TRIM =>  open,
            A2F_BOARD_LED_D1_N =>  open,
            A2F_BOARD_LED_D2_N =>  open,
            A2F_BOARD_LED_D3_N =>  open,
            A2F_BOARD_LED_D4_N =>  open,
            MPM_Channel_1_DMPM_DB_APOL1_PWM_TRIM =>  open,
            MPM_Channel_2_DMPM_DB_APOL2_PWM_TRIM =>  open,
            UART_0_TXD =>  open,

            -- Inouts
            I2C_0_SCL =>  open,
            I2C_0_SDA =>  open,
            I2C_1_SDA =>  open,
            I2C_1_SCL =>  open,
            MPM_PMBus_SCL =>  open,
            MPM_PMBus_SDA =>  open,
            MPM_PMBus_SMBALERT =>  open

        );

end behavioral;

