-- Version: 10.0 SP2 10.0.20.2

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;
library COREAPB3_LIB;
use COREAPB3_LIB.all;
use COREAPB3_LIB.components.all;
library COREI2C_LIB;
use COREI2C_LIB.all;
library COREPWM_LIB;
use COREPWM_LIB.all;
library COREGPIO_LIB;
use COREGPIO_LIB.all;
use COREGPIO_LIB.components.all;

entity SmartFusion_MPM_Reference_Design is

    port( I2C_0_SCL                             : inout std_logic := 'Z';
          I2C_0_SDA                             : inout std_logic := 'Z';
          I2C_1_SDA                             : inout std_logic := 'Z';
          I2C_1_SCL                             : inout std_logic := 'Z';
          MSS_RESET_N                           : in    std_logic;
          DMPM_DB_DPOL3_EN                      : out   std_logic;
          DMPM_DB_DPOL2_EN                      : out   std_logic;
          DMPM_DB_DPOL1_EN                      : out   std_logic;
          DMPM_DB_APOL2_EN                      : out   std_logic;
          DMPM_DB_APOL1_EN                      : out   std_logic;
          DMPM_DB_LED_D7_N                      : out   std_logic;
          DMPM_DB_LED_D6_N                      : out   std_logic;
          DMPM_DB_LED_D5_N                      : out   std_logic;
          DMPM_DB_LED_D4_N                      : out   std_logic;
          DMPM_DB_LED_D3_N                      : out   std_logic;
          DMPM_DB_LED_D2_N                      : out   std_logic;
          DMPM_DB_LED_D1_N                      : out   std_logic;
          DMPM_DB_LED_D0_N                      : out   std_logic;
          MPM_Channel_5_DMPM_DB_DPOL3_PG        : in    std_logic;
          MPM_Channel_4_DMPM_DB_DPOL2_PG        : in    std_logic;
          MPM_Channel_3_DMPM_DB_DPOL1_PG        : in    std_logic;
          MPM_Channel_1_DMPM_DB_APOL1_SDD_TRIM  : out   std_logic;
          MPM_Channel_2_DMPM_DB_APOL2_SDD_TRIM  : out   std_logic;
          MPM_Channel_1_DMPM_DB_APOL1_3P3V      : in    std_logic;
          MPM_Channel_2_DMPM_DB_APOL2_1P5V      : in    std_logic;
          MPM_Channel_6_A2F_BOARD_RV1_POT_2P56V : in    std_logic;
          VAREF0                                : in    std_logic;
          VAREF1                                : in    std_logic;
          A2F_BOARD_SW2_N                       : in    std_logic;
          A2F_BOARD_SW1_N                       : in    std_logic;
          A2F_BOARD_LED_D1_N                    : out   std_logic;
          A2F_BOARD_LED_D2_N                    : out   std_logic;
          A2F_BOARD_LED_D3_N                    : out   std_logic;
          A2F_BOARD_LED_D4_N                    : out   std_logic;
          MPM_PMBus_SCL                         : inout std_logic := 'Z';
          MPM_PMBus_SDA                         : inout std_logic := 'Z';
          MPM_PMBus_SMBALERT                    : inout std_logic := 'Z';
          MPM_Channel_1_DMPM_DB_APOL1_PWM_TRIM  : out   std_logic;
          MPM_Channel_2_DMPM_DB_APOL2_PWM_TRIM  : out   std_logic;
          UART_0_TXD                            : out   std_logic;
          UART_0_RXD                            : in    std_logic
        );

end SmartFusion_MPM_Reference_Design;

architecture DEF_ARCH of SmartFusion_MPM_Reference_Design is 

  component SF_MPM_RefDesign_MSS
    port( MSS_RESET_N                           : in    std_logic := 'U';
          I2C_1_SCL                             : inout   std_logic;
          I2C_1_SDA                             : inout   std_logic;
          I2C_0_SCL                             : inout   std_logic;
          I2C_0_SDA                             : inout   std_logic;
          MSSPSEL                               : out   std_logic;
          MSSPENABLE                            : out   std_logic;
          MSSPWRITE                             : out   std_logic;
          MSSPREADY                             : in    std_logic := 'U';
          MSSPSLVERR                            : in    std_logic := 'U';
          FAB_CLK                               : out   std_logic;
          M2F_RESET_N                           : out   std_logic;
          FABINT                                : in    std_logic := 'U';
          IO_12_PADTRI                          : out   std_logic;
          IO_12_D                               : in    std_logic := 'U';
          IO_12_E                               : in    std_logic := 'U';
          IO_11_PADTRI                          : out   std_logic;
          IO_11_D                               : in    std_logic := 'U';
          IO_11_E                               : in    std_logic := 'U';
          IO_10_PADTRI                          : out   std_logic;
          IO_10_D                               : in    std_logic := 'U';
          IO_10_E                               : in    std_logic := 'U';
          IO_9_PADTRI                           : out   std_logic;
          IO_9_D                                : in    std_logic := 'U';
          IO_9_E                                : in    std_logic := 'U';
          IO_8_PADTRI                           : out   std_logic;
          IO_8_D                                : in    std_logic := 'U';
          IO_8_E                                : in    std_logic := 'U';
          IO_7_PADOUT                           : out   std_logic;
          IO_7_D                                : in    std_logic := 'U';
          IO_6_PADOUT                           : out   std_logic;
          IO_6_D                                : in    std_logic := 'U';
          IO_5_PADOUT                           : out   std_logic;
          IO_5_D                                : in    std_logic := 'U';
          IO_4_PADOUT                           : out   std_logic;
          IO_4_D                                : in    std_logic := 'U';
          IO_3_PADOUT                           : out   std_logic;
          IO_3_D                                : in    std_logic := 'U';
          IO_2_PADOUT                           : out   std_logic;
          IO_2_D                                : in    std_logic := 'U';
          IO_1_PADOUT                           : out   std_logic;
          IO_1_D                                : in    std_logic := 'U';
          IO_0_PADOUT                           : out   std_logic;
          IO_0_D                                : in    std_logic := 'U';
          F2M_GPI_29                            : in    std_logic := 'U';
          F2M_GPI_28                            : in    std_logic := 'U';
          GPIO_15_IN                            : in    std_logic := 'U';
          GPIO_14_IN                            : in    std_logic := 'U';
          GPIO_13_IN                            : in    std_logic := 'U';
          SDD0                                  : out   std_logic;
          SDD1                                  : out   std_logic;
          MPM_Channel_1_DMPM_DB_APOL1_3P3V      : in    std_logic := 'U';
          MPM_Channel_2_DMPM_DB_APOL2_1P5V      : in    std_logic := 'U';
          MPM_Channel_6_A2F_BOARD_RV1_POT_2P56V : in    std_logic := 'U';
          VAREF0                                : in    std_logic := 'U';
          VAREF1                                : in    std_logic := 'U';
          MSSPADDR                              : out   std_logic_vector(19 downto 0);
          MSSPRDATA                             : in    std_logic_vector(31 downto 0) := (others => 'U');
          MSSPWDATA                             : out   std_logic_vector(31 downto 0);
          UART_0_TXD                            : out   std_logic;
          UART_0_RXD                            : in    std_logic := 'U'
        );
  end component;

  component INV
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CoreAPB3
    generic (APB_DWIDTH:integer := 0; APBSLOT0ENABLE:integer := 0; 
        APBSLOT1ENABLE:integer := 0; APBSLOT2ENABLE:integer := 0; 
        APBSLOT3ENABLE:integer := 0; APBSLOT4ENABLE:integer := 0; 
        APBSLOT5ENABLE:integer := 0; APBSLOT6ENABLE:integer := 0; 
        APBSLOT7ENABLE:integer := 0; APBSLOT8ENABLE:integer := 0; 
        APBSLOT9ENABLE:integer := 0; APBSLOT10ENABLE:integer := 0; 
        APBSLOT11ENABLE:integer := 0; 
        APBSLOT12ENABLE:integer := 0; 
        APBSLOT13ENABLE:integer := 0; 
        APBSLOT14ENABLE:integer := 0; 
        APBSLOT15ENABLE:integer := 0; IADDR_ENABLE:integer := 0; 
        RANGESIZE:integer := 0);

    port( PRESETN    : in    std_logic := 'U';
          PCLK       : in    std_logic := 'U';
          PWRITE     : in    std_logic := 'U';
          PENABLE    : in    std_logic := 'U';
          PSEL       : in    std_logic := 'U';
          PREADY     : out   std_logic;
          PSLVERR    : out   std_logic;
          PWRITES    : out   std_logic;
          PENABLES   : out   std_logic;
          PSELS0     : out   std_logic;
          PREADYS0   : in    std_logic := 'U';
          PSLVERRS0  : in    std_logic := 'U';
          PSELS1     : out   std_logic;
          PREADYS1   : in    std_logic := 'U';
          PSLVERRS1  : in    std_logic := 'U';
          PSELS2     : out   std_logic;
          PREADYS2   : in    std_logic := 'U';
          PSLVERRS2  : in    std_logic := 'U';
          PSELS3     : out   std_logic;
          PREADYS3   : in    std_logic := 'U';
          PSLVERRS3  : in    std_logic := 'U';
          PSELS4     : out   std_logic;
          PREADYS4   : in    std_logic := 'U';
          PSLVERRS4  : in    std_logic := 'U';
          PSELS5     : out   std_logic;
          PREADYS5   : in    std_logic := 'U';
          PSLVERRS5  : in    std_logic := 'U';
          PSELS6     : out   std_logic;
          PREADYS6   : in    std_logic := 'U';
          PSLVERRS6  : in    std_logic := 'U';
          PSELS7     : out   std_logic;
          PREADYS7   : in    std_logic := 'U';
          PSLVERRS7  : in    std_logic := 'U';
          PSELS8     : out   std_logic;
          PREADYS8   : in    std_logic := 'U';
          PSLVERRS8  : in    std_logic := 'U';
          PSELS9     : out   std_logic;
          PREADYS9   : in    std_logic := 'U';
          PSLVERRS9  : in    std_logic := 'U';
          PSELS10    : out   std_logic;
          PREADYS10  : in    std_logic := 'U';
          PSLVERRS10 : in    std_logic := 'U';
          PSELS11    : out   std_logic;
          PREADYS11  : in    std_logic := 'U';
          PSLVERRS11 : in    std_logic := 'U';
          PSELS12    : out   std_logic;
          PREADYS12  : in    std_logic := 'U';
          PSLVERRS12 : in    std_logic := 'U';
          PSELS13    : out   std_logic;
          PREADYS13  : in    std_logic := 'U';
          PSLVERRS13 : in    std_logic := 'U';
          PSELS14    : out   std_logic;
          PREADYS14  : in    std_logic := 'U';
          PSLVERRS14 : in    std_logic := 'U';
          PSELS15    : out   std_logic;
          PREADYS15  : in    std_logic := 'U';
          PSLVERRS15 : in    std_logic := 'U';
          PADDR      : in    std_logic_vector(23 downto 0) := (others => 'U');
          PWDATA     : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATA     : out   std_logic_vector(31 downto 0);
          PADDRS     : out   std_logic_vector(23 downto 0);
          PADDRS0    : out   std_logic_vector(23 downto 0);
          PWDATAS    : out   std_logic_vector(31 downto 0);
          PRDATAS0   : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS1   : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS2   : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS3   : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS4   : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS5   : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS6   : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS7   : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS8   : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS9   : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS10  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS11  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS12  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS13  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS14  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS15  : in    std_logic_vector(31 downto 0) := (others => 'U')
        );
  end component;

  component BIBUF
    port( PAD : inout   std_logic;
          D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component COREI2C
    generic (ADD_SLAVE1_ADDRESS_EN:integer := 0; 
        BAUD_RATE_FIXED:integer := 0; 
        BAUD_RATE_VALUE:integer := 0; BCLK_ENABLED:integer := 0; 
        FIXED_SLAVE0_ADDR_EN:integer := 0; 
        FIXED_SLAVE0_ADDR_VALUE:integer := 0; 
        FIXED_SLAVE1_ADDR_EN:integer := 0; 
        FIXED_SLAVE1_ADDR_VALUE:integer := 0; 
        FREQUENCY:integer := 0; GLITCHREG_NUM:integer := 0; 
        I2C_NUM:integer := 0; IPMI_EN:integer := 0; 
        OPERATING_MODE:integer := 0; SMB_EN:integer := 0);

    port( BCLK        : in    std_logic := 'U';
          PCLK        : in    std_logic := 'U';
          PENABLE     : in    std_logic := 'U';
          PRESETN     : in    std_logic := 'U';
          PSEL        : in    std_logic := 'U';
          PWRITE      : in    std_logic := 'U';
          INT         : out   std_logic_vector(0 to 0);
          PADDR       : in    std_logic_vector(8 downto 0) := (others => 'U');
          PRDATA      : out   std_logic_vector(7 downto 0);
          PWDATA      : in    std_logic_vector(7 downto 0) := (others => 'U');
          SCLI        : in    std_logic_vector(0 to 0) := (others => 'U');
          SCLO        : out   std_logic_vector(0 to 0);
          SDAI        : in    std_logic_vector(0 to 0) := (others => 'U');
          SDAO        : out   std_logic_vector(0 to 0);
          SMBALERT_NI : in    std_logic_vector(0 to 0) := (others => 'U');
          SMBALERT_NO : out   std_logic_vector(0 to 0);
          SMBA_INT    : out   std_logic_vector(0 to 0);
          SMBSUS_NI   : in    std_logic_vector(0 to 0) := (others => 'U');
          SMBSUS_NO   : out   std_logic_vector(0 to 0);
          SMBS_INT    : out   std_logic_vector(0 to 0)
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component corepwm
    generic (APB_DWIDTH:integer := 0; CONFIG_MODE:integer := 0; 
        DAC_MODE1:integer := 0; DAC_MODE2:integer := 0; 
        DAC_MODE3:integer := 0; DAC_MODE4:integer := 0; 
        DAC_MODE5:integer := 0; DAC_MODE6:integer := 0; 
        DAC_MODE7:integer := 0; DAC_MODE8:integer := 0; 
        DAC_MODE9:integer := 0; DAC_MODE10:integer := 0; 
        DAC_MODE11:integer := 0; DAC_MODE12:integer := 0; 
        DAC_MODE13:integer := 0; DAC_MODE14:integer := 0; 
        DAC_MODE15:integer := 0; DAC_MODE16:integer := 0; 
        FAMILY:integer := 0; FIXED_PERIOD:integer := 0; 
        FIXED_PERIOD_EN:integer := 0; FIXED_PRESCALE:integer := 0; 
        FIXED_PRESCALE_EN:integer := 0; 
        FIXED_PWM_NEG_EN1:integer := 0; 
        FIXED_PWM_NEG_EN2:integer := 0; 
        FIXED_PWM_NEG_EN3:integer := 0; 
        FIXED_PWM_NEG_EN4:integer := 0; 
        FIXED_PWM_NEG_EN5:integer := 0; 
        FIXED_PWM_NEG_EN6:integer := 0; 
        FIXED_PWM_NEG_EN7:integer := 0; 
        FIXED_PWM_NEG_EN8:integer := 0; 
        FIXED_PWM_NEG_EN9:integer := 0; 
        FIXED_PWM_NEG_EN10:integer := 0; 
        FIXED_PWM_NEG_EN11:integer := 0; 
        FIXED_PWM_NEG_EN12:integer := 0; 
        FIXED_PWM_NEG_EN13:integer := 0; 
        FIXED_PWM_NEG_EN14:integer := 0; 
        FIXED_PWM_NEG_EN15:integer := 0; 
        FIXED_PWM_NEG_EN16:integer := 0; 
        FIXED_PWM_NEGEDGE1:integer := 0; 
        FIXED_PWM_NEGEDGE2:integer := 0; 
        FIXED_PWM_NEGEDGE3:integer := 0; 
        FIXED_PWM_NEGEDGE4:integer := 0; 
        FIXED_PWM_NEGEDGE5:integer := 0; 
        FIXED_PWM_NEGEDGE6:integer := 0; 
        FIXED_PWM_NEGEDGE7:integer := 0; 
        FIXED_PWM_NEGEDGE8:integer := 0; 
        FIXED_PWM_NEGEDGE9:integer := 0; 
        FIXED_PWM_NEGEDGE10:integer := 0; 
        FIXED_PWM_NEGEDGE11:integer := 0; 
        FIXED_PWM_NEGEDGE12:integer := 0; 
        FIXED_PWM_NEGEDGE13:integer := 0; 
        FIXED_PWM_NEGEDGE14:integer := 0; 
        FIXED_PWM_NEGEDGE15:integer := 0; 
        FIXED_PWM_NEGEDGE16:integer := 0; 
        FIXED_PWM_POS_EN1:integer := 0; 
        FIXED_PWM_POS_EN2:integer := 0; 
        FIXED_PWM_POS_EN3:integer := 0; 
        FIXED_PWM_POS_EN4:integer := 0; 
        FIXED_PWM_POS_EN5:integer := 0; 
        FIXED_PWM_POS_EN6:integer := 0; 
        FIXED_PWM_POS_EN7:integer := 0; 
        FIXED_PWM_POS_EN8:integer := 0; 
        FIXED_PWM_POS_EN9:integer := 0; 
        FIXED_PWM_POS_EN10:integer := 0; 
        FIXED_PWM_POS_EN11:integer := 0; 
        FIXED_PWM_POS_EN12:integer := 0; 
        FIXED_PWM_POS_EN13:integer := 0; 
        FIXED_PWM_POS_EN14:integer := 0; 
        FIXED_PWM_POS_EN15:integer := 0; 
        FIXED_PWM_POS_EN16:integer := 0; 
        FIXED_PWM_POSEDGE1:integer := 0; 
        FIXED_PWM_POSEDGE2:integer := 0; 
        FIXED_PWM_POSEDGE3:integer := 0; 
        FIXED_PWM_POSEDGE4:integer := 0; 
        FIXED_PWM_POSEDGE5:integer := 0; 
        FIXED_PWM_POSEDGE6:integer := 0; 
        FIXED_PWM_POSEDGE7:integer := 0; 
        FIXED_PWM_POSEDGE8:integer := 0; 
        FIXED_PWM_POSEDGE9:integer := 0; 
        FIXED_PWM_POSEDGE10:integer := 0; 
        FIXED_PWM_POSEDGE11:integer := 0; 
        FIXED_PWM_POSEDGE12:integer := 0; 
        FIXED_PWM_POSEDGE13:integer := 0; 
        FIXED_PWM_POSEDGE14:integer := 0; 
        FIXED_PWM_POSEDGE15:integer := 0; 
        FIXED_PWM_POSEDGE16:integer := 0; PWM_NUM:integer := 0; 
        PWM_STRETCH_VALUE1:integer := 0; 
        PWM_STRETCH_VALUE2:integer := 0; 
        PWM_STRETCH_VALUE3:integer := 0; 
        PWM_STRETCH_VALUE4:integer := 0; 
        PWM_STRETCH_VALUE5:integer := 0; 
        PWM_STRETCH_VALUE6:integer := 0; 
        PWM_STRETCH_VALUE7:integer := 0; 
        PWM_STRETCH_VALUE8:integer := 0; 
        PWM_STRETCH_VALUE9:integer := 0; 
        PWM_STRETCH_VALUE10:integer := 0; 
        PWM_STRETCH_VALUE11:integer := 0; 
        PWM_STRETCH_VALUE12:integer := 0; 
        PWM_STRETCH_VALUE13:integer := 0; 
        PWM_STRETCH_VALUE14:integer := 0; 
        PWM_STRETCH_VALUE15:integer := 0; 
        PWM_STRETCH_VALUE16:integer := 0; 
        SHADOW_REG_EN1:integer := 0; SHADOW_REG_EN2:integer := 0; 
        SHADOW_REG_EN3:integer := 0; SHADOW_REG_EN4:integer := 0; 
        SHADOW_REG_EN5:integer := 0; SHADOW_REG_EN6:integer := 0; 
        SHADOW_REG_EN7:integer := 0; SHADOW_REG_EN8:integer := 0; 
        SHADOW_REG_EN9:integer := 0; SHADOW_REG_EN10:integer := 0; 
        SHADOW_REG_EN11:integer := 0; 
        SHADOW_REG_EN12:integer := 0; 
        SHADOW_REG_EN13:integer := 0; 
        SHADOW_REG_EN14:integer := 0; 
        SHADOW_REG_EN15:integer := 0; 
        SHADOW_REG_EN16:integer := 0; TACH_EDGE1:integer := 0; 
        TACH_EDGE2:integer := 0; TACH_EDGE3:integer := 0; 
        TACH_EDGE4:integer := 0; TACH_EDGE5:integer := 0; 
        TACH_EDGE6:integer := 0; TACH_EDGE7:integer := 0; 
        TACH_EDGE8:integer := 0; TACH_EDGE9:integer := 0; 
        TACH_EDGE10:integer := 0; TACH_EDGE11:integer := 0; 
        TACH_EDGE12:integer := 0; TACH_EDGE13:integer := 0; 
        TACH_EDGE14:integer := 0; TACH_EDGE15:integer := 0; 
        TACH_EDGE16:integer := 0; TACH_NUM:integer := 0; 
        TACHINT_ACT_LEVEL:integer := 0);

    port( PCLK    : in    std_logic := 'U';
          PENABLE : in    std_logic := 'U';
          PRESETN : in    std_logic := 'U';
          PSEL    : in    std_logic := 'U';
          PREADY  : out   std_logic;
          PSLVERR : out   std_logic;
          TACHINT : out   std_logic;
          PWRITE  : in    std_logic := 'U';
          PADDR   : in    std_logic_vector(7 downto 0) := (others => 'U');
          PRDATA  : out   std_logic_vector(15 downto 0);
          PWDATA  : in    std_logic_vector(15 downto 0) := (others => 'U');
          TACHIN  : in    std_logic_vector(1 to 1) := (others => 'U');
          PWM     : out   std_logic_vector(3 downto 1)
        );
  end component;

  component CoreGPIO
    generic (APB_WIDTH:integer := 0; FAMILY:integer := 0; 
        FIXED_CONFIG_0:integer := 0; FIXED_CONFIG_1:integer := 0; 
        FIXED_CONFIG_2:integer := 0; FIXED_CONFIG_3:integer := 0; 
        FIXED_CONFIG_4:integer := 0; FIXED_CONFIG_5:integer := 0; 
        FIXED_CONFIG_6:integer := 0; FIXED_CONFIG_7:integer := 0; 
        FIXED_CONFIG_8:integer := 0; FIXED_CONFIG_9:integer := 0; 
        FIXED_CONFIG_10:integer := 0; 
        FIXED_CONFIG_11:integer := 0; 
        FIXED_CONFIG_12:integer := 0; 
        FIXED_CONFIG_13:integer := 0; 
        FIXED_CONFIG_14:integer := 0; 
        FIXED_CONFIG_15:integer := 0; 
        FIXED_CONFIG_16:integer := 0; 
        FIXED_CONFIG_17:integer := 0; 
        FIXED_CONFIG_18:integer := 0; 
        FIXED_CONFIG_19:integer := 0; 
        FIXED_CONFIG_20:integer := 0; 
        FIXED_CONFIG_21:integer := 0; 
        FIXED_CONFIG_22:integer := 0; 
        FIXED_CONFIG_23:integer := 0; 
        FIXED_CONFIG_24:integer := 0; 
        FIXED_CONFIG_25:integer := 0; 
        FIXED_CONFIG_26:integer := 0; 
        FIXED_CONFIG_27:integer := 0; 
        FIXED_CONFIG_28:integer := 0; 
        FIXED_CONFIG_29:integer := 0; 
        FIXED_CONFIG_30:integer := 0; 
        FIXED_CONFIG_31:integer := 0; INT_BUS:integer := 0; 
        IO_INT_TYPE_0:integer := 0; IO_INT_TYPE_1:integer := 0; 
        IO_INT_TYPE_2:integer := 0; IO_INT_TYPE_3:integer := 0; 
        IO_INT_TYPE_4:integer := 0; IO_INT_TYPE_5:integer := 0; 
        IO_INT_TYPE_6:integer := 0; IO_INT_TYPE_7:integer := 0; 
        IO_INT_TYPE_8:integer := 0; IO_INT_TYPE_9:integer := 0; 
        IO_INT_TYPE_10:integer := 0; IO_INT_TYPE_11:integer := 0; 
        IO_INT_TYPE_12:integer := 0; IO_INT_TYPE_13:integer := 0; 
        IO_INT_TYPE_14:integer := 0; IO_INT_TYPE_15:integer := 0; 
        IO_INT_TYPE_16:integer := 0; IO_INT_TYPE_17:integer := 0; 
        IO_INT_TYPE_18:integer := 0; IO_INT_TYPE_19:integer := 0; 
        IO_INT_TYPE_20:integer := 0; IO_INT_TYPE_21:integer := 0; 
        IO_INT_TYPE_22:integer := 0; IO_INT_TYPE_23:integer := 0; 
        IO_INT_TYPE_24:integer := 0; IO_INT_TYPE_25:integer := 0; 
        IO_INT_TYPE_26:integer := 0; IO_INT_TYPE_27:integer := 0; 
        IO_INT_TYPE_28:integer := 0; IO_INT_TYPE_29:integer := 0; 
        IO_INT_TYPE_30:integer := 0; IO_INT_TYPE_31:integer := 0; 
        IO_NUM:integer := 0; IO_TYPE_0:integer := 0; 
        IO_TYPE_1:integer := 0; IO_TYPE_2:integer := 0; 
        IO_TYPE_3:integer := 0; IO_TYPE_4:integer := 0; 
        IO_TYPE_5:integer := 0; IO_TYPE_6:integer := 0; 
        IO_TYPE_7:integer := 0; IO_TYPE_8:integer := 0; 
        IO_TYPE_9:integer := 0; IO_TYPE_10:integer := 0; 
        IO_TYPE_11:integer := 0; IO_TYPE_12:integer := 0; 
        IO_TYPE_13:integer := 0; IO_TYPE_14:integer := 0; 
        IO_TYPE_15:integer := 0; IO_TYPE_16:integer := 0; 
        IO_TYPE_17:integer := 0; IO_TYPE_18:integer := 0; 
        IO_TYPE_19:integer := 0; IO_TYPE_20:integer := 0; 
        IO_TYPE_21:integer := 0; IO_TYPE_22:integer := 0; 
        IO_TYPE_23:integer := 0; IO_TYPE_24:integer := 0; 
        IO_TYPE_25:integer := 0; IO_TYPE_26:integer := 0; 
        IO_TYPE_27:integer := 0; IO_TYPE_28:integer := 0; 
        IO_TYPE_29:integer := 0; IO_TYPE_30:integer := 0; 
        IO_TYPE_31:integer := 0; IO_VAL_0:integer := 0; 
        IO_VAL_1:integer := 0; IO_VAL_2:integer := 0; 
        IO_VAL_3:integer := 0; IO_VAL_4:integer := 0; 
        IO_VAL_5:integer := 0; IO_VAL_6:integer := 0; 
        IO_VAL_7:integer := 0; IO_VAL_8:integer := 0; 
        IO_VAL_9:integer := 0; IO_VAL_10:integer := 0; 
        IO_VAL_11:integer := 0; IO_VAL_12:integer := 0; 
        IO_VAL_13:integer := 0; IO_VAL_14:integer := 0; 
        IO_VAL_15:integer := 0; IO_VAL_16:integer := 0; 
        IO_VAL_17:integer := 0; IO_VAL_18:integer := 0; 
        IO_VAL_19:integer := 0; IO_VAL_20:integer := 0; 
        IO_VAL_21:integer := 0; IO_VAL_22:integer := 0; 
        IO_VAL_23:integer := 0; IO_VAL_24:integer := 0; 
        IO_VAL_25:integer := 0; IO_VAL_26:integer := 0; 
        IO_VAL_27:integer := 0; IO_VAL_28:integer := 0; 
        IO_VAL_29:integer := 0; IO_VAL_30:integer := 0; 
        IO_VAL_31:integer := 0; OE_TYPE:integer := 0);

    port( PRESETN  : in    std_logic := 'U';
          PCLK     : in    std_logic := 'U';
          PSEL     : in    std_logic := 'U';
          PENABLE  : in    std_logic := 'U';
          PWRITE   : in    std_logic := 'U';
          PSLVERR  : out   std_logic;
          PREADY   : out   std_logic;
          INT_OR   : out   std_logic;
          PADDR    : in    std_logic_vector(7 downto 0) := (others => 'U');
          PWDATA   : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATA   : out   std_logic_vector(31 downto 0);
          INT      : out   std_logic_vector(31 downto 0);
          GPIO_IN  : in    std_logic_vector(31 downto 0) := (others => 'U');
          GPIO_OUT : out   std_logic_vector(31 downto 0);
          GPIO_OE  : out   std_logic_vector(31 downto 0)
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

    signal \CoreAPB3_0_APBmslave0_PADDR_[0]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[1]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[2]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[3]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[4]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[5]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[6]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[7]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[8]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[9]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[10]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[11]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[12]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[13]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[14]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[15]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[16]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[17]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[18]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[19]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[20]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[21]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[22]\, 
        \CoreAPB3_0_APBmslave0_PADDR_[23]\, 
        CoreAPB3_0_APBmslave0_PENABLE, 
        \CoreAPB3_0_APBmslave0_PRDATA_[0]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[1]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[2]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[3]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[4]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[5]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[6]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[7]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[8]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[9]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[10]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[11]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[12]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[13]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[14]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[15]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[16]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[17]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[18]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[19]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[20]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[21]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[22]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[23]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[24]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[25]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[26]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[27]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[28]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[29]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[30]\, 
        \CoreAPB3_0_APBmslave0_PRDATA_[31]\, 
        CoreAPB3_0_APBmslave0_PREADY, CoreAPB3_0_APBmslave0_PSELx, 
        CoreAPB3_0_APBmslave0_PSLVERR, 
        \CoreAPB3_0_APBmslave0_PWDATA_[0]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[1]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[2]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[3]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[4]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[5]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[6]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[7]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[8]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[9]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[10]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[11]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[12]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[13]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[14]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[15]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[16]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[17]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[18]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[19]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[20]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[21]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[22]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[23]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[24]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[25]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[26]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[27]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[28]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[29]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[30]\, 
        \CoreAPB3_0_APBmslave0_PWDATA_[31]\, 
        CoreAPB3_0_APBmslave0_PWRITE, 
        \CoreAPB3_0_APBmslave1_PADDR_[0]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[1]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[2]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[3]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[4]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[5]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[6]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[7]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[8]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[9]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[10]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[11]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[12]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[13]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[14]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[15]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[16]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[17]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[18]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[19]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[20]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[21]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[22]\, 
        \CoreAPB3_0_APBmslave1_PADDR_[23]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[0]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[1]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[2]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[3]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[4]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[5]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[6]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[7]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[8]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[9]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[10]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[11]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[12]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[13]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[14]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[15]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[16]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[17]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[18]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[19]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[20]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[21]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[22]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[23]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[24]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[25]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[26]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[27]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[28]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[29]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[30]\, 
        \CoreAPB3_0_APBmslave1_PRDATA_[31]\, 
        CoreAPB3_0_APBmslave1_PREADY, CoreAPB3_0_APBmslave1_PSELx, 
        CoreAPB3_0_APBmslave1_PSLVERR, 
        \CoreAPB3_0_APBmslave2_PRDATA_[0]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[1]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[2]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[3]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[4]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[5]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[6]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[7]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[8]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[9]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[10]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[11]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[12]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[13]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[14]\, 
        \CoreAPB3_0_APBmslave2_PRDATA_[15]\, 
        CoreAPB3_0_APBmslave2_PREADY, CoreAPB3_0_APBmslave2_PSELx, 
        CoreAPB3_0_APBmslave2_PSLVERR, 
        \CoreAPB3_0_APBmslave3_PRDATA_[0]\, 
        \CoreAPB3_0_APBmslave3_PRDATA_[1]\, 
        \CoreAPB3_0_APBmslave3_PRDATA_[2]\, 
        \CoreAPB3_0_APBmslave3_PRDATA_[3]\, 
        \CoreAPB3_0_APBmslave3_PRDATA_[4]\, 
        \CoreAPB3_0_APBmslave3_PRDATA_[5]\, 
        \CoreAPB3_0_APBmslave3_PRDATA_[6]\, 
        \CoreAPB3_0_APBmslave3_PRDATA_[7]\, 
        CoreAPB3_0_APBmslave3_PSELx, 
        MPM_GPIO_Digital_IOs_GPIO_OUT0to0, 
        MPM_GPIO_Digital_IOs_GPIO_OUT1to1, 
        MPM_GPIO_Digital_IOs_GPIO_OUT2to2, 
        MPM_GPIO_Digital_IOs_GPIO_OUT3to3, 
        MPM_GPIO_Digital_IOs_GPIO_OUT4to4, 
        MPM_GPIO_Digital_IOs_GPIO_OUT5to5, 
        MPM_GPIO_Digital_IOs_GPIO_OUT6to6, 
        MPM_GPIO_Digital_IOs_GPIO_OUT7to7, 
        MPM_GPIO_Regulator_Enables_GPIO_OUT0to0, INV_0_Y, 
        MPM_GPIO_Regulator_Enables_GPIO_OUT1to1, INV_1_Y, 
        MPM_GPIO_Regulator_Enables_GPIO_OUT2to2, INV_2_Y, 
        MPM_GPIO_Regulator_Enables_GPIO_OUT3to3, INV_3_Y, 
        MPM_GPIO_Regulator_Enables_GPIO_OUT4to4, INV_4_Y, 
        MPM_PMBus_I2C_INT, MPM_PMBus_I2C_SCLO, INV_5_Y, 
        MPM_PMBus_I2C_SDAO, INV_6_Y, MPM_PMBus_I2C_SMBALERT_NO, 
        INV_7_Y, MPM_PMBus_SCL_BIBUF_Y, MPM_PMBus_SDA_BIBUF_Y, 
        MPM_PMBus_SMBALERT_BIBUF_Y, 
        SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK, 
        SmartFusion_MPM_Reference_Design_MSS_0_M2F_RESET_N, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[0]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[1]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[2]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[3]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[4]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[5]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[6]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[7]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[8]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[9]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[10]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[11]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[12]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[13]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[14]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[15]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[16]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[17]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[18]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[19]\, 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PENABLE, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[0]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[1]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[2]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[3]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[4]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[5]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[6]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[7]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[8]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[9]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[10]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[11]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[12]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[13]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[14]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[15]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[16]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[17]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[18]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[19]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[20]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[21]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[22]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[23]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[24]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[25]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[26]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[27]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[28]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[29]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[30]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[31]\, 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PREADY, 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PSELx, 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PSLVERR, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[0]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[1]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[2]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[3]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[4]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[5]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[6]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[7]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[8]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[9]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[10]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[11]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[12]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[13]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[14]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[15]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[16]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[17]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[18]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[19]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[20]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[21]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[22]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[23]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[24]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[25]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[26]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[27]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[28]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[29]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[30]\, 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[31]\, 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWRITE, 
        GND_net, VCC_net : std_logic;
    signal nc151, nc23, nc175, nc58, nc116, nc74, nc133, nc167, 
        nc84, nc39, nc72, nc82, nc145, nc160, nc57, nc156, nc125, 
        nc73, nc107, nc66, nc83, nc9, nc171, nc54, nc135, nc41, 
        nc100, nc52, nc29, nc118, nc60, nc141, nc45, nc53, nc121, 
        nc176, nc158, nc162, nc11, nc131, nc96, nc79, nc146, nc89, 
        nc119, nc48, nc126, nc15, nc102, nc3, nc47, nc90, nc159, 
        nc136, nc178, nc59, nc18, nc44, nc117, nc164, nc148, nc42, 
        nc17, nc2, nc110, nc128, nc43, nc179, nc157, nc36, nc61, 
        nc104, nc138, nc14, nc150, nc149, nc12, nc30, nc65, nc7, 
        nc129, nc8, nc13, nc26, nc177, nc139, nc163, nc112, nc68, 
        nc49, nc170, nc91, nc5, nc20, nc147, nc67, nc152, nc127, 
        nc103, nc76, nc140, nc86, nc95, nc120, nc165, nc137, nc64, 
        nc19, nc70, nc62, nc80, nc130, nc98, nc114, nc56, nc105, 
        nc63, nc172, nc97, nc161, nc31, nc154, nc50, nc142, nc94, 
        nc122, nc35, nc4, nc92, nc101, nc166, nc132, nc21, nc93, 
        nc69, nc174, nc38, nc113, nc106, nc25, nc1, nc37, nc144, 
        nc153, nc46, nc71, nc124, nc81, nc168, nc34, nc28, nc115, 
        nc134, nc32, nc40, nc99, nc75, nc85, nc27, nc108, nc16, 
        nc155, nc51, nc33, nc173, nc169, nc78, nc24, nc88, nc111, 
        nc55, nc10, nc22, nc143, nc77, nc6, nc109, nc87, nc123
         : std_logic;

begin 


    \SF_MPM_RefDesign_MSS\ : SF_MPM_RefDesign_MSS
      port map(MSS_RESET_N => MSS_RESET_N, I2C_1_SCL => I2C_1_SCL, 
        I2C_1_SDA => I2C_1_SDA, I2C_0_SCL => I2C_0_SCL, I2C_0_SDA
         => I2C_0_SDA, MSSPSEL => 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PSELx, 
        MSSPENABLE => 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PENABLE, 
        MSSPWRITE => 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWRITE, 
        MSSPREADY => 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PREADY, 
        MSSPSLVERR => 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PSLVERR, 
        FAB_CLK => SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK, 
        M2F_RESET_N => 
        SmartFusion_MPM_Reference_Design_MSS_0_M2F_RESET_N, 
        FABINT => MPM_PMBus_I2C_INT, IO_12_PADTRI => 
        DMPM_DB_DPOL3_EN, IO_12_D => GND_net, IO_12_E => INV_4_Y, 
        IO_11_PADTRI => DMPM_DB_DPOL2_EN, IO_11_D => GND_net, 
        IO_11_E => INV_3_Y, IO_10_PADTRI => DMPM_DB_DPOL1_EN, 
        IO_10_D => GND_net, IO_10_E => INV_2_Y, IO_9_PADTRI => 
        DMPM_DB_APOL2_EN, IO_9_D => GND_net, IO_9_E => INV_1_Y, 
        IO_8_PADTRI => DMPM_DB_APOL1_EN, IO_8_D => GND_net, 
        IO_8_E => INV_0_Y, IO_7_PADOUT => DMPM_DB_LED_D7_N, 
        IO_7_D => MPM_GPIO_Digital_IOs_GPIO_OUT7to7, IO_6_PADOUT
         => DMPM_DB_LED_D6_N, IO_6_D => 
        MPM_GPIO_Digital_IOs_GPIO_OUT6to6, IO_5_PADOUT => 
        DMPM_DB_LED_D5_N, IO_5_D => 
        MPM_GPIO_Digital_IOs_GPIO_OUT5to5, IO_4_PADOUT => 
        DMPM_DB_LED_D4_N, IO_4_D => 
        MPM_GPIO_Digital_IOs_GPIO_OUT4to4, IO_3_PADOUT => 
        DMPM_DB_LED_D3_N, IO_3_D => 
        MPM_GPIO_Digital_IOs_GPIO_OUT3to3, IO_2_PADOUT => 
        DMPM_DB_LED_D2_N, IO_2_D => 
        MPM_GPIO_Digital_IOs_GPIO_OUT2to2, IO_1_PADOUT => 
        DMPM_DB_LED_D1_N, IO_1_D => 
        MPM_GPIO_Digital_IOs_GPIO_OUT1to1, IO_0_PADOUT => 
        DMPM_DB_LED_D0_N, IO_0_D => 
        MPM_GPIO_Digital_IOs_GPIO_OUT0to0, F2M_GPI_29 => 
        A2F_BOARD_SW2_N, F2M_GPI_28 => A2F_BOARD_SW1_N, 
        GPIO_15_IN => MPM_Channel_5_DMPM_DB_DPOL3_PG, GPIO_14_IN
         => MPM_Channel_4_DMPM_DB_DPOL2_PG, GPIO_13_IN => 
        MPM_Channel_3_DMPM_DB_DPOL1_PG, SDD0 => 
        MPM_Channel_1_DMPM_DB_APOL1_SDD_TRIM, SDD1 => 
        MPM_Channel_2_DMPM_DB_APOL2_SDD_TRIM, 
        MPM_Channel_1_DMPM_DB_APOL1_3P3V => 
        MPM_Channel_1_DMPM_DB_APOL1_3P3V, 
        MPM_Channel_2_DMPM_DB_APOL2_1P5V => 
        MPM_Channel_2_DMPM_DB_APOL2_1P5V, 
        MPM_Channel_6_A2F_BOARD_RV1_POT_2P56V => 
        MPM_Channel_6_A2F_BOARD_RV1_POT_2P56V, VAREF0 => VAREF0, 
        VAREF1 => VAREF1, MSSPADDR(19) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[19]\, 
        MSSPADDR(18) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[18]\, 
        MSSPADDR(17) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[17]\, 
        MSSPADDR(16) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[16]\, 
        MSSPADDR(15) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[15]\, 
        MSSPADDR(14) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[14]\, 
        MSSPADDR(13) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[13]\, 
        MSSPADDR(12) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[12]\, 
        MSSPADDR(11) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[11]\, 
        MSSPADDR(10) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[10]\, 
        MSSPADDR(9) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[9]\, 
        MSSPADDR(8) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[8]\, 
        MSSPADDR(7) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[7]\, 
        MSSPADDR(6) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[6]\, 
        MSSPADDR(5) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[5]\, 
        MSSPADDR(4) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[4]\, 
        MSSPADDR(3) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[3]\, 
        MSSPADDR(2) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[2]\, 
        MSSPADDR(1) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[1]\, 
        MSSPADDR(0) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[0]\, 
        MSSPRDATA(31) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[31]\, 
        MSSPRDATA(30) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[30]\, 
        MSSPRDATA(29) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[29]\, 
        MSSPRDATA(28) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[28]\, 
        MSSPRDATA(27) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[27]\, 
        MSSPRDATA(26) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[26]\, 
        MSSPRDATA(25) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[25]\, 
        MSSPRDATA(24) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[24]\, 
        MSSPRDATA(23) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[23]\, 
        MSSPRDATA(22) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[22]\, 
        MSSPRDATA(21) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[21]\, 
        MSSPRDATA(20) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[20]\, 
        MSSPRDATA(19) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[19]\, 
        MSSPRDATA(18) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[18]\, 
        MSSPRDATA(17) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[17]\, 
        MSSPRDATA(16) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[16]\, 
        MSSPRDATA(15) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[15]\, 
        MSSPRDATA(14) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[14]\, 
        MSSPRDATA(13) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[13]\, 
        MSSPRDATA(12) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[12]\, 
        MSSPRDATA(11) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[11]\, 
        MSSPRDATA(10) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[10]\, 
        MSSPRDATA(9) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[9]\, 
        MSSPRDATA(8) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[8]\, 
        MSSPRDATA(7) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[7]\, 
        MSSPRDATA(6) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[6]\, 
        MSSPRDATA(5) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[5]\, 
        MSSPRDATA(4) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[4]\, 
        MSSPRDATA(3) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[3]\, 
        MSSPRDATA(2) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[2]\, 
        MSSPRDATA(1) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[1]\, 
        MSSPRDATA(0) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[0]\, 
        MSSPWDATA(31) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[31]\, 
        MSSPWDATA(30) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[30]\, 
        MSSPWDATA(29) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[29]\, 
        MSSPWDATA(28) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[28]\, 
        MSSPWDATA(27) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[27]\, 
        MSSPWDATA(26) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[26]\, 
        MSSPWDATA(25) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[25]\, 
        MSSPWDATA(24) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[24]\, 
        MSSPWDATA(23) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[23]\, 
        MSSPWDATA(22) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[22]\, 
        MSSPWDATA(21) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[21]\, 
        MSSPWDATA(20) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[20]\, 
        MSSPWDATA(19) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[19]\, 
        MSSPWDATA(18) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[18]\, 
        MSSPWDATA(17) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[17]\, 
        MSSPWDATA(16) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[16]\, 
        MSSPWDATA(15) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[15]\, 
        MSSPWDATA(14) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[14]\, 
        MSSPWDATA(13) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[13]\, 
        MSSPWDATA(12) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[12]\, 
        MSSPWDATA(11) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[11]\, 
        MSSPWDATA(10) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[10]\, 
        MSSPWDATA(9) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[9]\, 
        MSSPWDATA(8) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[8]\, 
        MSSPWDATA(7) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[7]\, 
        MSSPWDATA(6) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[6]\, 
        MSSPWDATA(5) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[5]\, 
        MSSPWDATA(4) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[4]\, 
        MSSPWDATA(3) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[3]\, 
        MSSPWDATA(2) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[2]\, 
        MSSPWDATA(1) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[1]\, 
        MSSPWDATA(0) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[0]\, 
        UART_0_TXD => UART_0_TXD, UART_0_RXD => UART_0_RXD);
    
    INV_4 : INV
      port map(A => MPM_GPIO_Regulator_Enables_GPIO_OUT4to4, Y
         => INV_4_Y);
    
    CoreAPB3_0 : CoreAPB3
      generic map(APB_DWIDTH => 32, APBSLOT0ENABLE => 1,
         APBSLOT1ENABLE => 1, APBSLOT2ENABLE => 1,
         APBSLOT3ENABLE => 1, APBSLOT4ENABLE => 0,
         APBSLOT5ENABLE => 0, APBSLOT6ENABLE => 0,
         APBSLOT7ENABLE => 0, APBSLOT8ENABLE => 0,
         APBSLOT9ENABLE => 0, APBSLOT10ENABLE => 0,
         APBSLOT11ENABLE => 0, APBSLOT12ENABLE => 0,
         APBSLOT13ENABLE => 0, APBSLOT14ENABLE => 0,
         APBSLOT15ENABLE => 0, IADDR_ENABLE => 0,
         RANGESIZE => 512)

      port map(PRESETN => GND_net, PCLK => GND_net, PWRITE => 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWRITE, 
        PENABLE => 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PENABLE, 
        PSEL => 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PSELx, 
        PREADY => 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PREADY, 
        PSLVERR => 
        SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PSLVERR, 
        PWRITES => CoreAPB3_0_APBmslave0_PWRITE, PENABLES => 
        CoreAPB3_0_APBmslave0_PENABLE, PSELS0 => 
        CoreAPB3_0_APBmslave0_PSELx, PREADYS0 => 
        CoreAPB3_0_APBmslave0_PREADY, PSLVERRS0 => 
        CoreAPB3_0_APBmslave0_PSLVERR, PSELS1 => 
        CoreAPB3_0_APBmslave1_PSELx, PREADYS1 => 
        CoreAPB3_0_APBmslave1_PREADY, PSLVERRS1 => 
        CoreAPB3_0_APBmslave1_PSLVERR, PSELS2 => 
        CoreAPB3_0_APBmslave2_PSELx, PREADYS2 => 
        CoreAPB3_0_APBmslave2_PREADY, PSLVERRS2 => 
        CoreAPB3_0_APBmslave2_PSLVERR, PSELS3 => 
        CoreAPB3_0_APBmslave3_PSELx, PREADYS3 => VCC_net, 
        PSLVERRS3 => GND_net, PSELS4 => OPEN, PREADYS4 => VCC_net, 
        PSLVERRS4 => GND_net, PSELS5 => OPEN, PREADYS5 => VCC_net, 
        PSLVERRS5 => GND_net, PSELS6 => OPEN, PREADYS6 => VCC_net, 
        PSLVERRS6 => GND_net, PSELS7 => OPEN, PREADYS7 => VCC_net, 
        PSLVERRS7 => GND_net, PSELS8 => OPEN, PREADYS8 => VCC_net, 
        PSLVERRS8 => GND_net, PSELS9 => OPEN, PREADYS9 => VCC_net, 
        PSLVERRS9 => GND_net, PSELS10 => OPEN, PREADYS10 => 
        VCC_net, PSLVERRS10 => GND_net, PSELS11 => OPEN, 
        PREADYS11 => VCC_net, PSLVERRS11 => GND_net, PSELS12 => 
        OPEN, PREADYS12 => VCC_net, PSLVERRS12 => GND_net, 
        PSELS13 => OPEN, PREADYS13 => VCC_net, PSLVERRS13 => 
        GND_net, PSELS14 => OPEN, PREADYS14 => VCC_net, 
        PSLVERRS14 => GND_net, PSELS15 => OPEN, PREADYS15 => 
        VCC_net, PSLVERRS15 => GND_net, PADDR(23) => GND_net, 
        PADDR(22) => GND_net, PADDR(21) => GND_net, PADDR(20) => 
        GND_net, PADDR(19) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[19]\, 
        PADDR(18) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[18]\, 
        PADDR(17) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[17]\, 
        PADDR(16) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[16]\, 
        PADDR(15) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[15]\, 
        PADDR(14) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[14]\, 
        PADDR(13) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[13]\, 
        PADDR(12) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[12]\, 
        PADDR(11) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[11]\, 
        PADDR(10) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[10]\, 
        PADDR(9) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[9]\, 
        PADDR(8) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[8]\, 
        PADDR(7) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[7]\, 
        PADDR(6) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[6]\, 
        PADDR(5) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[5]\, 
        PADDR(4) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[4]\, 
        PADDR(3) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[3]\, 
        PADDR(2) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[2]\, 
        PADDR(1) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[1]\, 
        PADDR(0) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[0]\, 
        PWDATA(31) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[31]\, 
        PWDATA(30) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[30]\, 
        PWDATA(29) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[29]\, 
        PWDATA(28) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[28]\, 
        PWDATA(27) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[27]\, 
        PWDATA(26) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[26]\, 
        PWDATA(25) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[25]\, 
        PWDATA(24) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[24]\, 
        PWDATA(23) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[23]\, 
        PWDATA(22) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[22]\, 
        PWDATA(21) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[21]\, 
        PWDATA(20) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[20]\, 
        PWDATA(19) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[19]\, 
        PWDATA(18) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[18]\, 
        PWDATA(17) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[17]\, 
        PWDATA(16) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[16]\, 
        PWDATA(15) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[15]\, 
        PWDATA(14) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[14]\, 
        PWDATA(13) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[13]\, 
        PWDATA(12) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[12]\, 
        PWDATA(11) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[11]\, 
        PWDATA(10) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[10]\, 
        PWDATA(9) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[9]\, 
        PWDATA(8) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[8]\, 
        PWDATA(7) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[7]\, 
        PWDATA(6) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[6]\, 
        PWDATA(5) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[5]\, 
        PWDATA(4) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[4]\, 
        PWDATA(3) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[3]\, 
        PWDATA(2) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[2]\, 
        PWDATA(1) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[1]\, 
        PWDATA(0) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PWDATA_[0]\, 
        PRDATA(31) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[31]\, 
        PRDATA(30) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[30]\, 
        PRDATA(29) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[29]\, 
        PRDATA(28) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[28]\, 
        PRDATA(27) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[27]\, 
        PRDATA(26) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[26]\, 
        PRDATA(25) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[25]\, 
        PRDATA(24) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[24]\, 
        PRDATA(23) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[23]\, 
        PRDATA(22) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[22]\, 
        PRDATA(21) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[21]\, 
        PRDATA(20) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[20]\, 
        PRDATA(19) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[19]\, 
        PRDATA(18) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[18]\, 
        PRDATA(17) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[17]\, 
        PRDATA(16) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[16]\, 
        PRDATA(15) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[15]\, 
        PRDATA(14) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[14]\, 
        PRDATA(13) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[13]\, 
        PRDATA(12) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[12]\, 
        PRDATA(11) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[11]\, 
        PRDATA(10) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[10]\, 
        PRDATA(9) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[9]\, 
        PRDATA(8) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[8]\, 
        PRDATA(7) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[7]\, 
        PRDATA(6) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[6]\, 
        PRDATA(5) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[5]\, 
        PRDATA(4) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[4]\, 
        PRDATA(3) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[3]\, 
        PRDATA(2) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[2]\, 
        PRDATA(1) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[1]\, 
        PRDATA(0) => 
        \SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PRDATA_[0]\, 
        PADDRS(23) => \CoreAPB3_0_APBmslave1_PADDR_[23]\, 
        PADDRS(22) => \CoreAPB3_0_APBmslave1_PADDR_[22]\, 
        PADDRS(21) => \CoreAPB3_0_APBmslave1_PADDR_[21]\, 
        PADDRS(20) => \CoreAPB3_0_APBmslave1_PADDR_[20]\, 
        PADDRS(19) => \CoreAPB3_0_APBmslave1_PADDR_[19]\, 
        PADDRS(18) => \CoreAPB3_0_APBmslave1_PADDR_[18]\, 
        PADDRS(17) => \CoreAPB3_0_APBmslave1_PADDR_[17]\, 
        PADDRS(16) => \CoreAPB3_0_APBmslave1_PADDR_[16]\, 
        PADDRS(15) => \CoreAPB3_0_APBmslave1_PADDR_[15]\, 
        PADDRS(14) => \CoreAPB3_0_APBmslave1_PADDR_[14]\, 
        PADDRS(13) => \CoreAPB3_0_APBmslave1_PADDR_[13]\, 
        PADDRS(12) => \CoreAPB3_0_APBmslave1_PADDR_[12]\, 
        PADDRS(11) => \CoreAPB3_0_APBmslave1_PADDR_[11]\, 
        PADDRS(10) => \CoreAPB3_0_APBmslave1_PADDR_[10]\, 
        PADDRS(9) => \CoreAPB3_0_APBmslave1_PADDR_[9]\, PADDRS(8)
         => \CoreAPB3_0_APBmslave1_PADDR_[8]\, PADDRS(7) => 
        \CoreAPB3_0_APBmslave1_PADDR_[7]\, PADDRS(6) => 
        \CoreAPB3_0_APBmslave1_PADDR_[6]\, PADDRS(5) => 
        \CoreAPB3_0_APBmslave1_PADDR_[5]\, PADDRS(4) => 
        \CoreAPB3_0_APBmslave1_PADDR_[4]\, PADDRS(3) => 
        \CoreAPB3_0_APBmslave1_PADDR_[3]\, PADDRS(2) => 
        \CoreAPB3_0_APBmslave1_PADDR_[2]\, PADDRS(1) => 
        \CoreAPB3_0_APBmslave1_PADDR_[1]\, PADDRS(0) => 
        \CoreAPB3_0_APBmslave1_PADDR_[0]\, PADDRS0(23) => 
        \CoreAPB3_0_APBmslave0_PADDR_[23]\, PADDRS0(22) => 
        \CoreAPB3_0_APBmslave0_PADDR_[22]\, PADDRS0(21) => 
        \CoreAPB3_0_APBmslave0_PADDR_[21]\, PADDRS0(20) => 
        \CoreAPB3_0_APBmslave0_PADDR_[20]\, PADDRS0(19) => 
        \CoreAPB3_0_APBmslave0_PADDR_[19]\, PADDRS0(18) => 
        \CoreAPB3_0_APBmslave0_PADDR_[18]\, PADDRS0(17) => 
        \CoreAPB3_0_APBmslave0_PADDR_[17]\, PADDRS0(16) => 
        \CoreAPB3_0_APBmslave0_PADDR_[16]\, PADDRS0(15) => 
        \CoreAPB3_0_APBmslave0_PADDR_[15]\, PADDRS0(14) => 
        \CoreAPB3_0_APBmslave0_PADDR_[14]\, PADDRS0(13) => 
        \CoreAPB3_0_APBmslave0_PADDR_[13]\, PADDRS0(12) => 
        \CoreAPB3_0_APBmslave0_PADDR_[12]\, PADDRS0(11) => 
        \CoreAPB3_0_APBmslave0_PADDR_[11]\, PADDRS0(10) => 
        \CoreAPB3_0_APBmslave0_PADDR_[10]\, PADDRS0(9) => 
        \CoreAPB3_0_APBmslave0_PADDR_[9]\, PADDRS0(8) => 
        \CoreAPB3_0_APBmslave0_PADDR_[8]\, PADDRS0(7) => 
        \CoreAPB3_0_APBmslave0_PADDR_[7]\, PADDRS0(6) => 
        \CoreAPB3_0_APBmslave0_PADDR_[6]\, PADDRS0(5) => 
        \CoreAPB3_0_APBmslave0_PADDR_[5]\, PADDRS0(4) => 
        \CoreAPB3_0_APBmslave0_PADDR_[4]\, PADDRS0(3) => 
        \CoreAPB3_0_APBmslave0_PADDR_[3]\, PADDRS0(2) => 
        \CoreAPB3_0_APBmslave0_PADDR_[2]\, PADDRS0(1) => 
        \CoreAPB3_0_APBmslave0_PADDR_[1]\, PADDRS0(0) => 
        \CoreAPB3_0_APBmslave0_PADDR_[0]\, PWDATAS(31) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[31]\, PWDATAS(30) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[30]\, PWDATAS(29) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[29]\, PWDATAS(28) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[28]\, PWDATAS(27) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[27]\, PWDATAS(26) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[26]\, PWDATAS(25) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[25]\, PWDATAS(24) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[24]\, PWDATAS(23) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[23]\, PWDATAS(22) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[22]\, PWDATAS(21) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[21]\, PWDATAS(20) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[20]\, PWDATAS(19) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[19]\, PWDATAS(18) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[18]\, PWDATAS(17) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[17]\, PWDATAS(16) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[16]\, PWDATAS(15) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[15]\, PWDATAS(14) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[14]\, PWDATAS(13) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[13]\, PWDATAS(12) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[12]\, PWDATAS(11) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[11]\, PWDATAS(10) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[10]\, PWDATAS(9) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[9]\, PWDATAS(8) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[8]\, PWDATAS(7) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[7]\, PWDATAS(6) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[6]\, PWDATAS(5) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[5]\, PWDATAS(4) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[4]\, PWDATAS(3) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[3]\, PWDATAS(2) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[2]\, PWDATAS(1) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[1]\, PWDATAS(0) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[0]\, PRDATAS0(31) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[31]\, PRDATAS0(30) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[30]\, PRDATAS0(29) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[29]\, PRDATAS0(28) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[28]\, PRDATAS0(27) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[27]\, PRDATAS0(26) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[26]\, PRDATAS0(25) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[25]\, PRDATAS0(24) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[24]\, PRDATAS0(23) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[23]\, PRDATAS0(22) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[22]\, PRDATAS0(21) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[21]\, PRDATAS0(20) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[20]\, PRDATAS0(19) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[19]\, PRDATAS0(18) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[18]\, PRDATAS0(17) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[17]\, PRDATAS0(16) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[16]\, PRDATAS0(15) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[15]\, PRDATAS0(14) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[14]\, PRDATAS0(13) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[13]\, PRDATAS0(12) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[12]\, PRDATAS0(11) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[11]\, PRDATAS0(10) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[10]\, PRDATAS0(9) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[9]\, PRDATAS0(8) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[8]\, PRDATAS0(7) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[7]\, PRDATAS0(6) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[6]\, PRDATAS0(5) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[5]\, PRDATAS0(4) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[4]\, PRDATAS0(3) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[3]\, PRDATAS0(2) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[2]\, PRDATAS0(1) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[1]\, PRDATAS0(0) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[0]\, PRDATAS1(31) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[31]\, PRDATAS1(30) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[30]\, PRDATAS1(29) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[29]\, PRDATAS1(28) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[28]\, PRDATAS1(27) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[27]\, PRDATAS1(26) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[26]\, PRDATAS1(25) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[25]\, PRDATAS1(24) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[24]\, PRDATAS1(23) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[23]\, PRDATAS1(22) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[22]\, PRDATAS1(21) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[21]\, PRDATAS1(20) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[20]\, PRDATAS1(19) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[19]\, PRDATAS1(18) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[18]\, PRDATAS1(17) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[17]\, PRDATAS1(16) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[16]\, PRDATAS1(15) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[15]\, PRDATAS1(14) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[14]\, PRDATAS1(13) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[13]\, PRDATAS1(12) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[12]\, PRDATAS1(11) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[11]\, PRDATAS1(10) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[10]\, PRDATAS1(9) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[9]\, PRDATAS1(8) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[8]\, PRDATAS1(7) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[7]\, PRDATAS1(6) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[6]\, PRDATAS1(5) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[5]\, PRDATAS1(4) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[4]\, PRDATAS1(3) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[3]\, PRDATAS1(2) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[2]\, PRDATAS1(1) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[1]\, PRDATAS1(0) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[0]\, PRDATAS2(31) => 
        GND_net, PRDATAS2(30) => GND_net, PRDATAS2(29) => GND_net, 
        PRDATAS2(28) => GND_net, PRDATAS2(27) => GND_net, 
        PRDATAS2(26) => GND_net, PRDATAS2(25) => GND_net, 
        PRDATAS2(24) => GND_net, PRDATAS2(23) => GND_net, 
        PRDATAS2(22) => GND_net, PRDATAS2(21) => GND_net, 
        PRDATAS2(20) => GND_net, PRDATAS2(19) => GND_net, 
        PRDATAS2(18) => GND_net, PRDATAS2(17) => GND_net, 
        PRDATAS2(16) => GND_net, PRDATAS2(15) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[15]\, PRDATAS2(14) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[14]\, PRDATAS2(13) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[13]\, PRDATAS2(12) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[12]\, PRDATAS2(11) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[11]\, PRDATAS2(10) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[10]\, PRDATAS2(9) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[9]\, PRDATAS2(8) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[8]\, PRDATAS2(7) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[7]\, PRDATAS2(6) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[6]\, PRDATAS2(5) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[5]\, PRDATAS2(4) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[4]\, PRDATAS2(3) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[3]\, PRDATAS2(2) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[2]\, PRDATAS2(1) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[1]\, PRDATAS2(0) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[0]\, PRDATAS3(31) => 
        GND_net, PRDATAS3(30) => GND_net, PRDATAS3(29) => GND_net, 
        PRDATAS3(28) => GND_net, PRDATAS3(27) => GND_net, 
        PRDATAS3(26) => GND_net, PRDATAS3(25) => GND_net, 
        PRDATAS3(24) => GND_net, PRDATAS3(23) => GND_net, 
        PRDATAS3(22) => GND_net, PRDATAS3(21) => GND_net, 
        PRDATAS3(20) => GND_net, PRDATAS3(19) => GND_net, 
        PRDATAS3(18) => GND_net, PRDATAS3(17) => GND_net, 
        PRDATAS3(16) => GND_net, PRDATAS3(15) => GND_net, 
        PRDATAS3(14) => GND_net, PRDATAS3(13) => GND_net, 
        PRDATAS3(12) => GND_net, PRDATAS3(11) => GND_net, 
        PRDATAS3(10) => GND_net, PRDATAS3(9) => GND_net, 
        PRDATAS3(8) => GND_net, PRDATAS3(7) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[7]\, PRDATAS3(6) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[6]\, PRDATAS3(5) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[5]\, PRDATAS3(4) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[4]\, PRDATAS3(3) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[3]\, PRDATAS3(2) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[2]\, PRDATAS3(1) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[1]\, PRDATAS3(0) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[0]\, PRDATAS4(31) => 
        GND_net, PRDATAS4(30) => GND_net, PRDATAS4(29) => GND_net, 
        PRDATAS4(28) => GND_net, PRDATAS4(27) => GND_net, 
        PRDATAS4(26) => GND_net, PRDATAS4(25) => GND_net, 
        PRDATAS4(24) => GND_net, PRDATAS4(23) => GND_net, 
        PRDATAS4(22) => GND_net, PRDATAS4(21) => GND_net, 
        PRDATAS4(20) => GND_net, PRDATAS4(19) => GND_net, 
        PRDATAS4(18) => GND_net, PRDATAS4(17) => GND_net, 
        PRDATAS4(16) => GND_net, PRDATAS4(15) => GND_net, 
        PRDATAS4(14) => GND_net, PRDATAS4(13) => GND_net, 
        PRDATAS4(12) => GND_net, PRDATAS4(11) => GND_net, 
        PRDATAS4(10) => GND_net, PRDATAS4(9) => GND_net, 
        PRDATAS4(8) => GND_net, PRDATAS4(7) => GND_net, 
        PRDATAS4(6) => GND_net, PRDATAS4(5) => GND_net, 
        PRDATAS4(4) => GND_net, PRDATAS4(3) => GND_net, 
        PRDATAS4(2) => GND_net, PRDATAS4(1) => GND_net, 
        PRDATAS4(0) => GND_net, PRDATAS5(31) => GND_net, 
        PRDATAS5(30) => GND_net, PRDATAS5(29) => GND_net, 
        PRDATAS5(28) => GND_net, PRDATAS5(27) => GND_net, 
        PRDATAS5(26) => GND_net, PRDATAS5(25) => GND_net, 
        PRDATAS5(24) => GND_net, PRDATAS5(23) => GND_net, 
        PRDATAS5(22) => GND_net, PRDATAS5(21) => GND_net, 
        PRDATAS5(20) => GND_net, PRDATAS5(19) => GND_net, 
        PRDATAS5(18) => GND_net, PRDATAS5(17) => GND_net, 
        PRDATAS5(16) => GND_net, PRDATAS5(15) => GND_net, 
        PRDATAS5(14) => GND_net, PRDATAS5(13) => GND_net, 
        PRDATAS5(12) => GND_net, PRDATAS5(11) => GND_net, 
        PRDATAS5(10) => GND_net, PRDATAS5(9) => GND_net, 
        PRDATAS5(8) => GND_net, PRDATAS5(7) => GND_net, 
        PRDATAS5(6) => GND_net, PRDATAS5(5) => GND_net, 
        PRDATAS5(4) => GND_net, PRDATAS5(3) => GND_net, 
        PRDATAS5(2) => GND_net, PRDATAS5(1) => GND_net, 
        PRDATAS5(0) => GND_net, PRDATAS6(31) => GND_net, 
        PRDATAS6(30) => GND_net, PRDATAS6(29) => GND_net, 
        PRDATAS6(28) => GND_net, PRDATAS6(27) => GND_net, 
        PRDATAS6(26) => GND_net, PRDATAS6(25) => GND_net, 
        PRDATAS6(24) => GND_net, PRDATAS6(23) => GND_net, 
        PRDATAS6(22) => GND_net, PRDATAS6(21) => GND_net, 
        PRDATAS6(20) => GND_net, PRDATAS6(19) => GND_net, 
        PRDATAS6(18) => GND_net, PRDATAS6(17) => GND_net, 
        PRDATAS6(16) => GND_net, PRDATAS6(15) => GND_net, 
        PRDATAS6(14) => GND_net, PRDATAS6(13) => GND_net, 
        PRDATAS6(12) => GND_net, PRDATAS6(11) => GND_net, 
        PRDATAS6(10) => GND_net, PRDATAS6(9) => GND_net, 
        PRDATAS6(8) => GND_net, PRDATAS6(7) => GND_net, 
        PRDATAS6(6) => GND_net, PRDATAS6(5) => GND_net, 
        PRDATAS6(4) => GND_net, PRDATAS6(3) => GND_net, 
        PRDATAS6(2) => GND_net, PRDATAS6(1) => GND_net, 
        PRDATAS6(0) => GND_net, PRDATAS7(31) => GND_net, 
        PRDATAS7(30) => GND_net, PRDATAS7(29) => GND_net, 
        PRDATAS7(28) => GND_net, PRDATAS7(27) => GND_net, 
        PRDATAS7(26) => GND_net, PRDATAS7(25) => GND_net, 
        PRDATAS7(24) => GND_net, PRDATAS7(23) => GND_net, 
        PRDATAS7(22) => GND_net, PRDATAS7(21) => GND_net, 
        PRDATAS7(20) => GND_net, PRDATAS7(19) => GND_net, 
        PRDATAS7(18) => GND_net, PRDATAS7(17) => GND_net, 
        PRDATAS7(16) => GND_net, PRDATAS7(15) => GND_net, 
        PRDATAS7(14) => GND_net, PRDATAS7(13) => GND_net, 
        PRDATAS7(12) => GND_net, PRDATAS7(11) => GND_net, 
        PRDATAS7(10) => GND_net, PRDATAS7(9) => GND_net, 
        PRDATAS7(8) => GND_net, PRDATAS7(7) => GND_net, 
        PRDATAS7(6) => GND_net, PRDATAS7(5) => GND_net, 
        PRDATAS7(4) => GND_net, PRDATAS7(3) => GND_net, 
        PRDATAS7(2) => GND_net, PRDATAS7(1) => GND_net, 
        PRDATAS7(0) => GND_net, PRDATAS8(31) => GND_net, 
        PRDATAS8(30) => GND_net, PRDATAS8(29) => GND_net, 
        PRDATAS8(28) => GND_net, PRDATAS8(27) => GND_net, 
        PRDATAS8(26) => GND_net, PRDATAS8(25) => GND_net, 
        PRDATAS8(24) => GND_net, PRDATAS8(23) => GND_net, 
        PRDATAS8(22) => GND_net, PRDATAS8(21) => GND_net, 
        PRDATAS8(20) => GND_net, PRDATAS8(19) => GND_net, 
        PRDATAS8(18) => GND_net, PRDATAS8(17) => GND_net, 
        PRDATAS8(16) => GND_net, PRDATAS8(15) => GND_net, 
        PRDATAS8(14) => GND_net, PRDATAS8(13) => GND_net, 
        PRDATAS8(12) => GND_net, PRDATAS8(11) => GND_net, 
        PRDATAS8(10) => GND_net, PRDATAS8(9) => GND_net, 
        PRDATAS8(8) => GND_net, PRDATAS8(7) => GND_net, 
        PRDATAS8(6) => GND_net, PRDATAS8(5) => GND_net, 
        PRDATAS8(4) => GND_net, PRDATAS8(3) => GND_net, 
        PRDATAS8(2) => GND_net, PRDATAS8(1) => GND_net, 
        PRDATAS8(0) => GND_net, PRDATAS9(31) => GND_net, 
        PRDATAS9(30) => GND_net, PRDATAS9(29) => GND_net, 
        PRDATAS9(28) => GND_net, PRDATAS9(27) => GND_net, 
        PRDATAS9(26) => GND_net, PRDATAS9(25) => GND_net, 
        PRDATAS9(24) => GND_net, PRDATAS9(23) => GND_net, 
        PRDATAS9(22) => GND_net, PRDATAS9(21) => GND_net, 
        PRDATAS9(20) => GND_net, PRDATAS9(19) => GND_net, 
        PRDATAS9(18) => GND_net, PRDATAS9(17) => GND_net, 
        PRDATAS9(16) => GND_net, PRDATAS9(15) => GND_net, 
        PRDATAS9(14) => GND_net, PRDATAS9(13) => GND_net, 
        PRDATAS9(12) => GND_net, PRDATAS9(11) => GND_net, 
        PRDATAS9(10) => GND_net, PRDATAS9(9) => GND_net, 
        PRDATAS9(8) => GND_net, PRDATAS9(7) => GND_net, 
        PRDATAS9(6) => GND_net, PRDATAS9(5) => GND_net, 
        PRDATAS9(4) => GND_net, PRDATAS9(3) => GND_net, 
        PRDATAS9(2) => GND_net, PRDATAS9(1) => GND_net, 
        PRDATAS9(0) => GND_net, PRDATAS10(31) => GND_net, 
        PRDATAS10(30) => GND_net, PRDATAS10(29) => GND_net, 
        PRDATAS10(28) => GND_net, PRDATAS10(27) => GND_net, 
        PRDATAS10(26) => GND_net, PRDATAS10(25) => GND_net, 
        PRDATAS10(24) => GND_net, PRDATAS10(23) => GND_net, 
        PRDATAS10(22) => GND_net, PRDATAS10(21) => GND_net, 
        PRDATAS10(20) => GND_net, PRDATAS10(19) => GND_net, 
        PRDATAS10(18) => GND_net, PRDATAS10(17) => GND_net, 
        PRDATAS10(16) => GND_net, PRDATAS10(15) => GND_net, 
        PRDATAS10(14) => GND_net, PRDATAS10(13) => GND_net, 
        PRDATAS10(12) => GND_net, PRDATAS10(11) => GND_net, 
        PRDATAS10(10) => GND_net, PRDATAS10(9) => GND_net, 
        PRDATAS10(8) => GND_net, PRDATAS10(7) => GND_net, 
        PRDATAS10(6) => GND_net, PRDATAS10(5) => GND_net, 
        PRDATAS10(4) => GND_net, PRDATAS10(3) => GND_net, 
        PRDATAS10(2) => GND_net, PRDATAS10(1) => GND_net, 
        PRDATAS10(0) => GND_net, PRDATAS11(31) => GND_net, 
        PRDATAS11(30) => GND_net, PRDATAS11(29) => GND_net, 
        PRDATAS11(28) => GND_net, PRDATAS11(27) => GND_net, 
        PRDATAS11(26) => GND_net, PRDATAS11(25) => GND_net, 
        PRDATAS11(24) => GND_net, PRDATAS11(23) => GND_net, 
        PRDATAS11(22) => GND_net, PRDATAS11(21) => GND_net, 
        PRDATAS11(20) => GND_net, PRDATAS11(19) => GND_net, 
        PRDATAS11(18) => GND_net, PRDATAS11(17) => GND_net, 
        PRDATAS11(16) => GND_net, PRDATAS11(15) => GND_net, 
        PRDATAS11(14) => GND_net, PRDATAS11(13) => GND_net, 
        PRDATAS11(12) => GND_net, PRDATAS11(11) => GND_net, 
        PRDATAS11(10) => GND_net, PRDATAS11(9) => GND_net, 
        PRDATAS11(8) => GND_net, PRDATAS11(7) => GND_net, 
        PRDATAS11(6) => GND_net, PRDATAS11(5) => GND_net, 
        PRDATAS11(4) => GND_net, PRDATAS11(3) => GND_net, 
        PRDATAS11(2) => GND_net, PRDATAS11(1) => GND_net, 
        PRDATAS11(0) => GND_net, PRDATAS12(31) => GND_net, 
        PRDATAS12(30) => GND_net, PRDATAS12(29) => GND_net, 
        PRDATAS12(28) => GND_net, PRDATAS12(27) => GND_net, 
        PRDATAS12(26) => GND_net, PRDATAS12(25) => GND_net, 
        PRDATAS12(24) => GND_net, PRDATAS12(23) => GND_net, 
        PRDATAS12(22) => GND_net, PRDATAS12(21) => GND_net, 
        PRDATAS12(20) => GND_net, PRDATAS12(19) => GND_net, 
        PRDATAS12(18) => GND_net, PRDATAS12(17) => GND_net, 
        PRDATAS12(16) => GND_net, PRDATAS12(15) => GND_net, 
        PRDATAS12(14) => GND_net, PRDATAS12(13) => GND_net, 
        PRDATAS12(12) => GND_net, PRDATAS12(11) => GND_net, 
        PRDATAS12(10) => GND_net, PRDATAS12(9) => GND_net, 
        PRDATAS12(8) => GND_net, PRDATAS12(7) => GND_net, 
        PRDATAS12(6) => GND_net, PRDATAS12(5) => GND_net, 
        PRDATAS12(4) => GND_net, PRDATAS12(3) => GND_net, 
        PRDATAS12(2) => GND_net, PRDATAS12(1) => GND_net, 
        PRDATAS12(0) => GND_net, PRDATAS13(31) => GND_net, 
        PRDATAS13(30) => GND_net, PRDATAS13(29) => GND_net, 
        PRDATAS13(28) => GND_net, PRDATAS13(27) => GND_net, 
        PRDATAS13(26) => GND_net, PRDATAS13(25) => GND_net, 
        PRDATAS13(24) => GND_net, PRDATAS13(23) => GND_net, 
        PRDATAS13(22) => GND_net, PRDATAS13(21) => GND_net, 
        PRDATAS13(20) => GND_net, PRDATAS13(19) => GND_net, 
        PRDATAS13(18) => GND_net, PRDATAS13(17) => GND_net, 
        PRDATAS13(16) => GND_net, PRDATAS13(15) => GND_net, 
        PRDATAS13(14) => GND_net, PRDATAS13(13) => GND_net, 
        PRDATAS13(12) => GND_net, PRDATAS13(11) => GND_net, 
        PRDATAS13(10) => GND_net, PRDATAS13(9) => GND_net, 
        PRDATAS13(8) => GND_net, PRDATAS13(7) => GND_net, 
        PRDATAS13(6) => GND_net, PRDATAS13(5) => GND_net, 
        PRDATAS13(4) => GND_net, PRDATAS13(3) => GND_net, 
        PRDATAS13(2) => GND_net, PRDATAS13(1) => GND_net, 
        PRDATAS13(0) => GND_net, PRDATAS14(31) => GND_net, 
        PRDATAS14(30) => GND_net, PRDATAS14(29) => GND_net, 
        PRDATAS14(28) => GND_net, PRDATAS14(27) => GND_net, 
        PRDATAS14(26) => GND_net, PRDATAS14(25) => GND_net, 
        PRDATAS14(24) => GND_net, PRDATAS14(23) => GND_net, 
        PRDATAS14(22) => GND_net, PRDATAS14(21) => GND_net, 
        PRDATAS14(20) => GND_net, PRDATAS14(19) => GND_net, 
        PRDATAS14(18) => GND_net, PRDATAS14(17) => GND_net, 
        PRDATAS14(16) => GND_net, PRDATAS14(15) => GND_net, 
        PRDATAS14(14) => GND_net, PRDATAS14(13) => GND_net, 
        PRDATAS14(12) => GND_net, PRDATAS14(11) => GND_net, 
        PRDATAS14(10) => GND_net, PRDATAS14(9) => GND_net, 
        PRDATAS14(8) => GND_net, PRDATAS14(7) => GND_net, 
        PRDATAS14(6) => GND_net, PRDATAS14(5) => GND_net, 
        PRDATAS14(4) => GND_net, PRDATAS14(3) => GND_net, 
        PRDATAS14(2) => GND_net, PRDATAS14(1) => GND_net, 
        PRDATAS14(0) => GND_net, PRDATAS15(31) => GND_net, 
        PRDATAS15(30) => GND_net, PRDATAS15(29) => GND_net, 
        PRDATAS15(28) => GND_net, PRDATAS15(27) => GND_net, 
        PRDATAS15(26) => GND_net, PRDATAS15(25) => GND_net, 
        PRDATAS15(24) => GND_net, PRDATAS15(23) => GND_net, 
        PRDATAS15(22) => GND_net, PRDATAS15(21) => GND_net, 
        PRDATAS15(20) => GND_net, PRDATAS15(19) => GND_net, 
        PRDATAS15(18) => GND_net, PRDATAS15(17) => GND_net, 
        PRDATAS15(16) => GND_net, PRDATAS15(15) => GND_net, 
        PRDATAS15(14) => GND_net, PRDATAS15(13) => GND_net, 
        PRDATAS15(12) => GND_net, PRDATAS15(11) => GND_net, 
        PRDATAS15(10) => GND_net, PRDATAS15(9) => GND_net, 
        PRDATAS15(8) => GND_net, PRDATAS15(7) => GND_net, 
        PRDATAS15(6) => GND_net, PRDATAS15(5) => GND_net, 
        PRDATAS15(4) => GND_net, PRDATAS15(3) => GND_net, 
        PRDATAS15(2) => GND_net, PRDATAS15(1) => GND_net, 
        PRDATAS15(0) => GND_net);
    
    MPM_PMBus_SMBALERT_BIBUF : BIBUF
      port map(PAD => MPM_PMBus_SMBALERT, D => 
        MPM_PMBus_I2C_SMBALERT_NO, E => INV_7_Y, Y => 
        MPM_PMBus_SMBALERT_BIBUF_Y);
    
    INV_7 : INV
      port map(A => MPM_PMBus_I2C_SMBALERT_NO, Y => INV_7_Y);
    
    MPM_PMBus_I2C : COREI2C
      generic map(ADD_SLAVE1_ADDRESS_EN => 0,
         BAUD_RATE_FIXED => 0, BAUD_RATE_VALUE => 0,
         BCLK_ENABLED => 0, FIXED_SLAVE0_ADDR_EN => 0,
         FIXED_SLAVE0_ADDR_VALUE => 16#0#,
         FIXED_SLAVE1_ADDR_EN => 0,
         FIXED_SLAVE1_ADDR_VALUE => 16#0#, FREQUENCY => 20,
         GLITCHREG_NUM => 3, I2C_NUM => 1, IPMI_EN => 0,
         OPERATING_MODE => 0, SMB_EN => 1)

      port map(BCLK => GND_net, PCLK => 
        SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK, PENABLE
         => CoreAPB3_0_APBmslave0_PENABLE, PRESETN => 
        SmartFusion_MPM_Reference_Design_MSS_0_M2F_RESET_N, PSEL
         => CoreAPB3_0_APBmslave3_PSELx, PWRITE => 
        CoreAPB3_0_APBmslave0_PWRITE, INT(0) => MPM_PMBus_I2C_INT, 
        PADDR(8) => \CoreAPB3_0_APBmslave1_PADDR_[8]\, PADDR(7)
         => \CoreAPB3_0_APBmslave1_PADDR_[7]\, PADDR(6) => 
        \CoreAPB3_0_APBmslave1_PADDR_[6]\, PADDR(5) => 
        \CoreAPB3_0_APBmslave1_PADDR_[5]\, PADDR(4) => 
        \CoreAPB3_0_APBmslave1_PADDR_[4]\, PADDR(3) => 
        \CoreAPB3_0_APBmslave1_PADDR_[3]\, PADDR(2) => 
        \CoreAPB3_0_APBmslave1_PADDR_[2]\, PADDR(1) => 
        \CoreAPB3_0_APBmslave1_PADDR_[1]\, PADDR(0) => 
        \CoreAPB3_0_APBmslave1_PADDR_[0]\, PRDATA(7) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[7]\, PRDATA(6) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[6]\, PRDATA(5) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[5]\, PRDATA(4) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[4]\, PRDATA(3) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[3]\, PRDATA(2) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[2]\, PRDATA(1) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[1]\, PRDATA(0) => 
        \CoreAPB3_0_APBmslave3_PRDATA_[0]\, PWDATA(7) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[7]\, PWDATA(6) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[6]\, PWDATA(5) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[5]\, PWDATA(4) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[4]\, PWDATA(3) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[3]\, PWDATA(2) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[2]\, PWDATA(1) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[1]\, PWDATA(0) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[0]\, SCLI(0) => 
        MPM_PMBus_SCL_BIBUF_Y, SCLO(0) => MPM_PMBus_I2C_SCLO, 
        SDAI(0) => MPM_PMBus_SDA_BIBUF_Y, SDAO(0) => 
        MPM_PMBus_I2C_SDAO, SMBALERT_NI(0) => 
        MPM_PMBus_SMBALERT_BIBUF_Y, SMBALERT_NO(0) => 
        MPM_PMBus_I2C_SMBALERT_NO, SMBA_INT(0) => nc151, 
        SMBSUS_NI(0) => VCC_net, SMBSUS_NO(0) => nc23, 
        SMBS_INT(0) => nc175);
    
    INV_0 : INV
      port map(A => MPM_GPIO_Regulator_Enables_GPIO_OUT0to0, Y
         => INV_0_Y);
    
    \GND\ : GND
      port map(Y => GND_net);
    
    INV_6 : INV
      port map(A => MPM_PMBus_I2C_SDAO, Y => INV_6_Y);
    
    MPM_PMBus_SDA_BIBUF : BIBUF
      port map(PAD => MPM_PMBus_SDA, D => MPM_PMBus_I2C_SDAO, E
         => INV_6_Y, Y => MPM_PMBus_SDA_BIBUF_Y);
    
    INV_5 : INV
      port map(A => MPM_PMBus_I2C_SCLO, Y => INV_5_Y);
    
    INV_3 : INV
      port map(A => MPM_GPIO_Regulator_Enables_GPIO_OUT3to3, Y
         => INV_3_Y);
    
    MPM_PWM_Trimming_Outputs : corepwm
      generic map(APB_DWIDTH => 16, CONFIG_MODE => 0,
         DAC_MODE1 => 1, DAC_MODE2 => 1, DAC_MODE3 => 0,
         DAC_MODE4 => 0, DAC_MODE5 => 0, DAC_MODE6 => 0,
         DAC_MODE7 => 0, DAC_MODE8 => 0, DAC_MODE9 => 0,
         DAC_MODE10 => 0, DAC_MODE11 => 0, DAC_MODE12 => 0,
         DAC_MODE13 => 0, DAC_MODE14 => 0, DAC_MODE15 => 0,
         DAC_MODE16 => 0, FAMILY => 15, FIXED_PERIOD => 1,
         FIXED_PERIOD_EN => 0, FIXED_PRESCALE => 0,
         FIXED_PRESCALE_EN => 0, FIXED_PWM_NEG_EN1 => 0,
         FIXED_PWM_NEG_EN2 => 0, FIXED_PWM_NEG_EN3 => 0,
         FIXED_PWM_NEG_EN4 => 0, FIXED_PWM_NEG_EN5 => 0,
         FIXED_PWM_NEG_EN6 => 0, FIXED_PWM_NEG_EN7 => 0,
         FIXED_PWM_NEG_EN8 => 0, FIXED_PWM_NEG_EN9 => 0,
         FIXED_PWM_NEG_EN10 => 0, FIXED_PWM_NEG_EN11 => 0,
         FIXED_PWM_NEG_EN12 => 0, FIXED_PWM_NEG_EN13 => 0,
         FIXED_PWM_NEG_EN14 => 0, FIXED_PWM_NEG_EN15 => 0,
         FIXED_PWM_NEG_EN16 => 0, FIXED_PWM_NEGEDGE1 => 0,
         FIXED_PWM_NEGEDGE2 => 0, FIXED_PWM_NEGEDGE3 => 0,
         FIXED_PWM_NEGEDGE4 => 0, FIXED_PWM_NEGEDGE5 => 0,
         FIXED_PWM_NEGEDGE6 => 0, FIXED_PWM_NEGEDGE7 => 0,
         FIXED_PWM_NEGEDGE8 => 0, FIXED_PWM_NEGEDGE9 => 0,
         FIXED_PWM_NEGEDGE10 => 0, FIXED_PWM_NEGEDGE11 => 0,
         FIXED_PWM_NEGEDGE12 => 0, FIXED_PWM_NEGEDGE13 => 0,
         FIXED_PWM_NEGEDGE14 => 0, FIXED_PWM_NEGEDGE15 => 0,
         FIXED_PWM_NEGEDGE16 => 0, FIXED_PWM_POS_EN1 => 0,
         FIXED_PWM_POS_EN2 => 0, FIXED_PWM_POS_EN3 => 1,
         FIXED_PWM_POS_EN4 => 1, FIXED_PWM_POS_EN5 => 1,
         FIXED_PWM_POS_EN6 => 1, FIXED_PWM_POS_EN7 => 1,
         FIXED_PWM_POS_EN8 => 1, FIXED_PWM_POS_EN9 => 1,
         FIXED_PWM_POS_EN10 => 1, FIXED_PWM_POS_EN11 => 1,
         FIXED_PWM_POS_EN12 => 1, FIXED_PWM_POS_EN13 => 1,
         FIXED_PWM_POS_EN14 => 1, FIXED_PWM_POS_EN15 => 1,
         FIXED_PWM_POS_EN16 => 1, FIXED_PWM_POSEDGE1 => 0,
         FIXED_PWM_POSEDGE2 => 0, FIXED_PWM_POSEDGE3 => 0,
         FIXED_PWM_POSEDGE4 => 0, FIXED_PWM_POSEDGE5 => 0,
         FIXED_PWM_POSEDGE6 => 0, FIXED_PWM_POSEDGE7 => 0,
         FIXED_PWM_POSEDGE8 => 0, FIXED_PWM_POSEDGE9 => 0,
         FIXED_PWM_POSEDGE10 => 0, FIXED_PWM_POSEDGE11 => 0,
         FIXED_PWM_POSEDGE12 => 0, FIXED_PWM_POSEDGE13 => 0,
         FIXED_PWM_POSEDGE14 => 0, FIXED_PWM_POSEDGE15 => 0,
         FIXED_PWM_POSEDGE16 => 0, PWM_NUM => 3,
         PWM_STRETCH_VALUE1 => 0, PWM_STRETCH_VALUE2 => 0,
         PWM_STRETCH_VALUE3 => 0, PWM_STRETCH_VALUE4 => 0,
         PWM_STRETCH_VALUE5 => 0, PWM_STRETCH_VALUE6 => 0,
         PWM_STRETCH_VALUE7 => 0, PWM_STRETCH_VALUE8 => 0,
         PWM_STRETCH_VALUE9 => 0, PWM_STRETCH_VALUE10 => 0,
         PWM_STRETCH_VALUE11 => 0, PWM_STRETCH_VALUE12 => 0,
         PWM_STRETCH_VALUE13 => 0, PWM_STRETCH_VALUE14 => 0,
         PWM_STRETCH_VALUE15 => 0, PWM_STRETCH_VALUE16 => 0,
         SHADOW_REG_EN1 => 0, SHADOW_REG_EN2 => 0,
         SHADOW_REG_EN3 => 0, SHADOW_REG_EN4 => 0,
         SHADOW_REG_EN5 => 0, SHADOW_REG_EN6 => 0,
         SHADOW_REG_EN7 => 0, SHADOW_REG_EN8 => 0,
         SHADOW_REG_EN9 => 0, SHADOW_REG_EN10 => 0,
         SHADOW_REG_EN11 => 0, SHADOW_REG_EN12 => 0,
         SHADOW_REG_EN13 => 0, SHADOW_REG_EN14 => 0,
         SHADOW_REG_EN15 => 0, SHADOW_REG_EN16 => 0,
         TACH_EDGE1 => 0, TACH_EDGE2 => 0, TACH_EDGE3 => 0,
         TACH_EDGE4 => 0, TACH_EDGE5 => 0, TACH_EDGE6 => 0,
         TACH_EDGE7 => 0, TACH_EDGE8 => 0, TACH_EDGE9 => 0,
         TACH_EDGE10 => 0, TACH_EDGE11 => 0, TACH_EDGE12 => 0,
         TACH_EDGE13 => 0, TACH_EDGE14 => 0, TACH_EDGE15 => 0,
         TACH_EDGE16 => 0, TACH_NUM => 1, TACHINT_ACT_LEVEL => 0
        )

      port map(PCLK => 
        SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK, PENABLE
         => CoreAPB3_0_APBmslave0_PENABLE, PRESETN => 
        SmartFusion_MPM_Reference_Design_MSS_0_M2F_RESET_N, PSEL
         => CoreAPB3_0_APBmslave2_PSELx, PREADY => 
        CoreAPB3_0_APBmslave2_PREADY, PSLVERR => 
        CoreAPB3_0_APBmslave2_PSLVERR, TACHINT => OPEN, PWRITE
         => CoreAPB3_0_APBmslave0_PWRITE, PADDR(7) => 
        \CoreAPB3_0_APBmslave1_PADDR_[7]\, PADDR(6) => 
        \CoreAPB3_0_APBmslave1_PADDR_[6]\, PADDR(5) => 
        \CoreAPB3_0_APBmslave1_PADDR_[5]\, PADDR(4) => 
        \CoreAPB3_0_APBmslave1_PADDR_[4]\, PADDR(3) => 
        \CoreAPB3_0_APBmslave1_PADDR_[3]\, PADDR(2) => 
        \CoreAPB3_0_APBmslave1_PADDR_[2]\, PADDR(1) => 
        \CoreAPB3_0_APBmslave1_PADDR_[1]\, PADDR(0) => 
        \CoreAPB3_0_APBmslave1_PADDR_[0]\, PRDATA(15) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[15]\, PRDATA(14) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[14]\, PRDATA(13) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[13]\, PRDATA(12) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[12]\, PRDATA(11) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[11]\, PRDATA(10) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[10]\, PRDATA(9) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[9]\, PRDATA(8) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[8]\, PRDATA(7) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[7]\, PRDATA(6) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[6]\, PRDATA(5) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[5]\, PRDATA(4) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[4]\, PRDATA(3) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[3]\, PRDATA(2) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[2]\, PRDATA(1) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[1]\, PRDATA(0) => 
        \CoreAPB3_0_APBmslave2_PRDATA_[0]\, PWDATA(15) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[15]\, PWDATA(14) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[14]\, PWDATA(13) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[13]\, PWDATA(12) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[12]\, PWDATA(11) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[11]\, PWDATA(10) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[10]\, PWDATA(9) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[9]\, PWDATA(8) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[8]\, PWDATA(7) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[7]\, PWDATA(6) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[6]\, PWDATA(5) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[5]\, PWDATA(4) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[4]\, PWDATA(3) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[3]\, PWDATA(2) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[2]\, PWDATA(1) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[1]\, PWDATA(0) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[0]\, TACHIN(1) => GND_net, 
        PWM(3) => nc58, PWM(2) => 
        MPM_Channel_2_DMPM_DB_APOL2_PWM_TRIM, PWM(1) => 
        MPM_Channel_1_DMPM_DB_APOL1_PWM_TRIM);
    
    INV_1 : INV
      port map(A => MPM_GPIO_Regulator_Enables_GPIO_OUT1to1, Y
         => INV_1_Y);
    
    MPM_PMBus_SCL_BIBUF : BIBUF
      port map(PAD => MPM_PMBus_SCL, D => MPM_PMBus_I2C_SCLO, E
         => INV_5_Y, Y => MPM_PMBus_SCL_BIBUF_Y);
    
    MPM_GPIO_Digital_IOs : CoreGPIO
      generic map(APB_WIDTH => 32, FAMILY => 15,
         FIXED_CONFIG_0 => 1, FIXED_CONFIG_1 => 1,
         FIXED_CONFIG_2 => 1, FIXED_CONFIG_3 => 1,
         FIXED_CONFIG_4 => 1, FIXED_CONFIG_5 => 1,
         FIXED_CONFIG_6 => 1, FIXED_CONFIG_7 => 1,
         FIXED_CONFIG_8 => 1, FIXED_CONFIG_9 => 1,
         FIXED_CONFIG_10 => 1, FIXED_CONFIG_11 => 1,
         FIXED_CONFIG_12 => 1, FIXED_CONFIG_13 => 1,
         FIXED_CONFIG_14 => 1, FIXED_CONFIG_15 => 1,
         FIXED_CONFIG_16 => 1, FIXED_CONFIG_17 => 1,
         FIXED_CONFIG_18 => 1, FIXED_CONFIG_19 => 1,
         FIXED_CONFIG_20 => 1, FIXED_CONFIG_21 => 1,
         FIXED_CONFIG_22 => 1, FIXED_CONFIG_23 => 1,
         FIXED_CONFIG_24 => 1, FIXED_CONFIG_25 => 1,
         FIXED_CONFIG_26 => 1, FIXED_CONFIG_27 => 1,
         FIXED_CONFIG_28 => 1, FIXED_CONFIG_29 => 1,
         FIXED_CONFIG_30 => 1, FIXED_CONFIG_31 => 1, INT_BUS => 1,
         IO_INT_TYPE_0 => 7, IO_INT_TYPE_1 => 7,
         IO_INT_TYPE_2 => 7, IO_INT_TYPE_3 => 7,
         IO_INT_TYPE_4 => 7, IO_INT_TYPE_5 => 7,
         IO_INT_TYPE_6 => 7, IO_INT_TYPE_7 => 7,
         IO_INT_TYPE_8 => 7, IO_INT_TYPE_9 => 7,
         IO_INT_TYPE_10 => 7, IO_INT_TYPE_11 => 7,
         IO_INT_TYPE_12 => 7, IO_INT_TYPE_13 => 7,
         IO_INT_TYPE_14 => 7, IO_INT_TYPE_15 => 7,
         IO_INT_TYPE_16 => 7, IO_INT_TYPE_17 => 7,
         IO_INT_TYPE_18 => 7, IO_INT_TYPE_19 => 7,
         IO_INT_TYPE_20 => 7, IO_INT_TYPE_21 => 7,
         IO_INT_TYPE_22 => 7, IO_INT_TYPE_23 => 7,
         IO_INT_TYPE_24 => 7, IO_INT_TYPE_25 => 7,
         IO_INT_TYPE_26 => 7, IO_INT_TYPE_27 => 7,
         IO_INT_TYPE_28 => 7, IO_INT_TYPE_29 => 7,
         IO_INT_TYPE_30 => 7, IO_INT_TYPE_31 => 7, IO_NUM => 32,
         IO_TYPE_0 => 2, IO_TYPE_1 => 2, IO_TYPE_2 => 2,
         IO_TYPE_3 => 2, IO_TYPE_4 => 2, IO_TYPE_5 => 2,
         IO_TYPE_6 => 2, IO_TYPE_7 => 2, IO_TYPE_8 => 2,
         IO_TYPE_9 => 2, IO_TYPE_10 => 2, IO_TYPE_11 => 2,
         IO_TYPE_12 => 2, IO_TYPE_13 => 2, IO_TYPE_14 => 2,
         IO_TYPE_15 => 2, IO_TYPE_16 => 2, IO_TYPE_17 => 2,
         IO_TYPE_18 => 2, IO_TYPE_19 => 2, IO_TYPE_20 => 2,
         IO_TYPE_21 => 2, IO_TYPE_22 => 2, IO_TYPE_23 => 2,
         IO_TYPE_24 => 2, IO_TYPE_25 => 2, IO_TYPE_26 => 2,
         IO_TYPE_27 => 2, IO_TYPE_28 => 2, IO_TYPE_29 => 2,
         IO_TYPE_30 => 2, IO_TYPE_31 => 2, IO_VAL_0 => 0,
         IO_VAL_1 => 0, IO_VAL_2 => 0, IO_VAL_3 => 0,
         IO_VAL_4 => 0, IO_VAL_5 => 0, IO_VAL_6 => 0,
         IO_VAL_7 => 0, IO_VAL_8 => 0, IO_VAL_9 => 0,
         IO_VAL_10 => 0, IO_VAL_11 => 0, IO_VAL_12 => 0,
         IO_VAL_13 => 0, IO_VAL_14 => 0, IO_VAL_15 => 0,
         IO_VAL_16 => 0, IO_VAL_17 => 0, IO_VAL_18 => 0,
         IO_VAL_19 => 0, IO_VAL_20 => 0, IO_VAL_21 => 0,
         IO_VAL_22 => 0, IO_VAL_23 => 0, IO_VAL_24 => 0,
         IO_VAL_25 => 0, IO_VAL_26 => 0, IO_VAL_27 => 0,
         IO_VAL_28 => 0, IO_VAL_29 => 0, IO_VAL_30 => 0,
         IO_VAL_31 => 0, OE_TYPE => 1)

      port map(PRESETN => 
        SmartFusion_MPM_Reference_Design_MSS_0_M2F_RESET_N, PCLK
         => SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK, PSEL
         => CoreAPB3_0_APBmslave1_PSELx, PENABLE => 
        CoreAPB3_0_APBmslave0_PENABLE, PWRITE => 
        CoreAPB3_0_APBmslave0_PWRITE, PSLVERR => 
        CoreAPB3_0_APBmslave1_PSLVERR, PREADY => 
        CoreAPB3_0_APBmslave1_PREADY, INT_OR => OPEN, PADDR(7)
         => \CoreAPB3_0_APBmslave1_PADDR_[7]\, PADDR(6) => 
        \CoreAPB3_0_APBmslave1_PADDR_[6]\, PADDR(5) => 
        \CoreAPB3_0_APBmslave1_PADDR_[5]\, PADDR(4) => 
        \CoreAPB3_0_APBmslave1_PADDR_[4]\, PADDR(3) => 
        \CoreAPB3_0_APBmslave1_PADDR_[3]\, PADDR(2) => 
        \CoreAPB3_0_APBmslave1_PADDR_[2]\, PADDR(1) => 
        \CoreAPB3_0_APBmslave1_PADDR_[1]\, PADDR(0) => 
        \CoreAPB3_0_APBmslave1_PADDR_[0]\, PWDATA(31) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[31]\, PWDATA(30) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[30]\, PWDATA(29) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[29]\, PWDATA(28) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[28]\, PWDATA(27) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[27]\, PWDATA(26) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[26]\, PWDATA(25) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[25]\, PWDATA(24) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[24]\, PWDATA(23) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[23]\, PWDATA(22) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[22]\, PWDATA(21) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[21]\, PWDATA(20) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[20]\, PWDATA(19) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[19]\, PWDATA(18) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[18]\, PWDATA(17) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[17]\, PWDATA(16) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[16]\, PWDATA(15) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[15]\, PWDATA(14) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[14]\, PWDATA(13) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[13]\, PWDATA(12) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[12]\, PWDATA(11) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[11]\, PWDATA(10) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[10]\, PWDATA(9) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[9]\, PWDATA(8) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[8]\, PWDATA(7) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[7]\, PWDATA(6) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[6]\, PWDATA(5) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[5]\, PWDATA(4) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[4]\, PWDATA(3) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[3]\, PWDATA(2) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[2]\, PWDATA(1) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[1]\, PWDATA(0) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[0]\, PRDATA(31) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[31]\, PRDATA(30) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[30]\, PRDATA(29) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[29]\, PRDATA(28) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[28]\, PRDATA(27) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[27]\, PRDATA(26) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[26]\, PRDATA(25) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[25]\, PRDATA(24) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[24]\, PRDATA(23) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[23]\, PRDATA(22) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[22]\, PRDATA(21) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[21]\, PRDATA(20) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[20]\, PRDATA(19) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[19]\, PRDATA(18) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[18]\, PRDATA(17) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[17]\, PRDATA(16) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[16]\, PRDATA(15) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[15]\, PRDATA(14) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[14]\, PRDATA(13) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[13]\, PRDATA(12) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[12]\, PRDATA(11) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[11]\, PRDATA(10) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[10]\, PRDATA(9) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[9]\, PRDATA(8) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[8]\, PRDATA(7) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[7]\, PRDATA(6) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[6]\, PRDATA(5) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[5]\, PRDATA(4) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[4]\, PRDATA(3) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[3]\, PRDATA(2) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[2]\, PRDATA(1) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[1]\, PRDATA(0) => 
        \CoreAPB3_0_APBmslave1_PRDATA_[0]\, INT(31) => nc116, 
        INT(30) => nc74, INT(29) => nc133, INT(28) => nc167, 
        INT(27) => nc84, INT(26) => nc39, INT(25) => nc72, 
        INT(24) => nc82, INT(23) => nc145, INT(22) => nc160, 
        INT(21) => nc57, INT(20) => nc156, INT(19) => nc125, 
        INT(18) => nc73, INT(17) => nc107, INT(16) => nc66, 
        INT(15) => nc83, INT(14) => nc9, INT(13) => nc171, 
        INT(12) => nc54, INT(11) => nc135, INT(10) => nc41, 
        INT(9) => nc100, INT(8) => nc52, INT(7) => nc29, INT(6)
         => nc118, INT(5) => nc60, INT(4) => nc141, INT(3) => 
        nc45, INT(2) => nc53, INT(1) => nc121, INT(0) => nc176, 
        GPIO_IN(31) => GND_net, GPIO_IN(30) => GND_net, 
        GPIO_IN(29) => GND_net, GPIO_IN(28) => GND_net, 
        GPIO_IN(27) => GND_net, GPIO_IN(26) => GND_net, 
        GPIO_IN(25) => GND_net, GPIO_IN(24) => GND_net, 
        GPIO_IN(23) => GND_net, GPIO_IN(22) => GND_net, 
        GPIO_IN(21) => GND_net, GPIO_IN(20) => GND_net, 
        GPIO_IN(19) => GND_net, GPIO_IN(18) => GND_net, 
        GPIO_IN(17) => GND_net, GPIO_IN(16) => GND_net, 
        GPIO_IN(15) => GND_net, GPIO_IN(14) => GND_net, 
        GPIO_IN(13) => GND_net, GPIO_IN(12) => GND_net, 
        GPIO_IN(11) => GND_net, GPIO_IN(10) => GND_net, 
        GPIO_IN(9) => GND_net, GPIO_IN(8) => GND_net, GPIO_IN(7)
         => GND_net, GPIO_IN(6) => GND_net, GPIO_IN(5) => GND_net, 
        GPIO_IN(4) => GND_net, GPIO_IN(3) => GND_net, GPIO_IN(2)
         => GND_net, GPIO_IN(1) => GND_net, GPIO_IN(0) => GND_net, 
        GPIO_OUT(31) => nc158, GPIO_OUT(30) => nc162, 
        GPIO_OUT(29) => nc11, GPIO_OUT(28) => nc131, GPIO_OUT(27)
         => nc96, GPIO_OUT(26) => nc79, GPIO_OUT(25) => nc146, 
        GPIO_OUT(24) => nc89, GPIO_OUT(23) => nc119, GPIO_OUT(22)
         => nc48, GPIO_OUT(21) => nc126, GPIO_OUT(20) => nc15, 
        GPIO_OUT(19) => nc102, GPIO_OUT(18) => nc3, GPIO_OUT(17)
         => nc47, GPIO_OUT(16) => nc90, GPIO_OUT(15) => nc159, 
        GPIO_OUT(14) => nc136, GPIO_OUT(13) => nc178, 
        GPIO_OUT(12) => nc59, GPIO_OUT(11) => A2F_BOARD_LED_D4_N, 
        GPIO_OUT(10) => A2F_BOARD_LED_D3_N, GPIO_OUT(9) => 
        A2F_BOARD_LED_D2_N, GPIO_OUT(8) => A2F_BOARD_LED_D1_N, 
        GPIO_OUT(7) => MPM_GPIO_Digital_IOs_GPIO_OUT7to7, 
        GPIO_OUT(6) => MPM_GPIO_Digital_IOs_GPIO_OUT6to6, 
        GPIO_OUT(5) => MPM_GPIO_Digital_IOs_GPIO_OUT5to5, 
        GPIO_OUT(4) => MPM_GPIO_Digital_IOs_GPIO_OUT4to4, 
        GPIO_OUT(3) => MPM_GPIO_Digital_IOs_GPIO_OUT3to3, 
        GPIO_OUT(2) => MPM_GPIO_Digital_IOs_GPIO_OUT2to2, 
        GPIO_OUT(1) => MPM_GPIO_Digital_IOs_GPIO_OUT1to1, 
        GPIO_OUT(0) => MPM_GPIO_Digital_IOs_GPIO_OUT0to0, 
        GPIO_OE(31) => nc18, GPIO_OE(30) => nc44, GPIO_OE(29) => 
        nc117, GPIO_OE(28) => nc164, GPIO_OE(27) => nc148, 
        GPIO_OE(26) => nc42, GPIO_OE(25) => nc17, GPIO_OE(24) => 
        nc2, GPIO_OE(23) => nc110, GPIO_OE(22) => nc128, 
        GPIO_OE(21) => nc43, GPIO_OE(20) => nc179, GPIO_OE(19)
         => nc157, GPIO_OE(18) => nc36, GPIO_OE(17) => nc61, 
        GPIO_OE(16) => nc104, GPIO_OE(15) => nc138, GPIO_OE(14)
         => nc14, GPIO_OE(13) => nc150, GPIO_OE(12) => nc149, 
        GPIO_OE(11) => nc12, GPIO_OE(10) => nc30, GPIO_OE(9) => 
        nc65, GPIO_OE(8) => nc7, GPIO_OE(7) => nc129, GPIO_OE(6)
         => nc8, GPIO_OE(5) => nc13, GPIO_OE(4) => nc26, 
        GPIO_OE(3) => nc177, GPIO_OE(2) => nc139, GPIO_OE(1) => 
        nc163, GPIO_OE(0) => nc112);
    
    INV_2 : INV
      port map(A => MPM_GPIO_Regulator_Enables_GPIO_OUT2to2, Y
         => INV_2_Y);
    
    \VCC\ : VCC
      port map(Y => VCC_net);
    
    MPM_GPIO_Regulator_Enables : CoreGPIO
      generic map(APB_WIDTH => 32, FAMILY => 15,
         FIXED_CONFIG_0 => 1, FIXED_CONFIG_1 => 1,
         FIXED_CONFIG_2 => 1, FIXED_CONFIG_3 => 1,
         FIXED_CONFIG_4 => 1, FIXED_CONFIG_5 => 1,
         FIXED_CONFIG_6 => 1, FIXED_CONFIG_7 => 1,
         FIXED_CONFIG_8 => 1, FIXED_CONFIG_9 => 1,
         FIXED_CONFIG_10 => 1, FIXED_CONFIG_11 => 1,
         FIXED_CONFIG_12 => 1, FIXED_CONFIG_13 => 1,
         FIXED_CONFIG_14 => 1, FIXED_CONFIG_15 => 1,
         FIXED_CONFIG_16 => 1, FIXED_CONFIG_17 => 1,
         FIXED_CONFIG_18 => 1, FIXED_CONFIG_19 => 1,
         FIXED_CONFIG_20 => 1, FIXED_CONFIG_21 => 1,
         FIXED_CONFIG_22 => 1, FIXED_CONFIG_23 => 1,
         FIXED_CONFIG_24 => 1, FIXED_CONFIG_25 => 1,
         FIXED_CONFIG_26 => 1, FIXED_CONFIG_27 => 1,
         FIXED_CONFIG_28 => 1, FIXED_CONFIG_29 => 1,
         FIXED_CONFIG_30 => 1, FIXED_CONFIG_31 => 1, INT_BUS => 0,
         IO_INT_TYPE_0 => 7, IO_INT_TYPE_1 => 7,
         IO_INT_TYPE_2 => 7, IO_INT_TYPE_3 => 7,
         IO_INT_TYPE_4 => 7, IO_INT_TYPE_5 => 7,
         IO_INT_TYPE_6 => 7, IO_INT_TYPE_7 => 7,
         IO_INT_TYPE_8 => 7, IO_INT_TYPE_9 => 7,
         IO_INT_TYPE_10 => 7, IO_INT_TYPE_11 => 7,
         IO_INT_TYPE_12 => 7, IO_INT_TYPE_13 => 7,
         IO_INT_TYPE_14 => 7, IO_INT_TYPE_15 => 7,
         IO_INT_TYPE_16 => 7, IO_INT_TYPE_17 => 7,
         IO_INT_TYPE_18 => 7, IO_INT_TYPE_19 => 7,
         IO_INT_TYPE_20 => 7, IO_INT_TYPE_21 => 7,
         IO_INT_TYPE_22 => 7, IO_INT_TYPE_23 => 7,
         IO_INT_TYPE_24 => 7, IO_INT_TYPE_25 => 7,
         IO_INT_TYPE_26 => 7, IO_INT_TYPE_27 => 7,
         IO_INT_TYPE_28 => 7, IO_INT_TYPE_29 => 7,
         IO_INT_TYPE_30 => 7, IO_INT_TYPE_31 => 7, IO_NUM => 32,
         IO_TYPE_0 => 1, IO_TYPE_1 => 1, IO_TYPE_2 => 1,
         IO_TYPE_3 => 1, IO_TYPE_4 => 1, IO_TYPE_5 => 0,
         IO_TYPE_6 => 1, IO_TYPE_7 => 1, IO_TYPE_8 => 1,
         IO_TYPE_9 => 1, IO_TYPE_10 => 1, IO_TYPE_11 => 1,
         IO_TYPE_12 => 1, IO_TYPE_13 => 1, IO_TYPE_14 => 1,
         IO_TYPE_15 => 1, IO_TYPE_16 => 1, IO_TYPE_17 => 1,
         IO_TYPE_18 => 1, IO_TYPE_19 => 1, IO_TYPE_20 => 1,
         IO_TYPE_21 => 1, IO_TYPE_22 => 1, IO_TYPE_23 => 1,
         IO_TYPE_24 => 1, IO_TYPE_25 => 1, IO_TYPE_26 => 1,
         IO_TYPE_27 => 1, IO_TYPE_28 => 1, IO_TYPE_29 => 1,
         IO_TYPE_30 => 1, IO_TYPE_31 => 1, IO_VAL_0 => 0,
         IO_VAL_1 => 0, IO_VAL_2 => 0, IO_VAL_3 => 0,
         IO_VAL_4 => 0, IO_VAL_5 => 0, IO_VAL_6 => 0,
         IO_VAL_7 => 0, IO_VAL_8 => 0, IO_VAL_9 => 0,
         IO_VAL_10 => 0, IO_VAL_11 => 0, IO_VAL_12 => 0,
         IO_VAL_13 => 0, IO_VAL_14 => 0, IO_VAL_15 => 0,
         IO_VAL_16 => 0, IO_VAL_17 => 0, IO_VAL_18 => 0,
         IO_VAL_19 => 0, IO_VAL_20 => 0, IO_VAL_21 => 0,
         IO_VAL_22 => 0, IO_VAL_23 => 0, IO_VAL_24 => 0,
         IO_VAL_25 => 0, IO_VAL_26 => 0, IO_VAL_27 => 0,
         IO_VAL_28 => 0, IO_VAL_29 => 0, IO_VAL_30 => 0,
         IO_VAL_31 => 0, OE_TYPE => 1)

      port map(PRESETN => 
        SmartFusion_MPM_Reference_Design_MSS_0_M2F_RESET_N, PCLK
         => SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK, PSEL
         => CoreAPB3_0_APBmslave0_PSELx, PENABLE => 
        CoreAPB3_0_APBmslave0_PENABLE, PWRITE => 
        CoreAPB3_0_APBmslave0_PWRITE, PSLVERR => 
        CoreAPB3_0_APBmslave0_PSLVERR, PREADY => 
        CoreAPB3_0_APBmslave0_PREADY, INT_OR => OPEN, PADDR(7)
         => \CoreAPB3_0_APBmslave0_PADDR_[7]\, PADDR(6) => 
        \CoreAPB3_0_APBmslave0_PADDR_[6]\, PADDR(5) => 
        \CoreAPB3_0_APBmslave0_PADDR_[5]\, PADDR(4) => 
        \CoreAPB3_0_APBmslave0_PADDR_[4]\, PADDR(3) => 
        \CoreAPB3_0_APBmslave0_PADDR_[3]\, PADDR(2) => 
        \CoreAPB3_0_APBmslave0_PADDR_[2]\, PADDR(1) => 
        \CoreAPB3_0_APBmslave0_PADDR_[1]\, PADDR(0) => 
        \CoreAPB3_0_APBmslave0_PADDR_[0]\, PWDATA(31) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[31]\, PWDATA(30) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[30]\, PWDATA(29) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[29]\, PWDATA(28) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[28]\, PWDATA(27) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[27]\, PWDATA(26) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[26]\, PWDATA(25) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[25]\, PWDATA(24) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[24]\, PWDATA(23) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[23]\, PWDATA(22) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[22]\, PWDATA(21) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[21]\, PWDATA(20) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[20]\, PWDATA(19) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[19]\, PWDATA(18) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[18]\, PWDATA(17) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[17]\, PWDATA(16) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[16]\, PWDATA(15) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[15]\, PWDATA(14) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[14]\, PWDATA(13) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[13]\, PWDATA(12) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[12]\, PWDATA(11) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[11]\, PWDATA(10) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[10]\, PWDATA(9) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[9]\, PWDATA(8) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[8]\, PWDATA(7) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[7]\, PWDATA(6) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[6]\, PWDATA(5) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[5]\, PWDATA(4) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[4]\, PWDATA(3) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[3]\, PWDATA(2) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[2]\, PWDATA(1) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[1]\, PWDATA(0) => 
        \CoreAPB3_0_APBmslave0_PWDATA_[0]\, PRDATA(31) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[31]\, PRDATA(30) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[30]\, PRDATA(29) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[29]\, PRDATA(28) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[28]\, PRDATA(27) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[27]\, PRDATA(26) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[26]\, PRDATA(25) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[25]\, PRDATA(24) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[24]\, PRDATA(23) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[23]\, PRDATA(22) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[22]\, PRDATA(21) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[21]\, PRDATA(20) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[20]\, PRDATA(19) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[19]\, PRDATA(18) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[18]\, PRDATA(17) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[17]\, PRDATA(16) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[16]\, PRDATA(15) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[15]\, PRDATA(14) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[14]\, PRDATA(13) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[13]\, PRDATA(12) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[12]\, PRDATA(11) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[11]\, PRDATA(10) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[10]\, PRDATA(9) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[9]\, PRDATA(8) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[8]\, PRDATA(7) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[7]\, PRDATA(6) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[6]\, PRDATA(5) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[5]\, PRDATA(4) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[4]\, PRDATA(3) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[3]\, PRDATA(2) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[2]\, PRDATA(1) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[1]\, PRDATA(0) => 
        \CoreAPB3_0_APBmslave0_PRDATA_[0]\, INT(31) => nc68, 
        INT(30) => nc49, INT(29) => nc170, INT(28) => nc91, 
        INT(27) => nc5, INT(26) => nc20, INT(25) => nc147, 
        INT(24) => nc67, INT(23) => nc152, INT(22) => nc127, 
        INT(21) => nc103, INT(20) => nc76, INT(19) => nc140, 
        INT(18) => nc86, INT(17) => nc95, INT(16) => nc120, 
        INT(15) => nc165, INT(14) => nc137, INT(13) => nc64, 
        INT(12) => nc19, INT(11) => nc70, INT(10) => nc62, INT(9)
         => nc80, INT(8) => nc130, INT(7) => nc98, INT(6) => 
        nc114, INT(5) => nc56, INT(4) => nc105, INT(3) => nc63, 
        INT(2) => nc172, INT(1) => nc97, INT(0) => nc161, 
        GPIO_IN(31) => GND_net, GPIO_IN(30) => GND_net, 
        GPIO_IN(29) => GND_net, GPIO_IN(28) => GND_net, 
        GPIO_IN(27) => GND_net, GPIO_IN(26) => GND_net, 
        GPIO_IN(25) => GND_net, GPIO_IN(24) => GND_net, 
        GPIO_IN(23) => GND_net, GPIO_IN(22) => GND_net, 
        GPIO_IN(21) => GND_net, GPIO_IN(20) => GND_net, 
        GPIO_IN(19) => GND_net, GPIO_IN(18) => GND_net, 
        GPIO_IN(17) => GND_net, GPIO_IN(16) => GND_net, 
        GPIO_IN(15) => GND_net, GPIO_IN(14) => GND_net, 
        GPIO_IN(13) => GND_net, GPIO_IN(12) => GND_net, 
        GPIO_IN(11) => GND_net, GPIO_IN(10) => GND_net, 
        GPIO_IN(9) => GND_net, GPIO_IN(8) => GND_net, GPIO_IN(7)
         => GND_net, GPIO_IN(6) => GND_net, GPIO_IN(5) => GND_net, 
        GPIO_IN(4) => GND_net, GPIO_IN(3) => GND_net, GPIO_IN(2)
         => GND_net, GPIO_IN(1) => GND_net, GPIO_IN(0) => GND_net, 
        GPIO_OUT(31) => nc31, GPIO_OUT(30) => nc154, GPIO_OUT(29)
         => nc50, GPIO_OUT(28) => nc142, GPIO_OUT(27) => nc94, 
        GPIO_OUT(26) => nc122, GPIO_OUT(25) => nc35, GPIO_OUT(24)
         => nc4, GPIO_OUT(23) => nc92, GPIO_OUT(22) => nc101, 
        GPIO_OUT(21) => nc166, GPIO_OUT(20) => nc132, 
        GPIO_OUT(19) => nc21, GPIO_OUT(18) => nc93, GPIO_OUT(17)
         => nc69, GPIO_OUT(16) => nc174, GPIO_OUT(15) => nc38, 
        GPIO_OUT(14) => nc113, GPIO_OUT(13) => nc106, 
        GPIO_OUT(12) => nc25, GPIO_OUT(11) => nc1, GPIO_OUT(10)
         => nc37, GPIO_OUT(9) => nc144, GPIO_OUT(8) => nc153, 
        GPIO_OUT(7) => nc46, GPIO_OUT(6) => nc71, GPIO_OUT(5) => 
        nc124, GPIO_OUT(4) => 
        MPM_GPIO_Regulator_Enables_GPIO_OUT4to4, GPIO_OUT(3) => 
        MPM_GPIO_Regulator_Enables_GPIO_OUT3to3, GPIO_OUT(2) => 
        MPM_GPIO_Regulator_Enables_GPIO_OUT2to2, GPIO_OUT(1) => 
        MPM_GPIO_Regulator_Enables_GPIO_OUT1to1, GPIO_OUT(0) => 
        MPM_GPIO_Regulator_Enables_GPIO_OUT0to0, GPIO_OE(31) => 
        nc81, GPIO_OE(30) => nc168, GPIO_OE(29) => nc34, 
        GPIO_OE(28) => nc28, GPIO_OE(27) => nc115, GPIO_OE(26)
         => nc134, GPIO_OE(25) => nc32, GPIO_OE(24) => nc40, 
        GPIO_OE(23) => nc99, GPIO_OE(22) => nc75, GPIO_OE(21) => 
        nc85, GPIO_OE(20) => nc27, GPIO_OE(19) => nc108, 
        GPIO_OE(18) => nc16, GPIO_OE(17) => nc155, GPIO_OE(16)
         => nc51, GPIO_OE(15) => nc33, GPIO_OE(14) => nc173, 
        GPIO_OE(13) => nc169, GPIO_OE(12) => nc78, GPIO_OE(11)
         => nc24, GPIO_OE(10) => nc88, GPIO_OE(9) => nc111, 
        GPIO_OE(8) => nc55, GPIO_OE(7) => nc10, GPIO_OE(6) => 
        nc22, GPIO_OE(5) => nc143, GPIO_OE(4) => nc77, GPIO_OE(3)
         => nc6, GPIO_OE(2) => nc109, GPIO_OE(1) => nc87, 
        GPIO_OE(0) => nc123);
    

end DEF_ARCH; 
