@W: MO111 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":308:13:308:77|Tristate driver un2_tri7 on net un2_tri7 has its enable tied to GND (module reg_IF) 
@W: MO111 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":308:13:308:77|Tristate driver un2_tri6 on net un2_tri6 has its enable tied to GND (module reg_IF) 
@W: MO111 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":308:13:308:77|Tristate driver un2_tri5 on net un2_tri5 has its enable tied to GND (module reg_IF) 
@W: MO111 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":308:13:308:77|Tristate driver un2_tri4 on net un2_tri4 has its enable tied to GND (module reg_IF) 
@W: MO111 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":308:13:308:77|Tristate driver un2_tri3 on net un2_tri3 has its enable tied to GND (module reg_IF) 
@W: MO111 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":308:13:308:77|Tristate driver un2_tri2 on net un2_tri2 has its enable tied to GND (module reg_IF) 
@W: MO111 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":308:13:308:77|Tristate driver un2_tri1 on net un2_tri1 has its enable tied to GND (module reg_IF) 
@W: MO111 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":308:13:308:77|Tristate driver un2_tri0 on net un2_tri0 has its enable tied to GND (module reg_IF) 
@W: MO111 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":306:13:306:76|Tristate driver un1_CPWMIOll_tri7 on net un1_CPWMIOll_tri7 has its enable tied to GND (module reg_IF) 
@W: MO111 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":306:13:306:76|Tristate driver un1_CPWMIOll_tri6 on net un1_CPWMIOll_tri6 has its enable tied to GND (module reg_IF) 
@W: MO111 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":306:13:306:76|Tristate driver un1_CPWMIOll_tri5 on net un1_CPWMIOll_tri5 has its enable tied to GND (module reg_IF) 
@W: MO111 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":306:13:306:76|Tristate driver un1_CPWMIOll_tri4 on net un1_CPWMIOll_tri4 has its enable tied to GND (module reg_IF) 
@W: MO111 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corepwm\4.1.106\rtl\vhdl\core_obfuscated\reg_if.vhd":306:13:306:76|Tristate driver un1_CPWMIOll_tri3 on net un1_CPWMIOll_tri3 has its enable tied to GND (module reg_IF) 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Regulator_Enables.CGPIOiOI\.5\.CGPIOI1[5] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":319:7:319:13|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.0\.CGPIOI1[0] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.1\.CGPIOI1[1] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.2\.CGPIOI1[2] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.3\.CGPIOI1[3] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.4\.CGPIOI1[4] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.5\.CGPIOI1[5] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.6\.CGPIOI1[6] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.7\.CGPIOI1[7] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.8\.CGPIOI1[8] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.9\.CGPIOI1[9] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.10\.CGPIOI1[10] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.11\.CGPIOI1[11] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.12\.CGPIOI1[12] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.13\.CGPIOI1[13] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.14\.CGPIOI1[14] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.15\.CGPIOI1[15] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.16\.CGPIOI1[16] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.17\.CGPIOI1[17] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.18\.CGPIOI1[18] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.19\.CGPIOI1[19] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.20\.CGPIOI1[20] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.21\.CGPIOI1[21] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.22\.CGPIOI1[22] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.23\.CGPIOI1[23] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.24\.CGPIOI1[24] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.25\.CGPIOI1[25] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.26\.CGPIOI1[26] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.27\.CGPIOI1[27] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.28\.CGPIOI1[28] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.29\.CGPIOI1[29] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.30\.CGPIOI1[30] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\coregpio\3.0.120\rtl\vhdl\core_obfuscated\coregpio.vhd":388:0:388:16|Sequential instance MPM_GPIO_Digital_IOs.CGPIOiOI\.31\.CGPIOI1[31] reduced to a combinational gate by constant propagation 
@W: MO171 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\actel\directcore\corei2c\7.0.102\rtl\vhdl\core_obfuscated\corei2creal.vhd":593:0:593:1|Sequential instance CI2CO0l.0.Ui2C.CI2CO0Oi reduced to a combinational gate by constant propagation 
@W: MT462 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\work\sf_mpm_refdesign_mss\mss_ccc_0\sf_mpm_refdesign_mss_tmp_mss_ccc_0_mss_ccc.vhd":118:4:118:11|Net \\SF_MPM_RefDesign_MSS\\.MSS_ADLIB_INST_FCLK appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\work\sf_mpm_refdesign_mss\mss_ccc_0\sf_mpm_refdesign_mss_tmp_mss_ccc_0_mss_ccc.vhd":118:4:118:11|Net MPM_PWM_Trimming_Outputs.pclk appears to be an unidentified clock source. Assuming default frequency. 
@W: MT246 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\work\sf_mpm_refdesign_mss\sf_mpm_refdesign_mss.vhd":827:4:827:16|Blackbox TRIBUFF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\microsemi\sf_mpm_refdesign_v4.0\design_files_orig\libero_project\sf_mpm_refdesign\component\work\sf_mpm_refdesign_mss\sf_mpm_refdesign_mss.vhd":811:4:811:16|Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock SmartFusion_MPM_Reference_Design|\\SF_MPM_RefDesign_MSS\\.MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:\SF_MPM_RefDesign_MSS\.MSS_ADLIB_INST_EMCCLK"
