***************************************************************************
                               Status Report
                          Fri Jun 29 16:39:15 2012 ***************************************************************************

Product: Designer
Release: v10.0 SP2
Version: 10.0.20.2
File Name: C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\designer\impl1\SmartFusion_MPM_Reference_Design.adb
Design Name: SmartFusion_MPM_Reference_Design  Design State: compile
Last Saved: Tue May 29 19:19:02 2012

***** Device Data **************************************************

Family: SmartFusion  Die: A2F200M3F  Package: 484 FBGA
Speed: STD  Voltage: 1.5

Restrict JTAG Pins: YES
Restrict Probe Pins: YES

Junction Temperature Range:   COM
Voltage Range:   COM

***** Import Variables *********************************************

Source File(s) Imported on Fri Jun 29 16:38:44 2012:
        C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\synthesis\SmartFusion_MPM_Reference_Design.edn
        C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\work\SmartFusion_MPM_Reference_Design\SmartFusion_MPM_Reference_Design.pdc


***** CAE Variables ************************************************

Back Annotation File: N/A


***** Bitstream Variables ******************************************

Bitstream File: N/A
     Lock Mode: OFF


***** Compile Variables ********************************************

Netlist PIN properties overwrite existing properties: 0

Compile Output:
=====================================================================
Parameters used to run compile:
===============================

Family      : SmartFusion
Device      : A2F200M3F
Package     : 484 FBGA
Source      :
C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\synthesis\\
SmartFusion_MPM_Reference_Design.edn

C:\Microsemi\SF_MPM_RefDesign_v4.0\design_files_orig\Libero_project\SF_MPM_RefDesign\component\\
work\SmartFusion_MPM_Reference_Design\SmartFusion_MPM_Reference_Design.pdc
Format      : EDIF
Topcell     : SmartFusion_MPM_Reference_Design
Speed grade : STD
Temp        : 0:25:85
Voltage     : 1.58:1.50:1.42

Keep Existing Physical Constraints : Yes
Keep Existing Timing Constraints   : Yes

pdc_abort_on_error                 : Yes
pdc_eco_display_unmatched_objects  : No
pdc_eco_max_warnings               : 10000

demote_globals                     : No
promote_globals                    : No
localclock_max_shared_instances    : 12
localclock_buffer_tree_max_fanout  : 12

combine_register                   : No
delete_buffer_tree                 : No

report_high_fanout_nets_limit      : 10

=====================================================================
Compile starts ...

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         _SF_MPM_RefDesign_MSS_/Z_SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[\
         13]_ drives no load.
Warning: CMP201: Net
         _SF_MPM_RefDesign_MSS_/Z_SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[\
         14]_ drives no load.
Warning: CMP201: Net
         _SF_MPM_RefDesign_MSS_/Z_SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[\
         15]_ drives no load.
Warning: CMP201: Net
         _SF_MPM_RefDesign_MSS_/Z_SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[\
         16]_ drives no load.
Warning: CMP201: Net
         _SF_MPM_RefDesign_MSS_/Z_SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[\
         17]_ drives no load.
Warning: CMP201: Net
         _SF_MPM_RefDesign_MSS_/Z_SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[\
         18]_ drives no load.
Warning: CMP201: Net
         _SF_MPM_RefDesign_MSS_/Z_SmartFusion_MPM_Reference_Design_MSS_0_MSS_MASTER_APB_PADDR_[\
         19]_ drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/PUFABn drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SDD2 drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SLEEP drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI0CLKO drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI0DO drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI0DOE drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI0MODE drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI0SSO[0] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI0SSO[1] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI0SSO[2] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI0SSO[3] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI0SSO[4] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI0SSO[5] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI0SSO[6] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI0SSO[7] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI1CLKO drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI1DO drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI1DOE drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI1MODE drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI1SSO[0] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI1SSO[1] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI1SSO[2] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI1SSO[3] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI1SSO[4] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI1SSO[5] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI1SSO[6] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/SPI1SSO[7] drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/TXEV drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/UART0DTRn drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/UART0RTSn drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/UART1DTRn drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/UART1RTSn drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/UART1TXD drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/VAREFOUT drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/VCC15GOOD drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/VCC33GOOD drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/WDINT drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC_GLA drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC_GLC drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC_LOCK drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC_YB drives no load.
Warning: CMP201: Net _SF_MPM_RefDesign_MSS_/MSS_CCC_0/I_MSSCCC_YC drives no load.

Netlist Optimization Report
===========================

Optimized macros:
  - Dangling net drivers:   0
  - Buffers:                2
  - Inverters:              0
  - Tieoff:                 0
  - Logic combining:        58

    Total macros optimized  60

Warning: CMP503: Remapped 336 enable flip-flop(s) to a 2-tile implementation because the CLR/PRE
         pin on the enable flip-flop is not being driven by a global net.

There were 0 error(s) and 280 warning(s) in this design.
=====================================================================

Reading previous post-compile physical placement constraints.


There were 0 error(s) and 0 warning(s).

=====================================================================

Reading user pdc (Physical Design Constraints) file(s) postcompile


There were 0 error(s) and 0 warning(s) in reading the user pdc.

=====================================================================
Compile report:
===============

    Microcontroller Subsystem  Used:      1  Total:      1   (100.00%)
    Fabric                     Used:   2075  Total:   4608   (45.03%)
    Fabric IO (W/ clocks)      Used:     11  Total:     94   (11.70%)
    Fabric Differential IO     Used:      0  Total:     47   (0.00%)
    Dedicated Analog IO        Used:      7  Total:     32   (21.88%)
    Dedicated MSS IO           Used:     23  Total:     43   (53.49%)
    GLOBAL (Chip+Quadrant)     Used:      0  Total:     15   (0.00%)
    MSS GLOBAL                 Used:      3  Total:      3   (100.00%)
    On-chip RC oscillator      Used:      1  Total:      1   (100.00%)
    Main Crystal oscillator    Used:      0  Total:      1   (0.00%)
    32 KHz Crystal oscillator  Used:      0  Total:      1   (0.00%)
    RAM/FIFO                   Used:      0  Total:      8   (0.00%)
    User JTAG                  Used:      0  Total:      1   (0.00%)

Global Information:

    Type            | Used   | Total
    ----------------|--------|--------------
    Chip global     | 0      | 3  (0.00%)*
    Quadrant global | 0      | 12 (0.00%)
    MSS global      | 3      | 3  (100.00%)

    (*) Chip globals may be assigned to Quadrant globals using the Multi-View Navigator (MVN)
        or Physical Design Constraints (PDC).
        They may also be assigned to Quadrant globals automatically during Layout.

Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 1651         | 1651
    SEQ     | 424          | 424

I/O Function:

    Type                          | w/o register  | w/ register  | w/ DDR register
    ------------------------------|---------------|--------------|----------------
    Input I/O                     | 2             | 0            | 0
    Output I/O                    | 6             | 0            | 0
    Bidirectional I/O             | 3             | 0            | 0
    Differential Input I/O Pairs  | 0             | 0            | 0
    Differential Output I/O Pairs | 0             | 0            | 0

I/O Technology:

                                    |   Voltages    |             I/Os
    --------------------------------|-------|-------|-------|--------|--------------
    I/O Standard(s)                 | Vcci  | Vref  | Input | Output | Bidirectional
    --------------------------------|-------|-------|-------|--------|--------------
    LVTTL                           | 3.30v | N/A   | 2     | 6      | 3

I/O Placement:

    Locked  :  11 ( 100.00% )
    Placed  :   0
    UnPlaced:   0

Net information report:
=======================

The following nets drive enable flip-flops that have been remapped to a 2-tile implementation:
    EffCnt  Type          Name
    --------------------------
    336     SET/RESET_NET Net   : SmartFusion_MPM_Reference_Design_MSS_0_M2F_RESET_N
                          Driver: \\SF_MPM_RefDesign_MSS\\/MSS_ADLIB_INST

The following nets have been assigned to a chip global resource:
    Fanout  Type          Name
    --------------------------
    425     CLK_NET       Net   : SmartFusion_MPM_Reference_Design_MSS_0_FAB_CLK
                          Driver: \\SF_MPM_RefDesign_MSS\\/MSS_CCC_0/I_MSSCCC
                          Source: ESSENTIAL

High fanout nets in the post compile netlist:
    Fanout  Type          Name
    --------------------------
    424     SET/RESET_NET Net   : SmartFusion_MPM_Reference_Design_MSS_0_M2F_RESET_N
                          Driver: \\SF_MPM_RefDesign_MSS\\/MSS_ADLIB_INST
    24      INT_NET       Net   : MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/N_52
                          Driver: MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/un9_psel_0_a2_0
    20      INT_NET       Net   : MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CL10l_i_0
                          Driver: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cll1L_RNI7DKO[6]
    20      INT_NET       Net   : MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[0]
                          Driver: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[0]/U1
    20      INT_NET       Net   : MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[4]
                          Driver: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[4]/U1
    20      INT_NET       Net   : MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[3]
                          Driver: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[3]/U1
    20      INT_NET       Net   : MPM_PWM_Trimming_Outputs/PWM_enable_reg[1]
                          Driver: MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMIOll[1]/U1
    20      INT_NET       Net   : MPM_PWM_Trimming_Outputs/PWM_enable_reg[2]
                          Driver: MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMIOll[2]/U1
    19      INT_NET       Net   : \\CoreAPB3_0_APBmslave1_PADDR_[3]\\
                          Driver: \\SF_MPM_RefDesign_MSS\\/MSS_ADLIB_INST
    19      INT_NET       Net   : MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[1]
                          Driver: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[1]/U1

Nets that are candidates for clock assignment and the resulting fanout:
    Fanout  Type          Name
    --------------------------
    424     SET/RESET_NET Net   : SmartFusion_MPM_Reference_Design_MSS_0_M2F_RESET_N
                          Driver: \\SF_MPM_RefDesign_MSS\\/MSS_ADLIB_INST
    24      INT_NET       Net   : MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/N_52
                          Driver: MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/un9_psel_0_a2_0
    20      INT_NET       Net   : MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2CL10l_i_0
                          Driver: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cll1L_RNI7DKO[6]
    20      INT_NET       Net   : MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[0]
                          Driver: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[0]/U1
    20      INT_NET       Net   : MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[4]
                          Driver: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[4]/U1
    20      INT_NET       Net   : MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[3]
                          Driver: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[3]/U1
    20      INT_NET       Net   : MPM_PWM_Trimming_Outputs/PWM_enable_reg[1]
                          Driver: MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMIOll[1]/U1
    20      INT_NET       Net   : MPM_PWM_Trimming_Outputs/PWM_enable_reg[2]
                          Driver: MPM_PWM_Trimming_Outputs/CPWMi01.CPWMo11/CPWMIOll[2]/U1
    19      INT_NET       Net   : \\CoreAPB3_0_APBmslave1_PADDR_[3]\\
                          Driver: \\SF_MPM_RefDesign_MSS\\/MSS_ADLIB_INST
    19      INT_NET       Net   : MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[1]
                          Driver: MPM_PMBus_I2C/CI2CO0l.0.Ui2C/CI2Cl00L[1]/U1


