rA_timer
stage_timer
wA_timer
stage_timer
ldCount
edge_0
slowTimer
fedge_0
outBuf_rA_0
rdFFTtimer_0
wrFFTtimer_0
inBuf_ldA_0
inBuf_rA_0
twid_rA_0
twid_wA_0
inBuf_wA_0
outBufA_0
actar_0
kitRndUp_0
wrapRam_0
memP
memQ
piBuf
poBuf
am3QrTr
am3QiTi
am3QiTr
am3QrTi
twidLUT_0
outBuf_0
outBuf_1
fedge_0
smTop_0
inBuf_0
preBflySw_0
bfly_0
lut_0
twidLUT_1
postBflySw_0
outBuff_0
autoScale_0
fftTop_inst
fifo512X32_inst
u_mux_p_to_b3
MSS_CCC_0
Aapb_int_fft_0
CoreAPB3_0
MultichannelFFT_MSS_0
DFN1_94
AND2_232
NOR2_15
XOR2_PP0_13_inst
XOR2_PP5_4_inst
AND2_23
XOR3_7
XOR3_18
AO1_22
XOR2_40
NOR2_12
AND2_91
DFN1_SumB_30_inst
XOR3_31
MAJ3_31
XOR2_PP6_6_inst
BUFF_7
XOR3_82
AO1_54
MAJ3_44
DFN1_SumA_1_inst
XOR2_PP6_4_inst
XOR2_PP5_13_inst
AND2_184
XOR2_PP6_10_inst
MX2_124
AO1_84
DFN1_117
MX2_89
DFN1_4
OR3_6
MX2_37
XOR2_92
MX2_54
MX2_75
DFN1_SumA_30_inst
AND2_55
XOR2_Mult_10_inst
MX2_112
MX2_23
MX2_94
MAJ3_19
XOR2_PP2_4_inst
MAJ3_18
AND2_181
DFN1_SumA_24_inst
MX2_65
MX2_1
DFN1_SumB_18_inst
XOR3_86
DFN1_73
DFN1_142
sign
zero
mul
genblk
begin
Bus
Bit
Core
LUT
cout
inter
push
pop
decode
encode
write
read
cache
shift
store
ADD
AND
MUX
BUF
BIN
BIT
COUNT
BYTE
CLK
SEL
CNT
FF
DSP
LUT
DLY
TRI
CNT
XOR
OR
NOT
div
add
and
mux
buf
bin
bit
count
byte
clk
sel
cnt
ff
dsp
dly
tri
cnt
xor
off
not
hex
HEX
sub
tran
state
mac
load
pass
next
log
inst
start
ibuf
obuf
DEC
DDR
OFF
OUT
FIR
memClk
cry
pipe
ret
U0
U1
U2
U3
U4
U5
core
reg
lock
co
di
enc
dec
pri
comp
Dly
clr
CLR
rst
RST
pre
PRE
ena
ENA
mult
MULT
rx
RX
tx
TX
lut
LUT
dsp
DSP
ram
RAM
so
mi
Bi
dir
in
out
get
put
gen
fft
fifo
ext
gate
net
Tri
end
cap
mod
pri
at
isbi
bu
to
at
ba
se
en
de
ar
fa
co
ca
vi
th
