Timing Report Max Delay Analysis

SmartTime Version v10.1 SP1
Actel Corporation - Actel Designer Software Release v10.1 SP1 (Version 10.1.1.6)
Copyright (c) 1989-2012
Date: Fri Nov 23 09:18:32 2012


Design: MultichannelFFT
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                9.359
Frequency (MHz):            106.849
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                21.208
Frequency (MHz):            47.152
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.206
External Hold (ns):         4.012
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MultichannelFFT_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[9]
  Delay (ns):                  11.554
  Slack (ns):                  3.141
  Arrival (ns):                15.558
  Required (ns):               18.699
  Setup (ns):                  -2.195
  Minimum Period (ns):         9.359

Path 2
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[13]
  Delay (ns):                  10.825
  Slack (ns):                  3.870
  Arrival (ns):                14.829
  Required (ns):               18.699
  Setup (ns):                  -2.195
  Minimum Period (ns):         8.630

Path 3
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[11]
  Delay (ns):                  10.696
  Slack (ns):                  3.997
  Arrival (ns):                14.700
  Required (ns):               18.697
  Setup (ns):                  -2.193
  Minimum Period (ns):         8.503

Path 4
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[5]
  Delay (ns):                  10.601
  Slack (ns):                  4.091
  Arrival (ns):                14.605
  Required (ns):               18.696
  Setup (ns):                  -2.192
  Minimum Period (ns):         8.409

Path 5
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[17]
  Delay (ns):                  10.332
  Slack (ns):                  4.351
  Arrival (ns):                14.336
  Required (ns):               18.687
  Setup (ns):                  -2.183
  Minimum Period (ns):         8.149


Expanded Path 1
  From: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[9]
  data required time                             18.699
  data arrival time                          -   15.558
  slack                                          3.141
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  4.004
               +     2.854          cell: ADLIB:MSS_APB_IP
  6.858                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[11] (r)
               +     0.124          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/MSSPADDR[11]INT_NET
  6.982                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_33:PIN3INT (r)
               +     0.086          cell: ADLIB:MSS_IF
  7.068                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_33:PIN3 (r)
               +     1.318          net: CoreAPB3_0_APBmslave0_PADDR[11]
  8.386                        CoreAPB3_0/iPSELS_1[0]:A (r)
               +     0.331          cell: ADLIB:NOR2
  8.717                        CoreAPB3_0/iPSELS_1[0]:Y (f)
               +     0.351          net: CoreAPB3_0/iPSELS_1[0]
  9.068                        CoreAPB3_0/iPSELS[0]:B (f)
               +     0.571          cell: ADLIB:OR2B
  9.639                        CoreAPB3_0/iPSELS[0]:Y (r)
               +     3.149          net: CoreAPB3_0_APBmslave0_PSELx
  12.788                       CoreAPB3_0/u_mux_p_to_b3/PRDATA_9:B (r)
               +     0.351          cell: ADLIB:NOR2A
  13.139                       CoreAPB3_0/u_mux_p_to_b3/PRDATA_9:Y (f)
               +     1.749          net: MultichannelFFT_MSS_0_MSS_MASTER_APB_PRDATA[9]
  14.888                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_39:PIN6 (f)
               +     0.174          cell: ADLIB:MSS_IF
  15.062                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_39:PIN6INT (f)
               +     0.496          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/MSSPRDATA[9]INT_NET
  15.558                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[9] (f)
                                    
  15.558                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_fabric_interface_clock
               +     0.000          Clock source
  12.500                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  16.504
               -    -2.195          Library setup time: ADLIB:MSS_APB_IP
  18.699                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[9]
                                    
  18.699                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int/U1:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  5.456
  Slack (ns):                  6.360
  Arrival (ns):                11.428
  Required (ns):               17.788
  Setup (ns):                  -1.284

Path 2
  From:                        Aapb_int_fft_0/PREADY0:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  5.033
  Slack (ns):                  6.823
  Arrival (ns):                10.965
  Required (ns):               17.788
  Setup (ns):                  -1.284

Path 3
  From:                        Aapb_int_fft_0/PREADY1:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  5.006
  Slack (ns):                  6.850
  Arrival (ns):                10.938
  Required (ns):               17.788
  Setup (ns):                  -1.284

Path 4
  From:                        Aapb_int_fft_0/EMPTY_OUT_REG/U1:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.674
  Slack (ns):                  7.074
  Arrival (ns):                10.606
  Required (ns):               17.680
  Setup (ns):                  -1.176

Path 5
  From:                        Aapb_int_fft_0/fifo512X32_inst/\\DFN1E1C0_Q[5]\\/U1:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[5]
  Delay (ns):                  5.662
  Slack (ns):                  7.081
  Arrival (ns):                11.615
  Required (ns):               18.696
  Setup (ns):                  -2.192


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int/U1:CLK
  To: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  data required time                             17.788
  data arrival time                          -   11.428
  slack                                          6.360
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.723          net: FAB_CLK
  5.972                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  6.643                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int/U1:Q (f)
               +     1.679          net: Aapb_int_fft_0_FFT_IP_RDY
  8.322                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int_RNIT1EF1:B (f)
               +     0.520          cell: ADLIB:MX2
  8.842                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int_RNIT1EF1:Y (f)
               +     0.282          net: CoreAPB3_0_APBmslave0_PREADY
  9.124                        CoreAPB3_0/u_mux_p_to_b3/PREADY:A (f)
               +     0.462          cell: ADLIB:OR2
  9.586                        CoreAPB3_0/u_mux_p_to_b3/PREADY:Y (f)
               +     1.175          net: MultichannelFFT_MSS_0_MSS_MASTER_APB_PREADY
  10.761                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_36:PIN5 (f)
               +     0.190          cell: ADLIB:MSS_IF
  10.951                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_36:PIN5INT (f)
               +     0.477          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/MSSPREADYINT_NET
  11.428                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY (f)
                                    
  11.428                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_fabric_interface_clock
               +     0.000          Clock source
  12.500                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  16.504
               -    -1.284          Library setup time: ADLIB:MSS_APB_IP
  17.788                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
                                    
  17.788                       data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_pclk1

Path 1
  From:                        Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  Delay (ns):                  4.426
  Slack (ns):                  7.447
  Arrival (ns):                10.343
  Required (ns):               17.790
  Setup (ns):                  -1.286

Path 2
  From:                        Aapb_int_fft_0/fifo512X32_inst/DFN1P0_EMPTY:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[3]
  Delay (ns):                  4.157
  Slack (ns):                  7.743
  Arrival (ns):                10.105
  Required (ns):               17.848
  Setup (ns):                  -1.344

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int/U1:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[0]
  Delay (ns):                  2.692
  Slack (ns):                  9.110
  Arrival (ns):                8.664
  Required (ns):               17.774
  Setup (ns):                  -1.270

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  2.065
  Slack (ns):                  9.774
  Arrival (ns):                7.992
  Required (ns):               17.766
  Setup (ns):                  -1.262


Expanded Path 1
  From: Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:CLK
  To: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  data required time                             17.790
  data arrival time                          -   10.343
  slack                                          7.447
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.668          net: FAB_CLK
  5.917                        Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:CLK (r)
               +     0.671          cell: ADLIB:DFN1P0
  6.588                        Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:Q (f)
               +     3.565          net: Aapb_int_fft_0_AEMPTY_OUT
  10.153                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_22:PIN5 (f)
               +     0.190          cell: ADLIB:MSS_IF
  10.343                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_22:PIN5INT (f)
               +     0.000          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/GPI[2]INT_NET
  10.343                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2] (f)
                                    
  10.343                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_pclk1
               +     0.000          Clock source
  12.500                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.004          Clock generation
  16.504
               -    -1.286          Library setup time: ADLIB:MSS_APB_IP
  17.790                       MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
                                    
  17.790                       data required time


END SET mss_ccc_gla1 to mss_pclk1

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Aapb_int_fft_0/PENABLE_reg:CLK
  To:                          Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:D
  Delay (ns):                  20.660
  Slack (ns):                  -8.708
  Arrival (ns):                26.603
  Required (ns):               17.895
  Setup (ns):                  0.522
  Minimum Period (ns):         21.208

Path 2
  From:                        Aapb_int_fft_0/fifo512X32_inst/DFN1C0_FULL:CLK
  To:                          Aapb_int_fft_0/fifo512X32_inst/DFN1C0_AFULL:D
  Delay (ns):                  19.390
  Slack (ns):                  -7.381
  Arrival (ns):                25.338
  Required (ns):               17.957
  Setup (ns):                  0.522
  Minimum Period (ns):         19.881

Path 3
  From:                        Aapb_int_fft_0/ifoY_valid:CLK
  To:                          Aapb_int_fft_0/fifo512X32_inst/DFN1C0_AFULL:D
  Delay (ns):                  18.830
  Slack (ns):                  -6.803
  Arrival (ns):                24.760
  Required (ns):               17.957
  Setup (ns):                  0.522
  Minimum Period (ns):         19.303

Path 4
  From:                        Aapb_int_fft_0/fifo512X32_inst/DFN1P0_EMPTY:CLK
  To:                          Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:D
  Delay (ns):                  18.523
  Slack (ns):                  -6.576
  Arrival (ns):                24.471
  Required (ns):               17.895
  Setup (ns):                  0.522
  Minimum Period (ns):         19.076

Path 5
  From:                        Aapb_int_fft_0/fifo512X32_inst/\\DFN1C0_MEM_WADDR[0]\\:CLK
  To:                          Aapb_int_fft_0/fifo512X32_inst/DFN1C0_AFULL:D
  Delay (ns):                  17.737
  Slack (ns):                  -5.709
  Arrival (ns):                23.666
  Required (ns):               17.957
  Setup (ns):                  0.522
  Minimum Period (ns):         18.209


Expanded Path 1
  From: Aapb_int_fft_0/PENABLE_reg:CLK
  To: Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:D
  data required time                             17.895
  data arrival time                          -   26.603
  slack                                          -8.708
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.694          net: FAB_CLK
  5.943                        Aapb_int_fft_0/PENABLE_reg:CLK (r)
               +     0.671          cell: ADLIB:DFN1P0
  6.614                        Aapb_int_fft_0/PENABLE_reg:Q (f)
               +     0.306          net: Aapb_int_fft_0/PENABLE_reg_i_0
  6.920                        Aapb_int_fft_0/PENABLE_reg_RNIE8K93:B (f)
               +     0.584          cell: ADLIB:NOR3B
  7.504                        Aapb_int_fft_0/PENABLE_reg_RNIE8K93:Y (f)
               +     2.425          net: Aapb_int_fft_0/REP
  9.929                        Aapb_int_fft_0/fifo512X32_inst/AND2_MEMORYRE:B (f)
               +     0.571          cell: ADLIB:AND2A
  10.500                       Aapb_int_fft_0/fifo512X32_inst/AND2_MEMORYRE:Y (f)
               +     0.442          net: Aapb_int_fft_0/fifo512X32_inst/MEMORYRE
  10.942                       Aapb_int_fft_0/fifo512X32_inst/AND2_88:B (f)
               +     0.574          cell: ADLIB:AND2
  11.516                       Aapb_int_fft_0/fifo512X32_inst/AND2_88:Y (f)
               +     0.877          net: Aapb_int_fft_0/fifo512X32_inst/AND2_88_Y
  12.393                       Aapb_int_fft_0/fifo512X32_inst/AO1_25:B (f)
               +     0.574          cell: ADLIB:NOR2B
  12.967                       Aapb_int_fft_0/fifo512X32_inst/AO1_25:Y (f)
               +     0.437          net: Aapb_int_fft_0/fifo512X32_inst/AO1_25_Y
  13.404                       Aapb_int_fft_0/fifo512X32_inst/AO1_26:C (f)
               +     0.620          cell: ADLIB:NOR3C
  14.024                       Aapb_int_fft_0/fifo512X32_inst/AO1_26:Y (f)
               +     1.136          net: Aapb_int_fft_0/fifo512X32_inst/AO1_26_Y
  15.160                       Aapb_int_fft_0/fifo512X32_inst/AO1_0:B (f)
               +     0.571          cell: ADLIB:NOR2B
  15.731                       Aapb_int_fft_0/fifo512X32_inst/AO1_0:Y (f)
               +     0.384          net: Aapb_int_fft_0/fifo512X32_inst/AO1_0_Y
  16.115                       Aapb_int_fft_0/fifo512X32_inst/\\XOR2_RBINNXTSHIFT[6]\\:B (f)
               +     0.899          cell: ADLIB:XOR2
  17.014                       Aapb_int_fft_0/fifo512X32_inst/\\XOR2_RBINNXTSHIFT[6]\\:Y (f)
               +     0.285          net: Aapb_int_fft_0/fifo512X32_inst/Z_RBINNXTSHIFT[6]_
  17.299                       Aapb_int_fft_0/fifo512X32_inst/INV_11:A (f)
               +     0.462          cell: ADLIB:INV
  17.761                       Aapb_int_fft_0/fifo512X32_inst/INV_11:Y (r)
               +     0.369          net: Aapb_int_fft_0/fifo512X32_inst/INV_11_Y
  18.130                       Aapb_int_fft_0/fifo512X32_inst/AND2_87:B (r)
               +     0.470          cell: ADLIB:AND2
  18.600                       Aapb_int_fft_0/fifo512X32_inst/AND2_87:Y (r)
               +     0.296          net: Aapb_int_fft_0/fifo512X32_inst/AND2_87_Y
  18.896                       Aapb_int_fft_0/fifo512X32_inst/AO1_24:C (r)
               +     0.698          cell: ADLIB:AO1
  19.594                       Aapb_int_fft_0/fifo512X32_inst/AO1_24:Y (r)
               +     0.306          net: Aapb_int_fft_0/fifo512X32_inst/AO1_24_Y
  19.900                       Aapb_int_fft_0/fifo512X32_inst/AO1_21:C (r)
               +     0.596          cell: ADLIB:AO1
  20.496                       Aapb_int_fft_0/fifo512X32_inst/AO1_21:Y (r)
               +     1.323          net: Aapb_int_fft_0/fifo512X32_inst/AO1_21_Y
  21.819                       Aapb_int_fft_0/fifo512X32_inst/AO1_40:B (r)
               +     0.516          cell: ADLIB:AO1
  22.335                       Aapb_int_fft_0/fifo512X32_inst/AO1_40:Y (r)
               +     0.306          net: Aapb_int_fft_0/fifo512X32_inst/AO1_40_Y
  22.641                       Aapb_int_fft_0/fifo512X32_inst/\\XOR2_RDIFF[8]\\:C (r)
               +     0.897          cell: ADLIB:XOR3
  23.538                       Aapb_int_fft_0/fifo512X32_inst/\\XOR2_RDIFF[8]\\:Y (f)
               +     0.586          net: Aapb_int_fft_0/fifo512X32_inst/Z_RDIFF[8]_
  24.124                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY_RNO_3:B (f)
               +     0.650          cell: ADLIB:AND3C
  24.774                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY_RNO_3:Y (r)
               +     0.306          net: Aapb_int_fft_0/fifo512X32_inst/m22_i_a3_1
  25.080                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY_RNO_0:A (r)
               +     0.606          cell: ADLIB:NOR3B
  25.686                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY_RNO_0:Y (r)
               +     0.294          net: Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY_RNO_0
  25.980                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY_RNO:A (r)
               +     0.327          cell: ADLIB:AND3B
  26.307                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY_RNO:Y (f)
               +     0.296          net: Aapb_int_fft_0/fifo512X32_inst/AOI1_0_Y
  26.603                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:D (f)
                                    
  26.603                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.668          net: FAB_CLK
  18.417                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1P0
  17.895                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:D
                                    
  17.895                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[0]/U1:CLR
  Delay (ns):                  5.653
  Slack (ns):                  6.564
  Arrival (ns):                11.584
  Required (ns):               18.148
  Recovery (ns):               0.271
  Minimum Period (ns):         5.936
  Skew (ns):                   0.012

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ldCount/tc_out/U1:CLR
  Delay (ns):                  5.474
  Slack (ns):                  6.747
  Arrival (ns):                11.405
  Required (ns):               18.152
  Recovery (ns):               0.271
  Minimum Period (ns):         5.753
  Skew (ns):                   0.008

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ldCount/Q_out[4]/U1:CLR
  Delay (ns):                  5.471
  Slack (ns):                  6.750
  Arrival (ns):                11.402
  Required (ns):               18.152
  Recovery (ns):               0.271
  Minimum Period (ns):         5.750
  Skew (ns):                   0.008

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/tc_out:CLR
  Delay (ns):                  5.258
  Slack (ns):                  6.947
  Arrival (ns):                11.189
  Required (ns):               18.136
  Recovery (ns):               0.271
  Minimum Period (ns):         5.553
  Skew (ns):                   0.024

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ldCount/Q_out[3]/U1:CLR
  Delay (ns):                  5.287
  Slack (ns):                  6.950
  Arrival (ns):                11.218
  Required (ns):               18.168
  Recovery (ns):               0.271
  Minimum Period (ns):         5.550
  Skew (ns):                   -0.008


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[0]/U1:CLR
  data required time                             18.148
  data arrival time                          -   11.584
  slack                                          6.564
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.682          net: FAB_CLK
  5.931                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK (r)
               +     0.671          cell: ADLIB:DFN1P0
  6.602                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:Q (f)
               +     1.418          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/initRst
  8.020                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNI4I1K:B (f)
               +     0.445          cell: ADLIB:NOR2A
  8.465                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNI4I1K:Y (r)
               +     3.119          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst
  11.584                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[0]/U1:CLR (r)
                                    
  11.584                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.670          net: FAB_CLK
  18.419                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[0]/U1:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1C0
  18.148                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[0]/U1:CLR
                                    
  18.148                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:D
  Delay (ns):                  27.117
  Slack (ns):                  -13.226
  Arrival (ns):                31.121
  Required (ns):               17.895
  Setup (ns):                  0.522

Path 2
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo512X32_inst/DFN1P0_EMPTY:D
  Delay (ns):                  22.004
  Slack (ns):                  -8.082
  Arrival (ns):                26.008
  Required (ns):               17.926
  Setup (ns):                  0.522

Path 3
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo512X32_inst/\\DFN1C0_MEM_RADDR[6]\\:D
  Delay (ns):                  18.689
  Slack (ns):                  -4.767
  Arrival (ns):                22.693
  Required (ns):               17.926
  Setup (ns):                  0.522

Path 4
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo512X32_inst/\\DFN1C0_MEM_RADDR[9]\\:D
  Delay (ns):                  18.518
  Slack (ns):                  -4.617
  Arrival (ns):                22.522
  Required (ns):               17.905
  Setup (ns):                  0.522

Path 5
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo512X32_inst/\\DFN1C0_MEM_RADDR[7]\\:D
  Delay (ns):                  18.492
  Slack (ns):                  -4.596
  Arrival (ns):                22.496
  Required (ns):               17.900
  Setup (ns):                  0.522


Expanded Path 1
  From: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:D
  data required time                             17.895
  data arrival time                          -   31.121
  slack                                          -13.226
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  4.004
               +     2.854          cell: ADLIB:MSS_APB_IP
  6.858                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[11] (r)
               +     0.124          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/MSSPADDR[11]INT_NET
  6.982                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_33:PIN3INT (r)
               +     0.086          cell: ADLIB:MSS_IF
  7.068                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_33:PIN3 (r)
               +     1.318          net: CoreAPB3_0_APBmslave0_PADDR[11]
  8.386                        CoreAPB3_0/iPSELS_1[0]:A (r)
               +     0.331          cell: ADLIB:NOR2
  8.717                        CoreAPB3_0/iPSELS_1[0]:Y (f)
               +     0.351          net: CoreAPB3_0/iPSELS_1[0]
  9.068                        CoreAPB3_0/iPSELS_0[0]:B (f)
               +     0.571          cell: ADLIB:OR2B
  9.639                        CoreAPB3_0/iPSELS_0[0]:Y (r)
               +     1.106          net: CoreAPB3_0_APBmslave0_PSELx_0
  10.745                       Aapb_int_fft_0/un3_fifo_rd_en_1:B (r)
               +     0.351          cell: ADLIB:NOR2A
  11.096                       Aapb_int_fft_0/un3_fifo_rd_en_1:Y (f)
               +     0.306          net: Aapb_int_fft_0/un3_fifo_rd_en_1
  11.402                       Aapb_int_fft_0/PENABLE_reg_RNIE8K93:A (f)
               +     0.620          cell: ADLIB:NOR3B
  12.022                       Aapb_int_fft_0/PENABLE_reg_RNIE8K93:Y (f)
               +     2.425          net: Aapb_int_fft_0/REP
  14.447                       Aapb_int_fft_0/fifo512X32_inst/AND2_MEMORYRE:B (f)
               +     0.571          cell: ADLIB:AND2A
  15.018                       Aapb_int_fft_0/fifo512X32_inst/AND2_MEMORYRE:Y (f)
               +     0.442          net: Aapb_int_fft_0/fifo512X32_inst/MEMORYRE
  15.460                       Aapb_int_fft_0/fifo512X32_inst/AND2_88:B (f)
               +     0.574          cell: ADLIB:AND2
  16.034                       Aapb_int_fft_0/fifo512X32_inst/AND2_88:Y (f)
               +     0.877          net: Aapb_int_fft_0/fifo512X32_inst/AND2_88_Y
  16.911                       Aapb_int_fft_0/fifo512X32_inst/AO1_25:B (f)
               +     0.574          cell: ADLIB:NOR2B
  17.485                       Aapb_int_fft_0/fifo512X32_inst/AO1_25:Y (f)
               +     0.437          net: Aapb_int_fft_0/fifo512X32_inst/AO1_25_Y
  17.922                       Aapb_int_fft_0/fifo512X32_inst/AO1_26:C (f)
               +     0.620          cell: ADLIB:NOR3C
  18.542                       Aapb_int_fft_0/fifo512X32_inst/AO1_26:Y (f)
               +     1.136          net: Aapb_int_fft_0/fifo512X32_inst/AO1_26_Y
  19.678                       Aapb_int_fft_0/fifo512X32_inst/AO1_0:B (f)
               +     0.571          cell: ADLIB:NOR2B
  20.249                       Aapb_int_fft_0/fifo512X32_inst/AO1_0:Y (f)
               +     0.384          net: Aapb_int_fft_0/fifo512X32_inst/AO1_0_Y
  20.633                       Aapb_int_fft_0/fifo512X32_inst/\\XOR2_RBINNXTSHIFT[6]\\:B (f)
               +     0.899          cell: ADLIB:XOR2
  21.532                       Aapb_int_fft_0/fifo512X32_inst/\\XOR2_RBINNXTSHIFT[6]\\:Y (f)
               +     0.285          net: Aapb_int_fft_0/fifo512X32_inst/Z_RBINNXTSHIFT[6]_
  21.817                       Aapb_int_fft_0/fifo512X32_inst/INV_11:A (f)
               +     0.462          cell: ADLIB:INV
  22.279                       Aapb_int_fft_0/fifo512X32_inst/INV_11:Y (r)
               +     0.369          net: Aapb_int_fft_0/fifo512X32_inst/INV_11_Y
  22.648                       Aapb_int_fft_0/fifo512X32_inst/AND2_87:B (r)
               +     0.470          cell: ADLIB:AND2
  23.118                       Aapb_int_fft_0/fifo512X32_inst/AND2_87:Y (r)
               +     0.296          net: Aapb_int_fft_0/fifo512X32_inst/AND2_87_Y
  23.414                       Aapb_int_fft_0/fifo512X32_inst/AO1_24:C (r)
               +     0.698          cell: ADLIB:AO1
  24.112                       Aapb_int_fft_0/fifo512X32_inst/AO1_24:Y (r)
               +     0.306          net: Aapb_int_fft_0/fifo512X32_inst/AO1_24_Y
  24.418                       Aapb_int_fft_0/fifo512X32_inst/AO1_21:C (r)
               +     0.596          cell: ADLIB:AO1
  25.014                       Aapb_int_fft_0/fifo512X32_inst/AO1_21:Y (r)
               +     1.323          net: Aapb_int_fft_0/fifo512X32_inst/AO1_21_Y
  26.337                       Aapb_int_fft_0/fifo512X32_inst/AO1_40:B (r)
               +     0.516          cell: ADLIB:AO1
  26.853                       Aapb_int_fft_0/fifo512X32_inst/AO1_40:Y (r)
               +     0.306          net: Aapb_int_fft_0/fifo512X32_inst/AO1_40_Y
  27.159                       Aapb_int_fft_0/fifo512X32_inst/\\XOR2_RDIFF[8]\\:C (r)
               +     0.897          cell: ADLIB:XOR3
  28.056                       Aapb_int_fft_0/fifo512X32_inst/\\XOR2_RDIFF[8]\\:Y (f)
               +     0.586          net: Aapb_int_fft_0/fifo512X32_inst/Z_RDIFF[8]_
  28.642                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY_RNO_3:B (f)
               +     0.650          cell: ADLIB:AND3C
  29.292                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY_RNO_3:Y (r)
               +     0.306          net: Aapb_int_fft_0/fifo512X32_inst/m22_i_a3_1
  29.598                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY_RNO_0:A (r)
               +     0.606          cell: ADLIB:NOR3B
  30.204                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY_RNO_0:Y (r)
               +     0.294          net: Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY_RNO_0
  30.498                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY_RNO:A (r)
               +     0.327          cell: ADLIB:AND3B
  30.825                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY_RNO:Y (f)
               +     0.296          net: Aapb_int_fft_0/fifo512X32_inst/AOI1_0_Y
  31.121                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:D (f)
                                    
  31.121                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.668          net: FAB_CLK
  18.417                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1P0
  17.895                       Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:D
                                    
  17.895                       data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ldCount/tc_out/U1:CLR
  Delay (ns):                  15.391
  Slack (ns):                  -1.243
  Arrival (ns):                19.395
  Required (ns):               18.152
  Setup (ns):

Path 2
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ldCount/Q_out[4]/U1:CLR
  Delay (ns):                  15.388
  Slack (ns):                  -1.240
  Arrival (ns):                19.392
  Required (ns):               18.152
  Setup (ns):

Path 3
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ldCount/Q_out[3]/U1:CLR
  Delay (ns):                  15.204
  Slack (ns):                  -1.040
  Arrival (ns):                19.208
  Required (ns):               18.168
  Setup (ns):

Path 4
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ldCount/Q_out[2]/U1:CLR
  Delay (ns):                  15.115
  Slack (ns):                  -0.951
  Arrival (ns):                19.119
  Required (ns):               18.168
  Setup (ns):

Path 5
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[0]/U1:CLR
  Delay (ns):                  15.074
  Slack (ns):                  -0.930
  Arrival (ns):                19.078
  Required (ns):               18.148
  Setup (ns):


Expanded Path 1
  From: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ldCount/tc_out/U1:CLR
  data required time                             18.152
  data arrival time                          -   19.395
  slack                                          -1.243
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  3.545
               +     0.459          net: MultichannelFFT_MSS_0/GLA0
  4.004                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     3.331          cell: ADLIB:MSS_APB_IP
  7.335                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.121          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  7.456                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.095          cell: ADLIB:MSS_IF
  7.551                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     3.000          net: MultichannelFFT_MSS_0_M2F_RESET_N
  10.551                       MultichannelFFT_MSS_0/MSS_ADLIB_INST_RNIC3SC_0:A (r)
               +     0.331          cell: ADLIB:BUFF
  10.882                       MultichannelFFT_MSS_0/MSS_ADLIB_INST_RNIC3SC_0:Y (r)
               +     1.496          net: MultichannelFFT_MSS_0_M2F_RESET_N_0_0
  12.378                       MultichannelFFT_MSS_0/MSS_ADLIB_INST_RNIC3SC_3:A (r)
               +     0.424          cell: ADLIB:BUFF
  12.802                       MultichannelFFT_MSS_0/MSS_ADLIB_INST_RNIC3SC_3:Y (r)
               +     2.580          net: MultichannelFFT_MSS_0_M2F_RESET_N_0
  15.382                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNI4I1K_1:A (r)
               +     0.538          cell: ADLIB:NOR2A
  15.920                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNI4I1K_1:Y (r)
               +     3.475          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst_0
  19.395                       Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ldCount/tc_out/U1:CLR (r)
                                    
  19.395                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.674          net: FAB_CLK
  18.423                       Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ldCount/tc_out/U1:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1C0
  18.152                       Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ldCount/tc_out/U1:CLR
                                    
  18.152                       data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.139
  External Setup (ns):         -5.206


Expanded Path 1
  From: MSS_RESET_N
  To: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MultichannelFFT_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        MultichannelFFT_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MultichannelFFT_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.459          net: MultichannelFFT_MSS_0/GLA0
  N/C                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.139          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MultichannelFFT_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

