Timing Report Min Delay Analysis

SmartTime Version v10.1 SP1
Actel Corporation - Actel Designer Software Release v10.1 SP1 (Version 10.1.1.6)
Copyright (c) 1989-2012
Date: Fri Nov 23 09:02:01 2012


Design: MultichannelFFT
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                9.213
Frequency (MHz):            108.542
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                18.358
Frequency (MHz):            54.472
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.434
External Hold (ns):         4.176
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MultichannelFFT_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  3.108
  Slack (ns):                  2.002
  Arrival (ns):                6.141
  Required (ns):               4.139
  Hold (ns):                   1.106

Path 2
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  Delay (ns):                  3.542
  Slack (ns):                  2.162
  Arrival (ns):                6.575
  Required (ns):               4.413
  Hold (ns):                   1.380

Path 3
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]
  Delay (ns):                  3.582
  Slack (ns):                  2.205
  Arrival (ns):                6.615
  Required (ns):               4.410
  Hold (ns):                   1.377

Path 4
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  Delay (ns):                  3.842
  Slack (ns):                  2.459
  Arrival (ns):                6.875
  Required (ns):               4.416
  Hold (ns):                   1.383

Path 5
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[10]
  Delay (ns):                  4.075
  Slack (ns):                  2.693
  Arrival (ns):                7.108
  Required (ns):               4.415
  Hold (ns):                   1.382


Expanded Path 1
  From: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  data arrival time                              6.141
  data required time                         -   4.139
  slack                                          2.002
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.481          cell: ADLIB:MSS_APB_IP
  4.514                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPWRITE (f)
               +     0.079          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/MSSPWRITEINT_NET
  4.593                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_42:PIN3INT (f)
               +     0.041          cell: ADLIB:MSS_IF
  4.634                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_42:PIN3 (f)
               +     0.514          net: CoreAPB3_0_APBmslave0_PWRITE
  5.148                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int_RNIT1EF1:S (f)
               +     0.172          cell: ADLIB:MX2
  5.320                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int_RNIT1EF1:Y (f)
               +     0.163          net: CoreAPB3_0_APBmslave0_PREADY
  5.483                        CoreAPB3_0/u_mux_p_to_b3/PREADY:A (f)
               +     0.220          cell: ADLIB:OR2
  5.703                        CoreAPB3_0/u_mux_p_to_b3/PREADY:Y (f)
               +     0.137          net: MultichannelFFT_MSS_0_MSS_MASTER_APB_PREADY
  5.840                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_36:PIN5 (f)
               +     0.091          cell: ADLIB:MSS_IF
  5.931                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_36:PIN5INT (f)
               +     0.210          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/MSSPREADYINT_NET
  6.141                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY (f)
                                    
  6.141                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.106          Library hold time: ADLIB:MSS_APB_IP
  4.139                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
                                    
  4.139                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        Aapb_int_fft_0/fifo256x16_inst/\\DFN1E1C0_Q[15]\\:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  Delay (ns):                  1.549
  Slack (ns):                  1.468
  Arrival (ns):                5.901
  Required (ns):               4.433
  Hold (ns):                   1.400

Path 2
  From:                        Aapb_int_fft_0/fifo256x16_inst/\\DFN1E1C0_Q[1]\\:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[1]
  Delay (ns):                  1.564
  Slack (ns):                  1.502
  Arrival (ns):                5.931
  Required (ns):               4.429
  Hold (ns):                   1.396

Path 3
  From:                        Aapb_int_fft_0/fifo256x16_inst/\\DFN1E1C0_Q[10]\\:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[10]
  Delay (ns):                  1.584
  Slack (ns):                  1.503
  Arrival (ns):                5.934
  Required (ns):               4.431
  Hold (ns):                   1.398

Path 4
  From:                        Aapb_int_fft_0/fifo256x16_inst/\\DFN1E1C0_Q[11]\\:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[11]
  Delay (ns):                  1.617
  Slack (ns):                  1.531
  Arrival (ns):                5.962
  Required (ns):               4.431
  Hold (ns):                   1.398

Path 5
  From:                        Aapb_int_fft_0/fifo256x16_inst/\\DFN1E1C0_Q[3]\\:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]
  Delay (ns):                  1.705
  Slack (ns):                  1.610
  Arrival (ns):                6.038
  Required (ns):               4.428
  Hold (ns):                   1.395


Expanded Path 1
  From: Aapb_int_fft_0/fifo256x16_inst/\\DFN1E1C0_Q[15]\\:CLK
  To: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  data arrival time                              5.901
  data required time                         -   4.433
  slack                                          1.468
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.317          net: FAB_CLK
  4.352                        Aapb_int_fft_0/fifo256x16_inst/\\DFN1E1C0_Q[15]\\:CLK (r)
               +     0.249          cell: ADLIB:DFN1E1C0
  4.601                        Aapb_int_fft_0/fifo256x16_inst/\\DFN1E1C0_Q[15]\\:Q (r)
               +     0.171          net: CoreAPB3_0_APBmslave0_PRDATA[15]
  4.772                        CoreAPB3_0/u_mux_p_to_b3/PRDATA_15:A (r)
               +     0.221          cell: ADLIB:NOR2A
  4.993                        CoreAPB3_0/u_mux_p_to_b3/PRDATA_15:Y (r)
               +     0.601          net: MultichannelFFT_MSS_0_MSS_MASTER_APB_PRDATA[15]
  5.594                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_41:PIN6 (r)
               +     0.090          cell: ADLIB:MSS_IF
  5.684                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_41:PIN6INT (r)
               +     0.217          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/MSSPRDATA[15]INT_NET
  5.901                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15] (r)
                                    
  5.901                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.400          Library hold time: ADLIB:MSS_APB_IP
  4.433                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
                                    
  4.433                        data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_pclk1

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  0.485
  Slack (ns):                  0.806
  Arrival (ns):                4.837
  Required (ns):               4.031
  Hold (ns):                   0.998

Path 2
  From:                        Aapb_int_fft_0/fifo256x16_inst/DFN1P0_AEMPTY:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  Delay (ns):                  1.108
  Slack (ns):                  1.395
  Arrival (ns):                5.442
  Required (ns):               4.047
  Hold (ns):                   1.014

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int/U1:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[0]
  Delay (ns):                  1.298
  Slack (ns):                  1.572
  Arrival (ns):                5.662
  Required (ns):               4.090
  Hold (ns):                   1.057

Path 4
  From:                        Aapb_int_fft_0/fifo256x16_inst/DFN1P0_EMPTY:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[3]
  Delay (ns):                  1.273
  Slack (ns):                  1.634
  Arrival (ns):                5.601
  Required (ns):               3.967
  Hold (ns):                   0.934


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:CLK
  To: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  data arrival time                              4.837
  data required time                         -   4.031
  slack                                          0.806
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.317          net: FAB_CLK
  4.352                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:CLK (r)
               +     0.249          cell: ADLIB:DFN1
  4.601                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:Q (r)
               +     0.134          net: Aapb_int_fft_0_FFT_OP_RDY
  4.735                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_21:PIN5 (r)
               +     0.102          cell: ADLIB:MSS_IF
  4.837                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_21:PIN5INT (r)
               +     0.000          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/GPI[1]INT_NET
  4.837                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1] (r)
                                    
  4.837                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.033          Clock generation
  3.033
               +     0.998          Library hold time: ADLIB:MSS_APB_IP
  4.031                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
                                    
  4.031                        data required time


END SET mss_ccc_gla1 to mss_pclk1

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD_xhdl1[9]:CLK
  To:                          Aapb_int_fft_0/data_out_reg[9]:D
  Delay (ns):                  0.397
  Slack (ns):                  0.229
  Arrival (ns):                4.732
  Required (ns):               4.503
  Hold (ns):                   0.000

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD_xhdl1[5]:CLK
  To:                          Aapb_int_fft_0/data_out_reg[5]:D
  Delay (ns):                  0.397
  Slack (ns):                  0.229
  Arrival (ns):                4.732
  Required (ns):               4.503
  Hold (ns):                   0.000

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD_xhdl1[14]:CLK
  To:                          Aapb_int_fft_0/data_out_reg[14]:D
  Delay (ns):                  0.397
  Slack (ns):                  0.229
  Arrival (ns):                4.732
  Required (ns):               4.503
  Hold (ns):                   0.000

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/bfly_0/PiT4_r[3]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/bfly_0/PiT5_r[3]:D
  Delay (ns):                  0.401
  Slack (ns):                  0.340
  Arrival (ns):                4.736
  Required (ns):               4.396
  Hold (ns):                   0.000

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD_xhdl1[1]:CLK
  To:                          Aapb_int_fft_0/data_out_reg[1]:D
  Delay (ns):                  0.397
  Slack (ns):                  0.347
  Arrival (ns):                4.778
  Required (ns):               4.431
  Hold (ns):                   0.000


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/outBuff_0/outD_xhdl1[9]:CLK
  To: Aapb_int_fft_0/data_out_reg[9]:D
  data arrival time                              4.732
  data required time                         -   4.503
  slack                                          0.229
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.300          net: FAB_CLK
  4.335                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD_xhdl1[9]:CLK (r)
               +     0.249          cell: ADLIB:DFN1
  4.584                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD_xhdl1[9]:Q (r)
               +     0.148          net: Aapb_int_fft_0/ifoY_im[1]
  4.732                        Aapb_int_fft_0/data_out_reg[9]:D (r)
                                    
  4.732                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.468          net: FAB_CLK
  4.503                        Aapb_int_fft_0/data_out_reg[9]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.503                        Aapb_int_fft_0/data_out_reg[9]:D
                                    
  4.503                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q_out[2]/U1:CLR
  Delay (ns):                  1.125
  Slack (ns):                  1.082
  Arrival (ns):                5.446
  Required (ns):               4.364
  Removal (ns):                0.000
  Skew (ns):                   -0.043

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q_out[0]/U1:CLR
  Delay (ns):                  1.125
  Slack (ns):                  1.082
  Arrival (ns):                5.446
  Required (ns):               4.364
  Removal (ns):                0.000
  Skew (ns):                   -0.043

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/smFft_runs/U1:CLR
  Delay (ns):                  1.169
  Slack (ns):                  1.082
  Arrival (ns):                5.490
  Required (ns):               4.408
  Removal (ns):                0.000
  Skew (ns):                   -0.087

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q_out[3]/U1:CLR
  Delay (ns):                  1.126
  Slack (ns):                  1.083
  Arrival (ns):                5.447
  Required (ns):               4.364
  Removal (ns):                0.000
  Skew (ns):                   -0.043

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/smFft_rdy/U1:CLR
  Delay (ns):                  1.169
  Slack (ns):                  1.129
  Arrival (ns):                5.490
  Required (ns):               4.361
  Removal (ns):                0.000
  Skew (ns):                   -0.040


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q_out[2]/U1:CLR
  data arrival time                              5.446
  data required time                         -   4.364
  slack                                          1.082
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.286          net: FAB_CLK
  4.321                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK (r)
               +     0.320          cell: ADLIB:DFN1P0
  4.641                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:Q (f)
               +     0.407          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/initRst
  5.048                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNI4I1K_1:B (f)
               +     0.209          cell: ADLIB:NOR2A
  5.257                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNI4I1K_1:Y (r)
               +     0.189          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst_0
  5.446                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q_out[2]/U1:CLR (r)
                                    
  5.446                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.329          net: FAB_CLK
  4.364                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q_out[2]/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  4.364                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q_out[2]/U1:CLR
                                    
  4.364                        data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/PENABLE_reg:D
  Delay (ns):                  2.310
  Slack (ns):                  0.966
  Arrival (ns):                5.343
  Required (ns):               4.377
  Hold (ns):                   0.000

Path 2
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memP/wrapRam_0/actram_R0C0:WD15
  Delay (ns):                  2.941
  Slack (ns):                  1.467
  Arrival (ns):                5.974
  Required (ns):               4.507
  Hold (ns):                   0.000

Path 3
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memP/wrapRam_0/actram_R0C0:WD7
  Delay (ns):                  3.076
  Slack (ns):                  1.602
  Arrival (ns):                6.109
  Required (ns):               4.507
  Hold (ns):                   0.000

Path 4
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memQ/wrapRam_0/actram_R0C0:WD11
  Delay (ns):                  3.077
  Slack (ns):                  1.621
  Arrival (ns):                6.110
  Required (ns):               4.489
  Hold (ns):                   0.000

Path 5
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memP/wrapRam_0/actram_R0C0:WD0
  Delay (ns):                  3.171
  Slack (ns):                  1.697
  Arrival (ns):                6.204
  Required (ns):               4.507
  Hold (ns):                   0.000


Expanded Path 1
  From: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: Aapb_int_fft_0/PENABLE_reg:D
  data arrival time                              5.343
  data required time                         -   4.377
  slack                                          0.966
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.407          cell: ADLIB:MSS_APB_IP
  4.440                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPENABLE (r)
               +     0.059          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/MSSPENABLEINT_NET
  4.499                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_42:PIN2INT (r)
               +     0.045          cell: ADLIB:MSS_IF
  4.544                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_42:PIN2 (r)
               +     0.493          net: CoreAPB3_0_APBmslave0_PENABLE
  5.037                        MultichannelFFT_MSS_0/MSS_ADLIB_INST_RNIC3SC_0:A (r)
               +     0.158          cell: ADLIB:INV
  5.195                        MultichannelFFT_MSS_0/MSS_ADLIB_INST_RNIC3SC_0:Y (f)
               +     0.148          net: CoreAPB3_0_APBmslave0_PENABLE_i
  5.343                        Aapb_int_fft_0/PENABLE_reg:D (f)
                                    
  5.343                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.342          net: FAB_CLK
  4.377                        Aapb_int_fft_0/PENABLE_reg:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1P0
  4.377                        Aapb_int_fft_0/PENABLE_reg:D
                                    
  4.377                        data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fifo256x16_inst/\\RAM512X18_QXI[15]\\:RESET
  Delay (ns):                  3.926
  Slack (ns):                  2.204
  Arrival (ns):                6.959
  Required (ns):               4.755
  Hold (ns):

Path 2
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/rstAfterInit_int:E
  Delay (ns):                  3.624
  Slack (ns):                  2.303
  Arrival (ns):                6.657
  Required (ns):               4.354
  Hold (ns):                   0.000

Path 3
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/preRstAfterInit:E
  Delay (ns):                  3.624
  Slack (ns):                  2.303
  Arrival (ns):                6.657
  Required (ns):               4.354
  Hold (ns):                   0.000

Path 4
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fifo256x16_inst/\\DFN1E1C0_Q[0]\\:CLR
  Delay (ns):                  3.709
  Slack (ns):                  2.306
  Arrival (ns):                6.742
  Required (ns):               4.436
  Hold (ns):

Path 5
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/data_out_reg[3]:CLR
  Delay (ns):                  3.716
  Slack (ns):                  2.341
  Arrival (ns):                6.749
  Required (ns):               4.408
  Hold (ns):


Expanded Path 1
  From: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: Aapb_int_fft_0/fifo256x16_inst/\\RAM512X18_QXI[15]\\:RESET
  data arrival time                              6.959
  data required time                         -   4.755
  slack                                          2.204
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.309          net: MultichannelFFT_MSS_0/GLA0
  3.033                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.710          cell: ADLIB:MSS_APB_IP
  4.743                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.060          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  4.803                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.045          cell: ADLIB:MSS_IF
  4.848                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     1.288          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST_M2FRESETn
  6.136                        MultichannelFFT_MSS_0/MSS_ADLIB_INST_RNIC3SC/U_CLKSRC:A (r)
               +     0.329          cell: ADLIB:CLKSRC
  6.465                        MultichannelFFT_MSS_0/MSS_ADLIB_INST_RNIC3SC/U_CLKSRC:Y (r)
               +     0.494          net: MultichannelFFT_MSS_0_M2F_RESET_N
  6.959                        Aapb_int_fft_0/fifo256x16_inst/\\RAM512X18_QXI[15]\\:RESET (r)
                                    
  6.959                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.550          net: FAB_CLK
  4.585                        Aapb_int_fft_0/fifo256x16_inst/\\RAM512X18_QXI[15]\\:WCLK (r)
               +     0.170          Library removal time: ADLIB:RAM512X18
  4.755                        Aapb_int_fft_0/fifo256x16_inst/\\RAM512X18_QXI[15]\\:RESET
                                    
  4.755                        data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.277
  Slack (ns):
  Arrival (ns):                0.277
  Required (ns):
  Hold (ns):                   1.358
  External Hold (ns):          4.176


Expanded Path 1
  From: MSS_RESET_N
  To: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.277
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        MultichannelFFT_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        MultichannelFFT_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: MultichannelFFT_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.277                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.277                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.371          net: MultichannelFFT_MSS_0/GLA0
  N/C                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.358          Library hold time: ADLIB:MSS_APB_IP
  N/C                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MultichannelFFT_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

