----------------------------------------------------------------------
-- Created by Actel SmartDesign Mon May 07 16:14:44 2012
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic 
-- clock and reset pins connected.  If your design has special
-- clock/reset or testbench driver requirements then you should 
-- copy this file and modify it. 
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

    constant SYSCLK_PERIOD : time := 100 ns;

    signal SYSCLK : std_logic := '0';
    signal NSYSRESET : std_logic := '0';

    component MultichannelFFT_MSS
        -- ports
        port( 
            -- Inputs
            MSSPREADY : in std_logic;
            MSSPSLVERR : in std_logic;
            F2M_GPI_3 : in std_logic;
            F2M_GPI_2 : in std_logic;
            F2M_GPI_1 : in std_logic;
            F2M_GPI_0 : in std_logic;
            MSSPRDATA : in std_logic_vector(31 downto 0);
            UART_0_RXD : in std_logic;
            ADC0_ch0 : in std_logic;
            ADC0_ch1 : in std_logic;
            ADC1_ch0 : in std_logic;
            ADC1_ch1 : in std_logic;
            ADC2_ch0 : in std_logic;
            ADC2_ch1 : in std_logic;
            VAREF0 : in std_logic;
            VAREF1 : in std_logic;
            VAREF2 : in std_logic;
            MSS_RESET_N : in std_logic;

            -- Outputs
            FAB_CLK : out std_logic;
            M2F_RESET_N : out std_logic;
            MSSPSEL : out std_logic;
            MSSPENABLE : out std_logic;
            MSSPWRITE : out std_logic;
            MSSPADDR : out std_logic_vector(19 downto 0);
            MSSPWDATA : out std_logic_vector(31 downto 0);
            UART_0_TXD : out std_logic;
            EMC_AB : out std_logic_vector(25 downto 0);
            EMC_BYTEN : out std_logic_vector(1 downto 0);
            EMC_CS0_N : out std_logic;
            EMC_CS1_N : out std_logic;
            EMC_OEN0_N : out std_logic;
            EMC_OEN1_N : out std_logic;
            EMC_CLK : out std_logic;
            EMC_RW_N : out std_logic;

            -- Inouts
            EMC_DB : inout std_logic_vector(15 downto 0)

        );
    end component;

begin

    process
        variable vhdl_initial : BOOLEAN := TRUE;

    begin
        if ( vhdl_initial ) then
            -- Assert Reset
            NSYSRESET <= '0';
            wait for ( SYSCLK_PERIOD * 10 );
            
            NSYSRESET <= '1';
            wait;
        end if;
    end process;

    -- 10MHz Clock Driver
    SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );

    -- Instantiate Unit Under Test:  MultichannelFFT_MSS
    MultichannelFFT_MSS_0 : MultichannelFFT_MSS
        -- port map
        port map( 
            -- Inputs
            MSSPREADY => '0',
            MSSPSLVERR => '0',
            F2M_GPI_3 => '0',
            F2M_GPI_2 => '0',
            F2M_GPI_1 => '0',
            F2M_GPI_0 => '0',
            MSSPRDATA => (others=> '0'),
            UART_0_RXD => '0',
            ADC0_ch0 => '0',
            ADC0_ch1 => '0',
            ADC1_ch0 => '0',
            ADC1_ch1 => '0',
            ADC2_ch0 => '0',
            ADC2_ch1 => '0',
            VAREF0 => '0',
            VAREF1 => '0',
            VAREF2 => '0',
            MSS_RESET_N => NSYSRESET,

            -- Outputs
            FAB_CLK =>  open,
            M2F_RESET_N =>  open,
            MSSPSEL =>  open,
            MSSPENABLE =>  open,
            MSSPWRITE =>  open,
            MSSPADDR => open,
            MSSPWDATA => open,
            UART_0_TXD =>  open,
            EMC_AB => open,
            EMC_BYTEN => open,
            EMC_CS0_N =>  open,
            EMC_CS1_N =>  open,
            EMC_OEN0_N =>  open,
            EMC_OEN1_N =>  open,
            EMC_CLK =>  open,
            EMC_RW_N =>  open,

            -- Inouts
            EMC_DB => open

        );

end behavioral;

