rA_timer
stage_timer
wA_timer
stage_timer
ldCount
edge_0
slowTimer
fedge_0
outBuf_rA_0
rdFFTtimer_0
wrFFTtimer_0
inBuf_ldA_0
inBuf_rA_0
twid_rA_0
twid_wA_0
inBuf_wA_0
outBufA_0
actar_0
wrapRam_0
memP
memQ
piBuf
poBuf
kitRndUp_0
am3QrTr
am3QiTi
am3QiTr
am3QrTi
twidLUT_0
outBuf_0
outBuf_1
fedge_0
smTop_0
inBuf_0
preBflySw_0
bfly_0
lut_0
twidLUT_1
postBflySw_0
outBuff_0
autoScale_0
fftTop_inst
fifo256x16_inst
u_mux_p_to_b3
MSS_CCC_0
Aapb_int_fft_0
CoreAPB3_0
MultichannelFFT_MSS_0
BUFF_8
MAJ3_8
ÜMX2_PP2Û8ÝÜ
DFN1_41
ÜXOR2_PP1Û0ÝÜ
XOR2_47
XOR2_38
MX2_21
DFN1_8
AO1_7
DFN1_43
ÜAOI1_EÛ2ÝÜ
ÜXOR2_PP2Û4ÝÜ
AND2_18
AND2_15
AO1_25
NOR2_6
ÜDFN1_MultÛ0ÝÜ
XOR2_45
MAJ3_9
ÜAND2_SÛ0ÝÜ
AND2_49
AO1_8
ÜDFN1_SumBÛ14ÝÜ
AND2_10
XOR2_20
AND2_7
ÜDFN1_SumBÛ7ÝÜ
AND2_70
OR3_1
ÜAND2_SÛ1ÝÜ
DFN1_12
AND2A_1
AND2_12
XOR2_52
AND2_72
AND2_61
AO1_15
MX2_5
ÜDFN1_SumBÛ8ÝÜ
MX2_25
MAJ3_13
XOR2_24
XOR2_21
BUFF_2
DFN1_44
ÜXOR2_PP0Û7ÝÜ
DFN1_25
ÜXOR2_PP3Û7ÝÜ
ÜDFN1_SumBÛ11ÝÜ
DFN1_30
DFN1_26
sign
zero
mul
genblk
begin
Bus
Bit
Core
LUT
cout
inter
push
pop
decode
encode
write
read
cache
shift
store
ADD
AND
MUX
BUF
BIN
BIT
COUNT
BYTE
CLK
SEL
CNT
FF
DSP
LUT
DLY
TRI
CNT
XOR
OR
NOT
div
add
and
mux
buf
bin
bit
count
byte
clk
sel
cnt
ff
dsp
dly
tri
cnt
xor
off
not
hex
HEX
sub
tran
state
mac
load
pass
next
log
inst
start
ibuf
obuf
DEC
DDR
OFF
OUT
FIR
memClk
cry
pipe
ret
U0
U1
U2
U3
U4
U5
core
reg
lock
co
di
enc
dec
pri
comp
Dly
clr
CLR
rst
RST
pre
PRE
ena
ENA
mult
MULT
rx
RX
tx
TX
lut
LUT
dsp
DSP
ram
RAM
so
mi
Bi
dir
in
out
get
put
gen
fft
fifo
ext
gate
net
Tri
end
cap
mod
pri
at
isbi
bu
to
at
ba
se
en
de
ar
fa
co
ca
vi
th
