-- Version: 10.0 10.0.9.37

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity fifo256x16 is

    port( DATA   : in    std_logic_vector(15 downto 0);
          Q      : out   std_logic_vector(15 downto 0);
          WE     : in    std_logic;
          RE     : in    std_logic;
          CLK    : in    std_logic;
          FULL   : out   std_logic;
          EMPTY  : out   std_logic;
          RESET  : in    std_logic;
          AEMPTY : out   std_logic;
          AFULL  : out   std_logic
        );

end fifo256x16;

architecture DEF_ARCH of fifo256x16 is 

  component INV
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AND2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AND3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component DFN1P0
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          PRE : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component XOR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component XNOR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AO1
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component DFN1C0
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          CLR : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component AO1C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR2A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR3A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component DFN1E1C0
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          CLR : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component AOI1
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NAND3A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component RAM512X18
    generic (MEMORYFILE:string := "");

    port( RADDR8 : in    std_logic := 'U';
          RADDR7 : in    std_logic := 'U';
          RADDR6 : in    std_logic := 'U';
          RADDR5 : in    std_logic := 'U';
          RADDR4 : in    std_logic := 'U';
          RADDR3 : in    std_logic := 'U';
          RADDR2 : in    std_logic := 'U';
          RADDR1 : in    std_logic := 'U';
          RADDR0 : in    std_logic := 'U';
          WADDR8 : in    std_logic := 'U';
          WADDR7 : in    std_logic := 'U';
          WADDR6 : in    std_logic := 'U';
          WADDR5 : in    std_logic := 'U';
          WADDR4 : in    std_logic := 'U';
          WADDR3 : in    std_logic := 'U';
          WADDR2 : in    std_logic := 'U';
          WADDR1 : in    std_logic := 'U';
          WADDR0 : in    std_logic := 'U';
          WD17   : in    std_logic := 'U';
          WD16   : in    std_logic := 'U';
          WD15   : in    std_logic := 'U';
          WD14   : in    std_logic := 'U';
          WD13   : in    std_logic := 'U';
          WD12   : in    std_logic := 'U';
          WD11   : in    std_logic := 'U';
          WD10   : in    std_logic := 'U';
          WD9    : in    std_logic := 'U';
          WD8    : in    std_logic := 'U';
          WD7    : in    std_logic := 'U';
          WD6    : in    std_logic := 'U';
          WD5    : in    std_logic := 'U';
          WD4    : in    std_logic := 'U';
          WD3    : in    std_logic := 'U';
          WD2    : in    std_logic := 'U';
          WD1    : in    std_logic := 'U';
          WD0    : in    std_logic := 'U';
          RW0    : in    std_logic := 'U';
          RW1    : in    std_logic := 'U';
          WW0    : in    std_logic := 'U';
          WW1    : in    std_logic := 'U';
          PIPE   : in    std_logic := 'U';
          REN    : in    std_logic := 'U';
          WEN    : in    std_logic := 'U';
          RCLK   : in    std_logic := 'U';
          WCLK   : in    std_logic := 'U';
          RESET  : in    std_logic := 'U';
          RD17   : out   std_logic;
          RD16   : out   std_logic;
          RD15   : out   std_logic;
          RD14   : out   std_logic;
          RD13   : out   std_logic;
          RD12   : out   std_logic;
          RD11   : out   std_logic;
          RD10   : out   std_logic;
          RD9    : out   std_logic;
          RD8    : out   std_logic;
          RD7    : out   std_logic;
          RD6    : out   std_logic;
          RD5    : out   std_logic;
          RD4    : out   std_logic;
          RD3    : out   std_logic;
          RD2    : out   std_logic;
          RD1    : out   std_logic;
          RD0    : out   std_logic
        );
  end component;

  component NAND2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AND2A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR2A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port(Y : out std_logic); 
  end component;

  component VCC
    port(Y : out std_logic); 
  end component;

    signal \FULL\, \EMPTY\, WEP, REP, \MEM_RADDR[0]\, 
        \RBINNXTSHIFT[0]\, \MEM_WADDR[0]\, \WBINNXTSHIFT[0]\, 
        \MEM_RADDR[1]\, \RBINNXTSHIFT[1]\, \MEM_WADDR[1]\, 
        \WBINNXTSHIFT[1]\, \MEM_RADDR[2]\, \RBINNXTSHIFT[2]\, 
        \MEM_WADDR[2]\, \WBINNXTSHIFT[2]\, \MEM_RADDR[3]\, 
        \RBINNXTSHIFT[3]\, \MEM_WADDR[3]\, \WBINNXTSHIFT[3]\, 
        \MEM_RADDR[4]\, \RBINNXTSHIFT[4]\, \MEM_WADDR[4]\, 
        \WBINNXTSHIFT[4]\, \MEM_RADDR[5]\, \RBINNXTSHIFT[5]\, 
        \MEM_WADDR[5]\, \WBINNXTSHIFT[5]\, \MEM_RADDR[6]\, 
        \RBINNXTSHIFT[6]\, \MEM_WADDR[6]\, \WBINNXTSHIFT[6]\, 
        \MEM_RADDR[7]\, \RBINNXTSHIFT[7]\, \MEM_WADDR[7]\, 
        \WBINNXTSHIFT[7]\, \MEM_RADDR[8]\, \RBINNXTSHIFT[8]\, 
        \MEM_WADDR[8]\, \WBINNXTSHIFT[8]\, FULLINT, MEMORYWE, 
        MEMWENEG, \WDIFF[0]\, \WDIFF[1]\, \WDIFF[2]\, \WDIFF[3]\, 
        \WDIFF[4]\, \WDIFF[5]\, \WDIFF[6]\, \WDIFF[7]\, 
        \WDIFF[8]\, \AFVALCONST[0]\, \AFVALCONST[1]\, \WGRY[0]\, 
        \WGRY[1]\, \WGRY[2]\, \WGRY[3]\, \WGRY[4]\, \WGRY[5]\, 
        \WGRY[6]\, \WGRY[7]\, \WGRY[8]\, EMPTYINT, MEMORYRE, 
        MEMRENEG, \RDIFF[0]\, \RDIFF[1]\, \RDIFF[2]\, \RDIFF[3]\, 
        \RDIFF[4]\, \RDIFF[5]\, \RDIFF[6]\, \RDIFF[7]\, 
        \RDIFF[8]\, \AEVALCONST[0]\, \AEVALCONST[2]\, DVLDI, 
        DVLDX, \RGRY[0]\, \RGRY[1]\, \RGRY[2]\, \RGRY[3]\, 
        \RGRY[4]\, \RGRY[5]\, \RGRY[6]\, \RGRY[7]\, \RGRY[8]\, 
        \QXI[0]\, \QXI[1]\, \QXI[2]\, \QXI[3]\, \QXI[4]\, 
        \QXI[5]\, \QXI[6]\, \QXI[7]\, \QXI[8]\, \QXI[9]\, 
        \QXI[10]\, \QXI[11]\, \QXI[12]\, \QXI[13]\, \QXI[14]\, 
        \QXI[15]\, NAND2_1_Y, AOI1_0_Y, AND3_0_Y, NAND3A_11_Y, 
        AO1_38_Y, AND3_5_Y, NAND3A_6_Y, NAND3A_8_Y, OR2A_3_Y, 
        AO1C_1_Y, NOR3A_5_Y, OR2A_10_Y, NAND3A_2_Y, OR2A_5_Y, 
        AO1C_0_Y, NOR3A_2_Y, OR2A_0_Y, NAND3A_7_Y, XNOR2_27_Y, 
        XNOR2_4_Y, XNOR2_9_Y, OR2A_1_Y, AO1C_5_Y, NOR3A_0_Y, 
        OR2A_8_Y, NAND3A_3_Y, XNOR2_26_Y, XNOR2_2_Y, XNOR2_11_Y, 
        NOR2A_1_Y, INV_0_Y, INV_14_Y, INV_4_Y, INV_17_Y, INV_16_Y, 
        INV_10_Y, INV_11_Y, INV_1_Y, INV_9_Y, AND2_29_Y, 
        AND2_20_Y, AND2_55_Y, AND2_46_Y, AND2_81_Y, AND2_43_Y, 
        AND2_44_Y, AND2_76_Y, AND2_61_Y, AND2_42_Y, XOR2_6_Y, 
        XOR2_7_Y, XOR2_0_Y, XOR2_43_Y, XOR2_15_Y, XOR2_38_Y, 
        XOR2_36_Y, XOR2_80_Y, AND2_1_Y, AO1_12_Y, AND2_75_Y, 
        AO1_23_Y, AND2_56_Y, AO1_15_Y, AND2_69_Y, AND2_8_Y, 
        AO1_13_Y, AND2_18_Y, AO1_3_Y, AND2_4_Y, AND2_24_Y, 
        AND2_73_Y, AND2_34_Y, AND2_84_Y, OR3_1_Y, AO1_5_Y, 
        AO1_39_Y, AO1_40_Y, AO1_7_Y, AO1_21_Y, AO1_34_Y, XOR2_9_Y, 
        XOR2_23_Y, XOR2_76_Y, XOR2_29_Y, XOR2_45_Y, XOR2_58_Y, 
        XOR2_27_Y, XOR2_79_Y, AOI1_1_Y, OR2_0_Y, AND3_1_Y, 
        NAND3A_9_Y, AO1_27_Y, AND3_6_Y, NAND3A_5_Y, NAND3A_10_Y, 
        OR2A_9_Y, AO1C_2_Y, NOR3A_4_Y, OR2A_7_Y, NAND3A_4_Y, 
        OR2A_4_Y, AO1C_3_Y, NOR3A_3_Y, OR2A_11_Y, NAND3A_1_Y, 
        XNOR2_28_Y, XNOR2_25_Y, XNOR2_8_Y, OR2A_2_Y, AO1C_4_Y, 
        NOR3A_1_Y, OR2A_6_Y, NAND3A_0_Y, XNOR2_13_Y, XNOR2_3_Y, 
        XNOR2_17_Y, XOR2_37_Y, XOR2_32_Y, XOR2_19_Y, XOR2_65_Y, 
        XOR2_57_Y, XOR2_33_Y, XOR2_47_Y, XOR2_54_Y, XOR2_56_Y, 
        AND2_54_Y, AND2_10_Y, AND2_5_Y, AND2_60_Y, AND2_11_Y, 
        AND2_63_Y, AND2_14_Y, AND2_67_Y, XOR2_42_Y, XOR2_35_Y, 
        XOR2_18_Y, XOR2_74_Y, XOR2_72_Y, XOR2_69_Y, XOR2_1_Y, 
        XOR2_59_Y, XOR2_21_Y, AND2_82_Y, AO1_30_Y, AND2_71_Y, 
        AO1_9_Y, AND2_19_Y, AO1_10_Y, AND2_12_Y, AND2_66_Y, 
        AO1_46_Y, AND2_65_Y, AND2_68_Y, AND2_53_Y, AND2_6_Y, 
        AND2_13_Y, AND2_32_Y, AO1_17_Y, AND2_28_Y, AND2_30_Y, 
        AO1_1_Y, AO1_36_Y, AO1_26_Y, AO1_11_Y, AO1_31_Y, AO1_22_Y, 
        AO1_32_Y, XOR2_71_Y, XOR2_30_Y, XOR2_60_Y, XOR2_13_Y, 
        XOR2_77_Y, XOR2_83_Y, XOR2_49_Y, XOR2_70_Y, AND2A_0_Y, 
        XOR2_14_Y, XOR2_25_Y, XOR2_51_Y, XOR2_53_Y, XOR2_73_Y, 
        XOR2_78_Y, XOR2_67_Y, XOR2_20_Y, XOR2_66_Y, AND2_40_Y, 
        AND2_17_Y, AND2_57_Y, AND2_3_Y, AND2_15_Y, AND2_0_Y, 
        AND2_37_Y, AND2_25_Y, XOR2_68_Y, XOR2_4_Y, XOR2_8_Y, 
        XOR2_2_Y, XOR2_10_Y, XOR2_28_Y, XOR2_63_Y, XOR2_3_Y, 
        XOR2_17_Y, AND2_45_Y, AO1_41_Y, AND2_27_Y, AO1_16_Y, 
        AND2_9_Y, AO1_47_Y, AND2_23_Y, AND2_21_Y, AO1_25_Y, 
        AND2_64_Y, AND2_22_Y, AND2_38_Y, AND2_59_Y, AND2_51_Y, 
        AND2_70_Y, AO1_8_Y, AND2_2_Y, AND2_77_Y, AO1_24_Y, 
        AO1_0_Y, AO1_43_Y, AO1_28_Y, AO1_44_Y, AO1_45_Y, AO1_14_Y, 
        XOR2_61_Y, XOR2_81_Y, XOR2_44_Y, XOR2_41_Y, XOR2_62_Y, 
        XOR2_82_Y, XOR2_24_Y, XOR2_75_Y, NAND2_0_Y, NOR2A_0_Y, 
        INV_5_Y, INV_15_Y, INV_7_Y, INV_3_Y, INV_2_Y, INV_12_Y, 
        INV_13_Y, INV_6_Y, INV_8_Y, AND2_58_Y, AND2_50_Y, 
        AND2_7_Y, AND2_85_Y, AND2_31_Y, AND2_80_Y, AND2_83_Y, 
        AND2_26_Y, AND2_16_Y, AND2_78_Y, XOR2_11_Y, XOR2_12_Y, 
        XOR2_5_Y, XOR2_55_Y, XOR2_22_Y, XOR2_46_Y, XOR2_39_Y, 
        XOR2_84_Y, AND2_52_Y, AO1_6_Y, AND2_33_Y, AO1_4_Y, 
        AND2_72_Y, AO1_19_Y, AND2_47_Y, AND2_39_Y, AO1_29_Y, 
        AND2_74_Y, AO1_42_Y, AND2_41_Y, AND2_62_Y, AND2_49_Y, 
        AND2_36_Y, AND2_48_Y, OR3_0_Y, AO1_20_Y, AO1_33_Y, 
        AO1_37_Y, AO1_18_Y, AO1_2_Y, AO1_35_Y, XOR2_16_Y, 
        XOR2_40_Y, XOR2_26_Y, XOR2_31_Y, XOR2_64_Y, XOR2_48_Y, 
        XOR2_52_Y, XOR2_34_Y, AND3_2_Y, XOR2_50_Y, XNOR2_1_Y, 
        XNOR2_18_Y, XNOR2_22_Y, XNOR2_20_Y, XNOR2_0_Y, XNOR2_5_Y, 
        XNOR2_16_Y, XNOR2_7_Y, AND3_4_Y, AND2_35_Y, AND3_3_Y, 
        AND3_9_Y, XNOR2_23_Y, XNOR2_12_Y, XNOR2_6_Y, XNOR2_14_Y, 
        XNOR2_15_Y, XNOR2_24_Y, XNOR2_10_Y, XNOR2_19_Y, 
        XNOR2_21_Y, AND3_8_Y, AND2_79_Y, AND3_7_Y, \VCC\, \GND\
         : std_logic;
    signal GND_power_net1 : std_logic;
    signal VCC_power_net1 : std_logic;

begin 

    FULL <= \FULL\;
    EMPTY <= \EMPTY\;
    \AEVALCONST[0]\ <= GND_power_net1;
    \GND\ <= GND_power_net1;
    \AFVALCONST[0]\ <= GND_power_net1;
    \VCC\ <= VCC_power_net1;
    \AEVALCONST[2]\ <= VCC_power_net1;
    \AFVALCONST[1]\ <= VCC_power_net1;

    INV_0 : INV
      port map(A => \RBINNXTSHIFT[1]\, Y => INV_0_Y);
    
    AND2_2 : AND2
      port map(A => AND2_22_Y, B => XOR2_17_Y, Y => AND2_2_Y);
    
    AND3_6 : AND3
      port map(A => XNOR2_28_Y, B => XNOR2_25_Y, C => XNOR2_8_Y, 
        Y => AND3_6_Y);
    
    DFN1P0_AEMPTY : DFN1P0
      port map(D => AOI1_0_Y, CLK => CLK, PRE => RESET, Q => 
        AEMPTY);
    
    AND2_20 : AND2
      port map(A => \MEM_WADDR[1]\, B => INV_9_Y, Y => AND2_20_Y);
    
    XOR2_82 : XOR2
      port map(A => \MEM_RADDR[6]\, B => \GND\, Y => XOR2_82_Y);
    
    XNOR2_13 : XNOR2
      port map(A => \AFVALCONST[1]\, B => \WDIFF[6]\, Y => 
        XNOR2_13_Y);
    
    AO1_11 : AO1
      port map(A => XOR2_72_Y, B => AO1_26_Y, C => AND2_60_Y, Y
         => AO1_11_Y);
    
    AND2_11 : AND2
      port map(A => \MEM_WADDR[5]\, B => \GND\, Y => AND2_11_Y);
    
    \XOR2_WBINNXTSHIFT[2]\ : XOR2
      port map(A => XOR2_30_Y, B => AO1_1_Y, Y => 
        \WBINNXTSHIFT[2]\);
    
    AND2_22 : AND2
      port map(A => AND2_21_Y, B => AND2_64_Y, Y => AND2_22_Y);
    
    DFN1C0_FULL : DFN1C0
      port map(D => FULLINT, CLK => CLK, CLR => RESET, Q => 
        \FULL\);
    
    XNOR2_9 : XNOR2
      port map(A => \AEVALCONST[0]\, B => \RDIFF[5]\, Y => 
        XNOR2_9_Y);
    
    AND2_71 : AND2
      port map(A => XOR2_18_Y, B => XOR2_74_Y, Y => AND2_71_Y);
    
    AO1C_3 : AO1C
      port map(A => \AFVALCONST[1]\, B => \WDIFF[4]\, C => 
        \AFVALCONST[1]\, Y => AO1C_3_Y);
    
    OR2A_7 : OR2A
      port map(A => \AFVALCONST[0]\, B => \WDIFF[2]\, Y => 
        OR2A_7_Y);
    
    XOR2_19 : XOR2
      port map(A => \WBINNXTSHIFT[2]\, B => \WBINNXTSHIFT[3]\, Y
         => XOR2_19_Y);
    
    AND2_44 : AND2
      port map(A => \MEM_WADDR[5]\, B => INV_16_Y, Y => AND2_44_Y);
    
    AO1_31 : AO1
      port map(A => AND2_19_Y, B => AO1_26_Y, C => AO1_9_Y, Y => 
        AO1_31_Y);
    
    XOR2_1 : XOR2
      port map(A => \MEM_WADDR[6]\, B => \GND\, Y => XOR2_1_Y);
    
    XOR2_23 : XOR2
      port map(A => \MEM_WADDR[2]\, B => INV_14_Y, Y => XOR2_23_Y);
    
    NOR3A_5 : NOR3A
      port map(A => OR2A_3_Y, B => AO1C_1_Y, C => \AEVALCONST[0]\, 
        Y => NOR3A_5_Y);
    
    \DFN1E1C0_Q[1]\ : DFN1E1C0
      port map(D => \QXI[1]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(1));
    
    \DFN1E1C0_Q[4]\ : DFN1E1C0
      port map(D => \QXI[4]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(4));
    
    INV_1 : INV
      port map(A => \RBINNXTSHIFT[8]\, Y => INV_1_Y);
    
    \DFN1E1C0_Q[7]\ : DFN1E1C0
      port map(D => \QXI[7]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(7));
    
    XOR2_47 : XOR2
      port map(A => \WBINNXTSHIFT[6]\, B => \WBINNXTSHIFT[7]\, Y
         => XOR2_47_Y);
    
    XOR2_38 : XOR2
      port map(A => \MEM_WADDR[6]\, B => INV_10_Y, Y => XOR2_38_Y);
    
    \XOR2_RBINNXTSHIFT[0]\ : XOR2
      port map(A => \MEM_RADDR[0]\, B => MEMORYRE, Y => 
        \RBINNXTSHIFT[0]\);
    
    AO1C_1 : AO1C
      port map(A => \RDIFF[1]\, B => \AEVALCONST[0]\, C => 
        \RDIFF[0]\, Y => AO1C_1_Y);
    
    AO1_7 : AO1
      port map(A => XOR2_15_Y, B => AO1_40_Y, C => AND2_44_Y, Y
         => AO1_7_Y);
    
    \DFN1C0_WGRY[6]\ : DFN1C0
      port map(D => XOR2_47_Y, CLK => CLK, CLR => RESET, Q => 
        \WGRY[6]\);
    
    AND2_18 : AND2
      port map(A => AND2_56_Y, B => AND2_69_Y, Y => AND2_18_Y);
    
    AND2_15 : AND2
      port map(A => \MEM_RADDR[5]\, B => \GND\, Y => AND2_15_Y);
    
    AND2_84 : AND2
      port map(A => AND2_24_Y, B => XOR2_36_Y, Y => AND2_84_Y);
    
    AO1_25 : AO1
      port map(A => AND2_23_Y, B => AO1_16_Y, C => AO1_47_Y, Y
         => AO1_25_Y);
    
    INV_7 : INV
      port map(A => \MEM_RADDR[3]\, Y => INV_7_Y);
    
    AND2_78 : AND2
      port map(A => \WBINNXTSHIFT[8]\, B => INV_6_Y, Y => 
        AND2_78_Y);
    
    AND2_75 : AND2
      port map(A => XOR2_0_Y, B => XOR2_43_Y, Y => AND2_75_Y);
    
    \XOR2_RDIFF[3]\ : XOR2
      port map(A => XOR2_76_Y, B => AO1_5_Y, Y => \RDIFF[3]\);
    
    XOR2_45 : XOR2
      port map(A => \MEM_WADDR[5]\, B => INV_16_Y, Y => XOR2_45_Y);
    
    AND2_1 : AND2
      port map(A => XOR2_6_Y, B => XOR2_7_Y, Y => AND2_1_Y);
    
    \DFN1C0_MEM_WADDR[0]\ : DFN1C0
      port map(D => \WBINNXTSHIFT[0]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_WADDR[0]\);
    
    XNOR2_21 : XNOR2
      port map(A => \RBINNXTSHIFT[7]\, B => \MEM_WADDR[7]\, Y => 
        XNOR2_21_Y);
    
    \DFN1C0_MEM_WADDR[3]\ : DFN1C0
      port map(D => \WBINNXTSHIFT[3]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_WADDR[3]\);
    
    AND2_49 : AND2
      port map(A => AND2_52_Y, B => XOR2_5_Y, Y => AND2_49_Y);
    
    \DFN1C0_MEM_RADDR[1]\ : DFN1C0
      port map(D => \RBINNXTSHIFT[1]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_RADDR[1]\);
    
    AO1_8 : AO1
      port map(A => XOR2_17_Y, B => AO1_14_Y, C => AND2_25_Y, Y
         => AO1_8_Y);
    
    AND2_10 : AND2
      port map(A => \MEM_WADDR[2]\, B => \GND\, Y => AND2_10_Y);
    
    AND2_7 : AND2
      port map(A => INV_5_Y, B => INV_8_Y, Y => AND2_7_Y);
    
    XOR2_20 : XOR2
      port map(A => \RBINNXTSHIFT[7]\, B => \RBINNXTSHIFT[8]\, Y
         => XOR2_20_Y);
    
    XOR2_63 : XOR2
      port map(A => \MEM_RADDR[6]\, B => \GND\, Y => XOR2_63_Y);
    
    AOI1_1 : AOI1
      port map(A => AND3_1_Y, B => AO1_27_Y, C => NAND3A_9_Y, Y
         => AOI1_1_Y);
    
    AND2_70 : AND2
      port map(A => AND2_38_Y, B => XOR2_63_Y, Y => AND2_70_Y);
    
    OR3_1 : OR3
      port map(A => AND2_29_Y, B => AND2_20_Y, C => AND2_55_Y, Y
         => OR3_1_Y);
    
    AND2_12 : AND2
      port map(A => XOR2_1_Y, B => XOR2_59_Y, Y => AND2_12_Y);
    
    \DFN1C0_WGRY[5]\ : DFN1C0
      port map(D => XOR2_33_Y, CLK => CLK, CLR => RESET, Q => 
        \WGRY[5]\);
    
    AO1_42 : AO1
      port map(A => AND2_74_Y, B => AO1_37_Y, C => AO1_29_Y, Y
         => AO1_42_Y);
    
    XOR2_52 : XOR2
      port map(A => \WBINNXTSHIFT[7]\, B => INV_13_Y, Y => 
        XOR2_52_Y);
    
    AO1C_4 : AO1C
      port map(A => \AFVALCONST[1]\, B => \WDIFF[7]\, C => 
        \AFVALCONST[1]\, Y => AO1C_4_Y);
    
    AND2_72 : AND2
      port map(A => XOR2_22_Y, B => XOR2_46_Y, Y => AND2_72_Y);
    
    AND2_61 : AND2
      port map(A => \MEM_WADDR[7]\, B => INV_11_Y, Y => AND2_61_Y);
    
    \DFN1C0_MEM_WADDR[4]\ : DFN1C0
      port map(D => \WBINNXTSHIFT[4]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_WADDR[4]\);
    
    \XOR2_WBINNXTSHIFT[0]\ : XOR2
      port map(A => \MEM_WADDR[0]\, B => MEMORYWE, Y => 
        \WBINNXTSHIFT[0]\);
    
    AO1_15 : AO1
      port map(A => XOR2_80_Y, B => AND2_61_Y, C => AND2_42_Y, Y
         => AO1_15_Y);
    
    \DFN1C0_WGRY[7]\ : DFN1C0
      port map(D => XOR2_54_Y, CLK => CLK, CLR => RESET, Q => 
        \WGRY[7]\);
    
    AND2_EMPTYINT : AND2
      port map(A => AND3_9_Y, B => XNOR2_23_Y, Y => EMPTYINT);
    
    XOR2_24 : XOR2
      port map(A => \MEM_RADDR[7]\, B => \GND\, Y => XOR2_24_Y);
    
    AND2_57 : AND2
      port map(A => \MEM_RADDR[3]\, B => \GND\, Y => AND2_57_Y);
    
    XOR2_21 : XOR2
      port map(A => \MEM_WADDR[8]\, B => \GND\, Y => XOR2_21_Y);
    
    NOR3A_2 : NOR3A
      port map(A => OR2A_5_Y, B => AO1C_0_Y, C => \AEVALCONST[0]\, 
        Y => NOR3A_2_Y);
    
    AO1_35 : AO1
      port map(A => XOR2_39_Y, B => AO1_2_Y, C => AND2_16_Y, Y
         => AO1_35_Y);
    
    NOR3A_4 : NOR3A
      port map(A => OR2A_9_Y, B => AO1C_2_Y, C => \WDIFF[0]\, Y
         => NOR3A_4_Y);
    
    \XOR2_WDIFF[5]\ : XOR2
      port map(A => XOR2_64_Y, B => AO1_37_Y, Y => \WDIFF[5]\);
    
    AND2_46 : AND2
      port map(A => \MEM_WADDR[2]\, B => INV_14_Y, Y => AND2_46_Y);
    
    INV_11 : INV
      port map(A => \RBINNXTSHIFT[7]\, Y => INV_11_Y);
    
    XNOR2_28 : XNOR2
      port map(A => \WDIFF[3]\, B => \AFVALCONST[1]\, Y => 
        XNOR2_28_Y);
    
    \XOR2_RBINNXTSHIFT[8]\ : XOR2
      port map(A => XOR2_75_Y, B => AO1_14_Y, Y => 
        \RBINNXTSHIFT[8]\);
    
    XOR2_16 : XOR2
      port map(A => \WBINNXTSHIFT[1]\, B => INV_5_Y, Y => 
        XOR2_16_Y);
    
    XOR2_60 : XOR2
      port map(A => \MEM_WADDR[3]\, B => \GND\, Y => XOR2_60_Y);
    
    AND2_68 : AND2
      port map(A => AND2_66_Y, B => AND2_65_Y, Y => AND2_68_Y);
    
    AND2_65 : AND2
      port map(A => AND2_19_Y, B => AND2_12_Y, Y => AND2_65_Y);
    
    AND2_43 : AND2
      port map(A => \MEM_WADDR[4]\, B => INV_17_Y, Y => AND2_43_Y);
    
    AO1_24 : AO1
      port map(A => XOR2_4_Y, B => AND2_77_Y, C => AND2_40_Y, Y
         => AO1_24_Y);
    
    AND3_3 : AND3
      port map(A => XNOR2_20_Y, B => XNOR2_0_Y, C => XNOR2_5_Y, Y
         => AND3_3_Y);
    
    NAND3A_7 : NAND3A
      port map(A => \AEVALCONST[0]\, B => \RDIFF[4]\, C => 
        OR2A_5_Y, Y => NAND3A_7_Y);
    
    INV_5 : INV
      port map(A => \MEM_RADDR[1]\, Y => INV_5_Y);
    
    OR2_0 : OR2
      port map(A => AOI1_1_Y, B => \FULL\, Y => OR2_0_Y);
    
    MEMWEBUBBLE : INV
      port map(A => MEMORYWE, Y => MEMWENEG);
    
    AND2_6 : AND2
      port map(A => AND2_82_Y, B => XOR2_18_Y, Y => AND2_6_Y);
    
    XOR2_64 : XOR2
      port map(A => \WBINNXTSHIFT[5]\, B => INV_2_Y, Y => 
        XOR2_64_Y);
    
    AND3_0 : AND3
      port map(A => XNOR2_26_Y, B => XNOR2_2_Y, C => XNOR2_11_Y, 
        Y => AND3_0_Y);
    
    \DFN1C0_MEM_RADDR[2]\ : DFN1C0
      port map(D => \RBINNXTSHIFT[2]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_RADDR[2]\);
    
    AND2_60 : AND2
      port map(A => \MEM_WADDR[4]\, B => \GND\, Y => AND2_60_Y);
    
    XOR2_61 : XOR2
      port map(A => \MEM_RADDR[1]\, B => \GND\, Y => XOR2_61_Y);
    
    OR2A_4 : OR2A
      port map(A => \WDIFF[5]\, B => \AFVALCONST[1]\, Y => 
        OR2A_4_Y);
    
    AND2_83 : AND2
      port map(A => \WBINNXTSHIFT[5]\, B => INV_2_Y, Y => 
        AND2_83_Y);
    
    XOR2_57 : XOR2
      port map(A => \WBINNXTSHIFT[4]\, B => \WBINNXTSHIFT[5]\, Y
         => XOR2_57_Y);
    
    \DFN1C0_RGRY[2]\ : DFN1C0
      port map(D => XOR2_51_Y, CLK => CLK, CLR => RESET, Q => 
        \RGRY[2]\);
    
    AND2_62 : AND2
      port map(A => AND2_39_Y, B => AND2_72_Y, Y => AND2_62_Y);
    
    XOR2_33 : XOR2
      port map(A => \WBINNXTSHIFT[5]\, B => \WBINNXTSHIFT[6]\, Y
         => XOR2_33_Y);
    
    INV_3 : INV
      port map(A => \MEM_RADDR[4]\, Y => INV_3_Y);
    
    XNOR2_2 : XNOR2
      port map(A => \RDIFF[7]\, B => \AEVALCONST[0]\, Y => 
        XNOR2_2_Y);
    
    \XOR2_WBINNXTSHIFT[8]\ : XOR2
      port map(A => XOR2_70_Y, B => AO1_32_Y, Y => 
        \WBINNXTSHIFT[8]\);
    
    XNOR2_19 : XNOR2
      port map(A => \RBINNXTSHIFT[6]\, B => \MEM_WADDR[6]\, Y => 
        XNOR2_19_Y);
    
    XOR2_49 : XOR2
      port map(A => \MEM_WADDR[7]\, B => \GND\, Y => XOR2_49_Y);
    
    AO1_14 : AO1
      port map(A => AND2_64_Y, B => AO1_43_Y, C => AO1_25_Y, Y
         => AO1_14_Y);
    
    XOR2_4 : XOR2
      port map(A => \MEM_RADDR[1]\, B => \GND\, Y => XOR2_4_Y);
    
    \XOR2_WDIFF[0]\ : XOR2
      port map(A => \WBINNXTSHIFT[0]\, B => \MEM_RADDR[0]\, Y => 
        \WDIFF[0]\);
    
    AND3_1 : AND3
      port map(A => XNOR2_13_Y, B => XNOR2_3_Y, C => XNOR2_17_Y, 
        Y => AND3_1_Y);
    
    XOR2_55 : XOR2
      port map(A => \WBINNXTSHIFT[4]\, B => INV_3_Y, Y => 
        XOR2_55_Y);
    
    AND2_24 : AND2
      port map(A => AND2_8_Y, B => AND2_56_Y, Y => AND2_24_Y);
    
    AO1C_5 : AO1C
      port map(A => \RDIFF[7]\, B => \AEVALCONST[0]\, C => 
        \RDIFF[6]\, Y => AO1C_5_Y);
    
    XOR2_72 : XOR2
      port map(A => \MEM_WADDR[4]\, B => \GND\, Y => XOR2_72_Y);
    
    AO1_40 : AO1
      port map(A => AND2_75_Y, B => AO1_5_Y, C => AO1_12_Y, Y => 
        AO1_40_Y);
    
    XNOR2_0 : XNOR2
      port map(A => \MEM_RADDR[4]\, B => \WBINNXTSHIFT[4]\, Y => 
        XNOR2_0_Y);
    
    OR2A_3 : OR2A
      port map(A => \AEVALCONST[2]\, B => \RDIFF[2]\, Y => 
        OR2A_3_Y);
    
    AND2_31 : AND2
      port map(A => \WBINNXTSHIFT[3]\, B => INV_7_Y, Y => 
        AND2_31_Y);
    
    AO1_34 : AO1
      port map(A => XOR2_36_Y, B => AO1_21_Y, C => AND2_61_Y, Y
         => AO1_34_Y);
    
    XOR2_18 : XOR2
      port map(A => \MEM_WADDR[2]\, B => \GND\, Y => XOR2_18_Y);
    
    XNOR2_25 : XNOR2
      port map(A => \WDIFF[4]\, B => \AFVALCONST[1]\, Y => 
        XNOR2_25_Y);
    
    \XOR2_RBINNXTSHIFT[4]\ : XOR2
      port map(A => XOR2_41_Y, B => AO1_43_Y, Y => 
        \RBINNXTSHIFT[4]\);
    
    OR2A_6 : OR2A
      port map(A => \AFVALCONST[0]\, B => \WDIFF[8]\, Y => 
        OR2A_6_Y);
    
    AO1_46 : AO1
      port map(A => AND2_12_Y, B => AO1_9_Y, C => AO1_10_Y, Y => 
        AO1_46_Y);
    
    \DFN1C0_MEM_WADDR[8]\ : DFN1C0
      port map(D => \WBINNXTSHIFT[8]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_WADDR[8]\);
    
    \DFN1C0_RGRY[1]\ : DFN1C0
      port map(D => XOR2_25_Y, CLK => CLK, CLR => RESET, Q => 
        \RGRY[1]\);
    
    \DFN1C0_WGRY[3]\ : DFN1C0
      port map(D => XOR2_65_Y, CLK => CLK, CLR => RESET, Q => 
        \WGRY[3]\);
    
    XOR2_8 : XOR2
      port map(A => \MEM_RADDR[2]\, B => \GND\, Y => XOR2_8_Y);
    
    \DFN1E1C0_Q[6]\ : DFN1E1C0
      port map(D => \QXI[6]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(6));
    
    NAND3A_0 : NAND3A
      port map(A => \WDIFF[7]\, B => \AFVALCONST[1]\, C => 
        OR2A_2_Y, Y => NAND3A_0_Y);
    
    AO1_43 : AO1
      port map(A => AND2_27_Y, B => AO1_24_Y, C => AO1_41_Y, Y
         => AO1_43_Y);
    
    \XOR2_RBINNXTSHIFT[6]\ : XOR2
      port map(A => XOR2_82_Y, B => AO1_44_Y, Y => 
        \RBINNXTSHIFT[6]\);
    
    XOR2_30 : XOR2
      port map(A => \MEM_WADDR[2]\, B => \GND\, Y => XOR2_30_Y);
    
    NAND3A_6 : NAND3A
      port map(A => NOR3A_2_Y, B => OR2A_0_Y, C => NAND3A_7_Y, Y
         => NAND3A_6_Y);
    
    OR2A_2 : OR2A
      port map(A => \WDIFF[8]\, B => \AFVALCONST[0]\, Y => 
        OR2A_2_Y);
    
    AND2_38 : AND2
      port map(A => AND2_21_Y, B => AND2_9_Y, Y => AND2_38_Y);
    
    \XOR2_RDIFF[0]\ : XOR2
      port map(A => \MEM_WADDR[0]\, B => \RBINNXTSHIFT[0]\, Y => 
        \RDIFF[0]\);
    
    AND2_35 : AND2
      port map(A => XNOR2_16_Y, B => XNOR2_7_Y, Y => AND2_35_Y);
    
    MEMREBUBBLE : INV
      port map(A => MEMORYRE, Y => MEMRENEG);
    
    \XNOR2_RDIFF[1]\ : XNOR2
      port map(A => XOR2_9_Y, B => NOR2A_1_Y, Y => \RDIFF[1]\);
    
    \DFN1C0_MEM_WADDR[7]\ : DFN1C0
      port map(D => \WBINNXTSHIFT[7]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_WADDR[7]\);
    
    AND2_29 : AND2
      port map(A => \MEM_WADDR[1]\, B => INV_0_Y, Y => AND2_29_Y);
    
    \DFN1C0_MEM_RADDR[4]\ : DFN1C0
      port map(D => \RBINNXTSHIFT[4]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_RADDR[4]\);
    
    XOR2_34 : XOR2
      port map(A => \WBINNXTSHIFT[8]\, B => INV_6_Y, Y => 
        XOR2_34_Y);
    
    XOR2_31 : XOR2
      port map(A => \WBINNXTSHIFT[4]\, B => INV_3_Y, Y => 
        XOR2_31_Y);
    
    \RAM512X18_QXI[15]\ : RAM512X18
      port map(RADDR8 => \GND\, RADDR7 => \MEM_RADDR[7]\, RADDR6
         => \MEM_RADDR[6]\, RADDR5 => \MEM_RADDR[5]\, RADDR4 => 
        \MEM_RADDR[4]\, RADDR3 => \MEM_RADDR[3]\, RADDR2 => 
        \MEM_RADDR[2]\, RADDR1 => \MEM_RADDR[1]\, RADDR0 => 
        \MEM_RADDR[0]\, WADDR8 => \GND\, WADDR7 => \MEM_WADDR[7]\, 
        WADDR6 => \MEM_WADDR[6]\, WADDR5 => \MEM_WADDR[5]\, 
        WADDR4 => \MEM_WADDR[4]\, WADDR3 => \MEM_WADDR[3]\, 
        WADDR2 => \MEM_WADDR[2]\, WADDR1 => \MEM_WADDR[1]\, 
        WADDR0 => \MEM_WADDR[0]\, WD17 => \GND\, WD16 => DATA(15), 
        WD15 => DATA(14), WD14 => DATA(13), WD13 => DATA(12), 
        WD12 => DATA(11), WD11 => DATA(10), WD10 => DATA(9), WD9
         => DATA(8), WD8 => \GND\, WD7 => DATA(7), WD6 => DATA(6), 
        WD5 => DATA(5), WD4 => DATA(4), WD3 => DATA(3), WD2 => 
        DATA(2), WD1 => DATA(1), WD0 => DATA(0), RW0 => \GND\, 
        RW1 => \VCC\, WW0 => \GND\, WW1 => \VCC\, PIPE => \GND\, 
        REN => MEMRENEG, WEN => MEMWENEG, RCLK => CLK, WCLK => 
        CLK, RESET => RESET, RD17 => OPEN, RD16 => \QXI[15]\, 
        RD15 => \QXI[14]\, RD14 => \QXI[13]\, RD13 => \QXI[12]\, 
        RD12 => \QXI[11]\, RD11 => \QXI[10]\, RD10 => \QXI[9]\, 
        RD9 => \QXI[8]\, RD8 => OPEN, RD7 => \QXI[7]\, RD6 => 
        \QXI[6]\, RD5 => \QXI[5]\, RD4 => \QXI[4]\, RD3 => 
        \QXI[3]\, RD2 => \QXI[2]\, RD1 => \QXI[1]\, RD0 => 
        \QXI[0]\);
    
    WEBUBBLE : INV
      port map(A => WE, Y => WEP);
    
    AND2_3 : AND2
      port map(A => \MEM_RADDR[4]\, B => \GND\, Y => AND2_3_Y);
    
    NAND3A_11 : NAND3A
      port map(A => NOR3A_0_Y, B => OR2A_8_Y, C => NAND3A_3_Y, Y
         => NAND3A_11_Y);
    
    AND2_30 : AND2
      port map(A => \MEM_WADDR[0]\, B => MEMORYWE, Y => AND2_30_Y);
    
    \XOR2_WBINNXTSHIFT[4]\ : XOR2
      port map(A => XOR2_13_Y, B => AO1_26_Y, Y => 
        \WBINNXTSHIFT[4]\);
    
    XNOR2_6 : XNOR2
      port map(A => \RBINNXTSHIFT[1]\, B => \MEM_WADDR[1]\, Y => 
        XNOR2_6_Y);
    
    AND2_14 : AND2
      port map(A => \MEM_WADDR[7]\, B => \GND\, Y => AND2_14_Y);
    
    INV_4 : INV
      port map(A => \RBINNXTSHIFT[3]\, Y => INV_4_Y);
    
    AND2_74 : AND2
      port map(A => AND2_72_Y, B => AND2_47_Y, Y => AND2_74_Y);
    
    XOR2_77 : XOR2
      port map(A => \MEM_WADDR[5]\, B => \GND\, Y => XOR2_77_Y);
    
    AND2_32 : AND2
      port map(A => AND2_53_Y, B => XOR2_1_Y, Y => AND2_32_Y);
    
    OR2A_1 : OR2A
      port map(A => \AEVALCONST[0]\, B => \RDIFF[8]\, Y => 
        OR2A_1_Y);
    
    \XOR2_WBINNXTSHIFT[6]\ : XOR2
      port map(A => XOR2_83_Y, B => AO1_31_Y, Y => 
        \WBINNXTSHIFT[6]\);
    
    \DFN1C0_MEM_RADDR[5]\ : DFN1C0
      port map(D => \RBINNXTSHIFT[5]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_RADDR[5]\);
    
    AND3_8 : AND3
      port map(A => XNOR2_12_Y, B => XNOR2_6_Y, C => XNOR2_14_Y, 
        Y => AND3_8_Y);
    
    OR2A_8 : OR2A
      port map(A => \RDIFF[8]\, B => \AEVALCONST[0]\, Y => 
        OR2A_8_Y);
    
    NAND3A_2 : NAND3A
      port map(A => \AEVALCONST[0]\, B => \RDIFF[1]\, C => 
        OR2A_3_Y, Y => NAND3A_2_Y);
    
    XOR2_46 : XOR2
      port map(A => \WBINNXTSHIFT[6]\, B => INV_12_Y, Y => 
        XOR2_46_Y);
    
    XNOR2_11 : XNOR2
      port map(A => \RDIFF[8]\, B => \AEVALCONST[0]\, Y => 
        XNOR2_11_Y);
    
    AO1_2 : AO1
      port map(A => AND2_72_Y, B => AO1_37_Y, C => AO1_4_Y, Y => 
        AO1_2_Y);
    
    \DFN1C0_MEM_RADDR[8]\ : DFN1C0
      port map(D => \RBINNXTSHIFT[8]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_RADDR[8]\);
    
    \DFN1C0_WGRY[0]\ : DFN1C0
      port map(D => XOR2_37_Y, CLK => CLK, CLR => RESET, Q => 
        \WGRY[0]\);
    
    XOR2_75 : XOR2
      port map(A => \MEM_RADDR[8]\, B => \GND\, Y => XOR2_75_Y);
    
    AND2_26 : AND2
      port map(A => \WBINNXTSHIFT[6]\, B => INV_12_Y, Y => 
        AND2_26_Y);
    
    XOR2_9 : XOR2
      port map(A => \MEM_WADDR[1]\, B => INV_0_Y, Y => XOR2_9_Y);
    
    AND3_5 : AND3
      port map(A => XNOR2_27_Y, B => XNOR2_4_Y, C => XNOR2_9_Y, Y
         => AND3_5_Y);
    
    \XOR2_WDIFF[2]\ : XOR2
      port map(A => XOR2_40_Y, B => OR3_0_Y, Y => \WDIFF[2]\);
    
    XOR2_59 : XOR2
      port map(A => \MEM_WADDR[7]\, B => \GND\, Y => XOR2_59_Y);
    
    INV_12 : INV
      port map(A => \MEM_RADDR[6]\, Y => INV_12_Y);
    
    AND2_23 : AND2
      port map(A => XOR2_63_Y, B => XOR2_3_Y, Y => AND2_23_Y);
    
    XNOR2_4 : XNOR2
      port map(A => \AEVALCONST[0]\, B => \RDIFF[4]\, Y => 
        XNOR2_4_Y);
    
    \DFN1C0_RGRY[8]\ : DFN1C0
      port map(D => XOR2_66_Y, CLK => CLK, CLR => RESET, Q => 
        \RGRY[8]\);
    
    XOR2_5 : XOR2
      port map(A => \WBINNXTSHIFT[3]\, B => INV_7_Y, Y => 
        XOR2_5_Y);
    
    XNOR2_20 : XNOR2
      port map(A => \MEM_RADDR[3]\, B => \WBINNXTSHIFT[3]\, Y => 
        XNOR2_20_Y);
    
    AO1_28 : AO1
      port map(A => XOR2_10_Y, B => AO1_43_Y, C => AND2_3_Y, Y
         => AO1_28_Y);
    
    AND2_19 : AND2
      port map(A => XOR2_72_Y, B => XOR2_69_Y, Y => AND2_19_Y);
    
    AND2_79 : AND2
      port map(A => XNOR2_19_Y, B => XNOR2_21_Y, Y => AND2_79_Y);
    
    \DFN1C0_MEM_RADDR[6]\ : DFN1C0
      port map(D => \RBINNXTSHIFT[6]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_RADDR[6]\);
    
    \DFN1E1C0_Q[0]\ : DFN1E1C0
      port map(D => \QXI[0]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(0));
    
    XOR2_22 : XOR2
      port map(A => \WBINNXTSHIFT[5]\, B => INV_2_Y, Y => 
        XOR2_22_Y);
    
    AO1_1 : AO1
      port map(A => XOR2_35_Y, B => AND2_30_Y, C => AND2_54_Y, Y
         => AO1_1_Y);
    
    XOR2_13 : XOR2
      port map(A => \MEM_WADDR[4]\, B => \GND\, Y => XOR2_13_Y);
    
    INV_6 : INV
      port map(A => \MEM_RADDR[8]\, Y => INV_6_Y);
    
    XNOR2_18 : XNOR2
      port map(A => \MEM_RADDR[1]\, B => \WBINNXTSHIFT[1]\, Y => 
        XNOR2_18_Y);
    
    NAND3A_9 : NAND3A
      port map(A => NOR3A_1_Y, B => OR2A_6_Y, C => NAND3A_0_Y, Y
         => NAND3A_9_Y);
    
    AND2_51 : AND2
      port map(A => AND2_21_Y, B => XOR2_10_Y, Y => AND2_51_Y);
    
    REBUBBLE : INV
      port map(A => RE, Y => REP);
    
    AO1_3 : AO1
      port map(A => AND2_18_Y, B => AO1_40_Y, C => AO1_13_Y, Y
         => AO1_3_Y);
    
    AND2_64 : AND2
      port map(A => AND2_9_Y, B => AND2_23_Y, Y => AND2_64_Y);
    
    AND2_47 : AND2
      port map(A => XOR2_39_Y, B => XOR2_84_Y, Y => AND2_47_Y);
    
    AO1_18 : AO1
      port map(A => XOR2_22_Y, B => AO1_37_Y, C => AND2_83_Y, Y
         => AO1_18_Y);
    
    XOR2_48 : XOR2
      port map(A => \WBINNXTSHIFT[6]\, B => INV_12_Y, Y => 
        XOR2_48_Y);
    
    AO1_47 : AO1
      port map(A => XOR2_3_Y, B => AND2_0_Y, C => AND2_37_Y, Y
         => AO1_47_Y);
    
    \XOR2_RBINNXTSHIFT[3]\ : XOR2
      port map(A => XOR2_44_Y, B => AO1_0_Y, Y => 
        \RBINNXTSHIFT[3]\);
    
    AO1C_0 : AO1C
      port map(A => \RDIFF[4]\, B => \AEVALCONST[0]\, C => 
        \RDIFF[3]\, Y => AO1C_0_Y);
    
    \DFN1C0_MEM_RADDR[7]\ : DFN1C0
      port map(D => \RBINNXTSHIFT[7]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_RADDR[7]\);
    
    AND2_16 : AND2
      port map(A => \WBINNXTSHIFT[7]\, B => INV_13_Y, Y => 
        AND2_16_Y);
    
    \XOR2_RDIFF[8]\ : XOR2
      port map(A => XOR2_79_Y, B => AO1_34_Y, Y => \RDIFF[8]\);
    
    \XOR2_WDIFF[3]\ : XOR2
      port map(A => XOR2_26_Y, B => AO1_20_Y, Y => \WDIFF[3]\);
    
    AND2_76 : AND2
      port map(A => \MEM_WADDR[6]\, B => INV_10_Y, Y => AND2_76_Y);
    
    AO1_38 : AO1
      port map(A => AND3_5_Y, B => NAND3A_8_Y, C => NAND3A_6_Y, Y
         => AO1_38_Y);
    
    OR2A_5 : OR2A
      port map(A => \AEVALCONST[0]\, B => \RDIFF[5]\, Y => 
        OR2A_5_Y);
    
    XOR2_62 : XOR2
      port map(A => \MEM_RADDR[5]\, B => \GND\, Y => XOR2_62_Y);
    
    AND2_13 : AND2
      port map(A => AND2_66_Y, B => XOR2_72_Y, Y => AND2_13_Y);
    
    AND2_73 : AND2
      port map(A => AND2_1_Y, B => XOR2_0_Y, Y => AND2_73_Y);
    
    XOR2_10 : XOR2
      port map(A => \MEM_RADDR[4]\, B => \GND\, Y => XOR2_10_Y);
    
    XNOR2_1 : XNOR2
      port map(A => \MEM_RADDR[0]\, B => \WBINNXTSHIFT[0]\, Y => 
        XNOR2_1_Y);
    
    AND2_58 : AND2
      port map(A => \WBINNXTSHIFT[1]\, B => INV_5_Y, Y => 
        AND2_58_Y);
    
    AND2_55 : AND2
      port map(A => INV_0_Y, B => INV_9_Y, Y => AND2_55_Y);
    
    INV_8 : INV
      port map(A => NOR2A_0_Y, Y => INV_8_Y);
    
    \DFN1C0_RGRY[4]\ : DFN1C0
      port map(D => XOR2_73_Y, CLK => CLK, CLR => RESET, Q => 
        \RGRY[4]\);
    
    INV_14 : INV
      port map(A => \RBINNXTSHIFT[2]\, Y => INV_14_Y);
    
    AND2_69 : AND2
      port map(A => XOR2_36_Y, B => XOR2_80_Y, Y => AND2_69_Y);
    
    \DFN1C0_MEM_WADDR[2]\ : DFN1C0
      port map(D => \WBINNXTSHIFT[2]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_WADDR[2]\);
    
    XOR2_79 : XOR2
      port map(A => \MEM_WADDR[8]\, B => INV_1_Y, Y => XOR2_79_Y);
    
    XOR2_27 : XOR2
      port map(A => \MEM_WADDR[7]\, B => INV_11_Y, Y => XOR2_27_Y);
    
    AND2_MEMORYRE : AND2
      port map(A => NAND2_1_Y, B => REP, Y => MEMORYRE);
    
    \XOR2_WBINNXTSHIFT[3]\ : XOR2
      port map(A => XOR2_60_Y, B => AO1_36_Y, Y => 
        \WBINNXTSHIFT[3]\);
    
    XOR2_7 : XOR2
      port map(A => \MEM_WADDR[2]\, B => INV_14_Y, Y => XOR2_7_Y);
    
    AND2_5 : AND2
      port map(A => \MEM_WADDR[3]\, B => \GND\, Y => AND2_5_Y);
    
    XOR2_56 : XOR2
      port map(A => \WBINNXTSHIFT[8]\, B => \GND\, Y => XOR2_56_Y);
    
    XOR2_14 : XOR2
      port map(A => \RBINNXTSHIFT[0]\, B => \RBINNXTSHIFT[1]\, Y
         => XOR2_14_Y);
    
    AND2_50 : AND2
      port map(A => \WBINNXTSHIFT[1]\, B => INV_8_Y, Y => 
        AND2_50_Y);
    
    XNOR2_3 : XNOR2
      port map(A => \AFVALCONST[1]\, B => \WDIFF[7]\, Y => 
        XNOR2_3_Y);
    
    XOR2_11 : XOR2
      port map(A => \WBINNXTSHIFT[1]\, B => INV_5_Y, Y => 
        XOR2_11_Y);
    
    XNOR2_22 : XNOR2
      port map(A => \MEM_RADDR[2]\, B => \WBINNXTSHIFT[2]\, Y => 
        XNOR2_22_Y);
    
    NAND3A_3 : NAND3A
      port map(A => \AEVALCONST[0]\, B => \RDIFF[7]\, C => 
        OR2A_1_Y, Y => NAND3A_3_Y);
    
    AND2_52 : AND2
      port map(A => XOR2_11_Y, B => XOR2_12_Y, Y => AND2_52_Y);
    
    XOR2_25 : XOR2
      port map(A => \RBINNXTSHIFT[1]\, B => \RBINNXTSHIFT[2]\, Y
         => XOR2_25_Y);
    
    XNOR2_15 : XNOR2
      port map(A => \RBINNXTSHIFT[3]\, B => \MEM_WADDR[3]\, Y => 
        XNOR2_15_Y);
    
    AO1_22 : AO1
      port map(A => XOR2_1_Y, B => AO1_31_Y, C => AND2_63_Y, Y
         => AO1_22_Y);
    
    \DFN1E1C0_Q[11]\ : DFN1E1C0
      port map(D => \QXI[11]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(11));
    
    NOR3A_3 : NOR3A
      port map(A => OR2A_4_Y, B => AO1C_3_Y, C => \WDIFF[3]\, Y
         => NOR3A_3_Y);
    
    AND2_34 : AND2
      port map(A => AND2_8_Y, B => XOR2_15_Y, Y => AND2_34_Y);
    
    AND2_66 : AND2
      port map(A => AND2_82_Y, B => AND2_71_Y, Y => AND2_66_Y);
    
    AO1_41 : AO1
      port map(A => XOR2_2_Y, B => AND2_17_Y, C => AND2_57_Y, Y
         => AO1_41_Y);
    
    AO1_6 : AO1
      port map(A => XOR2_55_Y, B => AND2_31_Y, C => AND2_80_Y, Y
         => AO1_6_Y);
    
    \DFN1E1C0_Q[10]\ : DFN1E1C0
      port map(D => \QXI[10]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(10));
    
    \DFN1C0_MEM_RADDR[3]\ : DFN1C0
      port map(D => \RBINNXTSHIFT[3]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_RADDR[3]\);
    
    XOR2_67 : XOR2
      port map(A => \RBINNXTSHIFT[6]\, B => \RBINNXTSHIFT[7]\, Y
         => XOR2_67_Y);
    
    AND2_63 : AND2
      port map(A => \MEM_WADDR[6]\, B => \GND\, Y => AND2_63_Y);
    
    AND3_2 : AND3
      port map(A => AND2_35_Y, B => AND3_4_Y, C => AND3_3_Y, Y
         => AND3_2_Y);
    
    XNOR2_26 : XNOR2
      port map(A => \RDIFF[6]\, B => \AEVALCONST[0]\, Y => 
        XNOR2_26_Y);
    
    AO1_12 : AO1
      port map(A => XOR2_43_Y, B => AND2_81_Y, C => AND2_43_Y, Y
         => AO1_12_Y);
    
    NOR3A_1 : NOR3A
      port map(A => OR2A_2_Y, B => AO1C_4_Y, C => \WDIFF[6]\, Y
         => NOR3A_1_Y);
    
    XOR2_32 : XOR2
      port map(A => \WBINNXTSHIFT[1]\, B => \WBINNXTSHIFT[2]\, Y
         => XOR2_32_Y);
    
    OR3_0 : OR3
      port map(A => AND2_58_Y, B => AND2_50_Y, C => AND2_7_Y, Y
         => OR3_0_Y);
    
    \XOR2_RDIFF[7]\ : XOR2
      port map(A => XOR2_27_Y, B => AO1_21_Y, Y => \RDIFF[7]\);
    
    \DFN1E1C0_Q[9]\ : DFN1E1C0
      port map(D => \QXI[9]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(9));
    
    AND2_9 : AND2
      port map(A => XOR2_10_Y, B => XOR2_28_Y, Y => AND2_9_Y);
    
    \DFN1E1C0_Q[5]\ : DFN1E1C0
      port map(D => \QXI[5]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(5));
    
    XOR2_65 : XOR2
      port map(A => \WBINNXTSHIFT[3]\, B => \WBINNXTSHIFT[4]\, Y
         => XOR2_65_Y);
    
    NOR3A_0 : NOR3A
      port map(A => OR2A_1_Y, B => AO1C_5_Y, C => \AEVALCONST[0]\, 
        Y => NOR3A_0_Y);
    
    DFN1C0_AFULL : DFN1C0
      port map(D => OR2_0_Y, CLK => CLK, CLR => RESET, Q => AFULL);
    
    XOR2_58 : XOR2
      port map(A => \MEM_WADDR[6]\, B => INV_10_Y, Y => XOR2_58_Y);
    
    \XOR2_RDIFF[2]\ : XOR2
      port map(A => XOR2_23_Y, B => OR3_1_Y, Y => \RDIFF[2]\);
    
    AO1_32 : AO1
      port map(A => AND2_65_Y, B => AO1_26_Y, C => AO1_46_Y, Y
         => AO1_32_Y);
    
    XOR2_43 : XOR2
      port map(A => \MEM_WADDR[4]\, B => INV_17_Y, Y => XOR2_43_Y);
    
    INV_2 : INV
      port map(A => \MEM_RADDR[5]\, Y => INV_2_Y);
    
    AO1_9 : AO1
      port map(A => XOR2_69_Y, B => AND2_60_Y, C => AND2_11_Y, Y
         => AO1_9_Y);
    
    DFN1C0_DVLDX : DFN1C0
      port map(D => DVLDI, CLK => CLK, CLR => RESET, Q => DVLDX);
    
    AND2_39 : AND2
      port map(A => AND2_52_Y, B => AND2_33_Y, Y => AND2_39_Y);
    
    NAND2_0 : NAND2
      port map(A => \FULL\, B => \VCC\, Y => NAND2_0_Y);
    
    NAND3A_1 : NAND3A
      port map(A => \WDIFF[4]\, B => \AFVALCONST[1]\, C => 
        OR2A_4_Y, Y => NAND3A_1_Y);
    
    \DFN1C0_RGRY[6]\ : DFN1C0
      port map(D => XOR2_67_Y, CLK => CLK, CLR => RESET, Q => 
        \RGRY[6]\);
    
    XOR2_76 : XOR2
      port map(A => \MEM_WADDR[3]\, B => INV_4_Y, Y => XOR2_76_Y);
    
    AND2_27 : AND2
      port map(A => XOR2_8_Y, B => XOR2_2_Y, Y => AND2_27_Y);
    
    DFN1C0_DVLDI : DFN1C0
      port map(D => AND2A_0_Y, CLK => CLK, CLR => RESET, Q => 
        DVLDI);
    
    XNOR2_10 : XNOR2
      port map(A => \RBINNXTSHIFT[5]\, B => \MEM_WADDR[5]\, Y => 
        XNOR2_10_Y);
    
    \DFN1E1C0_Q[12]\ : DFN1E1C0
      port map(D => \QXI[12]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(12));
    
    XOR2_83 : XOR2
      port map(A => \MEM_WADDR[6]\, B => \GND\, Y => XOR2_83_Y);
    
    XNOR2_27 : XNOR2
      port map(A => \AEVALCONST[0]\, B => \RDIFF[3]\, Y => 
        XNOR2_27_Y);
    
    AND2_MEMORYWE : AND2
      port map(A => NAND2_0_Y, B => WEP, Y => MEMORYWE);
    
    AO1_20 : AO1
      port map(A => XOR2_12_Y, B => OR3_0_Y, C => AND2_85_Y, Y
         => AO1_20_Y);
    
    INV_13 : INV
      port map(A => \MEM_RADDR[7]\, Y => INV_13_Y);
    
    \DFN1C0_WGRY[2]\ : DFN1C0
      port map(D => XOR2_19_Y, CLK => CLK, CLR => RESET, Q => 
        \WGRY[2]\);
    
    AO1_0 : AO1
      port map(A => XOR2_8_Y, B => AO1_24_Y, C => AND2_17_Y, Y
         => AO1_0_Y);
    
    XOR2_29 : XOR2
      port map(A => \MEM_WADDR[4]\, B => INV_17_Y, Y => XOR2_29_Y);
    
    AO1_45 : AO1
      port map(A => XOR2_63_Y, B => AO1_44_Y, C => AND2_0_Y, Y
         => AO1_45_Y);
    
    XOR2_40 : XOR2
      port map(A => \WBINNXTSHIFT[2]\, B => INV_15_Y, Y => 
        XOR2_40_Y);
    
    XOR2_2 : XOR2
      port map(A => \MEM_RADDR[3]\, B => \GND\, Y => XOR2_2_Y);
    
    \DFN1C0_RGRY[5]\ : DFN1C0
      port map(D => XOR2_78_Y, CLK => CLK, CLR => RESET, Q => 
        \RGRY[5]\);
    
    \XNOR2_WDIFF[1]\ : XNOR2
      port map(A => XOR2_16_Y, B => NOR2A_0_Y, Y => \WDIFF[1]\);
    
    AND2A_0 : AND2A
      port map(A => \EMPTY\, B => REP, Y => AND2A_0_Y);
    
    XOR2_37 : XOR2
      port map(A => \WBINNXTSHIFT[0]\, B => \WBINNXTSHIFT[1]\, Y
         => XOR2_37_Y);
    
    AND2_36 : AND2
      port map(A => AND2_39_Y, B => XOR2_22_Y, Y => AND2_36_Y);
    
    AO1_26 : AO1
      port map(A => AND2_71_Y, B => AO1_1_Y, C => AO1_30_Y, Y => 
        AO1_26_Y);
    
    \DFN1C0_RGRY[7]\ : DFN1C0
      port map(D => XOR2_20_Y, CLK => CLK, CLR => RESET, Q => 
        \RGRY[7]\);
    
    AND3_9 : AND3
      port map(A => AND2_79_Y, B => AND3_8_Y, C => AND3_7_Y, Y
         => AND3_9_Y);
    
    \XOR2_RBINNXTSHIFT[5]\ : XOR2
      port map(A => XOR2_62_Y, B => AO1_28_Y, Y => 
        \RBINNXTSHIFT[5]\);
    
    AO1_23 : AO1
      port map(A => XOR2_38_Y, B => AND2_44_Y, C => AND2_76_Y, Y
         => AO1_23_Y);
    
    AOI1_0 : AOI1
      port map(A => AND3_0_Y, B => AO1_38_Y, C => NAND3A_11_Y, Y
         => AOI1_0_Y);
    
    AND2_33 : AND2
      port map(A => XOR2_5_Y, B => XOR2_55_Y, Y => AND2_33_Y);
    
    XOR2_44 : XOR2
      port map(A => \MEM_RADDR[3]\, B => \GND\, Y => XOR2_44_Y);
    
    AO1_10 : AO1
      port map(A => XOR2_59_Y, B => AND2_63_Y, C => AND2_14_Y, Y
         => AO1_10_Y);
    
    XOR2_41 : XOR2
      port map(A => \MEM_RADDR[4]\, B => \GND\, Y => XOR2_41_Y);
    
    XOR2_35 : XOR2
      port map(A => \MEM_WADDR[1]\, B => \GND\, Y => XOR2_35_Y);
    
    INV_15 : INV
      port map(A => \MEM_RADDR[2]\, Y => INV_15_Y);
    
    XNOR2_24 : XNOR2
      port map(A => \RBINNXTSHIFT[4]\, B => \MEM_WADDR[4]\, Y => 
        XNOR2_24_Y);
    
    XOR2_80 : XOR2
      port map(A => \MEM_WADDR[8]\, B => INV_1_Y, Y => XOR2_80_Y);
    
    \DFN1C0_WGRY[1]\ : DFN1C0
      port map(D => XOR2_32_Y, CLK => CLK, CLR => RESET, Q => 
        \WGRY[1]\);
    
    DFN1P0_EMPTY : DFN1P0
      port map(D => EMPTYINT, CLK => CLK, PRE => RESET, Q => 
        \EMPTY\);
    
    \DFN1E1C0_Q[3]\ : DFN1E1C0
      port map(D => \QXI[3]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(3));
    
    XOR2_78 : XOR2
      port map(A => \RBINNXTSHIFT[5]\, B => \RBINNXTSHIFT[6]\, Y
         => XOR2_78_Y);
    
    NOR2A_1 : NOR2A
      port map(A => \RBINNXTSHIFT[0]\, B => \MEM_WADDR[0]\, Y => 
        NOR2A_1_Y);
    
    AO1_30 : AO1
      port map(A => XOR2_74_Y, B => AND2_10_Y, C => AND2_5_Y, Y
         => AO1_30_Y);
    
    AND2_41 : AND2
      port map(A => AND2_39_Y, B => AND2_74_Y, Y => AND2_41_Y);
    
    \XOR2_RBINNXTSHIFT[7]\ : XOR2
      port map(A => XOR2_24_Y, B => AO1_45_Y, Y => 
        \RBINNXTSHIFT[7]\);
    
    AND2_0 : AND2
      port map(A => \MEM_RADDR[6]\, B => \GND\, Y => AND2_0_Y);
    
    XOR2_69 : XOR2
      port map(A => \MEM_WADDR[5]\, B => \GND\, Y => XOR2_69_Y);
    
    AO1_16 : AO1
      port map(A => XOR2_28_Y, B => AND2_3_Y, C => AND2_15_Y, Y
         => AO1_16_Y);
    
    AND2_17 : AND2
      port map(A => \MEM_RADDR[2]\, B => \GND\, Y => AND2_17_Y);
    
    NOR2A_0 : NOR2A
      port map(A => \MEM_RADDR[0]\, B => \WBINNXTSHIFT[0]\, Y => 
        NOR2A_0_Y);
    
    AO1_29 : AO1
      port map(A => AND2_47_Y, B => AO1_4_Y, C => AO1_19_Y, Y => 
        AO1_29_Y);
    
    XOR2_6 : XOR2
      port map(A => \MEM_WADDR[1]\, B => INV_0_Y, Y => XOR2_6_Y);
    
    AND2_77 : AND2
      port map(A => \MEM_RADDR[0]\, B => MEMORYRE, Y => AND2_77_Y);
    
    AND2_54 : AND2
      port map(A => \MEM_WADDR[1]\, B => \GND\, Y => AND2_54_Y);
    
    AO1_13 : AO1
      port map(A => AND2_69_Y, B => AO1_23_Y, C => AO1_15_Y, Y
         => AO1_13_Y);
    
    \DFN1E1C0_Q[13]\ : DFN1E1C0
      port map(D => \QXI[13]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(13));
    
    XOR2_84 : XOR2
      port map(A => \WBINNXTSHIFT[8]\, B => INV_6_Y, Y => 
        XOR2_84_Y);
    
    \DFN1C0_MEM_WADDR[6]\ : DFN1C0
      port map(D => \WBINNXTSHIFT[6]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_WADDR[6]\);
    
    \XOR2_WBINNXTSHIFT[5]\ : XOR2
      port map(A => XOR2_77_Y, B => AO1_11_Y, Y => 
        \WBINNXTSHIFT[5]\);
    
    XOR2_81 : XOR2
      port map(A => \MEM_RADDR[2]\, B => \GND\, Y => XOR2_81_Y);
    
    \XOR2_WDIFF[7]\ : XOR2
      port map(A => XOR2_52_Y, B => AO1_2_Y, Y => \WDIFF[7]\);
    
    \XOR2_RDIFF[6]\ : XOR2
      port map(A => XOR2_58_Y, B => AO1_7_Y, Y => \RDIFF[6]\);
    
    AO1_36 : AO1
      port map(A => XOR2_18_Y, B => AO1_1_Y, C => AND2_10_Y, Y
         => AO1_36_Y);
    
    XOR2_53 : XOR2
      port map(A => \RBINNXTSHIFT[3]\, B => \RBINNXTSHIFT[4]\, Y
         => XOR2_53_Y);
    
    XNOR2_23 : XNOR2
      port map(A => \RBINNXTSHIFT[8]\, B => \MEM_WADDR[8]\, Y => 
        XNOR2_23_Y);
    
    AND2_81 : AND2
      port map(A => \MEM_WADDR[3]\, B => INV_4_Y, Y => AND2_81_Y);
    
    AO1_33 : AO1
      port map(A => XOR2_5_Y, B => AO1_20_Y, C => AND2_31_Y, Y
         => AO1_33_Y);
    
    AO1_44 : AO1
      port map(A => AND2_9_Y, B => AO1_43_Y, C => AO1_16_Y, Y => 
        AO1_44_Y);
    
    OR2A_0 : OR2A
      port map(A => \RDIFF[5]\, B => \AEVALCONST[0]\, Y => 
        OR2A_0_Y);
    
    OR2A_10 : OR2A
      port map(A => \RDIFF[2]\, B => \AEVALCONST[2]\, Y => 
        OR2A_10_Y);
    
    XNOR2_12 : XNOR2
      port map(A => \RBINNXTSHIFT[0]\, B => \MEM_WADDR[0]\, Y => 
        XNOR2_12_Y);
    
    XNOR2_7 : XNOR2
      port map(A => \MEM_RADDR[7]\, B => \WBINNXTSHIFT[7]\, Y => 
        XNOR2_7_Y);
    
    XOR2_12 : XOR2
      port map(A => \WBINNXTSHIFT[2]\, B => INV_15_Y, Y => 
        XOR2_12_Y);
    
    AND2_48 : AND2
      port map(A => AND2_62_Y, B => XOR2_39_Y, Y => AND2_48_Y);
    
    AND2_45 : AND2
      port map(A => XOR2_68_Y, B => XOR2_4_Y, Y => AND2_45_Y);
    
    AO1_19 : AO1
      port map(A => XOR2_84_Y, B => AND2_16_Y, C => AND2_78_Y, Y
         => AO1_19_Y);
    
    \XOR2_WBINNXTSHIFT[7]\ : XOR2
      port map(A => XOR2_49_Y, B => AO1_22_Y, Y => 
        \WBINNXTSHIFT[7]\);
    
    XOR2_26 : XOR2
      port map(A => \WBINNXTSHIFT[3]\, B => INV_7_Y, Y => 
        XOR2_26_Y);
    
    AND2_59 : AND2
      port map(A => AND2_45_Y, B => XOR2_8_Y, Y => AND2_59_Y);
    
    \XOR2_RDIFF[4]\ : XOR2
      port map(A => XOR2_29_Y, B => AO1_39_Y, Y => \RDIFF[4]\);
    
    AND2_4 : AND2
      port map(A => AND2_8_Y, B => AND2_18_Y, Y => AND2_4_Y);
    
    AND2_FULLINT : AND2
      port map(A => AND3_2_Y, B => XOR2_50_Y, Y => FULLINT);
    
    AO1_39 : AO1
      port map(A => XOR2_0_Y, B => AO1_5_Y, C => AND2_81_Y, Y => 
        AO1_39_Y);
    
    \XOR2_WDIFF[6]\ : XOR2
      port map(A => XOR2_48_Y, B => AO1_18_Y, Y => \WDIFF[6]\);
    
    AND2_40 : AND2
      port map(A => \MEM_RADDR[1]\, B => \GND\, Y => AND2_40_Y);
    
    OR2A_11 : OR2A
      port map(A => \AFVALCONST[1]\, B => \WDIFF[5]\, Y => 
        OR2A_11_Y);
    
    AND2_85 : AND2
      port map(A => \WBINNXTSHIFT[2]\, B => INV_15_Y, Y => 
        AND2_85_Y);
    
    XOR2_50 : XOR2
      port map(A => \MEM_RADDR[8]\, B => \WBINNXTSHIFT[8]\, Y => 
        XOR2_50_Y);
    
    AND2_42 : AND2
      port map(A => \MEM_WADDR[8]\, B => INV_1_Y, Y => AND2_42_Y);
    
    \DFN1E1C0_Q[2]\ : DFN1E1C0
      port map(D => \QXI[2]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(2));
    
    \DFN1C0_WGRY[8]\ : DFN1C0
      port map(D => XOR2_56_Y, CLK => CLK, CLR => RESET, Q => 
        \WGRY[8]\);
    
    XNOR2_5 : XNOR2
      port map(A => \MEM_RADDR[5]\, B => \WBINNXTSHIFT[5]\, Y => 
        XNOR2_5_Y);
    
    AO1_5 : AO1
      port map(A => XOR2_7_Y, B => OR3_1_Y, C => AND2_46_Y, Y => 
        AO1_5_Y);
    
    AND2_67 : AND2
      port map(A => \MEM_WADDR[8]\, B => \GND\, Y => AND2_67_Y);
    
    XNOR2_16 : XNOR2
      port map(A => \MEM_RADDR[6]\, B => \WBINNXTSHIFT[6]\, Y => 
        XNOR2_16_Y);
    
    \XOR2_WDIFF[4]\ : XOR2
      port map(A => XOR2_31_Y, B => AO1_33_Y, Y => \WDIFF[4]\);
    
    \DFN1C0_RGRY[3]\ : DFN1C0
      port map(D => XOR2_53_Y, CLK => CLK, CLR => RESET, Q => 
        \RGRY[3]\);
    
    INV_17 : INV
      port map(A => \RBINNXTSHIFT[4]\, Y => INV_17_Y);
    
    XOR2_39 : XOR2
      port map(A => \WBINNXTSHIFT[7]\, B => INV_13_Y, Y => 
        XOR2_39_Y);
    
    AND2_8 : AND2
      port map(A => AND2_1_Y, B => AND2_75_Y, Y => AND2_8_Y);
    
    AND2_80 : AND2
      port map(A => \WBINNXTSHIFT[4]\, B => INV_3_Y, Y => 
        AND2_80_Y);
    
    \XOR2_WDIFF[8]\ : XOR2
      port map(A => XOR2_34_Y, B => AO1_35_Y, Y => \WDIFF[8]\);
    
    XOR2_3 : XOR2
      port map(A => \MEM_RADDR[7]\, B => \GND\, Y => XOR2_3_Y);
    
    XOR2_54 : XOR2
      port map(A => \WBINNXTSHIFT[7]\, B => \WBINNXTSHIFT[8]\, Y
         => XOR2_54_Y);
    
    XOR2_51 : XOR2
      port map(A => \RBINNXTSHIFT[2]\, B => \RBINNXTSHIFT[3]\, Y
         => XOR2_51_Y);
    
    AO1_27 : AO1
      port map(A => AND3_6_Y, B => NAND3A_10_Y, C => NAND3A_5_Y, 
        Y => AO1_27_Y);
    
    AND2_82 : AND2
      port map(A => XOR2_42_Y, B => XOR2_35_Y, Y => AND2_82_Y);
    
    XOR2_66 : XOR2
      port map(A => \RBINNXTSHIFT[8]\, B => \GND\, Y => XOR2_66_Y);
    
    AND2_56 : AND2
      port map(A => XOR2_15_Y, B => XOR2_38_Y, Y => AND2_56_Y);
    
    INV_10 : INV
      port map(A => \RBINNXTSHIFT[6]\, Y => INV_10_Y);
    
    \DFN1C0_MEM_WADDR[1]\ : DFN1C0
      port map(D => \WBINNXTSHIFT[1]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_WADDR[1]\);
    
    \XOR2_RBINNXTSHIFT[1]\ : XOR2
      port map(A => XOR2_61_Y, B => AND2_77_Y, Y => 
        \RBINNXTSHIFT[1]\);
    
    INV_16 : INV
      port map(A => \RBINNXTSHIFT[5]\, Y => INV_16_Y);
    
    XOR2_17 : XOR2
      port map(A => \MEM_RADDR[8]\, B => \GND\, Y => XOR2_17_Y);
    
    XOR2_73 : XOR2
      port map(A => \RBINNXTSHIFT[4]\, B => \RBINNXTSHIFT[5]\, Y
         => XOR2_73_Y);
    
    AND2_53 : AND2
      port map(A => AND2_66_Y, B => AND2_19_Y, Y => AND2_53_Y);
    
    AND3_7 : AND3
      port map(A => XNOR2_15_Y, B => XNOR2_24_Y, C => XNOR2_10_Y, 
        Y => AND3_7_Y);
    
    \DFN1E1C0_Q[15]\ : DFN1E1C0
      port map(D => \QXI[15]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(15));
    
    XOR2_28 : XOR2
      port map(A => \MEM_RADDR[5]\, B => \GND\, Y => XOR2_28_Y);
    
    INV_9 : INV
      port map(A => NOR2A_1_Y, Y => INV_9_Y);
    
    \DFN1E1C0_Q[14]\ : DFN1E1C0
      port map(D => \QXI[14]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(14));
    
    \DFN1C0_MEM_WADDR[5]\ : DFN1C0
      port map(D => \WBINNXTSHIFT[5]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_WADDR[5]\);
    
    XOR2_15 : XOR2
      port map(A => \MEM_WADDR[5]\, B => INV_16_Y, Y => XOR2_15_Y);
    
    \DFN1C0_MEM_RADDR[0]\ : DFN1C0
      port map(D => \RBINNXTSHIFT[0]\, CLK => CLK, CLR => RESET, 
        Q => \MEM_RADDR[0]\);
    
    \XOR2_RDIFF[5]\ : XOR2
      port map(A => XOR2_45_Y, B => AO1_40_Y, Y => \RDIFF[5]\);
    
    AO1_17 : AO1
      port map(A => XOR2_21_Y, B => AO1_32_Y, C => AND2_67_Y, Y
         => AO1_17_Y);
    
    XNOR2_17 : XNOR2
      port map(A => \AFVALCONST[0]\, B => \WDIFF[8]\, Y => 
        XNOR2_17_Y);
    
    NAND3A_4 : NAND3A
      port map(A => \WDIFF[1]\, B => \AFVALCONST[1]\, C => 
        OR2A_9_Y, Y => NAND3A_4_Y);
    
    \DFN1E1C0_Q[8]\ : DFN1E1C0
      port map(D => \QXI[8]\, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(8));
    
    AND3_4 : AND3
      port map(A => XNOR2_1_Y, B => XNOR2_18_Y, C => XNOR2_22_Y, 
        Y => AND3_4_Y);
    
    \DFN1C0_RGRY[0]\ : DFN1C0
      port map(D => XOR2_14_Y, CLK => CLK, CLR => RESET, Q => 
        \RGRY[0]\);
    
    \XOR2_WBINNXTSHIFT[1]\ : XOR2
      port map(A => XOR2_71_Y, B => AND2_30_Y, Y => 
        \WBINNXTSHIFT[1]\);
    
    AND2_21 : AND2
      port map(A => AND2_45_Y, B => AND2_27_Y, Y => AND2_21_Y);
    
    AO1_37 : AO1
      port map(A => AND2_33_Y, B => AO1_20_Y, C => AO1_6_Y, Y => 
        AO1_37_Y);
    
    \DFN1C0_WGRY[4]\ : DFN1C0
      port map(D => XOR2_57_Y, CLK => CLK, CLR => RESET, Q => 
        \WGRY[4]\);
    
    OR2A_9 : OR2A
      port map(A => \WDIFF[2]\, B => \AFVALCONST[0]\, Y => 
        OR2A_9_Y);
    
    XOR2_0 : XOR2
      port map(A => \MEM_WADDR[3]\, B => INV_4_Y, Y => XOR2_0_Y);
    
    XOR2_70 : XOR2
      port map(A => \MEM_WADDR[8]\, B => \GND\, Y => XOR2_70_Y);
    
    NAND2_1 : NAND2
      port map(A => \EMPTY\, B => \VCC\, Y => NAND2_1_Y);
    
    AO1_4 : AO1
      port map(A => XOR2_46_Y, B => AND2_83_Y, C => AND2_26_Y, Y
         => AO1_4_Y);
    
    NAND3A_5 : NAND3A
      port map(A => NOR3A_3_Y, B => OR2A_11_Y, C => NAND3A_1_Y, Y
         => NAND3A_5_Y);
    
    XOR2_68 : XOR2
      port map(A => \MEM_RADDR[0]\, B => MEMORYRE, Y => XOR2_68_Y);
    
    AND2_37 : AND2
      port map(A => \MEM_RADDR[7]\, B => \GND\, Y => AND2_37_Y);
    
    XNOR2_14 : XNOR2
      port map(A => \RBINNXTSHIFT[2]\, B => \MEM_WADDR[2]\, Y => 
        XNOR2_14_Y);
    
    XOR2_42 : XOR2
      port map(A => \MEM_WADDR[0]\, B => MEMORYWE, Y => XOR2_42_Y);
    
    \XOR2_RBINNXTSHIFT[2]\ : XOR2
      port map(A => XOR2_81_Y, B => AO1_24_Y, Y => 
        \RBINNXTSHIFT[2]\);
    
    NAND3A_8 : NAND3A
      port map(A => NOR3A_5_Y, B => OR2A_10_Y, C => NAND3A_2_Y, Y
         => NAND3A_8_Y);
    
    AO1_21 : AO1
      port map(A => AND2_56_Y, B => AO1_40_Y, C => AO1_23_Y, Y
         => AO1_21_Y);
    
    XOR2_36 : XOR2
      port map(A => \MEM_WADDR[7]\, B => INV_11_Y, Y => XOR2_36_Y);
    
    XOR2_74 : XOR2
      port map(A => \MEM_WADDR[3]\, B => \GND\, Y => XOR2_74_Y);
    
    XNOR2_8 : XNOR2
      port map(A => \WDIFF[5]\, B => \AFVALCONST[1]\, Y => 
        XNOR2_8_Y);
    
    XOR2_71 : XOR2
      port map(A => \MEM_WADDR[1]\, B => \GND\, Y => XOR2_71_Y);
    
    AND2_28 : AND2
      port map(A => AND2_68_Y, B => XOR2_21_Y, Y => AND2_28_Y);
    
    AND2_25 : AND2
      port map(A => \MEM_RADDR[8]\, B => \GND\, Y => AND2_25_Y);
    
    NAND3A_10 : NAND3A
      port map(A => NOR3A_4_Y, B => OR2A_7_Y, C => NAND3A_4_Y, Y
         => NAND3A_10_Y);
    
    AO1C_2 : AO1C
      port map(A => \AFVALCONST[1]\, B => \WDIFF[1]\, C => 
        \AFVALCONST[0]\, Y => AO1C_2_Y);
    
    GND_power_inst1 : GND
      port map( Y => GND_power_net1);

    VCC_power_inst1 : VCC
      port map( Y => VCC_power_net1);


end DEF_ARCH; 

-- _Disclaimer: Please leave the following comments in the file, they are for internal purposes only._


-- _GEN_File_Contents_

-- Version:10.0.9.37
-- ACTGENU_CALL:1
-- BATCH:T
-- FAM:PA3SOC2
-- OUTFORMAT:VHDL
-- LPMTYPE:LPM_SOFTFIFO
-- LPM_HINT:MEMFF
-- INSERT_PAD:NO
-- INSERT_IOREG:NO
-- GEN_BHV_VHDL_VAL:F
-- GEN_BHV_VERILOG_VAL:F
-- MGNTIMER:F
-- MGNCMPL:T
-- DESDIR:F:/A2F_AC381/A2F200/VHDL/MultichannelFFT/smartgen\fifo256x16
-- GEN_BEHV_MODULE:F
-- SMARTGEN_DIE:IP6X5M2
-- SMARTGEN_PACKAGE:fg484
-- AGENIII_IS_SUBPROJECT_LIBERO:T
-- WWIDTH:16
-- WDEPTH:256
-- RWIDTH:16
-- RDEPTH:256
-- CLKS:1
-- CLOCK_PN:CLK
-- WCLK_EDGE:RISE
-- ACLR_PN:RESET
-- RESET_POLARITY:0
-- INIT_RAM:F
-- WE_POLARITY:0
-- RE_POLARITY:0
-- FF_PN:FULL
-- AF_PN:AFULL
-- WACK_PN:WACK
-- OVRFLOW_PN:OVERFLOW
-- WRCNT_PN:WRCNT
-- WE_PN:WE
-- EF_PN:EMPTY
-- AE_PN:AEMPTY
-- DVLD_PN:DVLD
-- UDRFLOW_PN:UNDERFLOW
-- RDCNT_PN:RDCNT
-- RE_PN:RE
-- CONTROLLERONLY:F
-- FSTOP:YES
-- ESTOP:YES
-- WRITEACK:NO
-- OVERFLOW:NO
-- WRCOUNT:NO
-- DATAVALID:NO
-- UNDERFLOW:NO
-- RDCOUNT:NO
-- AF_PORT_PN:AFVAL
-- AE_PORT_PN:AEVAL
-- AFFLAG:STATIC
-- AEFLAG:STATIC
-- AFVAL:250
-- AEVAL:4
-- DATA_IN_PN:DATA
-- DATA_OUT_PN:Q
-- CASCADE:0

-- _End_Comments_

