-- Version: 10.0 10.0.9.37

library ieee;
use ieee.std_logic_1164.all;
library proasic3;
use proasic3.all;

entity actram is

    port( DI     : in    std_logic_vector(15 downto 0);
          DO     : out   std_logic_vector(15 downto 0);
          WRB    : in    std_logic;
          RDB    : in    std_logic;
          WADDR  : in    std_logic_vector(6 downto 0);
          RADDR  : in    std_logic_vector(6 downto 0);
          WCLOCK : in    std_logic;
          RCLOCK : in    std_logic
        );

end actram;

architecture DEF_ARCH of actram is 

  component RAM512X18
    generic (MEMORYFILE:string := "");

    port( RADDR8 : in    std_logic := 'U';
          RADDR7 : in    std_logic := 'U';
          RADDR6 : in    std_logic := 'U';
          RADDR5 : in    std_logic := 'U';
          RADDR4 : in    std_logic := 'U';
          RADDR3 : in    std_logic := 'U';
          RADDR2 : in    std_logic := 'U';
          RADDR1 : in    std_logic := 'U';
          RADDR0 : in    std_logic := 'U';
          WADDR8 : in    std_logic := 'U';
          WADDR7 : in    std_logic := 'U';
          WADDR6 : in    std_logic := 'U';
          WADDR5 : in    std_logic := 'U';
          WADDR4 : in    std_logic := 'U';
          WADDR3 : in    std_logic := 'U';
          WADDR2 : in    std_logic := 'U';
          WADDR1 : in    std_logic := 'U';
          WADDR0 : in    std_logic := 'U';
          WD17   : in    std_logic := 'U';
          WD16   : in    std_logic := 'U';
          WD15   : in    std_logic := 'U';
          WD14   : in    std_logic := 'U';
          WD13   : in    std_logic := 'U';
          WD12   : in    std_logic := 'U';
          WD11   : in    std_logic := 'U';
          WD10   : in    std_logic := 'U';
          WD9    : in    std_logic := 'U';
          WD8    : in    std_logic := 'U';
          WD7    : in    std_logic := 'U';
          WD6    : in    std_logic := 'U';
          WD5    : in    std_logic := 'U';
          WD4    : in    std_logic := 'U';
          WD3    : in    std_logic := 'U';
          WD2    : in    std_logic := 'U';
          WD1    : in    std_logic := 'U';
          WD0    : in    std_logic := 'U';
          RW0    : in    std_logic := 'U';
          RW1    : in    std_logic := 'U';
          WW0    : in    std_logic := 'U';
          WW1    : in    std_logic := 'U';
          PIPE   : in    std_logic := 'U';
          REN    : in    std_logic := 'U';
          WEN    : in    std_logic := 'U';
          RCLK   : in    std_logic := 'U';
          WCLK   : in    std_logic := 'U';
          RESET  : in    std_logic := 'U';
          RD17   : out   std_logic;
          RD16   : out   std_logic;
          RD15   : out   std_logic;
          RD14   : out   std_logic;
          RD13   : out   std_logic;
          RD12   : out   std_logic;
          RD11   : out   std_logic;
          RD10   : out   std_logic;
          RD9    : out   std_logic;
          RD8    : out   std_logic;
          RD7    : out   std_logic;
          RD6    : out   std_logic;
          RD5    : out   std_logic;
          RD4    : out   std_logic;
          RD3    : out   std_logic;
          RD2    : out   std_logic;
          RD1    : out   std_logic;
          RD0    : out   std_logic
        );
  end component;

  component GND
    port(Y : out std_logic); 
  end component;

  component VCC
    port(Y : out std_logic); 
  end component;

    signal \VCC\, \GND\ : std_logic;
    signal GND_power_net1 : std_logic;
    signal VCC_power_net1 : std_logic;

begin 

    \GND\ <= GND_power_net1;
    \VCC\ <= VCC_power_net1;

    actram_R0C0 : RAM512X18
      port map(RADDR8 => \GND\, RADDR7 => \GND\, RADDR6 => 
        RADDR(6), RADDR5 => RADDR(5), RADDR4 => RADDR(4), RADDR3
         => RADDR(3), RADDR2 => RADDR(2), RADDR1 => RADDR(1), 
        RADDR0 => RADDR(0), WADDR8 => \GND\, WADDR7 => \GND\, 
        WADDR6 => WADDR(6), WADDR5 => WADDR(5), WADDR4 => 
        WADDR(4), WADDR3 => WADDR(3), WADDR2 => WADDR(2), WADDR1
         => WADDR(1), WADDR0 => WADDR(0), WD17 => \GND\, WD16 => 
        DI(15), WD15 => DI(14), WD14 => DI(13), WD13 => DI(12), 
        WD12 => DI(11), WD11 => DI(10), WD10 => DI(9), WD9 => 
        DI(8), WD8 => \GND\, WD7 => DI(7), WD6 => DI(6), WD5 => 
        DI(5), WD4 => DI(4), WD3 => DI(3), WD2 => DI(2), WD1 => 
        DI(1), WD0 => DI(0), RW0 => \GND\, RW1 => \VCC\, WW0 => 
        \GND\, WW1 => \VCC\, PIPE => \VCC\, REN => RDB, WEN => 
        WRB, RCLK => RCLOCK, WCLK => WCLOCK, RESET => \VCC\, RD17
         => OPEN, RD16 => DO(15), RD15 => DO(14), RD14 => DO(13), 
        RD13 => DO(12), RD12 => DO(11), RD11 => DO(10), RD10 => 
        DO(9), RD9 => DO(8), RD8 => OPEN, RD7 => DO(7), RD6 => 
        DO(6), RD5 => DO(5), RD4 => DO(4), RD3 => DO(3), RD2 => 
        DO(2), RD1 => DO(1), RD0 => DO(0));
    
    GND_power_inst1 : GND
      port map( Y => GND_power_net1);

    VCC_power_inst1 : VCC
      port map( Y => VCC_power_net1);


end DEF_ARCH; 
