Timing Report Min Delay Analysis

SmartTime Version v10.1 SP1
Actel Corporation - Actel Designer Software Release v10.1 SP1 (Version 10.1.1.6)
Copyright (c) 1989-2012
Date: Fri Nov 23 09:18:37 2012


Design: MultichannelFFT
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                9.359
Frequency (MHz):            106.849
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                21.208
Frequency (MHz):            47.152
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.206
External Hold (ns):         4.012
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MultichannelFFT_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  3.416
  Slack (ns):                  2.321
  Arrival (ns):                6.365
  Required (ns):               4.044
  Hold (ns):                   1.095

Path 2
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[24]
  Delay (ns):                  4.016
  Slack (ns):                  2.690
  Arrival (ns):                6.965
  Required (ns):               4.275
  Hold (ns):                   1.326

Path 3
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
  Delay (ns):                  4.078
  Slack (ns):                  2.744
  Arrival (ns):                7.027
  Required (ns):               4.283
  Hold (ns):                   1.334

Path 4
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[23]
  Delay (ns):                  4.077
  Slack (ns):                  2.751
  Arrival (ns):                7.026
  Required (ns):               4.275
  Hold (ns):                   1.326

Path 5
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[16]
  Delay (ns):                  4.086
  Slack (ns):                  2.757
  Arrival (ns):                7.035
  Required (ns):               4.278
  Hold (ns):                   1.329


Expanded Path 1
  From: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  data arrival time                              6.365
  data required time                         -   4.044
  slack                                          2.321
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.282          cell: ADLIB:MSS_APB_IP
  4.231                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPWRITE (r)
               +     0.061          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/MSSPWRITEINT_NET
  4.292                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_42:PIN3INT (r)
               +     0.040          cell: ADLIB:MSS_IF
  4.332                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_42:PIN3 (r)
               +     0.711          net: CoreAPB3_0_APBmslave0_PWRITE
  5.043                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int_RNIT1EF1:S (r)
               +     0.156          cell: ADLIB:MX2
  5.199                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int_RNIT1EF1:Y (r)
               +     0.144          net: CoreAPB3_0_APBmslave0_PREADY
  5.343                        CoreAPB3_0/u_mux_p_to_b3/PREADY:A (r)
               +     0.156          cell: ADLIB:OR2
  5.499                        CoreAPB3_0/u_mux_p_to_b3/PREADY:Y (r)
               +     0.562          net: MultichannelFFT_MSS_0_MSS_MASTER_APB_PREADY
  6.061                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_36:PIN5 (r)
               +     0.102          cell: ADLIB:MSS_IF
  6.163                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_36:PIN5INT (r)
               +     0.202          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/MSSPREADYINT_NET
  6.365                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY (r)
                                    
  6.365                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.095          Library hold time: ADLIB:MSS_APB_IP
  4.044                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
                                    
  4.044                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        Aapb_int_fft_0/fifo512X32_inst/\\DFN1E1C0_Q[24]\\/U1:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[24]
  Delay (ns):                  1.273
  Slack (ns):                  1.373
  Arrival (ns):                5.648
  Required (ns):               4.275
  Hold (ns):                   1.326

Path 2
  From:                        Aapb_int_fft_0/fifo512X32_inst/\\DFN1E1C0_Q[3]\\/U1:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]
  Delay (ns):                  1.383
  Slack (ns):                  1.465
  Arrival (ns):                5.747
  Required (ns):               4.282
  Hold (ns):                   1.333

Path 3
  From:                        Aapb_int_fft_0/fifo512X32_inst/\\DFN1E1C0_Q[12]\\/U1:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[12]
  Delay (ns):                  1.403
  Slack (ns):                  1.482
  Arrival (ns):                5.767
  Required (ns):               4.285
  Hold (ns):                   1.336

Path 4
  From:                        Aapb_int_fft_0/fifo512X32_inst/\\DFN1E1C0_Q[16]\\/U1:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[16]
  Delay (ns):                  1.398
  Slack (ns):                  1.495
  Arrival (ns):                5.773
  Required (ns):               4.278
  Hold (ns):                   1.329

Path 5
  From:                        Aapb_int_fft_0/fifo512X32_inst/\\DFN1E1C0_Q[1]\\/U1:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[1]
  Delay (ns):                  1.445
  Slack (ns):                  1.531
  Arrival (ns):                5.814
  Required (ns):               4.283
  Hold (ns):                   1.334


Expanded Path 1
  From: Aapb_int_fft_0/fifo512X32_inst/\\DFN1E1C0_Q[24]\\/U1:CLK
  To: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[24]
  data arrival time                              5.648
  data required time                         -   4.275
  slack                                          1.373
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.340          net: FAB_CLK
  4.375                        Aapb_int_fft_0/fifo512X32_inst/\\DFN1E1C0_Q[24]\\/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.624                        Aapb_int_fft_0/fifo512X32_inst/\\DFN1E1C0_Q[24]\\/U1:Q (r)
               +     0.181          net: CoreAPB3_0_APBmslave0_PRDATA[24]
  4.805                        CoreAPB3_0/u_mux_p_to_b3/PRDATA_24:A (r)
               +     0.221          cell: ADLIB:NOR2A
  5.026                        CoreAPB3_0/u_mux_p_to_b3/PRDATA_24:Y (r)
               +     0.322          net: MultichannelFFT_MSS_0_MSS_MASTER_APB_PRDATA[24]
  5.348                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_55:PIN6 (r)
               +     0.090          cell: ADLIB:MSS_IF
  5.438                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_55:PIN6INT (r)
               +     0.210          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/MSSPRDATA[24]INT_NET
  5.648                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[24] (r)
                                    
  5.648                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.326          Library hold time: ADLIB:MSS_APB_IP
  4.275                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[24]
                                    
  4.275                        data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_pclk1

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  0.918
  Slack (ns):                  1.537
  Arrival (ns):                5.285
  Required (ns):               3.748
  Hold (ns):                   0.799

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int/U1:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[0]
  Delay (ns):                  1.266
  Slack (ns):                  1.896
  Arrival (ns):                5.656
  Required (ns):               3.760
  Hold (ns):                   0.811

Path 3
  From:                        Aapb_int_fft_0/fifo512X32_inst/DFN1P0_EMPTY:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[3]
  Delay (ns):                  1.917
  Slack (ns):                  2.479
  Arrival (ns):                6.294
  Required (ns):               3.815
  Hold (ns):                   0.866

Path 4
  From:                        Aapb_int_fft_0/fifo512X32_inst/DFN1P0_AEMPTY:CLK
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  Delay (ns):                  2.050
  Slack (ns):                  2.645
  Arrival (ns):                6.413
  Required (ns):               3.768
  Hold (ns):                   0.819


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:CLK
  To: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  data arrival time                              5.285
  data required time                         -   3.748
  slack                                          1.537
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.332          net: FAB_CLK
  4.367                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:CLK (r)
               +     0.249          cell: ADLIB:DFN1
  4.616                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:Q (r)
               +     0.567          net: Aapb_int_fft_0_FFT_OP_RDY
  5.183                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_21:PIN5 (r)
               +     0.102          cell: ADLIB:MSS_IF
  5.285                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_21:PIN5INT (r)
               +     0.000          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/GPI[1]INT_NET
  5.285                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1] (r)
                                    
  5.285                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     2.949          Clock generation
  2.949
               +     0.799          Library hold time: ADLIB:MSS_APB_IP
  3.748                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
                                    
  3.748                        data required time


END SET mss_ccc_gla1 to mss_pclk1

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/bfly_0/PrT5_r[5]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/bfly_0/PrT6_r[5]:D
  Delay (ns):                  0.395
  Slack (ns):                  0.337
  Arrival (ns):                4.785
  Required (ns):               4.448
  Hold (ns):                   0.000

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/bfly_0/PrT3_r[6]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/bfly_0/PrT4_r[6]:D
  Delay (ns):                  0.395
  Slack (ns):                  0.337
  Arrival (ns):                4.785
  Required (ns):               4.448
  Hold (ns):                   0.000

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/bfly_0/outQ_xhdl2[4]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/postBflySw_0/leftQ_r[4]:D
  Delay (ns):                  0.395
  Slack (ns):                  0.340
  Arrival (ns):                4.788
  Required (ns):               4.448
  Hold (ns):                   0.000

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/postBflySw_0/rightP_r[14]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/postBflySw_0/outP_xhdl1[14]:D
  Delay (ns):                  0.395
  Slack (ns):                  0.340
  Arrival (ns):                4.773
  Required (ns):               4.433
  Hold (ns):                   0.000

Path 5
  From:                        Aapb_int_fft_0/fifo512X32_inst/\\DFN1C0_MEM_WADDR[0]\\:CLK
  To:                          Aapb_int_fft_0/fifo512X32_inst/\\RAM4K9_QXI[31]\\:ADDRA0
  Delay (ns):                  0.512
  Slack (ns):                  0.346
  Arrival (ns):                4.881
  Required (ns):               4.535
  Hold (ns):                   0.000


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/bfly_0/PrT5_r[5]:CLK
  To: Aapb_int_fft_0/fftTop_inst/bfly_0/PrT6_r[5]:D
  data arrival time                              4.785
  data required time                         -   4.448
  slack                                          0.337
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.355          net: FAB_CLK
  4.390                        Aapb_int_fft_0/fftTop_inst/bfly_0/PrT5_r[5]:CLK (r)
               +     0.249          cell: ADLIB:DFN1
  4.639                        Aapb_int_fft_0/fftTop_inst/bfly_0/PrT5_r[5]:Q (r)
               +     0.146          net: Aapb_int_fft_0/fftTop_inst/bfly_0/PrT5_r[5]
  4.785                        Aapb_int_fft_0/fftTop_inst/bfly_0/PrT6_r[5]:D (r)
                                    
  4.785                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.413          net: FAB_CLK
  4.448                        Aapb_int_fft_0/fftTop_inst/bfly_0/PrT6_r[5]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1
  4.448                        Aapb_int_fft_0/fftTop_inst/bfly_0/PrT6_r[5]:D
                                    
  4.448                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/rdFFTtimer_0/preRdValid/U1:CLR
  Delay (ns):                  1.556
  Slack (ns):                  1.520
  Arrival (ns):                5.926
  Required (ns):               4.406
  Removal (ns):                0.000
  Skew (ns):                   -0.036

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/smFft_runs/U1:CLR
  Delay (ns):                  1.758
  Slack (ns):                  1.722
  Arrival (ns):                6.128
  Required (ns):               4.406
  Removal (ns):                0.000
  Skew (ns):                   -0.036

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/smFft_rdy/U1:CLR
  Delay (ns):                  1.765
  Slack (ns):                  1.724
  Arrival (ns):                6.135
  Required (ns):               4.411
  Removal (ns):                0.000
  Skew (ns):                   -0.041

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q_out[7]/U1:CLR
  Delay (ns):                  1.836
  Slack (ns):                  1.807
  Arrival (ns):                6.206
  Required (ns):               4.399
  Removal (ns):                0.000
  Skew (ns):                   -0.029

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q_out[4]/U1:CLR
  Delay (ns):                  1.834
  Slack (ns):                  1.816
  Arrival (ns):                6.204
  Required (ns):               4.388
  Removal (ns):                0.000
  Skew (ns):                   -0.018


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/rdFFTtimer_0/preRdValid/U1:CLR
  data arrival time                              5.926
  data required time                         -   4.406
  slack                                          1.520
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.335          net: FAB_CLK
  4.370                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK (r)
               +     0.320          cell: ADLIB:DFN1P0
  4.690                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:Q (f)
               +     0.877          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/initRst
  5.567                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNI4I1K_0:B (f)
               +     0.209          cell: ADLIB:NOR2A
  5.776                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNI4I1K_0:Y (r)
               +     0.150          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst_1
  5.926                        Aapb_int_fft_0/fftTop_inst/smTop_0/rdFFTtimer_0/preRdValid/U1:CLR (r)
                                    
  5.926                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.371          net: FAB_CLK
  4.406                        Aapb_int_fft_0/fftTop_inst/smTop_0/rdFFTtimer_0/preRdValid/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  4.406                        Aapb_int_fft_0/fftTop_inst/smTop_0/rdFFTtimer_0/preRdValid/U1:CLR
                                    
  4.406                        data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/PENABLE_reg:D
  Delay (ns):                  2.137
  Slack (ns):                  0.692
  Arrival (ns):                5.086
  Required (ns):               4.394
  Hold (ns):                   0.000

Path 2
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memQ/wrapRam_0/actram_R0C1:WD15
  Delay (ns):                  2.707
  Slack (ns):                  1.115
  Arrival (ns):                5.656
  Required (ns):               4.541
  Hold (ns):                   0.000

Path 3
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memQ/wrapRam_0/actram_R0C1:WD14
  Delay (ns):                  2.720
  Slack (ns):                  1.128
  Arrival (ns):                5.669
  Required (ns):               4.541
  Hold (ns):                   0.000

Path 4
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/poBuf/memQ/wrapRam_0/actram_R0C1:WD15
  Delay (ns):                  2.771
  Slack (ns):                  1.180
  Arrival (ns):                5.720
  Required (ns):               4.540
  Hold (ns):                   0.000

Path 5
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memQ/wrapRam_0/actram_R0C1:WD4
  Delay (ns):                  2.776
  Slack (ns):                  1.184
  Arrival (ns):                5.725
  Required (ns):               4.541
  Hold (ns):                   0.000


Expanded Path 1
  From: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: Aapb_int_fft_0/PENABLE_reg:D
  data arrival time                              5.086
  data required time                         -   4.394
  slack                                          0.692
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.287          cell: ADLIB:MSS_APB_IP
  4.236                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPENABLE (r)
               +     0.059          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/MSSPENABLEINT_NET
  4.295                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_42:PIN2INT (r)
               +     0.045          cell: ADLIB:MSS_IF
  4.340                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_42:PIN2 (r)
               +     0.440          net: CoreAPB3_0_APBmslave0_PENABLE
  4.780                        MultichannelFFT_MSS_0/MSS_ADLIB_INST_RNIC3SC:A (r)
               +     0.158          cell: ADLIB:INV
  4.938                        MultichannelFFT_MSS_0/MSS_ADLIB_INST_RNIC3SC:Y (f)
               +     0.148          net: CoreAPB3_0_APBmslave0_PENABLE_i
  5.086                        Aapb_int_fft_0/PENABLE_reg:D (f)
                                    
  5.086                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.359          net: FAB_CLK
  4.394                        Aapb_int_fft_0/PENABLE_reg:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1P0
  4.394                        Aapb_int_fft_0/PENABLE_reg:D
                                    
  4.394                        data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/flag:PRE
  Delay (ns):                  3.182
  Slack (ns):                  1.735
  Arrival (ns):                6.131
  Required (ns):               4.396
  Hold (ns):

Path 2
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fifo512X32_inst/\\DFN1C0_MEM_WADDR[0]\\:CLR
  Delay (ns):                  3.459
  Slack (ns):                  2.023
  Arrival (ns):                6.408
  Required (ns):               4.385
  Hold (ns):

Path 3
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fifo512X32_inst/DFN1P0_EMPTY:PRE
  Delay (ns):                  3.487
  Slack (ns):                  2.040
  Arrival (ns):                6.436
  Required (ns):               4.396
  Hold (ns):

Path 4
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fifo512X32_inst/\\DFN1C0_MEM_RADDR[5]\\:CLR
  Delay (ns):                  3.487
  Slack (ns):                  2.040
  Arrival (ns):                6.436
  Required (ns):               4.396
  Hold (ns):

Path 5
  From:                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fifo512X32_inst/\\DFN1C0_MEM_WADDR[8]\\:CLR
  Delay (ns):                  3.570
  Slack (ns):                  2.135
  Arrival (ns):                6.519
  Required (ns):               4.384
  Hold (ns):


Expanded Path 1
  From: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: Aapb_int_fft_0/flag:PRE
  data arrival time                              6.131
  data required time                         -   4.396
  slack                                          1.735
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.225          net: MultichannelFFT_MSS_0/GLA0
  2.949                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.569          cell: ADLIB:MSS_APB_IP
  4.518                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.059          net: MultichannelFFT_MSS_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  4.577                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.045          cell: ADLIB:MSS_IF
  4.622                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     1.509          net: MultichannelFFT_MSS_0_M2F_RESET_N
  6.131                        Aapb_int_fft_0/flag:PRE (r)
                                    
  6.131                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.361          net: FAB_CLK
  4.396                        Aapb_int_fft_0/flag:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1P0
  4.396                        Aapb_int_fft_0/flag:PRE
                                    
  4.396                        data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.277
  Slack (ns):
  Arrival (ns):                0.277
  Required (ns):
  Hold (ns):                   1.294
  External Hold (ns):          4.012


Expanded Path 1
  From: MSS_RESET_N
  To: MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.277
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        MultichannelFFT_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        MultichannelFFT_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: MultichannelFFT_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.277                        MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.277                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MultichannelFFT_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.271          net: MultichannelFFT_MSS_0/GLA0
  N/C                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.294          Library hold time: ADLIB:MSS_APB_IP
  N/C                          MultichannelFFT_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MultichannelFFT_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

