----------------------------------------------------------------------
-- Created by SmartDesign Fri Nov 23 08:57:46 2012
-- Version: 10.1 SP1 10.1.1.6
----------------------------------------------------------------------

----------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

library smartfusion;
use smartfusion.all;
library COREAPB3_LIB;
use COREAPB3_LIB.all;
----------------------------------------------------------------------
-- MultichannelFFT entity declaration
----------------------------------------------------------------------
entity MultichannelFFT is
    -- Port list
    port(
        -- Inputs
        ADC0_ch0    : in  std_logic;
        ADC0_ch1    : in  std_logic;
        ADC1_ch0    : in  std_logic;
        ADC1_ch1    : in  std_logic;
        MSS_RESET_N : in  std_logic;
        UART_0_RXD  : in  std_logic;
        VAREF0      : in  std_logic;
        VAREF1      : in  std_logic;
        -- Outputs
        UART_0_TXD  : out std_logic
        );
end MultichannelFFT;
----------------------------------------------------------------------
-- MultichannelFFT architecture body
----------------------------------------------------------------------
architecture RTL of MultichannelFFT is
----------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------
-- Aapb_int_fft
component Aapb_int_fft
    -- Port list
    port(
        -- Inputs
        PADDR      : in  std_logic_vector(31 downto 0);
        PCLK       : in  std_logic;
        PENABLE    : in  std_logic;
        PRESETn    : in  std_logic;
        PSEL_S0    : in  std_logic;
        PWDATA     : in  std_logic_vector(31 downto 0);
        PWRITE     : in  std_logic;
        -- Outputs
        AEMPTY_OUT : out std_logic;
        EMPTY_OUT  : out std_logic;
        FFT_IP_RDY : out std_logic;
        FFT_OP_RDY : out std_logic;
        PRDATA     : out std_logic_vector(31 downto 0);
        PREADY     : out std_logic;
        PSLVERR    : out std_logic
        );
end component;
-- CoreAPB3   -   Actel:DirectCore:CoreAPB3:3.0.103
component CoreAPB3
    generic( 
        APB_DWIDTH      : integer := 32 ;
        APBSLOT0ENABLE  : integer := 1 ;
        APBSLOT1ENABLE  : integer := 0 ;
        APBSLOT2ENABLE  : integer := 0 ;
        APBSLOT3ENABLE  : integer := 0 ;
        APBSLOT4ENABLE  : integer := 0 ;
        APBSLOT5ENABLE  : integer := 0 ;
        APBSLOT6ENABLE  : integer := 0 ;
        APBSLOT7ENABLE  : integer := 0 ;
        APBSLOT8ENABLE  : integer := 0 ;
        APBSLOT9ENABLE  : integer := 0 ;
        APBSLOT10ENABLE : integer := 0 ;
        APBSLOT11ENABLE : integer := 0 ;
        APBSLOT12ENABLE : integer := 0 ;
        APBSLOT13ENABLE : integer := 0 ;
        APBSLOT14ENABLE : integer := 0 ;
        APBSLOT15ENABLE : integer := 0 ;
        IADDR_ENABLE    : integer := 0 ;
        RANGESIZE       : integer := 256 
        );
    -- Port list
    port(
        -- Inputs
        PADDR      : in  std_logic_vector(23 downto 0);
        PCLK       : in  std_logic;
        PENABLE    : in  std_logic;
        PRDATAS0   : in  std_logic_vector(31 downto 0);
        PRDATAS1   : in  std_logic_vector(31 downto 0);
        PRDATAS10  : in  std_logic_vector(31 downto 0);
        PRDATAS11  : in  std_logic_vector(31 downto 0);
        PRDATAS12  : in  std_logic_vector(31 downto 0);
        PRDATAS13  : in  std_logic_vector(31 downto 0);
        PRDATAS14  : in  std_logic_vector(31 downto 0);
        PRDATAS15  : in  std_logic_vector(31 downto 0);
        PRDATAS2   : in  std_logic_vector(31 downto 0);
        PRDATAS3   : in  std_logic_vector(31 downto 0);
        PRDATAS4   : in  std_logic_vector(31 downto 0);
        PRDATAS5   : in  std_logic_vector(31 downto 0);
        PRDATAS6   : in  std_logic_vector(31 downto 0);
        PRDATAS7   : in  std_logic_vector(31 downto 0);
        PRDATAS8   : in  std_logic_vector(31 downto 0);
        PRDATAS9   : in  std_logic_vector(31 downto 0);
        PREADYS0   : in  std_logic;
        PREADYS1   : in  std_logic;
        PREADYS10  : in  std_logic;
        PREADYS11  : in  std_logic;
        PREADYS12  : in  std_logic;
        PREADYS13  : in  std_logic;
        PREADYS14  : in  std_logic;
        PREADYS15  : in  std_logic;
        PREADYS2   : in  std_logic;
        PREADYS3   : in  std_logic;
        PREADYS4   : in  std_logic;
        PREADYS5   : in  std_logic;
        PREADYS6   : in  std_logic;
        PREADYS7   : in  std_logic;
        PREADYS8   : in  std_logic;
        PREADYS9   : in  std_logic;
        PRESETN    : in  std_logic;
        PSEL       : in  std_logic;
        PSLVERRS0  : in  std_logic;
        PSLVERRS1  : in  std_logic;
        PSLVERRS10 : in  std_logic;
        PSLVERRS11 : in  std_logic;
        PSLVERRS12 : in  std_logic;
        PSLVERRS13 : in  std_logic;
        PSLVERRS14 : in  std_logic;
        PSLVERRS15 : in  std_logic;
        PSLVERRS2  : in  std_logic;
        PSLVERRS3  : in  std_logic;
        PSLVERRS4  : in  std_logic;
        PSLVERRS5  : in  std_logic;
        PSLVERRS6  : in  std_logic;
        PSLVERRS7  : in  std_logic;
        PSLVERRS8  : in  std_logic;
        PSLVERRS9  : in  std_logic;
        PWDATA     : in  std_logic_vector(31 downto 0);
        PWRITE     : in  std_logic;
        -- Outputs
        PADDRS     : out std_logic_vector(23 downto 0);
        PADDRS0    : out std_logic_vector(23 downto 0);
        PENABLES   : out std_logic;
        PRDATA     : out std_logic_vector(31 downto 0);
        PREADY     : out std_logic;
        PSELS0     : out std_logic;
        PSELS1     : out std_logic;
        PSELS10    : out std_logic;
        PSELS11    : out std_logic;
        PSELS12    : out std_logic;
        PSELS13    : out std_logic;
        PSELS14    : out std_logic;
        PSELS15    : out std_logic;
        PSELS2     : out std_logic;
        PSELS3     : out std_logic;
        PSELS4     : out std_logic;
        PSELS5     : out std_logic;
        PSELS6     : out std_logic;
        PSELS7     : out std_logic;
        PSELS8     : out std_logic;
        PSELS9     : out std_logic;
        PSLVERR    : out std_logic;
        PWDATAS    : out std_logic_vector(31 downto 0);
        PWRITES    : out std_logic
        );
end component;
-- MultichannelFFT_MSS
component MultichannelFFT_MSS
    -- Port list
    port(
        -- Inputs
        ADC0_ch0    : in  std_logic;
        ADC0_ch1    : in  std_logic;
        ADC1_ch0    : in  std_logic;
        ADC1_ch1    : in  std_logic;
        F2M_GPI_0   : in  std_logic;
        F2M_GPI_1   : in  std_logic;
        F2M_GPI_2   : in  std_logic;
        F2M_GPI_3   : in  std_logic;
        MSSPRDATA   : in  std_logic_vector(31 downto 0);
        MSSPREADY   : in  std_logic;
        MSSPSLVERR  : in  std_logic;
        MSS_RESET_N : in  std_logic;
        UART_0_RXD  : in  std_logic;
        VAREF0      : in  std_logic;
        VAREF1      : in  std_logic;
        -- Outputs
        FAB_CLK     : out std_logic;
        M2F_RESET_N : out std_logic;
        MSSPADDR    : out std_logic_vector(19 downto 0);
        MSSPENABLE  : out std_logic;
        MSSPSEL     : out std_logic;
        MSSPWDATA   : out std_logic_vector(31 downto 0);
        MSSPWRITE   : out std_logic;
        UART_0_TXD  : out std_logic
        );
end component;
----------------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------------
signal Aapb_int_fft_0_AEMPTY_OUT                    : std_logic;
signal Aapb_int_fft_0_EMPTY_OUT                     : std_logic;
signal Aapb_int_fft_0_FFT_IP_RDY                    : std_logic;
signal Aapb_int_fft_0_FFT_OP_RDY                    : std_logic;
signal CoreAPB3_0_APBmslave0_PENABLE                : std_logic;
signal CoreAPB3_0_APBmslave0_PRDATA                 : std_logic_vector(31 downto 0);
signal CoreAPB3_0_APBmslave0_PREADY                 : std_logic;
signal CoreAPB3_0_APBmslave0_PSELx                  : std_logic;
signal CoreAPB3_0_APBmslave0_PSLVERR                : std_logic;
signal CoreAPB3_0_APBmslave0_PWDATA                 : std_logic_vector(31 downto 0);
signal CoreAPB3_0_APBmslave0_PWRITE                 : std_logic;
signal MultichannelFFT_MSS_0_FAB_CLK                : std_logic;
signal MultichannelFFT_MSS_0_M2F_RESET_N            : std_logic;
signal MultichannelFFT_MSS_0_MSS_MASTER_APB_PENABLE : std_logic;
signal MultichannelFFT_MSS_0_MSS_MASTER_APB_PRDATA  : std_logic_vector(31 downto 0);
signal MultichannelFFT_MSS_0_MSS_MASTER_APB_PREADY  : std_logic;
signal MultichannelFFT_MSS_0_MSS_MASTER_APB_PSELx   : std_logic;
signal MultichannelFFT_MSS_0_MSS_MASTER_APB_PSLVERR : std_logic;
signal MultichannelFFT_MSS_0_MSS_MASTER_APB_PWDATA  : std_logic_vector(31 downto 0);
signal MultichannelFFT_MSS_0_MSS_MASTER_APB_PWRITE  : std_logic;
signal UART_0_TXD_net_0                             : std_logic;
signal UART_0_TXD_net_1                             : std_logic;
----------------------------------------------------------------------
-- TiedOff Signals
----------------------------------------------------------------------
signal GND_net                                      : std_logic;
signal VCC_net                                      : std_logic;
signal PRDATAS1_const_net_0                         : std_logic_vector(31 downto 0);
signal PRDATAS2_const_net_0                         : std_logic_vector(31 downto 0);
signal PRDATAS3_const_net_0                         : std_logic_vector(31 downto 0);
signal PRDATAS4_const_net_0                         : std_logic_vector(31 downto 0);
signal PRDATAS5_const_net_0                         : std_logic_vector(31 downto 0);
signal PRDATAS6_const_net_0                         : std_logic_vector(31 downto 0);
signal PRDATAS7_const_net_0                         : std_logic_vector(31 downto 0);
signal PRDATAS8_const_net_0                         : std_logic_vector(31 downto 0);
signal PRDATAS9_const_net_0                         : std_logic_vector(31 downto 0);
signal PRDATAS10_const_net_0                        : std_logic_vector(31 downto 0);
signal PRDATAS11_const_net_0                        : std_logic_vector(31 downto 0);
signal PRDATAS12_const_net_0                        : std_logic_vector(31 downto 0);
signal PRDATAS13_const_net_0                        : std_logic_vector(31 downto 0);
signal PRDATAS14_const_net_0                        : std_logic_vector(31 downto 0);
signal PRDATAS15_const_net_0                        : std_logic_vector(31 downto 0);
----------------------------------------------------------------------
-- Bus Interface Nets Declarations - Unequal Pin Widths
----------------------------------------------------------------------
signal CoreAPB3_0_APBmslave0_PADDR_0_31to24         : std_logic_vector(31 downto 24);
signal CoreAPB3_0_APBmslave0_PADDR_0_23to0          : std_logic_vector(23 downto 0);
signal CoreAPB3_0_APBmslave0_PADDR_0                : std_logic_vector(31 downto 0);
signal CoreAPB3_0_APBmslave0_PADDR                  : std_logic_vector(23 downto 0);

signal MultichannelFFT_MSS_0_MSS_MASTER_APB_PADDR_0_23to20: std_logic_vector(23 downto 20);
signal MultichannelFFT_MSS_0_MSS_MASTER_APB_PADDR_0_19to0: std_logic_vector(19 downto 0);
signal MultichannelFFT_MSS_0_MSS_MASTER_APB_PADDR_0 : std_logic_vector(23 downto 0);
signal MultichannelFFT_MSS_0_MSS_MASTER_APB_PADDR   : std_logic_vector(19 downto 0);


begin
----------------------------------------------------------------------
-- Constant assignments
----------------------------------------------------------------------
 GND_net               <= '0';
 VCC_net               <= '1';
 PRDATAS1_const_net_0  <= B"00000000000000000000000000000000";
 PRDATAS2_const_net_0  <= B"00000000000000000000000000000000";
 PRDATAS3_const_net_0  <= B"00000000000000000000000000000000";
 PRDATAS4_const_net_0  <= B"00000000000000000000000000000000";
 PRDATAS5_const_net_0  <= B"00000000000000000000000000000000";
 PRDATAS6_const_net_0  <= B"00000000000000000000000000000000";
 PRDATAS7_const_net_0  <= B"00000000000000000000000000000000";
 PRDATAS8_const_net_0  <= B"00000000000000000000000000000000";
 PRDATAS9_const_net_0  <= B"00000000000000000000000000000000";
 PRDATAS10_const_net_0 <= B"00000000000000000000000000000000";
 PRDATAS11_const_net_0 <= B"00000000000000000000000000000000";
 PRDATAS12_const_net_0 <= B"00000000000000000000000000000000";
 PRDATAS13_const_net_0 <= B"00000000000000000000000000000000";
 PRDATAS14_const_net_0 <= B"00000000000000000000000000000000";
 PRDATAS15_const_net_0 <= B"00000000000000000000000000000000";
----------------------------------------------------------------------
-- Top level output port assignments
----------------------------------------------------------------------
 UART_0_TXD_net_1 <= UART_0_TXD_net_0;
 UART_0_TXD       <= UART_0_TXD_net_1;
----------------------------------------------------------------------
-- Bus Interface Nets Assignments - Unequal Pin Widths
----------------------------------------------------------------------
 CoreAPB3_0_APBmslave0_PADDR_0_31to24(31 downto 24) <= B"00000000";
 CoreAPB3_0_APBmslave0_PADDR_0_23to0(23 downto 0) <= CoreAPB3_0_APBmslave0_PADDR(23 downto 0);
 CoreAPB3_0_APBmslave0_PADDR_0 <= ( CoreAPB3_0_APBmslave0_PADDR_0_31to24(31 downto 24) & CoreAPB3_0_APBmslave0_PADDR_0_23to0(23 downto 0) );

 MultichannelFFT_MSS_0_MSS_MASTER_APB_PADDR_0_23to20(23 downto 20) <= B"0000";
 MultichannelFFT_MSS_0_MSS_MASTER_APB_PADDR_0_19to0(19 downto 0) <= MultichannelFFT_MSS_0_MSS_MASTER_APB_PADDR(19 downto 0);
 MultichannelFFT_MSS_0_MSS_MASTER_APB_PADDR_0 <= ( MultichannelFFT_MSS_0_MSS_MASTER_APB_PADDR_0_23to20(23 downto 20) & MultichannelFFT_MSS_0_MSS_MASTER_APB_PADDR_0_19to0(19 downto 0) );

----------------------------------------------------------------------
-- Component instances
----------------------------------------------------------------------
-- Aapb_int_fft_0
Aapb_int_fft_0 : Aapb_int_fft
    port map( 
        -- Inputs
        PRESETn    => MultichannelFFT_MSS_0_M2F_RESET_N,
        PCLK       => MultichannelFFT_MSS_0_FAB_CLK,
        PSEL_S0    => CoreAPB3_0_APBmslave0_PSELx,
        PWRITE     => CoreAPB3_0_APBmslave0_PWRITE,
        PENABLE    => CoreAPB3_0_APBmslave0_PENABLE,
        PADDR      => CoreAPB3_0_APBmslave0_PADDR_0,
        PWDATA     => CoreAPB3_0_APBmslave0_PWDATA,
        -- Outputs
        PSLVERR    => CoreAPB3_0_APBmslave0_PSLVERR,
        PREADY     => CoreAPB3_0_APBmslave0_PREADY,
        FFT_IP_RDY => Aapb_int_fft_0_FFT_IP_RDY,
        FFT_OP_RDY => Aapb_int_fft_0_FFT_OP_RDY,
        AEMPTY_OUT => Aapb_int_fft_0_AEMPTY_OUT,
        EMPTY_OUT  => Aapb_int_fft_0_EMPTY_OUT,
        PRDATA     => CoreAPB3_0_APBmslave0_PRDATA 
        );
-- CoreAPB3_0   -   Actel:DirectCore:CoreAPB3:3.0.103
CoreAPB3_0 : CoreAPB3
    generic map( 
        APB_DWIDTH      => ( 32 ),
        APBSLOT0ENABLE  => ( 1 ),
        APBSLOT1ENABLE  => ( 0 ),
        APBSLOT2ENABLE  => ( 0 ),
        APBSLOT3ENABLE  => ( 0 ),
        APBSLOT4ENABLE  => ( 0 ),
        APBSLOT5ENABLE  => ( 0 ),
        APBSLOT6ENABLE  => ( 0 ),
        APBSLOT7ENABLE  => ( 0 ),
        APBSLOT8ENABLE  => ( 0 ),
        APBSLOT9ENABLE  => ( 0 ),
        APBSLOT10ENABLE => ( 0 ),
        APBSLOT11ENABLE => ( 0 ),
        APBSLOT12ENABLE => ( 0 ),
        APBSLOT13ENABLE => ( 0 ),
        APBSLOT14ENABLE => ( 0 ),
        APBSLOT15ENABLE => ( 0 ),
        IADDR_ENABLE    => ( 0 ),
        RANGESIZE       => ( 256 )
        )
    port map( 
        -- Inputs
        PRESETN    => GND_net, -- tied to '0' from definition
        PCLK       => GND_net, -- tied to '0' from definition
        PWRITE     => MultichannelFFT_MSS_0_MSS_MASTER_APB_PWRITE,
        PENABLE    => MultichannelFFT_MSS_0_MSS_MASTER_APB_PENABLE,
        PSEL       => MultichannelFFT_MSS_0_MSS_MASTER_APB_PSELx,
        PREADYS0   => CoreAPB3_0_APBmslave0_PREADY,
        PSLVERRS0  => CoreAPB3_0_APBmslave0_PSLVERR,
        PREADYS1   => VCC_net, -- tied to '1' from definition
        PSLVERRS1  => GND_net, -- tied to '0' from definition
        PREADYS2   => VCC_net, -- tied to '1' from definition
        PSLVERRS2  => GND_net, -- tied to '0' from definition
        PREADYS3   => VCC_net, -- tied to '1' from definition
        PSLVERRS3  => GND_net, -- tied to '0' from definition
        PREADYS4   => VCC_net, -- tied to '1' from definition
        PSLVERRS4  => GND_net, -- tied to '0' from definition
        PREADYS5   => VCC_net, -- tied to '1' from definition
        PSLVERRS5  => GND_net, -- tied to '0' from definition
        PREADYS6   => VCC_net, -- tied to '1' from definition
        PSLVERRS6  => GND_net, -- tied to '0' from definition
        PREADYS7   => VCC_net, -- tied to '1' from definition
        PSLVERRS7  => GND_net, -- tied to '0' from definition
        PREADYS8   => VCC_net, -- tied to '1' from definition
        PSLVERRS8  => GND_net, -- tied to '0' from definition
        PREADYS9   => VCC_net, -- tied to '1' from definition
        PSLVERRS9  => GND_net, -- tied to '0' from definition
        PREADYS10  => VCC_net, -- tied to '1' from definition
        PSLVERRS10 => GND_net, -- tied to '0' from definition
        PREADYS11  => VCC_net, -- tied to '1' from definition
        PSLVERRS11 => GND_net, -- tied to '0' from definition
        PREADYS12  => VCC_net, -- tied to '1' from definition
        PSLVERRS12 => GND_net, -- tied to '0' from definition
        PREADYS13  => VCC_net, -- tied to '1' from definition
        PSLVERRS13 => GND_net, -- tied to '0' from definition
        PREADYS14  => VCC_net, -- tied to '1' from definition
        PSLVERRS14 => GND_net, -- tied to '0' from definition
        PREADYS15  => VCC_net, -- tied to '1' from definition
        PSLVERRS15 => GND_net, -- tied to '0' from definition
        PADDR      => MultichannelFFT_MSS_0_MSS_MASTER_APB_PADDR_0,
        PWDATA     => MultichannelFFT_MSS_0_MSS_MASTER_APB_PWDATA,
        PRDATAS0   => CoreAPB3_0_APBmslave0_PRDATA,
        PRDATAS1   => PRDATAS1_const_net_0, -- tied to X"0" from definition
        PRDATAS2   => PRDATAS2_const_net_0, -- tied to X"0" from definition
        PRDATAS3   => PRDATAS3_const_net_0, -- tied to X"0" from definition
        PRDATAS4   => PRDATAS4_const_net_0, -- tied to X"0" from definition
        PRDATAS5   => PRDATAS5_const_net_0, -- tied to X"0" from definition
        PRDATAS6   => PRDATAS6_const_net_0, -- tied to X"0" from definition
        PRDATAS7   => PRDATAS7_const_net_0, -- tied to X"0" from definition
        PRDATAS8   => PRDATAS8_const_net_0, -- tied to X"0" from definition
        PRDATAS9   => PRDATAS9_const_net_0, -- tied to X"0" from definition
        PRDATAS10  => PRDATAS10_const_net_0, -- tied to X"0" from definition
        PRDATAS11  => PRDATAS11_const_net_0, -- tied to X"0" from definition
        PRDATAS12  => PRDATAS12_const_net_0, -- tied to X"0" from definition
        PRDATAS13  => PRDATAS13_const_net_0, -- tied to X"0" from definition
        PRDATAS14  => PRDATAS14_const_net_0, -- tied to X"0" from definition
        PRDATAS15  => PRDATAS15_const_net_0, -- tied to X"0" from definition
        -- Outputs
        PREADY     => MultichannelFFT_MSS_0_MSS_MASTER_APB_PREADY,
        PSLVERR    => MultichannelFFT_MSS_0_MSS_MASTER_APB_PSLVERR,
        PWRITES    => CoreAPB3_0_APBmslave0_PWRITE,
        PENABLES   => CoreAPB3_0_APBmslave0_PENABLE,
        PSELS0     => CoreAPB3_0_APBmslave0_PSELx,
        PSELS1     => OPEN,
        PSELS2     => OPEN,
        PSELS3     => OPEN,
        PSELS4     => OPEN,
        PSELS5     => OPEN,
        PSELS6     => OPEN,
        PSELS7     => OPEN,
        PSELS8     => OPEN,
        PSELS9     => OPEN,
        PSELS10    => OPEN,
        PSELS11    => OPEN,
        PSELS12    => OPEN,
        PSELS13    => OPEN,
        PSELS14    => OPEN,
        PSELS15    => OPEN,
        PRDATA     => MultichannelFFT_MSS_0_MSS_MASTER_APB_PRDATA,
        PADDRS     => OPEN,
        PADDRS0    => CoreAPB3_0_APBmslave0_PADDR,
        PWDATAS    => CoreAPB3_0_APBmslave0_PWDATA 
        );
-- MultichannelFFT_MSS_0
MultichannelFFT_MSS_0 : MultichannelFFT_MSS
    port map( 
        -- Inputs
        UART_0_RXD  => UART_0_RXD,
        MSS_RESET_N => MSS_RESET_N,
        MSSPREADY   => MultichannelFFT_MSS_0_MSS_MASTER_APB_PREADY,
        MSSPSLVERR  => MultichannelFFT_MSS_0_MSS_MASTER_APB_PSLVERR,
        ADC1_ch0    => ADC1_ch0,
        ADC1_ch1    => ADC1_ch1,
        VAREF0      => VAREF0,
        VAREF1      => VAREF1,
        F2M_GPI_3   => Aapb_int_fft_0_EMPTY_OUT,
        F2M_GPI_2   => Aapb_int_fft_0_AEMPTY_OUT,
        F2M_GPI_1   => Aapb_int_fft_0_FFT_OP_RDY,
        F2M_GPI_0   => Aapb_int_fft_0_FFT_IP_RDY,
        ADC0_ch0    => ADC0_ch0,
        ADC0_ch1    => ADC0_ch1,
        MSSPRDATA   => MultichannelFFT_MSS_0_MSS_MASTER_APB_PRDATA,
        -- Outputs
        UART_0_TXD  => UART_0_TXD_net_0,
        FAB_CLK     => MultichannelFFT_MSS_0_FAB_CLK,
        M2F_RESET_N => MultichannelFFT_MSS_0_M2F_RESET_N,
        MSSPSEL     => MultichannelFFT_MSS_0_MSS_MASTER_APB_PSELx,
        MSSPENABLE  => MultichannelFFT_MSS_0_MSS_MASTER_APB_PENABLE,
        MSSPWRITE   => MultichannelFFT_MSS_0_MSS_MASTER_APB_PWRITE,
        MSSPADDR    => MultichannelFFT_MSS_0_MSS_MASTER_APB_PADDR,
        MSSPWDATA   => MultichannelFFT_MSS_0_MSS_MASTER_APB_PWDATA 
        );

end RTL;
