-- Version: 10.0 SP1 10.0.10.4

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity MultichannelFFT_MSS is

    port( FAB_CLK     : out   std_logic;
          M2F_RESET_N : out   std_logic;
          MSSPSEL     : out   std_logic;
          MSSPENABLE  : out   std_logic;
          MSSPWRITE   : out   std_logic;
          MSSPREADY   : in    std_logic;
          MSSPSLVERR  : in    std_logic;
          F2M_GPI_3   : in    std_logic;
          F2M_GPI_2   : in    std_logic;
          F2M_GPI_1   : in    std_logic;
          F2M_GPI_0   : in    std_logic;
          MSSPADDR    : out   std_logic_vector(19 downto 0);
          MSSPRDATA   : in    std_logic_vector(31 downto 0);
          MSSPWDATA   : out   std_logic_vector(31 downto 0);
          UART_0_TXD  : out   std_logic;
          UART_0_RXD  : in    std_logic;
          EMC_DB      : inout std_logic_vector(15 downto 0) := (others => 'Z');
          EMC_AB      : out   std_logic_vector(25 downto 0);
          EMC_BYTEN   : out   std_logic_vector(1 downto 0);
          EMC_CS0_N   : out   std_logic;
          EMC_CS1_N   : out   std_logic;
          EMC_OEN0_N  : out   std_logic;
          EMC_OEN1_N  : out   std_logic;
          EMC_CLK     : out   std_logic;
          EMC_RW_N    : out   std_logic;
          ADC0_ch0    : in    std_logic;
          ADC0_ch1    : in    std_logic;
          ADC1_ch0    : in    std_logic;
          ADC1_ch1    : in    std_logic;
          ADC2_ch0    : in    std_logic;
          ADC2_ch1    : in    std_logic;
          VAREF0      : in    std_logic;
          VAREF1      : in    std_logic;
          VAREF2      : in    std_logic;
          MSS_RESET_N : in    std_logic
        );

end MultichannelFFT_MSS;

architecture DEF_ARCH of MultichannelFFT_MSS is 

  component BIBUF_MSS
    generic (ACT_CONFIG:integer := 0; ACT_PIN:string := "");

    port( PAD : inout   std_logic;
          D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component OUTBUF_MSS
    generic (ACT_CONFIG:integer := 0; ACT_PIN:string := "");

    port( D   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component INBUF_A
    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component MSSINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component INBUF_MSS
    generic (ACT_CONFIG:integer := 0; ACT_PIN:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component MultichannelFFT_MSS_tmp_MSS_CCC_0_MSS_CCC
    port( CLKA           : in    std_logic := 'U';
          CLKA_PAD       : in    std_logic := 'U';
          CLKA_PADP      : in    std_logic := 'U';
          CLKA_PADN      : in    std_logic := 'U';
          CLKB           : in    std_logic := 'U';
          CLKB_PAD       : in    std_logic := 'U';
          CLKB_PADP      : in    std_logic := 'U';
          CLKB_PADN      : in    std_logic := 'U';
          CLKC           : in    std_logic := 'U';
          CLKC_PAD       : in    std_logic := 'U';
          CLKC_PADP      : in    std_logic := 'U';
          CLKC_PADN      : in    std_logic := 'U';
          GLA            : out   std_logic;
          GLB            : out   std_logic;
          GLC            : out   std_logic;
          FAB_CLK        : out   std_logic;
          YB             : out   std_logic;
          YC             : out   std_logic;
          MAINXIN        : in    std_logic := 'U';
          LPXIN          : in    std_logic := 'U';
          FAB_LOCK       : out   std_logic;
          MAC_CLK        : in    std_logic := 'U';
          RCOSC_CLKOUT   : out   std_logic;
          MAINXIN_CLKOUT : out   std_logic;
          LPXIN_CLKOUT   : out   std_logic;
          GLA0           : out   std_logic;
          MSS_LOCK       : out   std_logic;
          MAC_CLK_CCC    : out   std_logic;
          MAC_CLK_IO     : out   std_logic
        );
  end component;

  component MSS_APB
    generic (ACT_CONFIG:integer := 0; ACT_DIE:string := ""; 
        ACT_FCLK:integer := 0; ACT_PKG:string := "");

    port( MSSPADDR       : out   std_logic_vector(19 downto 0);
          MSSPWDATA      : out   std_logic_vector(31 downto 0);
          MSSPWRITE      : out   std_logic;
          MSSPSEL        : out   std_logic;
          MSSPENABLE     : out   std_logic;
          MSSPRDATA      : in    std_logic_vector(31 downto 0) := (others => 'U');
          MSSPREADY      : in    std_logic := 'U';
          MSSPSLVERR     : in    std_logic := 'U';
          FABPADDR       : in    std_logic_vector(31 downto 0) := (others => 'U');
          FABPWDATA      : in    std_logic_vector(31 downto 0) := (others => 'U');
          FABPWRITE      : in    std_logic := 'U';
          FABPSEL        : in    std_logic := 'U';
          FABPENABLE     : in    std_logic := 'U';
          FABPRDATA      : out   std_logic_vector(31 downto 0);
          FABPREADY      : out   std_logic;
          FABPSLVERR     : out   std_logic;
          SYNCCLKFDBK    : in    std_logic := 'U';
          CALIBOUT       : out   std_logic;
          CALIBIN        : in    std_logic := 'U';
          FABINT         : in    std_logic := 'U';
          MSSINT         : out   std_logic_vector(7 downto 0);
          WDINT          : out   std_logic;
          F2MRESETn      : in    std_logic := 'U';
          DMAREADY       : in    std_logic_vector(1 downto 0) := (others => 'U');
          RXEV           : in    std_logic := 'U';
          VRON           : in    std_logic := 'U';
          M2FRESETn      : out   std_logic;
          DEEPSLEEP      : out   std_logic;
          SLEEP          : out   std_logic;
          TXEV           : out   std_logic;
          GPI            : in    std_logic_vector(31 downto 0) := (others => 'U');
          GPO            : out   std_logic_vector(31 downto 0);
          UART0CTSn      : in    std_logic := 'U';
          UART0DSRn      : in    std_logic := 'U';
          UART0RIn       : in    std_logic := 'U';
          UART0DCDn      : in    std_logic := 'U';
          UART0RTSn      : out   std_logic;
          UART0DTRn      : out   std_logic;
          UART1CTSn      : in    std_logic := 'U';
          UART1DSRn      : in    std_logic := 'U';
          UART1RIn       : in    std_logic := 'U';
          UART1DCDn      : in    std_logic := 'U';
          UART1RTSn      : out   std_logic;
          UART1DTRn      : out   std_logic;
          I2C0SMBUSNI    : in    std_logic := 'U';
          I2C0SMBALERTNI : in    std_logic := 'U';
          I2C0BCLK       : in    std_logic := 'U';
          I2C0SMBUSNO    : out   std_logic;
          I2C0SMBALERTNO : out   std_logic;
          I2C1SMBUSNI    : in    std_logic := 'U';
          I2C1SMBALERTNI : in    std_logic := 'U';
          I2C1BCLK       : in    std_logic := 'U';
          I2C1SMBUSNO    : out   std_logic;
          I2C1SMBALERTNO : out   std_logic;
          MACM2FTXD      : out   std_logic_vector(1 downto 0);
          MACF2MRXD      : in    std_logic_vector(1 downto 0) := (others => 'U');
          MACM2FTXEN     : out   std_logic;
          MACF2MCRSDV    : in    std_logic := 'U';
          MACF2MRXER     : in    std_logic := 'U';
          MACF2MMDI      : in    std_logic := 'U';
          MACM2FMDO      : out   std_logic;
          MACM2FMDEN     : out   std_logic;
          MACM2FMDC      : out   std_logic;
          FABSDD0D       : in    std_logic := 'U';
          FABSDD1D       : in    std_logic := 'U';
          FABSDD2D       : in    std_logic := 'U';
          FABSDD0CLK     : in    std_logic := 'U';
          FABSDD1CLK     : in    std_logic := 'U';
          FABSDD2CLK     : in    std_logic := 'U';
          FABACETRIG     : in    std_logic := 'U';
          ACEFLAGS       : out   std_logic_vector(31 downto 0);
          CMP0           : out   std_logic;
          CMP1           : out   std_logic;
          CMP2           : out   std_logic;
          CMP3           : out   std_logic;
          CMP4           : out   std_logic;
          CMP5           : out   std_logic;
          CMP6           : out   std_logic;
          CMP7           : out   std_logic;
          CMP8           : out   std_logic;
          CMP9           : out   std_logic;
          CMP10          : out   std_logic;
          CMP11          : out   std_logic;
          LVTTL0EN       : in    std_logic := 'U';
          LVTTL1EN       : in    std_logic := 'U';
          LVTTL2EN       : in    std_logic := 'U';
          LVTTL3EN       : in    std_logic := 'U';
          LVTTL4EN       : in    std_logic := 'U';
          LVTTL5EN       : in    std_logic := 'U';
          LVTTL6EN       : in    std_logic := 'U';
          LVTTL7EN       : in    std_logic := 'U';
          LVTTL8EN       : in    std_logic := 'U';
          LVTTL9EN       : in    std_logic := 'U';
          LVTTL10EN      : in    std_logic := 'U';
          LVTTL11EN      : in    std_logic := 'U';
          LVTTL0         : out   std_logic;
          LVTTL1         : out   std_logic;
          LVTTL2         : out   std_logic;
          LVTTL3         : out   std_logic;
          LVTTL4         : out   std_logic;
          LVTTL5         : out   std_logic;
          LVTTL6         : out   std_logic;
          LVTTL7         : out   std_logic;
          LVTTL8         : out   std_logic;
          LVTTL9         : out   std_logic;
          LVTTL10        : out   std_logic;
          LVTTL11        : out   std_logic;
          PUFABn         : out   std_logic;
          VCC15GOOD      : out   std_logic;
          VCC33GOOD      : out   std_logic;
          FCLK           : in    std_logic := 'U';
          MACCLKCCC      : in    std_logic := 'U';
          RCOSC          : in    std_logic := 'U';
          MACCLK         : in    std_logic := 'U';
          PLLLOCK        : in    std_logic := 'U';
          MSSRESETn      : in    std_logic := 'U';
          GPOE           : out   std_logic_vector(31 downto 0);
          SPI0DO         : out   std_logic;
          SPI0DOE        : out   std_logic;
          SPI0DI         : in    std_logic := 'U';
          SPI0CLKI       : in    std_logic := 'U';
          SPI0CLKO       : out   std_logic;
          SPI0MODE       : out   std_logic;
          SPI0SSI        : in    std_logic := 'U';
          SPI0SSO        : out   std_logic_vector(7 downto 0);
          UART0TXD       : out   std_logic;
          UART0RXD       : in    std_logic := 'U';
          I2C0SDAI       : in    std_logic := 'U';
          I2C0SDAO       : out   std_logic;
          I2C0SCLI       : in    std_logic := 'U';
          I2C0SCLO       : out   std_logic;
          SPI1DO         : out   std_logic;
          SPI1DOE        : out   std_logic;
          SPI1DI         : in    std_logic := 'U';
          SPI1CLKI       : in    std_logic := 'U';
          SPI1CLKO       : out   std_logic;
          SPI1MODE       : out   std_logic;
          SPI1SSI        : in    std_logic := 'U';
          SPI1SSO        : out   std_logic_vector(7 downto 0);
          UART1TXD       : out   std_logic;
          UART1RXD       : in    std_logic := 'U';
          I2C1SDAI       : in    std_logic := 'U';
          I2C1SDAO       : out   std_logic;
          I2C1SCLI       : in    std_logic := 'U';
          I2C1SCLO       : out   std_logic;
          MACTXD         : out   std_logic_vector(1 downto 0);
          MACRXD         : in    std_logic_vector(1 downto 0) := (others => 'U');
          MACTXEN        : out   std_logic;
          MACCRSDV       : in    std_logic := 'U';
          MACRXER        : in    std_logic := 'U';
          MACMDI         : in    std_logic := 'U';
          MACMDO         : out   std_logic;
          MACMDEN        : out   std_logic;
          MACMDC         : out   std_logic;
          EMCCLK         : out   std_logic;
          EMCCLKRTN      : in    std_logic := 'U';
          EMCRDB         : in    std_logic_vector(15 downto 0) := (others => 'U');
          EMCAB          : out   std_logic_vector(25 downto 0);
          EMCWDB         : out   std_logic_vector(15 downto 0);
          EMCRWn         : out   std_logic;
          EMCCS0n        : out   std_logic;
          EMCCS1n        : out   std_logic;
          EMCOEN0n       : out   std_logic;
          EMCOEN1n       : out   std_logic;
          EMCBYTEN       : out   std_logic_vector(1 downto 0);
          EMCDBOE        : out   std_logic;
          ADC0           : in    std_logic := 'U';
          ADC1           : in    std_logic := 'U';
          ADC2           : in    std_logic := 'U';
          ADC3           : in    std_logic := 'U';
          ADC4           : in    std_logic := 'U';
          ADC5           : in    std_logic := 'U';
          ADC6           : in    std_logic := 'U';
          ADC7           : in    std_logic := 'U';
          ADC8           : in    std_logic := 'U';
          ADC9           : in    std_logic := 'U';
          ADC10          : in    std_logic := 'U';
          ADC11          : in    std_logic := 'U';
          SDD0           : out   std_logic;
          SDD1           : out   std_logic;
          SDD2           : out   std_logic;
          ABPS0          : in    std_logic := 'U';
          ABPS1          : in    std_logic := 'U';
          ABPS2          : in    std_logic := 'U';
          ABPS3          : in    std_logic := 'U';
          ABPS4          : in    std_logic := 'U';
          ABPS5          : in    std_logic := 'U';
          ABPS6          : in    std_logic := 'U';
          ABPS7          : in    std_logic := 'U';
          ABPS8          : in    std_logic := 'U';
          ABPS9          : in    std_logic := 'U';
          ABPS10         : in    std_logic := 'U';
          ABPS11         : in    std_logic := 'U';
          TM0            : in    std_logic := 'U';
          TM1            : in    std_logic := 'U';
          TM2            : in    std_logic := 'U';
          TM3            : in    std_logic := 'U';
          TM4            : in    std_logic := 'U';
          TM5            : in    std_logic := 'U';
          CM0            : in    std_logic := 'U';
          CM1            : in    std_logic := 'U';
          CM2            : in    std_logic := 'U';
          CM3            : in    std_logic := 'U';
          CM4            : in    std_logic := 'U';
          CM5            : in    std_logic := 'U';
          GNDTM0         : in    std_logic := 'U';
          GNDTM1         : in    std_logic := 'U';
          GNDTM2         : in    std_logic := 'U';
          VAREF0         : in    std_logic := 'U';
          VAREF1         : in    std_logic := 'U';
          VAREF2         : in    std_logic := 'U';
          VAREFOUT       : out   std_logic;
          GNDVAREF       : in    std_logic := 'U';
          PUn            : in    std_logic := 'U'
        );
  end component;

    signal MSS_ACE_0_ADC0_Y, MSS_ACE_0_ADC1_Y, MSS_ACE_0_ADC4_Y, 
        MSS_ACE_0_ADC5_Y, MSS_ACE_0_ADC8_Y, MSS_ACE_0_ADC9_Y, 
        MSS_ACE_0_VAREF0_Y, MSS_ACE_0_VAREF1_Y, 
        MSS_ACE_0_VAREF2_Y, MSS_ADLIB_INST_FCLK, 
        MSS_ADLIB_INST_MACCLK, MSS_ADLIB_INST_MACCLKCCC, 
        MSS_ADLIB_INST_PLLLOCK, MSS_ADLIB_INST_SYNCCLKFDBK, 
        MSS_EMI_0_AB_0_D, MSS_EMI_0_AB_1_D, MSS_EMI_0_AB_2_D, 
        MSS_EMI_0_AB_3_D, MSS_EMI_0_AB_4_D, MSS_EMI_0_AB_5_D, 
        MSS_EMI_0_AB_6_D, MSS_EMI_0_AB_7_D, MSS_EMI_0_AB_8_D, 
        MSS_EMI_0_AB_9_D, MSS_EMI_0_AB_10_D, MSS_EMI_0_AB_11_D, 
        MSS_EMI_0_AB_12_D, MSS_EMI_0_AB_13_D, MSS_EMI_0_AB_14_D, 
        MSS_EMI_0_AB_15_D, MSS_EMI_0_AB_16_D, MSS_EMI_0_AB_17_D, 
        MSS_EMI_0_AB_18_D, MSS_EMI_0_AB_19_D, MSS_EMI_0_AB_20_D, 
        MSS_EMI_0_AB_21_D, MSS_EMI_0_AB_22_D, MSS_EMI_0_AB_23_D, 
        MSS_EMI_0_AB_24_D, MSS_EMI_0_AB_25_D, MSS_EMI_0_BYTEN_0_D, 
        MSS_EMI_0_BYTEN_1_D, MSS_EMI_0_CLK_D, MSS_EMI_0_CS0_N_D, 
        MSS_EMI_0_CS1_N_D, MSS_EMI_0_DB_0_D, MSS_EMI_0_DB_0_Y, 
        MSS_EMI_0_DB_1_D, MSS_EMI_0_DB_1_Y, MSS_EMI_0_DB_2_D, 
        MSS_EMI_0_DB_2_Y, MSS_EMI_0_DB_3_D, MSS_EMI_0_DB_3_Y, 
        MSS_EMI_0_DB_4_D, MSS_EMI_0_DB_4_Y, MSS_EMI_0_DB_5_D, 
        MSS_EMI_0_DB_5_Y, MSS_EMI_0_DB_6_D, MSS_EMI_0_DB_6_Y, 
        MSS_EMI_0_DB_7_D, MSS_EMI_0_DB_7_Y, MSS_EMI_0_DB_8_D, 
        MSS_EMI_0_DB_8_Y, MSS_EMI_0_DB_9_D, MSS_EMI_0_DB_9_Y, 
        MSS_EMI_0_DB_10_D, MSS_EMI_0_DB_10_Y, MSS_EMI_0_DB_11_D, 
        MSS_EMI_0_DB_11_Y, MSS_EMI_0_DB_12_D, MSS_EMI_0_DB_12_Y, 
        MSS_EMI_0_DB_13_D, MSS_EMI_0_DB_13_Y, MSS_EMI_0_DB_14_D, 
        MSS_EMI_0_DB_14_Y, MSS_EMI_0_DB_15_D, MSS_EMI_0_DB_15_E, 
        MSS_EMI_0_DB_15_Y, MSS_EMI_0_OEN0_N_D, MSS_EMI_0_OEN1_N_D, 
        MSS_EMI_0_RW_N_D, MSS_RESET_0_MSS_RESET_N_Y, 
        MSS_UART_0_RXD_Y, MSS_UART_0_TXD_D, MSSINT_GPI_0_Y, 
        MSSINT_GPI_1_Y, MSSINT_GPI_2_Y, MSSINT_GPI_3_Y, GND_net, 
        VCC_net : std_logic;
    signal nc151, nc23, nc58, nc116, nc74, nc133, nc84, nc39, 
        nc72, nc82, nc145, nc57, nc156, nc125, nc73, nc107, nc66, 
        nc83, nc9, nc54, nc135, nc41, nc100, nc52, nc29, nc118, 
        nc60, nc141, nc45, nc53, nc121, nc11, nc131, nc96, nc79, 
        nc146, nc89, nc119, nc48, nc126, nc15, nc102, nc3, nc47, 
        nc90, nc136, nc59, nc18, nc44, nc117, nc148, nc42, nc17, 
        nc2, nc110, nc128, nc43, nc36, nc61, nc104, nc138, nc14, 
        nc150, nc149, nc12, nc30, nc65, nc7, nc129, nc8, nc13, 
        nc26, nc139, nc112, nc68, nc49, nc91, nc5, nc20, nc147, 
        nc67, nc152, nc127, nc103, nc76, nc140, nc86, nc95, nc120, 
        nc137, nc64, nc19, nc70, nc62, nc80, nc130, nc98, nc114, 
        nc56, nc105, nc63, nc97, nc31, nc154, nc50, nc142, nc94, 
        nc122, nc35, nc4, nc92, nc101, nc132, nc21, nc93, nc69, 
        nc38, nc113, nc106, nc25, nc1, nc37, nc144, nc153, nc46, 
        nc71, nc124, nc81, nc34, nc28, nc115, nc134, nc32, nc40, 
        nc99, nc75, nc85, nc27, nc108, nc16, nc155, nc51, nc33, 
        nc78, nc24, nc88, nc111, nc55, nc10, nc22, nc143, nc77, 
        nc6, nc109, nc87, nc123 : std_logic;

begin 

    FAB_CLK <= MSS_ADLIB_INST_SYNCCLKFDBK;

    MSS_EMI_0_DB_12 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D2")

      port map(PAD => EMC_DB(12), D => MSS_EMI_0_DB_12_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_12_Y);
    
    MSS_EMI_0_AB_24 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C16")

      port map(D => MSS_EMI_0_AB_24_D, PAD => EMC_AB(24));
    
    MSS_EMI_0_AB_4 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "E11")

      port map(D => MSS_EMI_0_AB_4_D, PAD => EMC_AB(4));
    
    MSS_EMI_0_AB_22 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C17")

      port map(D => MSS_EMI_0_AB_22_D, PAD => EMC_AB(22));
    
    MSS_EMI_0_OEN0_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D10")

      port map(D => MSS_EMI_0_OEN0_N_D, PAD => EMC_OEN0_N);
    
    MSS_ACE_0_ADC0 : INBUF_A
      port map(PAD => ADC0_ch0, Y => MSS_ACE_0_ADC0_Y);
    
    MSS_ACE_0_ADC1 : INBUF_A
      port map(PAD => ADC0_ch1, Y => MSS_ACE_0_ADC1_Y);
    
    MSSINT_GPI_1 : MSSINT
      port map(A => F2M_GPI_1, Y => MSSINT_GPI_1_Y);
    
    MSS_EMI_0_CS1_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A6")

      port map(D => MSS_EMI_0_CS1_N_D, PAD => EMC_CS1_N);
    
    MSS_EMI_0_AB_7 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A12")

      port map(D => MSS_EMI_0_AB_7_D, PAD => EMC_AB(7));
    
    MSS_EMI_0_AB_23 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C18")

      port map(D => MSS_EMI_0_AB_23_D, PAD => EMC_AB(23));
    
    MSS_EMI_0_DB_10 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "F4")

      port map(PAD => EMC_DB(10), D => MSS_EMI_0_DB_10_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_10_Y);
    
    MSS_EMI_0_DB_2 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "K5")

      port map(PAD => EMC_DB(2), D => MSS_EMI_0_DB_2_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_2_Y);
    
    MSS_EMI_0_BYTEN_0 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B9")

      port map(D => MSS_EMI_0_BYTEN_0_D, PAD => EMC_BYTEN(0));
    
    MSS_ACE_0_VAREF0 : INBUF_A
      port map(PAD => VAREF0, Y => MSS_ACE_0_VAREF0_Y);
    
    MSS_ACE_0_ADC5 : INBUF_A
      port map(PAD => ADC1_ch1, Y => MSS_ACE_0_ADC5_Y);
    
    MSS_EMI_0_AB_25 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D16")

      port map(D => MSS_EMI_0_AB_25_D, PAD => EMC_AB(25));
    
    MSS_EMI_0_AB_19 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B17")

      port map(D => MSS_EMI_0_AB_19_D, PAD => EMC_AB(19));
    
    \VCC\ : VCC
      port map(Y => VCC_net);
    
    MSS_EMI_0_OEN1_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C10")

      port map(D => MSS_EMI_0_OEN1_N_D, PAD => EMC_OEN1_N);
    
    MSS_EMI_0_AB_14 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B13")

      port map(D => MSS_EMI_0_AB_14_D, PAD => EMC_AB(14));
    
    MSS_EMI_0_AB_2 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B10")

      port map(D => MSS_EMI_0_AB_2_D, PAD => EMC_AB(2));
    
    MSS_EMI_0_AB_12 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A14")

      port map(D => MSS_EMI_0_AB_12_D, PAD => EMC_AB(12));
    
    MSS_ACE_0_ADC8 : INBUF_A
      port map(PAD => ADC2_ch0, Y => MSS_ACE_0_ADC8_Y);
    
    MSS_EMI_0_AB_20 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "F13")

      port map(D => MSS_EMI_0_AB_20_D, PAD => EMC_AB(20));
    
    MSS_EMI_0_DB_3 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "J4")

      port map(PAD => EMC_DB(3), D => MSS_EMI_0_DB_3_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_3_Y);
    
    MSS_EMI_0_AB_17 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C15")

      port map(D => MSS_EMI_0_AB_17_D, PAD => EMC_AB(17));
    
    MSS_EMI_0_DB_8 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "H3")

      port map(PAD => EMC_DB(8), D => MSS_EMI_0_DB_8_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_8_Y);
    
    MSS_EMI_0_DB_6 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "J1")

      port map(PAD => EMC_DB(6), D => MSS_EMI_0_DB_6_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_6_Y);
    
    MSS_EMI_0_AB_13 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A15")

      port map(D => MSS_EMI_0_AB_13_D, PAD => EMC_AB(13));
    
    MSS_EMI_0_AB_21 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "F14")

      port map(D => MSS_EMI_0_AB_21_D, PAD => EMC_AB(21));
    
    MSS_ACE_0_VAREF2 : INBUF_A
      port map(PAD => VAREF2, Y => MSS_ACE_0_VAREF2_Y);
    
    MSS_EMI_0_DB_1 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "K3")

      port map(PAD => EMC_DB(1), D => MSS_EMI_0_DB_1_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_1_Y);
    
    MSS_EMI_0_AB_16 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C14")

      port map(D => MSS_EMI_0_AB_16_D, PAD => EMC_AB(16));
    
    MSS_EMI_0_DB_11 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "G5")

      port map(PAD => EMC_DB(11), D => MSS_EMI_0_DB_11_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_11_Y);
    
    \GND\ : GND
      port map(Y => GND_net);
    
    MSS_RESET_0_MSS_RESET_N : INBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "R1")

      port map(PAD => MSS_RESET_N, Y => MSS_RESET_0_MSS_RESET_N_Y);
    
    MSS_EMI_0_DB_0 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "K2")

      port map(PAD => EMC_DB(0), D => MSS_EMI_0_DB_0_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_0_Y);
    
    MSS_EMI_0_AB_15 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B14")

      port map(D => MSS_EMI_0_AB_15_D, PAD => EMC_AB(15));
    
    MSS_CCC_0 : MultichannelFFT_MSS_tmp_MSS_CCC_0_MSS_CCC
      port map(CLKA => GND_net, CLKA_PAD => GND_net, CLKA_PADP
         => GND_net, CLKA_PADN => GND_net, CLKB => GND_net, 
        CLKB_PAD => GND_net, CLKB_PADP => GND_net, CLKB_PADN => 
        GND_net, CLKC => GND_net, CLKC_PAD => GND_net, CLKC_PADP
         => GND_net, CLKC_PADN => GND_net, GLA => OPEN, GLB => 
        OPEN, GLC => OPEN, FAB_CLK => MSS_ADLIB_INST_SYNCCLKFDBK, 
        YB => OPEN, YC => OPEN, MAINXIN => GND_net, LPXIN => 
        GND_net, FAB_LOCK => OPEN, MAC_CLK => GND_net, 
        RCOSC_CLKOUT => OPEN, MAINXIN_CLKOUT => OPEN, 
        LPXIN_CLKOUT => OPEN, GLA0 => MSS_ADLIB_INST_FCLK, 
        MSS_LOCK => MSS_ADLIB_INST_PLLLOCK, MAC_CLK_CCC => 
        MSS_ADLIB_INST_MACCLKCCC, MAC_CLK_IO => 
        MSS_ADLIB_INST_MACCLK);
    
    MSS_EMI_0_AB_3 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B11")

      port map(D => MSS_EMI_0_AB_3_D, PAD => EMC_AB(3));
    
    MSS_EMI_0_AB_8 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C13")

      port map(D => MSS_EMI_0_AB_8_D, PAD => EMC_AB(8));
    
    MSS_EMI_0_AB_6 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B12")

      port map(D => MSS_EMI_0_AB_6_D, PAD => EMC_AB(6));
    
    MSS_ACE_0_ADC9 : INBUF_A
      port map(PAD => ADC2_ch1, Y => MSS_ACE_0_ADC9_Y);
    
    MSS_ADLIB_INST : MSS_APB
      generic map(ACT_CONFIG => 32768, ACT_DIE => "IP6X5M2",
         ACT_FCLK => 80000000, ACT_PKG => "fg484")

      port map(MSSPADDR(19) => MSSPADDR(19), MSSPADDR(18) => 
        MSSPADDR(18), MSSPADDR(17) => MSSPADDR(17), MSSPADDR(16)
         => MSSPADDR(16), MSSPADDR(15) => MSSPADDR(15), 
        MSSPADDR(14) => MSSPADDR(14), MSSPADDR(13) => 
        MSSPADDR(13), MSSPADDR(12) => MSSPADDR(12), MSSPADDR(11)
         => MSSPADDR(11), MSSPADDR(10) => MSSPADDR(10), 
        MSSPADDR(9) => MSSPADDR(9), MSSPADDR(8) => MSSPADDR(8), 
        MSSPADDR(7) => MSSPADDR(7), MSSPADDR(6) => MSSPADDR(6), 
        MSSPADDR(5) => MSSPADDR(5), MSSPADDR(4) => MSSPADDR(4), 
        MSSPADDR(3) => MSSPADDR(3), MSSPADDR(2) => MSSPADDR(2), 
        MSSPADDR(1) => MSSPADDR(1), MSSPADDR(0) => MSSPADDR(0), 
        MSSPWDATA(31) => MSSPWDATA(31), MSSPWDATA(30) => 
        MSSPWDATA(30), MSSPWDATA(29) => MSSPWDATA(29), 
        MSSPWDATA(28) => MSSPWDATA(28), MSSPWDATA(27) => 
        MSSPWDATA(27), MSSPWDATA(26) => MSSPWDATA(26), 
        MSSPWDATA(25) => MSSPWDATA(25), MSSPWDATA(24) => 
        MSSPWDATA(24), MSSPWDATA(23) => MSSPWDATA(23), 
        MSSPWDATA(22) => MSSPWDATA(22), MSSPWDATA(21) => 
        MSSPWDATA(21), MSSPWDATA(20) => MSSPWDATA(20), 
        MSSPWDATA(19) => MSSPWDATA(19), MSSPWDATA(18) => 
        MSSPWDATA(18), MSSPWDATA(17) => MSSPWDATA(17), 
        MSSPWDATA(16) => MSSPWDATA(16), MSSPWDATA(15) => 
        MSSPWDATA(15), MSSPWDATA(14) => MSSPWDATA(14), 
        MSSPWDATA(13) => MSSPWDATA(13), MSSPWDATA(12) => 
        MSSPWDATA(12), MSSPWDATA(11) => MSSPWDATA(11), 
        MSSPWDATA(10) => MSSPWDATA(10), MSSPWDATA(9) => 
        MSSPWDATA(9), MSSPWDATA(8) => MSSPWDATA(8), MSSPWDATA(7)
         => MSSPWDATA(7), MSSPWDATA(6) => MSSPWDATA(6), 
        MSSPWDATA(5) => MSSPWDATA(5), MSSPWDATA(4) => 
        MSSPWDATA(4), MSSPWDATA(3) => MSSPWDATA(3), MSSPWDATA(2)
         => MSSPWDATA(2), MSSPWDATA(1) => MSSPWDATA(1), 
        MSSPWDATA(0) => MSSPWDATA(0), MSSPWRITE => MSSPWRITE, 
        MSSPSEL => MSSPSEL, MSSPENABLE => MSSPENABLE, 
        MSSPRDATA(31) => MSSPRDATA(31), MSSPRDATA(30) => 
        MSSPRDATA(30), MSSPRDATA(29) => MSSPRDATA(29), 
        MSSPRDATA(28) => MSSPRDATA(28), MSSPRDATA(27) => 
        MSSPRDATA(27), MSSPRDATA(26) => MSSPRDATA(26), 
        MSSPRDATA(25) => MSSPRDATA(25), MSSPRDATA(24) => 
        MSSPRDATA(24), MSSPRDATA(23) => MSSPRDATA(23), 
        MSSPRDATA(22) => MSSPRDATA(22), MSSPRDATA(21) => 
        MSSPRDATA(21), MSSPRDATA(20) => MSSPRDATA(20), 
        MSSPRDATA(19) => MSSPRDATA(19), MSSPRDATA(18) => 
        MSSPRDATA(18), MSSPRDATA(17) => MSSPRDATA(17), 
        MSSPRDATA(16) => MSSPRDATA(16), MSSPRDATA(15) => 
        MSSPRDATA(15), MSSPRDATA(14) => MSSPRDATA(14), 
        MSSPRDATA(13) => MSSPRDATA(13), MSSPRDATA(12) => 
        MSSPRDATA(12), MSSPRDATA(11) => MSSPRDATA(11), 
        MSSPRDATA(10) => MSSPRDATA(10), MSSPRDATA(9) => 
        MSSPRDATA(9), MSSPRDATA(8) => MSSPRDATA(8), MSSPRDATA(7)
         => MSSPRDATA(7), MSSPRDATA(6) => MSSPRDATA(6), 
        MSSPRDATA(5) => MSSPRDATA(5), MSSPRDATA(4) => 
        MSSPRDATA(4), MSSPRDATA(3) => MSSPRDATA(3), MSSPRDATA(2)
         => MSSPRDATA(2), MSSPRDATA(1) => MSSPRDATA(1), 
        MSSPRDATA(0) => MSSPRDATA(0), MSSPREADY => MSSPREADY, 
        MSSPSLVERR => MSSPSLVERR, FABPADDR(31) => GND_net, 
        FABPADDR(30) => GND_net, FABPADDR(29) => GND_net, 
        FABPADDR(28) => GND_net, FABPADDR(27) => GND_net, 
        FABPADDR(26) => GND_net, FABPADDR(25) => GND_net, 
        FABPADDR(24) => GND_net, FABPADDR(23) => GND_net, 
        FABPADDR(22) => GND_net, FABPADDR(21) => GND_net, 
        FABPADDR(20) => GND_net, FABPADDR(19) => GND_net, 
        FABPADDR(18) => GND_net, FABPADDR(17) => GND_net, 
        FABPADDR(16) => GND_net, FABPADDR(15) => GND_net, 
        FABPADDR(14) => GND_net, FABPADDR(13) => GND_net, 
        FABPADDR(12) => GND_net, FABPADDR(11) => GND_net, 
        FABPADDR(10) => GND_net, FABPADDR(9) => GND_net, 
        FABPADDR(8) => GND_net, FABPADDR(7) => GND_net, 
        FABPADDR(6) => GND_net, FABPADDR(5) => GND_net, 
        FABPADDR(4) => GND_net, FABPADDR(3) => GND_net, 
        FABPADDR(2) => GND_net, FABPADDR(1) => GND_net, 
        FABPADDR(0) => GND_net, FABPWDATA(31) => GND_net, 
        FABPWDATA(30) => GND_net, FABPWDATA(29) => GND_net, 
        FABPWDATA(28) => GND_net, FABPWDATA(27) => GND_net, 
        FABPWDATA(26) => GND_net, FABPWDATA(25) => GND_net, 
        FABPWDATA(24) => GND_net, FABPWDATA(23) => GND_net, 
        FABPWDATA(22) => GND_net, FABPWDATA(21) => GND_net, 
        FABPWDATA(20) => GND_net, FABPWDATA(19) => GND_net, 
        FABPWDATA(18) => GND_net, FABPWDATA(17) => GND_net, 
        FABPWDATA(16) => GND_net, FABPWDATA(15) => GND_net, 
        FABPWDATA(14) => GND_net, FABPWDATA(13) => GND_net, 
        FABPWDATA(12) => GND_net, FABPWDATA(11) => GND_net, 
        FABPWDATA(10) => GND_net, FABPWDATA(9) => GND_net, 
        FABPWDATA(8) => GND_net, FABPWDATA(7) => GND_net, 
        FABPWDATA(6) => GND_net, FABPWDATA(5) => GND_net, 
        FABPWDATA(4) => GND_net, FABPWDATA(3) => GND_net, 
        FABPWDATA(2) => GND_net, FABPWDATA(1) => GND_net, 
        FABPWDATA(0) => GND_net, FABPWRITE => GND_net, FABPSEL
         => GND_net, FABPENABLE => GND_net, FABPRDATA(31) => 
        nc151, FABPRDATA(30) => nc23, FABPRDATA(29) => nc58, 
        FABPRDATA(28) => nc116, FABPRDATA(27) => nc74, 
        FABPRDATA(26) => nc133, FABPRDATA(25) => nc84, 
        FABPRDATA(24) => nc39, FABPRDATA(23) => nc72, 
        FABPRDATA(22) => nc82, FABPRDATA(21) => nc145, 
        FABPRDATA(20) => nc57, FABPRDATA(19) => nc156, 
        FABPRDATA(18) => nc125, FABPRDATA(17) => nc73, 
        FABPRDATA(16) => nc107, FABPRDATA(15) => nc66, 
        FABPRDATA(14) => nc83, FABPRDATA(13) => nc9, 
        FABPRDATA(12) => nc54, FABPRDATA(11) => nc135, 
        FABPRDATA(10) => nc41, FABPRDATA(9) => nc100, 
        FABPRDATA(8) => nc52, FABPRDATA(7) => nc29, FABPRDATA(6)
         => nc118, FABPRDATA(5) => nc60, FABPRDATA(4) => nc141, 
        FABPRDATA(3) => nc45, FABPRDATA(2) => nc53, FABPRDATA(1)
         => nc121, FABPRDATA(0) => nc11, FABPREADY => OPEN, 
        FABPSLVERR => OPEN, SYNCCLKFDBK => 
        MSS_ADLIB_INST_SYNCCLKFDBK, CALIBOUT => OPEN, CALIBIN => 
        GND_net, FABINT => GND_net, MSSINT(7) => nc131, MSSINT(6)
         => nc96, MSSINT(5) => nc79, MSSINT(4) => nc146, 
        MSSINT(3) => nc89, MSSINT(2) => nc119, MSSINT(1) => nc48, 
        MSSINT(0) => nc126, WDINT => OPEN, F2MRESETn => VCC_net, 
        DMAREADY(1) => GND_net, DMAREADY(0) => GND_net, RXEV => 
        GND_net, VRON => GND_net, M2FRESETn => M2F_RESET_N, 
        DEEPSLEEP => OPEN, SLEEP => OPEN, TXEV => OPEN, GPI(31)
         => GND_net, GPI(30) => GND_net, GPI(29) => GND_net, 
        GPI(28) => GND_net, GPI(27) => GND_net, GPI(26) => 
        GND_net, GPI(25) => GND_net, GPI(24) => GND_net, GPI(23)
         => GND_net, GPI(22) => GND_net, GPI(21) => GND_net, 
        GPI(20) => GND_net, GPI(19) => GND_net, GPI(18) => 
        GND_net, GPI(17) => GND_net, GPI(16) => GND_net, GPI(15)
         => GND_net, GPI(14) => GND_net, GPI(13) => GND_net, 
        GPI(12) => GND_net, GPI(11) => GND_net, GPI(10) => 
        GND_net, GPI(9) => GND_net, GPI(8) => GND_net, GPI(7) => 
        GND_net, GPI(6) => GND_net, GPI(5) => GND_net, GPI(4) => 
        GND_net, GPI(3) => MSSINT_GPI_3_Y, GPI(2) => 
        MSSINT_GPI_2_Y, GPI(1) => MSSINT_GPI_1_Y, GPI(0) => 
        MSSINT_GPI_0_Y, GPO(31) => nc15, GPO(30) => nc102, 
        GPO(29) => nc3, GPO(28) => nc47, GPO(27) => nc90, GPO(26)
         => nc136, GPO(25) => nc59, GPO(24) => nc18, GPO(23) => 
        nc44, GPO(22) => nc117, GPO(21) => nc148, GPO(20) => nc42, 
        GPO(19) => nc17, GPO(18) => nc2, GPO(17) => nc110, 
        GPO(16) => nc128, GPO(15) => nc43, GPO(14) => nc36, 
        GPO(13) => nc61, GPO(12) => nc104, GPO(11) => nc138, 
        GPO(10) => nc14, GPO(9) => nc150, GPO(8) => nc149, GPO(7)
         => nc12, GPO(6) => nc30, GPO(5) => nc65, GPO(4) => nc7, 
        GPO(3) => nc129, GPO(2) => nc8, GPO(1) => nc13, GPO(0)
         => nc26, UART0CTSn => GND_net, UART0DSRn => GND_net, 
        UART0RIn => GND_net, UART0DCDn => GND_net, UART0RTSn => 
        OPEN, UART0DTRn => OPEN, UART1CTSn => GND_net, UART1DSRn
         => GND_net, UART1RIn => GND_net, UART1DCDn => GND_net, 
        UART1RTSn => OPEN, UART1DTRn => OPEN, I2C0SMBUSNI => 
        GND_net, I2C0SMBALERTNI => GND_net, I2C0BCLK => GND_net, 
        I2C0SMBUSNO => OPEN, I2C0SMBALERTNO => OPEN, I2C1SMBUSNI
         => GND_net, I2C1SMBALERTNI => GND_net, I2C1BCLK => 
        GND_net, I2C1SMBUSNO => OPEN, I2C1SMBALERTNO => OPEN, 
        MACM2FTXD(1) => nc139, MACM2FTXD(0) => nc112, 
        MACF2MRXD(1) => GND_net, MACF2MRXD(0) => GND_net, 
        MACM2FTXEN => OPEN, MACF2MCRSDV => GND_net, MACF2MRXER
         => GND_net, MACF2MMDI => GND_net, MACM2FMDO => OPEN, 
        MACM2FMDEN => OPEN, MACM2FMDC => OPEN, FABSDD0D => 
        GND_net, FABSDD1D => GND_net, FABSDD2D => GND_net, 
        FABSDD0CLK => GND_net, FABSDD1CLK => GND_net, FABSDD2CLK
         => GND_net, FABACETRIG => GND_net, ACEFLAGS(31) => nc68, 
        ACEFLAGS(30) => nc49, ACEFLAGS(29) => nc91, ACEFLAGS(28)
         => nc5, ACEFLAGS(27) => nc20, ACEFLAGS(26) => nc147, 
        ACEFLAGS(25) => nc67, ACEFLAGS(24) => nc152, ACEFLAGS(23)
         => nc127, ACEFLAGS(22) => nc103, ACEFLAGS(21) => nc76, 
        ACEFLAGS(20) => nc140, ACEFLAGS(19) => nc86, ACEFLAGS(18)
         => nc95, ACEFLAGS(17) => nc120, ACEFLAGS(16) => nc137, 
        ACEFLAGS(15) => nc64, ACEFLAGS(14) => nc19, ACEFLAGS(13)
         => nc70, ACEFLAGS(12) => nc62, ACEFLAGS(11) => nc80, 
        ACEFLAGS(10) => nc130, ACEFLAGS(9) => nc98, ACEFLAGS(8)
         => nc114, ACEFLAGS(7) => nc56, ACEFLAGS(6) => nc105, 
        ACEFLAGS(5) => nc63, ACEFLAGS(4) => nc97, ACEFLAGS(3) => 
        nc31, ACEFLAGS(2) => nc154, ACEFLAGS(1) => nc50, 
        ACEFLAGS(0) => nc142, CMP0 => OPEN, CMP1 => OPEN, CMP2
         => OPEN, CMP3 => OPEN, CMP4 => OPEN, CMP5 => OPEN, CMP6
         => OPEN, CMP7 => OPEN, CMP8 => OPEN, CMP9 => OPEN, CMP10
         => OPEN, CMP11 => OPEN, LVTTL0EN => GND_net, LVTTL1EN
         => GND_net, LVTTL2EN => GND_net, LVTTL3EN => GND_net, 
        LVTTL4EN => GND_net, LVTTL5EN => GND_net, LVTTL6EN => 
        GND_net, LVTTL7EN => GND_net, LVTTL8EN => GND_net, 
        LVTTL9EN => GND_net, LVTTL10EN => GND_net, LVTTL11EN => 
        GND_net, LVTTL0 => OPEN, LVTTL1 => OPEN, LVTTL2 => OPEN, 
        LVTTL3 => OPEN, LVTTL4 => OPEN, LVTTL5 => OPEN, LVTTL6
         => OPEN, LVTTL7 => OPEN, LVTTL8 => OPEN, LVTTL9 => OPEN, 
        LVTTL10 => OPEN, LVTTL11 => OPEN, PUFABn => OPEN, 
        VCC15GOOD => OPEN, VCC33GOOD => OPEN, FCLK => 
        MSS_ADLIB_INST_FCLK, MACCLKCCC => 
        MSS_ADLIB_INST_MACCLKCCC, RCOSC => GND_net, MACCLK => 
        MSS_ADLIB_INST_MACCLK, PLLLOCK => MSS_ADLIB_INST_PLLLOCK, 
        MSSRESETn => MSS_RESET_0_MSS_RESET_N_Y, GPOE(31) => nc94, 
        GPOE(30) => nc122, GPOE(29) => nc35, GPOE(28) => nc4, 
        GPOE(27) => nc92, GPOE(26) => nc101, GPOE(25) => nc132, 
        GPOE(24) => nc21, GPOE(23) => nc93, GPOE(22) => nc69, 
        GPOE(21) => nc38, GPOE(20) => nc113, GPOE(19) => nc106, 
        GPOE(18) => nc25, GPOE(17) => nc1, GPOE(16) => nc37, 
        GPOE(15) => nc144, GPOE(14) => nc153, GPOE(13) => nc46, 
        GPOE(12) => nc71, GPOE(11) => nc124, GPOE(10) => nc81, 
        GPOE(9) => nc34, GPOE(8) => nc28, GPOE(7) => nc115, 
        GPOE(6) => nc134, GPOE(5) => nc32, GPOE(4) => nc40, 
        GPOE(3) => nc99, GPOE(2) => nc75, GPOE(1) => nc85, 
        GPOE(0) => nc27, SPI0DO => OPEN, SPI0DOE => OPEN, SPI0DI
         => GND_net, SPI0CLKI => GND_net, SPI0CLKO => OPEN, 
        SPI0MODE => OPEN, SPI0SSI => GND_net, SPI0SSO(7) => nc108, 
        SPI0SSO(6) => nc16, SPI0SSO(5) => nc155, SPI0SSO(4) => 
        nc51, SPI0SSO(3) => nc33, SPI0SSO(2) => nc78, SPI0SSO(1)
         => nc24, SPI0SSO(0) => nc88, UART0TXD => 
        MSS_UART_0_TXD_D, UART0RXD => MSS_UART_0_RXD_Y, I2C0SDAI
         => GND_net, I2C0SDAO => OPEN, I2C0SCLI => GND_net, 
        I2C0SCLO => OPEN, SPI1DO => OPEN, SPI1DOE => OPEN, SPI1DI
         => GND_net, SPI1CLKI => GND_net, SPI1CLKO => OPEN, 
        SPI1MODE => OPEN, SPI1SSI => GND_net, SPI1SSO(7) => nc111, 
        SPI1SSO(6) => nc55, SPI1SSO(5) => nc10, SPI1SSO(4) => 
        nc22, SPI1SSO(3) => nc143, SPI1SSO(2) => nc77, SPI1SSO(1)
         => nc6, SPI1SSO(0) => nc109, UART1TXD => OPEN, UART1RXD
         => GND_net, I2C1SDAI => GND_net, I2C1SDAO => OPEN, 
        I2C1SCLI => GND_net, I2C1SCLO => OPEN, MACTXD(1) => nc87, 
        MACTXD(0) => nc123, MACRXD(1) => GND_net, MACRXD(0) => 
        GND_net, MACTXEN => OPEN, MACCRSDV => GND_net, MACRXER
         => GND_net, MACMDI => GND_net, MACMDO => OPEN, MACMDEN
         => OPEN, MACMDC => OPEN, EMCCLK => MSS_EMI_0_CLK_D, 
        EMCCLKRTN => MSS_EMI_0_CLK_D, EMCRDB(15) => 
        MSS_EMI_0_DB_15_Y, EMCRDB(14) => MSS_EMI_0_DB_14_Y, 
        EMCRDB(13) => MSS_EMI_0_DB_13_Y, EMCRDB(12) => 
        MSS_EMI_0_DB_12_Y, EMCRDB(11) => MSS_EMI_0_DB_11_Y, 
        EMCRDB(10) => MSS_EMI_0_DB_10_Y, EMCRDB(9) => 
        MSS_EMI_0_DB_9_Y, EMCRDB(8) => MSS_EMI_0_DB_8_Y, 
        EMCRDB(7) => MSS_EMI_0_DB_7_Y, EMCRDB(6) => 
        MSS_EMI_0_DB_6_Y, EMCRDB(5) => MSS_EMI_0_DB_5_Y, 
        EMCRDB(4) => MSS_EMI_0_DB_4_Y, EMCRDB(3) => 
        MSS_EMI_0_DB_3_Y, EMCRDB(2) => MSS_EMI_0_DB_2_Y, 
        EMCRDB(1) => MSS_EMI_0_DB_1_Y, EMCRDB(0) => 
        MSS_EMI_0_DB_0_Y, EMCAB(25) => MSS_EMI_0_AB_25_D, 
        EMCAB(24) => MSS_EMI_0_AB_24_D, EMCAB(23) => 
        MSS_EMI_0_AB_23_D, EMCAB(22) => MSS_EMI_0_AB_22_D, 
        EMCAB(21) => MSS_EMI_0_AB_21_D, EMCAB(20) => 
        MSS_EMI_0_AB_20_D, EMCAB(19) => MSS_EMI_0_AB_19_D, 
        EMCAB(18) => MSS_EMI_0_AB_18_D, EMCAB(17) => 
        MSS_EMI_0_AB_17_D, EMCAB(16) => MSS_EMI_0_AB_16_D, 
        EMCAB(15) => MSS_EMI_0_AB_15_D, EMCAB(14) => 
        MSS_EMI_0_AB_14_D, EMCAB(13) => MSS_EMI_0_AB_13_D, 
        EMCAB(12) => MSS_EMI_0_AB_12_D, EMCAB(11) => 
        MSS_EMI_0_AB_11_D, EMCAB(10) => MSS_EMI_0_AB_10_D, 
        EMCAB(9) => MSS_EMI_0_AB_9_D, EMCAB(8) => 
        MSS_EMI_0_AB_8_D, EMCAB(7) => MSS_EMI_0_AB_7_D, EMCAB(6)
         => MSS_EMI_0_AB_6_D, EMCAB(5) => MSS_EMI_0_AB_5_D, 
        EMCAB(4) => MSS_EMI_0_AB_4_D, EMCAB(3) => 
        MSS_EMI_0_AB_3_D, EMCAB(2) => MSS_EMI_0_AB_2_D, EMCAB(1)
         => MSS_EMI_0_AB_1_D, EMCAB(0) => MSS_EMI_0_AB_0_D, 
        EMCWDB(15) => MSS_EMI_0_DB_15_D, EMCWDB(14) => 
        MSS_EMI_0_DB_14_D, EMCWDB(13) => MSS_EMI_0_DB_13_D, 
        EMCWDB(12) => MSS_EMI_0_DB_12_D, EMCWDB(11) => 
        MSS_EMI_0_DB_11_D, EMCWDB(10) => MSS_EMI_0_DB_10_D, 
        EMCWDB(9) => MSS_EMI_0_DB_9_D, EMCWDB(8) => 
        MSS_EMI_0_DB_8_D, EMCWDB(7) => MSS_EMI_0_DB_7_D, 
        EMCWDB(6) => MSS_EMI_0_DB_6_D, EMCWDB(5) => 
        MSS_EMI_0_DB_5_D, EMCWDB(4) => MSS_EMI_0_DB_4_D, 
        EMCWDB(3) => MSS_EMI_0_DB_3_D, EMCWDB(2) => 
        MSS_EMI_0_DB_2_D, EMCWDB(1) => MSS_EMI_0_DB_1_D, 
        EMCWDB(0) => MSS_EMI_0_DB_0_D, EMCRWn => MSS_EMI_0_RW_N_D, 
        EMCCS0n => MSS_EMI_0_CS0_N_D, EMCCS1n => 
        MSS_EMI_0_CS1_N_D, EMCOEN0n => MSS_EMI_0_OEN0_N_D, 
        EMCOEN1n => MSS_EMI_0_OEN1_N_D, EMCBYTEN(1) => 
        MSS_EMI_0_BYTEN_1_D, EMCBYTEN(0) => MSS_EMI_0_BYTEN_0_D, 
        EMCDBOE => MSS_EMI_0_DB_15_E, ADC0 => MSS_ACE_0_ADC0_Y, 
        ADC1 => MSS_ACE_0_ADC1_Y, ADC2 => GND_net, ADC3 => 
        GND_net, ADC4 => MSS_ACE_0_ADC4_Y, ADC5 => 
        MSS_ACE_0_ADC5_Y, ADC6 => GND_net, ADC7 => GND_net, ADC8
         => MSS_ACE_0_ADC8_Y, ADC9 => MSS_ACE_0_ADC9_Y, ADC10 => 
        GND_net, ADC11 => GND_net, SDD0 => OPEN, SDD1 => OPEN, 
        SDD2 => OPEN, ABPS0 => GND_net, ABPS1 => GND_net, ABPS2
         => GND_net, ABPS3 => GND_net, ABPS4 => GND_net, ABPS5
         => GND_net, ABPS6 => GND_net, ABPS7 => GND_net, ABPS8
         => GND_net, ABPS9 => GND_net, ABPS10 => GND_net, ABPS11
         => GND_net, TM0 => GND_net, TM1 => GND_net, TM2 => 
        GND_net, TM3 => GND_net, TM4 => GND_net, TM5 => GND_net, 
        CM0 => GND_net, CM1 => GND_net, CM2 => GND_net, CM3 => 
        GND_net, CM4 => GND_net, CM5 => GND_net, GNDTM0 => 
        GND_net, GNDTM1 => GND_net, GNDTM2 => GND_net, VAREF0 => 
        MSS_ACE_0_VAREF0_Y, VAREF1 => MSS_ACE_0_VAREF1_Y, VAREF2
         => MSS_ACE_0_VAREF2_Y, VAREFOUT => OPEN, GNDVAREF => 
        GND_net, PUn => GND_net);
    
    MSS_EMI_0_AB_1 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A9")

      port map(D => MSS_EMI_0_AB_1_D, PAD => EMC_AB(1));
    
    MSSINT_GPI_3 : MSSINT
      port map(A => F2M_GPI_3, Y => MSSINT_GPI_3_Y);
    
    MSS_EMI_0_AB_0 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A8")

      port map(D => MSS_EMI_0_AB_0_D, PAD => EMC_AB(0));
    
    MSS_EMI_0_DB_15 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B1")

      port map(PAD => EMC_DB(15), D => MSS_EMI_0_DB_15_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_15_Y);
    
    MSS_EMI_0_DB_14 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C1")

      port map(PAD => EMC_DB(14), D => MSS_EMI_0_DB_14_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_14_Y);
    
    MSSINT_GPI_2 : MSSINT
      port map(A => F2M_GPI_2, Y => MSSINT_GPI_2_Y);
    
    MSSINT_GPI_0 : MSSINT
      port map(A => F2M_GPI_0, Y => MSSINT_GPI_0_Y);
    
    MSS_EMI_0_AB_10 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D11")

      port map(D => MSS_EMI_0_AB_10_D, PAD => EMC_AB(10));
    
    MSS_EMI_0_AB_11 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D12")

      port map(D => MSS_EMI_0_AB_11_D, PAD => EMC_AB(11));
    
    MSS_EMI_0_DB_9 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "G3")

      port map(PAD => EMC_DB(9), D => MSS_EMI_0_DB_9_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_9_Y);
    
    MSS_EMI_0_BYTEN_1 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C9")

      port map(D => MSS_EMI_0_BYTEN_1_D, PAD => EMC_BYTEN(1));
    
    MSS_ACE_0_VAREF1 : INBUF_A
      port map(PAD => VAREF1, Y => MSS_ACE_0_VAREF1_Y);
    
    MSS_EMI_0_AB_18 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B16")

      port map(D => MSS_EMI_0_AB_18_D, PAD => EMC_AB(18));
    
    MSS_EMI_0_DB_5 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "J2")

      port map(PAD => EMC_DB(5), D => MSS_EMI_0_DB_5_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_5_Y);
    
    MSS_EMI_0_DB_4 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "J3")

      port map(PAD => EMC_DB(4), D => MSS_EMI_0_DB_4_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_4_Y);
    
    MSS_UART_0_RXD : INBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "U18")

      port map(PAD => UART_0_RXD, Y => MSS_UART_0_RXD_Y);
    
    MSS_EMI_0_AB_9 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D13")

      port map(D => MSS_EMI_0_AB_9_D, PAD => EMC_AB(9));
    
    MSS_EMI_0_CLK : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C6")

      port map(D => MSS_EMI_0_CLK_D, PAD => EMC_CLK);
    
    MSS_EMI_0_DB_13 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D3")

      port map(PAD => EMC_DB(13), D => MSS_EMI_0_DB_13_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_13_Y);
    
    MSS_ACE_0_ADC4 : INBUF_A
      port map(PAD => ADC1_ch0, Y => MSS_ACE_0_ADC4_Y);
    
    MSS_UART_0_TXD : OUTBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "Y22")

      port map(D => MSS_UART_0_TXD_D, PAD => UART_0_TXD);
    
    MSS_EMI_0_CS0_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A5")

      port map(D => MSS_EMI_0_CS0_N_D, PAD => EMC_CS0_N);
    
    MSS_EMI_0_RW_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B6")

      port map(D => MSS_EMI_0_RW_N_D, PAD => EMC_RW_N);
    
    MSS_EMI_0_AB_5 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "E12")

      port map(D => MSS_EMI_0_AB_5_D, PAD => EMC_AB(5));
    
    MSS_EMI_0_DB_7 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "H1")

      port map(PAD => EMC_DB(7), D => MSS_EMI_0_DB_7_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_7_Y);
    

end DEF_ARCH; 
