`

    #Build: Synplify Pro E-2011.03A, Build 002R, Mar 15 2011
    #install: C:\Synopsys\synplify_E201103A
    #OS: Windows XP 5.1
    #Hostname: WXP-MARISETTIP

    #Implementation: synthesis

    #Fri Jul 29 16:28:51 2011

    $ Start of Compile
    #Fri Jul 29 16:28:51 2011

    Synopsys VHDL Compiler, version comp550rc, Build 051R, built Mar 22 2011
    @N: :  | Running in 32-bit mode
    Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    @N: : top_level_fan_control.vhd(8) | Top entity is set to top_level_fan_control.
    VHDL syntax check successful!
    File D:\Pavan\Projects\SmartFusion\FAN_Control\Fan_control_AN_20_june_all_tacho_working_2nd_3rd_tacho_values_are_same\Fan_control_AN\HW\component\Actel\SmartFusionMSS\MSS\2.5.6\mss_comps.vhd changed - recompiling
    File D:\Pavan\Projects\SmartFusion\FAN_Control\Fan_control_AN_20_june_all_tacho_working_2nd_3rd_tacho_values_are_same\Fan_control_AN\HW\component\work\mss_fan_control\mss_tshell.vhd changed - recompiling
    File D:\Pavan\Projects\SmartFusion\FAN_Control\Fan_control_AN_20_june_all_tacho_working_2nd_3rd_tacho_values_are_same\Fan_control_AN\HW\hdl\reg_if.vhd changed - recompiling
    File C:\Synopsys\synplify_E201103A\lib\vhd\unsigned.vhd changed - recompiling
    File C:\Synopsys\synplify_E201103A\lib\vhd\arith.vhd changed - recompiling
    File C:\Synopsys\synplify_E201103A\lib\vhd\numeric.vhd changed - recompiling
    File D:\Pavan\Projects\SmartFusion\FAN_Control\Fan_control_AN_20_june_all_tacho_working_2nd_3rd_tacho_values_are_same\Fan_control_AN\HW\hdl\timebase.vhd changed - recompiling
    File D:\Pavan\Projects\SmartFusion\FAN_Control\Fan_control_AN_20_june_all_tacho_working_2nd_3rd_tacho_values_are_same\Fan_control_AN\HW\hdl\pwm_gen.vhd changed - recompiling
    File D:\Pavan\Projects\SmartFusion\FAN_Control\Fan_control_AN_20_june_all_tacho_working_2nd_3rd_tacho_values_are_same\Fan_control_AN\HW\hdl\tach_measure.vhd changed - recompiling
    File D:\Pavan\Projects\SmartFusion\FAN_Control\Fan_control_AN_20_june_all_tacho_working_2nd_3rd_tacho_values_are_same\Fan_control_AN\HW\hdl\dig_sch_trig.vhd changed - recompiling
    File D:\Pavan\Projects\SmartFusion\FAN_Control\Fan_control_AN_20_june_all_tacho_working_2nd_3rd_tacho_values_are_same\Fan_control_AN\HW\component\work\mss_fan_control\MSS_CCC_0\mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd changed - recompiling
    File C:\Synopsys\synplify_E201103A\lib\proasic\smartfusion.vhd changed - recompiling
    File D:\Pavan\Projects\SmartFusion\FAN_Control\Fan_control_AN_20_june_all_tacho_working_2nd_3rd_tacho_values_are_same\Fan_control_AN\HW\component\work\mss_fan_control\mss_fan_control.vhd changed - recompiling
    File D:\Pavan\Projects\SmartFusion\FAN_Control\Fan_control_AN_20_june_all_tacho_working_2nd_3rd_tacho_values_are_same\Fan_control_AN\HW\hdl\pwm_top.vhd changed - recompiling
    File D:\Pavan\Projects\SmartFusion\FAN_Control\Fan_control_AN_20_june_all_tacho_working_2nd_3rd_tacho_values_are_same\Fan_control_AN\HW\hdl\top_level_tach_measure.vhd changed - recompiling
    File D:\Pavan\Projects\SmartFusion\FAN_Control\Fan_control_AN_20_june_all_tacho_working_2nd_3rd_tacho_values_are_same\Fan_control_AN\HW\hdl\pwm_n_tach.vhd changed - recompiling
    File D:\Pavan\Projects\SmartFusion\FAN_Control\Fan_control_AN_20_june_all_tacho_working_2nd_3rd_tacho_values_are_same\Fan_control_AN\HW\component\work\top_level_fan_control\top_level_fan_control.vhd changed - recompiling
    @N:CD630 : top_level_fan_control.vhd(8) | Synthesizing work.top_level_fan_control.def_arch
    @N:CD630 : smartfusion.vhd(1784) | Synthesizing smartfusion.gnd.syn_black_box
    Post processing for smartfusion.gnd.syn_black_box
    @N:CD630 : pwm_n_tach.vhd(24) | Synthesizing work.pwm_n_tach.pwm_n_tach
    @W:CD279 : pwm_n_tach.vhd(149) | Port tachout of component top_level_tach_measure not found on corresponding entity
    @W:CD730 : pwm_n_tach.vhd(243) | Component declaration has 13 ports but entity declares 12 ports
    @N:CD630 : dig_sch_trig.vhd(25) | Synthesizing work.dig_sch_trig.dig_sch_trig
    @N:CD233 : dig_sch_trig.vhd(38) | Using sequential encoding for type sch_trig_fsm
    Post processing for work.dig_sch_trig.dig_sch_trig
    @N:CD630 : top_level_tach_measure.vhd(26) | Synthesizing work.top_level_tach_measure.top_level_tach_measure
    @N:CD233 : top_level_tach_measure.vhd(44) | Using sequential encoding for type tach_tdm_fsm
    @N:CD630 : tach_measure.vhd(25) | Synthesizing work.tach_measure.tach_measure
    Post processing for work.tach_measure.tach_measure
    Post processing for work.top_level_tach_measure.top_level_tach_measure
    @W:CL190 : top_level_tach_measure.vhd(99) | Optimizing register bit PRDATA(26) to a constant 0
    @W:CL190 : top_level_tach_measure.vhd(99) | Optimizing register bit PRDATA(27) to a constant 0
    @W:CL190 : top_level_tach_measure.vhd(99) | Optimizing register bit PRDATA(28) to a constant 0
    @W:CL190 : top_level_tach_measure.vhd(99) | Optimizing register bit PRDATA(29) to a constant 0
    @W:CL190 : top_level_tach_measure.vhd(99) | Optimizing register bit PRDATA(30) to a constant 0
    @W:CL190 : top_level_tach_measure.vhd(99) | Optimizing register bit PRDATA(31) to a constant 0
    @W:CL260 : top_level_tach_measure.vhd(99) | Pruning Register bit 31 of PRDATA(31 downto 0)
    @W:CL260 : top_level_tach_measure.vhd(99) | Pruning Register bit 30 of PRDATA(31 downto 0)
    @W:CL260 : top_level_tach_measure.vhd(99) | Pruning Register bit 29 of PRDATA(31 downto 0)
    @W:CL260 : top_level_tach_measure.vhd(99) | Pruning Register bit 28 of PRDATA(31 downto 0)
    @W:CL260 : top_level_tach_measure.vhd(99) | Pruning Register bit 27 of PRDATA(31 downto 0)
    @W:CL260 : top_level_tach_measure.vhd(99) | Pruning Register bit 26 of PRDATA(31 downto 0)
    @N:CD630 : pwm_top.vhd(25) | Synthesizing work.pwm_top.pwm_top
    @N:CD630 : pwm_gen.vhd(27) | Synthesizing work.pwm_gen.trans
    @W:CD638 : pwm_gen.vhd(47) | Signal acc is undriven
    Post processing for work.pwm_gen.trans
    @N:CD630 : timebase.vhd(26) | Synthesizing work.timebase.trans
    Post processing for work.timebase.trans
    @N:CD630 : reg_if.vhd(25) | Synthesizing work.reg_if.trans
    @N:CD364 : reg_if.vhd(131) | Removed redundant assignment
    @W:CG296 : reg_if.vhd(263) | Incomplete sensitivity list - assuming completeness
    @W:CG290 : reg_if.vhd(271) | Referenced variable pwm_stretch is not in sensitivity list
    @W:CD796 : reg_if.vhd(77) | Bit 1 of signal pwm_enable_out_wire is undriven
    @W:CD796 : reg_if.vhd(77) | Bit 2 of signal pwm_enable_out_wire is undriven
    @W:CD796 : reg_if.vhd(77) | Bit 3 of signal pwm_enable_out_wire is undriven
    @W:CD796 : reg_if.vhd(77) | Bit 4 of signal pwm_enable_out_wire is undriven
    @W:CD796 : reg_if.vhd(77) | Bit 5 of signal pwm_enable_out_wire is undriven
    @W:CD796 : reg_if.vhd(77) | Bit 6 of signal pwm_enable_out_wire is undriven
    @W:CD796 : reg_if.vhd(77) | Bit 7 of signal pwm_enable_out_wire is undriven
    @W:CD796 : reg_if.vhd(77) | Bit 8 of signal pwm_enable_out_wire is undriven
    @W:CD796 : reg_if.vhd(77) | Bit 9 of signal pwm_enable_out_wire is undriven
    @W:CD796 : reg_if.vhd(77) | Bit 10 of signal pwm_enable_out_wire is undriven
    @W:CD796 : reg_if.vhd(77) | Bit 11 of signal pwm_enable_out_wire is undriven
    @W:CD796 : reg_if.vhd(77) | Bit 12 of signal pwm_enable_out_wire is undriven
    @W:CD796 : reg_if.vhd(77) | Bit 13 of signal pwm_enable_out_wire is undriven
    @W:CD796 : reg_if.vhd(77) | Bit 14 of signal pwm_enable_out_wire is undriven
    @W:CD796 : reg_if.vhd(77) | Bit 15 of signal pwm_enable_out_wire is undriven
    Post processing for work.reg_if.trans
    @W:CL169 : reg_if.vhd(192) | Pruning Register pwm_enable_reg(16 downto 1)
    @W:CL169 : reg_if.vhd(159) | Pruning Register pwm_negedge_reg(8 downto 1)
    @W:CL169 : reg_if.vhd(159) | Pruning Register pwm_posedge_reg(8 downto 1)
    @W:CL265 : reg_if.vhd(93) | Pruning bit 8 of psh_enable_reg1(8 downto 1) - not in use ...
    @W:CL265 : reg_if.vhd(93) | Pruning bit 7 of psh_enable_reg1(8 downto 1) - not in use ...
    @W:CL265 : reg_if.vhd(93) | Pruning bit 6 of psh_enable_reg1(8 downto 1) - not in use ...
    @W:CL265 : reg_if.vhd(93) | Pruning bit 5 of psh_enable_reg1(8 downto 1) - not in use ...
    @W:CL265 : reg_if.vhd(93) | Pruning bit 4 of psh_enable_reg1(8 downto 1) - not in use ...
    @W:CL265 : reg_if.vhd(93) | Pruning bit 3 of psh_enable_reg1(8 downto 1) - not in use ...
    @W:CL265 : reg_if.vhd(93) | Pruning bit 2 of psh_enable_reg1(8 downto 1) - not in use ...
    Post processing for work.pwm_top.pwm_top
    Post processing for work.pwm_n_tach.pwm_n_tach
    @N:CD630 : smartfusion.vhd(2742) | Synthesizing smartfusion.vcc.syn_black_box
    Post processing for smartfusion.vcc.syn_black_box
    @N:CD630 : mss_fan_control.vhd(8) | Synthesizing work.mss_fan_control.def_arch
    @N:CD630 : mss_comps.vhd(4) | Synthesizing work.inbuf_mss.def_arch
    Post processing for work.inbuf_mss.def_arch
    @N:CD630 : mss_tshell.vhd(4) | Synthesizing work.mss_apb.def_arch
    Post processing for work.mss_apb.def_arch
    @N:CD630 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(8) | Synthesizing work.mss_fan_control_tmp_mss_ccc_0_mss_ccc.def_arch
    @N:CD630 : mss_comps.vhd(432) | Synthesizing work.mss_xtlosc.def_arch
    Post processing for work.mss_xtlosc.def_arch
    @N:CD630 : mss_comps.vhd(472) | Synthesizing work.mss_ccc.def_arch
    Post processing for work.mss_ccc.def_arch
    Post processing for work.mss_fan_control_tmp_mss_ccc_0_mss_ccc.def_arch
    @W:CL240 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(38) | LPXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(37) | MAINXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(36) | RCOSC_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible
    @N:CD630 : mss_comps.vhd(24) | Synthesizing work.outbuf_mss.def_arch
    Post processing for work.outbuf_mss.def_arch
    Post processing for work.mss_fan_control.def_arch
    Post processing for work.top_level_fan_control.def_arch
    @W:CL168 : top_level_fan_control.vhd(461) | Pruning instance 	GND - not in use ...
    @W:CL168 : top_level_fan_control.vhd(321) | Pruning instance 	VCC - not in use ...
    @W:CL159 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(10) | Input CLKA is unused
    @W:CL159 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(11) | Input CLKA_PAD is unused
    @W:CL159 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(12) | Input CLKA_PADP is unused
    @W:CL159 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(13) | Input CLKA_PADN is unused
    @W:CL159 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(14) | Input CLKB is unused
    @W:CL159 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(15) | Input CLKB_PAD is unused
    @W:CL159 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(16) | Input CLKB_PADP is unused
    @W:CL159 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(17) | Input CLKB_PADN is unused
    @W:CL159 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(18) | Input CLKC is unused
    @W:CL159 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(19) | Input CLKC_PAD is unused
    @W:CL159 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(20) | Input CLKC_PADP is unused
    @W:CL159 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(21) | Input CLKC_PADN is unused
    @W:CL159 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(23) | Input LPXIN is unused
    @W:CL159 : mss_fan_control_tmp_MSS_CCC_0_MSS_CCC.vhd(24) | Input MAC_CLK is unused
    @W:CL246 : pwm_top.vhd(68) | Input port bits 1 to 0 of paddr(7 downto 0) are unused
    @W:CL159 : tach_measure.vhd(30) | Input read_done is unused
    @W:CL246 : top_level_tach_measure.vhd(34) | Input port bits 7 to 4 of pwdata(7 downto 0) are unused
    @N:CL201 : dig_sch_trig.vhd(59) | Trying to extract state machine for register sch_trig_current_state
    Extracted state machine for register sch_trig_current_state
    State machine has 4 reachable states with original encodings of:
       00
       01
       10
       11
    @W:CL246 : pwm_n_tach.vhd(68) | Input port bits 31 to 8 of pwdata(31 downto 0) are unused
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Jul 29 16:28:51 2011

    ###########################################################]

`
Pre-mapping Report (contents appended below) @N: : top_level_fan_control_premapping.srr | "C:\Actelprj\A2F_AC377_DF\HW\synthesis\synlog\top_level_fan_control_premapping.srr" Synopsys Actel Technology Mapper, Version mapact, Build 405R, Built Mar 31 2011 09:15:44 Copyright (C) 1994-2011, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version E-2011.03A @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:BN132 : top_level_tach_measure.vhd(115) | Removing sequential instance tach_count_en, because it is equivalent to instance pulse_stretch Finished Pre Mapping Phase. (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) @N:BN225 : | Writing default property annotation file C:\Actelprj\A2F_AC377_DF\HW\synthesis\top_level_fan_control.sap. Pre Mapping successful! Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Jul 29 16:28:53 2011 ###########################################################] Mapping Report (contents appended below) @N: : top_level_fan_control_SmartFusion_Mapper.srr | "C:\Actelprj\A2F_AC377_DF\HW\synthesis\synlog\top_level_fan_control_SmartFusion_Mapper.srr" Synopsys Actel Technology Mapper, Version mapact, Build 405R, Built Mar 31 2011 09:15:44 Copyright (C) 1994-2011, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version E-2011.03A @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO111 : reg_if.vhd(214) | tristate driver un1_psh_enable_reg1_tri7 on net un1_psh_enable_reg1_tri7 has its enable tied to GND (module reg_if) @W:MO111 : reg_if.vhd(214) | tristate driver un1_psh_enable_reg1_tri6 on net un1_psh_enable_reg1_tri6 has its enable tied to GND (module reg_if) @W:MO111 : reg_if.vhd(214) | tristate driver un1_psh_enable_reg1_tri5 on net un1_psh_enable_reg1_tri5 has its enable tied to GND (module reg_if) @W:MO111 : reg_if.vhd(214) | tristate driver un1_psh_enable_reg1_tri4 on net un1_psh_enable_reg1_tri4 has its enable tied to GND (module reg_if) @W:MO111 : reg_if.vhd(214) | tristate driver un1_psh_enable_reg1_tri3 on net un1_psh_enable_reg1_tri3 has its enable tied to GND (module reg_if) @W:MO111 : reg_if.vhd(214) | tristate driver un1_psh_enable_reg1_tri2 on net un1_psh_enable_reg1_tri2 has its enable tied to GND (module reg_if) @W:MO111 : reg_if.vhd(214) | tristate driver un1_psh_enable_reg1_tri1 on net un1_psh_enable_reg1_tri1 has its enable tied to GND (module reg_if) Available hyper_sources - for debug and ip models None Found @W:MT462 : mss_fan_control_tmp_mss_ccc_0_mss_ccc.vhd(118) | Net mss_fan_control_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. @W:MT462 : mss_fan_control_tmp_mss_ccc_0_mss_ccc.vhd(118) | Net pwm_n_tach_0.PCLK appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) @N:MF179 : reg_if.vhd(201) | Found 8 bit by 8 bit '<' comparator, 'G2\.1\.un1_period_cnt' @N:MF179 : reg_if.vhd(201) | Found 8 bit by 8 bit '<' comparator, 'G2\.1\.un1_period_cnt' @N:BN115 : reg_if.vhd(201) | Removing instance G2\.1\.un1_period_cnt_2 of view:VhdlGenLib.CMP_LT__w8(fcomp) because there are no references to its outputs @N: : timebase.vhd(61) | Found counter in view:work.timebase(trans) inst period_cnt_int[7:0] @N: : timebase.vhd(48) | Found counter in view:work.timebase(trans) inst prescale_cnt[7:0] @N:MF179 : timebase.vhd(64) | Found 8 bit by 8 bit '<' comparator, 'un1_period_cnt_int' @N:MF179 : timebase.vhd(72) | Found 8 bit by 8 bit '<' comparator, 'sync_pulse_1' @N: : tach_measure.vhd(96) | Found counter in view:work.tach_measure(tach_measure) inst tach_count[23:0] @N: : tach_measure.vhd(68) | Found counter in view:work.tach_measure(tach_measure) inst edge_cntr[3:0] @N: : dig_sch_trig.vhd(111) | Found counter in view:work.dig_sch_trig(dig_sch_trig) inst raise_count[8:0] Encoding state machine work.dig_sch_trig(dig_sch_trig)-sch_trig_current_state[0:3] original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 59MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 59MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 59MB) Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 59MB) Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 59MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 59MB) Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 60MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes -------------------------------------------------------------------------------------------- mss_fan_control_0.MSS_CCC_0.I_MSSCCC / GLA 175 mss_fan_control_0.MSS_ADLIB_INST / M2FRESETn 174 : 174 asynchronous set/reset pwm_n_tach_0.xhdl51.un5_prdata / Y 27 pwm_n_tach_0.tach_inst.tach_measure_inst.count_done / Q 26 pwm_n_tach_0.tach_inst.TACHREAD_REG_p.un24_pclk / Y 27 ============================================================================================ Replicating Combinational Instance pwm_n_tach_0.tach_inst.TACHREAD_REG_p.un24_pclk, fanout 27 segments 2 Replicating Sequential Instance pwm_n_tach_0.tach_inst.tach_measure_inst.count_done, fanout 26 segments 2 Replicating Combinational Instance pwm_n_tach_0.xhdl51.un5_prdata, fanout 27 segments 2 Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 60MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 60MB) Added 0 Buffers Added 3 Cells via replication Added 1 Sequential Cells via replication Added 2 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 60MB peak: 60MB) Writing Analyst data base C:\Actelprj\A2F_AC377_DF\HW\synthesis\top_level_fan_control.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 60MB) Writing EDIF Netlist and constraint files E-2011.03A Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 60MB) @W:MT246 : mss_fan_control_tmp_mss_ccc_0_mss_ccc.vhd(156) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock mss_fan_control|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:mss_fan_control_0.MSS_ADLIB_INST_EMCCLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Jul 29 16:28:55 2011 # Top view: top_level_fan_control Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -14.766 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------- System 100.0 MHz 40.4 MHz 10.000 24.766 -14.766 system system_clkgroup ================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------- System System | 10.000 -14.766 | No paths - | No paths - | No paths - ========================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------- pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[0] System DFN1C0 Q tach_count[0] 0.580 -14.766 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[1] System DFN1C0 Q tach_count[1] 0.580 -14.361 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[2] System DFN1C0 Q tach_count[2] 0.580 -13.378 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[3] System DFN1C0 Q tach_count[3] 0.580 -12.564 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[4] System DFN1C0 Q tach_count[4] 0.580 -11.634 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[5] System DFN1C0 Q tach_count[5] 0.580 -10.733 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[6] System DFN1C0 Q tach_count[6] 0.580 -9.831 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[7] System DFN1C0 Q tach_count[7] 0.580 -9.012 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[8] System DFN1C0 Q tach_count[8] 0.580 -8.677 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[9] System DFN1C0 Q tach_count[9] 0.580 -7.095 ================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------ pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[23] System DFN1C0 D tach_count_n23 9.461 -14.766 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[22] System DFN1C0 D tach_count_n22 9.461 -13.798 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[21] System DFN1C0 D tach_count_n21 9.461 -12.766 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[20] System DFN1C0 D tach_count_n20 9.461 -11.733 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[19] System DFN1C0 D tach_count_n19 9.461 -10.701 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[18] System DFN1C0 D tach_count_n18 9.427 -9.881 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[17] System DFN1C0 D tach_count_n17 9.461 -9.007 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[16] System DFN1C0 D tach_count_n16 9.461 -7.975 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[15] System DFN1C0 D tach_count_n15 9.461 -6.942 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[14] System DFN1C0 D tach_count_n14 9.461 -5.910 ==================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 9.461 - Propagation time: 24.227 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : -14.766 Number of logic level(s): 22 Starting point: pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[0] / Q Ending point: pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[23] / D The start point is clocked by System [rising] on pin CLK The end point is clocked by System [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[0] DFN1C0 Q Out 0.580 0.580 - tach_count[0] Net - - 1.184 - 4 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID6H5[1] OR2B B In - 1.764 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID6H5[1] OR2B Y Out 0.516 2.280 - N_35 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNILV98[2] OR2A B In - 2.666 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNILV98[2] OR2A Y Out 0.646 3.312 - N_36 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUS2B[3] NOR2A B In - 3.698 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUS2B[3] NOR2A Y Out 0.407 4.105 - N_37 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI8URD[4] NOR2B B In - 4.491 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI8URD[4] NOR2B Y Out 0.516 5.007 - N_38 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJ3LG[5] NOR2B B In - 5.393 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJ3LG[5] NOR2B Y Out 0.516 5.909 - N_39 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIVCEJ[6] NOR2B B In - 6.294 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIVCEJ[6] NOR2B Y Out 0.516 6.811 - N_40 Net - - 0.806 - 3 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIQB1P[8] OR3C A In - 7.617 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIQB1P[8] OR3C Y Out 0.525 8.142 - N_42 Net - - 0.806 - 3 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI91RR[9] OR2A B In - 8.948 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI91RR[9] OR2A Y Out 0.646 9.595 - N_43 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIA5O31[10] OR2A B In - 9.980 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIA5O31[10] OR2A Y Out 0.646 10.627 - N_44 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIC9LB1[11] OR2A B In - 11.013 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIC9LB1[11] OR2A Y Out 0.646 11.659 - N_45 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIFDIJ1[12] OR2A B In - 12.045 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIFDIJ1[12] OR2A Y Out 0.646 12.692 - N_46 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJHFR1[13] OR2A B In - 13.077 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJHFR1[13] OR2A Y Out 0.646 13.724 - N_47 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIOLC32[14] OR2A B In - 14.110 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIOLC32[14] OR2A Y Out 0.646 14.756 - N_48 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUP9B2[15] OR2A B In - 15.142 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUP9B2[15] OR2A Y Out 0.646 15.788 - N_49 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI5U6J2[16] OR2A B In - 16.174 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI5U6J2[16] OR2A Y Out 0.646 16.821 - N_50 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID24R2[17] NOR2A B In - 17.206 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID24R2[17] NOR2A Y Out 0.407 17.613 - N_51 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIM6133[18] OR2B B In - 17.999 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIM6133[18] OR2B Y Out 0.516 18.515 - N_52 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI0BUA3[19] OR2A B In - 18.901 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI0BUA3[19] OR2A Y Out 0.646 19.547 - N_53 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI4JRI3[20] OR2A B In - 19.933 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI4JRI3[20] OR2A Y Out 0.646 20.580 - N_54 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI9ROQ3[21] OR2A B In - 20.965 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI9ROQ3[21] OR2A Y Out 0.646 21.612 - N_55 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO_0[23] OR2A B In - 21.998 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO_0[23] OR2A Y Out 0.646 22.644 - N_56 Net - - 0.322 - 1 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO[23] XA1A B In - 22.966 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO[23] XA1A Y Out 0.940 23.906 - tach_count_n23 Net - - 0.322 - 1 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[23] DFN1C0 D In - 24.227 - ================================================================================================================================= Total path delay (propagation time + setup) of 24.766 is 14.382(58.1%) logic and 10.384(41.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 9.461 - Propagation time: 23.822 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -14.361 Number of logic level(s): 22 Starting point: pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[1] / Q Ending point: pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[23] / D The start point is clocked by System [rising] on pin CLK The end point is clocked by System [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[1] DFN1C0 Q Out 0.580 0.580 - tach_count[1] Net - - 0.806 - 3 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID6H5[1] OR2B A In - 1.387 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID6H5[1] OR2B Y Out 0.488 1.875 - N_35 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNILV98[2] OR2A B In - 2.261 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNILV98[2] OR2A Y Out 0.646 2.907 - N_36 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUS2B[3] NOR2A B In - 3.293 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUS2B[3] NOR2A Y Out 0.407 3.700 - N_37 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI8URD[4] NOR2B B In - 4.086 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI8URD[4] NOR2B Y Out 0.516 4.602 - N_38 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJ3LG[5] NOR2B B In - 4.987 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJ3LG[5] NOR2B Y Out 0.516 5.504 - N_39 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIVCEJ[6] NOR2B B In - 5.889 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIVCEJ[6] NOR2B Y Out 0.516 6.406 - N_40 Net - - 0.806 - 3 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIQB1P[8] OR3C A In - 7.212 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIQB1P[8] OR3C Y Out 0.525 7.737 - N_42 Net - - 0.806 - 3 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI91RR[9] OR2A B In - 8.543 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI91RR[9] OR2A Y Out 0.646 9.190 - N_43 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIA5O31[10] OR2A B In - 9.575 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIA5O31[10] OR2A Y Out 0.646 10.222 - N_44 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIC9LB1[11] OR2A B In - 10.608 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIC9LB1[11] OR2A Y Out 0.646 11.254 - N_45 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIFDIJ1[12] OR2A B In - 11.640 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIFDIJ1[12] OR2A Y Out 0.646 12.287 - N_46 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJHFR1[13] OR2A B In - 12.672 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJHFR1[13] OR2A Y Out 0.646 13.319 - N_47 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIOLC32[14] OR2A B In - 13.705 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIOLC32[14] OR2A Y Out 0.646 14.351 - N_48 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUP9B2[15] OR2A B In - 14.737 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUP9B2[15] OR2A Y Out 0.646 15.383 - N_49 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI5U6J2[16] OR2A B In - 15.769 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI5U6J2[16] OR2A Y Out 0.646 16.416 - N_50 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID24R2[17] NOR2A B In - 16.802 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID24R2[17] NOR2A Y Out 0.407 17.208 - N_51 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIM6133[18] OR2B B In - 17.594 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIM6133[18] OR2B Y Out 0.516 18.110 - N_52 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI0BUA3[19] OR2A B In - 18.496 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI0BUA3[19] OR2A Y Out 0.646 19.142 - N_53 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI4JRI3[20] OR2A B In - 19.528 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI4JRI3[20] OR2A Y Out 0.646 20.175 - N_54 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI9ROQ3[21] OR2A B In - 20.560 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI9ROQ3[21] OR2A Y Out 0.646 21.207 - N_55 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO_0[23] OR2A B In - 21.593 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO_0[23] OR2A Y Out 0.646 22.239 - N_56 Net - - 0.322 - 1 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO[23] XA1A B In - 22.561 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO[23] XA1A Y Out 0.940 23.501 - tach_count_n23 Net - - 0.322 - 1 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[23] DFN1C0 D In - 23.822 - ================================================================================================================================= Total path delay (propagation time + setup) of 24.361 is 14.354(58.9%) logic and 10.007(41.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 9.461 - Propagation time: 23.259 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -13.798 Number of logic level(s): 21 Starting point: pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[0] / Q Ending point: pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[22] / D The start point is clocked by System [rising] on pin CLK The end point is clocked by System [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[0] DFN1C0 Q Out 0.580 0.580 - tach_count[0] Net - - 1.184 - 4 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID6H5[1] OR2B B In - 1.764 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID6H5[1] OR2B Y Out 0.516 2.280 - N_35 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNILV98[2] OR2A B In - 2.666 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNILV98[2] OR2A Y Out 0.646 3.312 - N_36 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUS2B[3] NOR2A B In - 3.698 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUS2B[3] NOR2A Y Out 0.407 4.105 - N_37 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI8URD[4] NOR2B B In - 4.491 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI8URD[4] NOR2B Y Out 0.516 5.007 - N_38 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJ3LG[5] NOR2B B In - 5.393 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJ3LG[5] NOR2B Y Out 0.516 5.909 - N_39 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIVCEJ[6] NOR2B B In - 6.294 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIVCEJ[6] NOR2B Y Out 0.516 6.811 - N_40 Net - - 0.806 - 3 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIQB1P[8] OR3C A In - 7.617 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIQB1P[8] OR3C Y Out 0.525 8.142 - N_42 Net - - 0.806 - 3 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI91RR[9] OR2A B In - 8.948 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI91RR[9] OR2A Y Out 0.646 9.595 - N_43 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIA5O31[10] OR2A B In - 9.980 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIA5O31[10] OR2A Y Out 0.646 10.627 - N_44 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIC9LB1[11] OR2A B In - 11.013 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIC9LB1[11] OR2A Y Out 0.646 11.659 - N_45 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIFDIJ1[12] OR2A B In - 12.045 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIFDIJ1[12] OR2A Y Out 0.646 12.692 - N_46 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJHFR1[13] OR2A B In - 13.077 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJHFR1[13] OR2A Y Out 0.646 13.724 - N_47 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIOLC32[14] OR2A B In - 14.110 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIOLC32[14] OR2A Y Out 0.646 14.756 - N_48 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUP9B2[15] OR2A B In - 15.142 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUP9B2[15] OR2A Y Out 0.646 15.788 - N_49 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI5U6J2[16] OR2A B In - 16.174 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI5U6J2[16] OR2A Y Out 0.646 16.821 - N_50 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID24R2[17] NOR2A B In - 17.206 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID24R2[17] NOR2A Y Out 0.407 17.613 - N_51 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIM6133[18] OR2B B In - 17.999 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIM6133[18] OR2B Y Out 0.516 18.515 - N_52 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI0BUA3[19] OR2A B In - 18.901 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI0BUA3[19] OR2A Y Out 0.646 19.547 - N_53 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI4JRI3[20] OR2A B In - 19.933 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI4JRI3[20] OR2A Y Out 0.646 20.580 - N_54 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI9ROQ3[21] OR2A B In - 20.965 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI9ROQ3[21] OR2A Y Out 0.646 21.612 - N_55 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO[22] XA1A B In - 21.998 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO[22] XA1A Y Out 0.940 22.938 - tach_count_n22 Net - - 0.322 - 1 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[22] DFN1C0 D In - 23.259 - ================================================================================================================================= Total path delay (propagation time + setup) of 23.798 is 13.736(57.7%) logic and 10.062(42.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 9.461 - Propagation time: 22.854 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -13.393 Number of logic level(s): 21 Starting point: pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[1] / Q Ending point: pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[22] / D The start point is clocked by System [rising] on pin CLK The end point is clocked by System [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[1] DFN1C0 Q Out 0.580 0.580 - tach_count[1] Net - - 0.806 - 3 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID6H5[1] OR2B A In - 1.387 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID6H5[1] OR2B Y Out 0.488 1.875 - N_35 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNILV98[2] OR2A B In - 2.261 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNILV98[2] OR2A Y Out 0.646 2.907 - N_36 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUS2B[3] NOR2A B In - 3.293 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUS2B[3] NOR2A Y Out 0.407 3.700 - N_37 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI8URD[4] NOR2B B In - 4.086 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI8URD[4] NOR2B Y Out 0.516 4.602 - N_38 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJ3LG[5] NOR2B B In - 4.987 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJ3LG[5] NOR2B Y Out 0.516 5.504 - N_39 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIVCEJ[6] NOR2B B In - 5.889 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIVCEJ[6] NOR2B Y Out 0.516 6.406 - N_40 Net - - 0.806 - 3 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIQB1P[8] OR3C A In - 7.212 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIQB1P[8] OR3C Y Out 0.525 7.737 - N_42 Net - - 0.806 - 3 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI91RR[9] OR2A B In - 8.543 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI91RR[9] OR2A Y Out 0.646 9.190 - N_43 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIA5O31[10] OR2A B In - 9.575 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIA5O31[10] OR2A Y Out 0.646 10.222 - N_44 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIC9LB1[11] OR2A B In - 10.608 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIC9LB1[11] OR2A Y Out 0.646 11.254 - N_45 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIFDIJ1[12] OR2A B In - 11.640 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIFDIJ1[12] OR2A Y Out 0.646 12.287 - N_46 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJHFR1[13] OR2A B In - 12.672 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJHFR1[13] OR2A Y Out 0.646 13.319 - N_47 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIOLC32[14] OR2A B In - 13.705 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIOLC32[14] OR2A Y Out 0.646 14.351 - N_48 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUP9B2[15] OR2A B In - 14.737 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUP9B2[15] OR2A Y Out 0.646 15.383 - N_49 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI5U6J2[16] OR2A B In - 15.769 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI5U6J2[16] OR2A Y Out 0.646 16.416 - N_50 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID24R2[17] NOR2A B In - 16.802 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID24R2[17] NOR2A Y Out 0.407 17.208 - N_51 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIM6133[18] OR2B B In - 17.594 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIM6133[18] OR2B Y Out 0.516 18.110 - N_52 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI0BUA3[19] OR2A B In - 18.496 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI0BUA3[19] OR2A Y Out 0.646 19.142 - N_53 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI4JRI3[20] OR2A B In - 19.528 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI4JRI3[20] OR2A Y Out 0.646 20.175 - N_54 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI9ROQ3[21] OR2A B In - 20.560 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI9ROQ3[21] OR2A Y Out 0.646 21.207 - N_55 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO[22] XA1A B In - 21.593 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO[22] XA1A Y Out 0.940 22.533 - tach_count_n22 Net - - 0.322 - 1 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[22] DFN1C0 D In - 22.854 - ================================================================================================================================= Total path delay (propagation time + setup) of 23.393 is 13.708(58.6%) logic and 9.685(41.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 9.461 - Propagation time: 22.839 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -13.378 Number of logic level(s): 21 Starting point: pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[2] / Q Ending point: pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[23] / D The start point is clocked by System [rising] on pin CLK The end point is clocked by System [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[2] DFN1C0 Q Out 0.580 0.580 - tach_count[2] Net - - 0.806 - 3 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNILV98[2] OR2A A In - 1.387 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNILV98[2] OR2A Y Out 0.537 1.924 - N_36 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUS2B[3] NOR2A B In - 2.310 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUS2B[3] NOR2A Y Out 0.407 2.716 - N_37 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI8URD[4] NOR2B B In - 3.102 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI8URD[4] NOR2B Y Out 0.516 3.618 - N_38 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJ3LG[5] NOR2B B In - 4.004 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJ3LG[5] NOR2B Y Out 0.516 4.520 - N_39 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIVCEJ[6] NOR2B B In - 4.906 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIVCEJ[6] NOR2B Y Out 0.516 5.422 - N_40 Net - - 0.806 - 3 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIQB1P[8] OR3C A In - 6.228 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIQB1P[8] OR3C Y Out 0.525 6.753 - N_42 Net - - 0.806 - 3 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI91RR[9] OR2A B In - 7.559 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI91RR[9] OR2A Y Out 0.646 8.206 - N_43 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIA5O31[10] OR2A B In - 8.592 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIA5O31[10] OR2A Y Out 0.646 9.238 - N_44 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIC9LB1[11] OR2A B In - 9.624 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIC9LB1[11] OR2A Y Out 0.646 10.271 - N_45 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIFDIJ1[12] OR2A B In - 10.656 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIFDIJ1[12] OR2A Y Out 0.646 11.303 - N_46 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJHFR1[13] OR2A B In - 11.689 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIJHFR1[13] OR2A Y Out 0.646 12.335 - N_47 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIOLC32[14] OR2A B In - 12.721 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIOLC32[14] OR2A Y Out 0.646 13.368 - N_48 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUP9B2[15] OR2A B In - 13.753 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIUP9B2[15] OR2A Y Out 0.646 14.400 - N_49 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI5U6J2[16] OR2A B In - 14.786 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI5U6J2[16] OR2A Y Out 0.646 15.432 - N_50 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID24R2[17] NOR2A B In - 15.818 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNID24R2[17] NOR2A Y Out 0.407 16.224 - N_51 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIM6133[18] OR2B B In - 16.610 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNIM6133[18] OR2B Y Out 0.516 17.126 - N_52 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI0BUA3[19] OR2A B In - 17.512 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI0BUA3[19] OR2A Y Out 0.646 18.159 - N_53 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI4JRI3[20] OR2A B In - 18.544 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI4JRI3[20] OR2A Y Out 0.646 19.191 - N_54 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI9ROQ3[21] OR2A B In - 19.577 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNI9ROQ3[21] OR2A Y Out 0.646 20.223 - N_55 Net - - 0.386 - 2 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO_0[23] OR2A B In - 20.609 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO_0[23] OR2A Y Out 0.646 21.256 - N_56 Net - - 0.322 - 1 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO[23] XA1A B In - 21.577 - pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count_RNO[23] XA1A Y Out 0.940 22.517 - tach_count_n23 Net - - 0.322 - 1 pwm_n_tach_0.tach_inst.tach_measure_inst.tach_count[23] DFN1C0 D In - 22.839 - ================================================================================================================================= Total path delay (propagation time + setup) of 23.377 is 13.757(58.8%) logic and 9.621(41.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F200M3F_FBGA256_Std Report for cell top_level_fan_control.def_arch Core Cell usage: cell count area count*area AND2A 6 1.0 6.0 AND3 3 1.0 3.0 AO1 7 1.0 7.0 AO13 1 1.0 1.0 AO16 1 1.0 1.0 AO1A 1 1.0 1.0 AO1B 3 1.0 3.0 AO1C 9 1.0 9.0 AOI1 4 1.0 4.0 AOI1A 6 1.0 6.0 AOI1B 3 1.0 3.0 GND 11 0.0 0.0 MSS_CCC 1 0.0 0.0 MX2 22 1.0 22.0 MX2B 1 1.0 1.0 MX2C 16 1.0 16.0 NOR2 10 1.0 10.0 NOR2A 39 1.0 39.0 NOR2B 18 1.0 18.0 NOR3 12 1.0 12.0 NOR3A 4 1.0 4.0 NOR3B 17 1.0 17.0 NOR3C 12 1.0 12.0 OA1 4 1.0 4.0 OA1A 7 1.0 7.0 OA1C 3 1.0 3.0 OAI1 1 1.0 1.0 OR2 6 1.0 6.0 OR2A 34 1.0 34.0 OR2B 10 1.0 10.0 OR3 1 1.0 1.0 OR3A 2 1.0 2.0 OR3B 1 1.0 1.0 OR3C 5 1.0 5.0 VCC 11 0.0 0.0 XA1 17 1.0 17.0 XA1A 28 1.0 28.0 XA1B 8 1.0 8.0 XA1C 1 1.0 1.0 XNOR2 30 1.0 30.0 DFN1C0 53 1.0 53.0 DFN1E0C0 2 1.0 2.0 DFN1E1C0 116 1.0 116.0 DFN1E1P0 4 1.0 4.0 MSS_APB 1 0.0 0.0 ----- ---------- TOTAL 552 528.0 IO Cell usage: cell count INBUF 4 INBUF_MSS 2 MSS_XTLOSC 1 OUTBUF 1 OUTBUF_MSS 1 ----- TOTAL 9 Core Cells : 528 of 4608 (11%) IO Cells : 9 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Jul 29 16:28:55 2011 ###########################################################]