#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 #install: D:\libero9.1_installation\Libero_v9.1\Synopsys\synplify_E201009A-1 #OS: Windows XP 5.1 #Hostname: WXPL-DONTHUS #Implementation: synthesis #Wed Aug 03 16:48:21 2011 $ Start of Compile #Wed Aug 03 16:48:21 2011 Synopsys VHDL Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 @N: : | Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : TOP_FLAC_PLAYER.vhd(8) | Top entity is set to TOP_FLAC_PLAYER. VHDL syntax check successful! File D:\temp4\A2F500_dac4\SmartFusion_FLAC_HW\component\Actel\SmartFusionMSS\MSS\2.4.105\mss_comps.vhd changed - recompiling File D:\temp4\A2F500_dac4\SmartFusion_FLAC_HW\component\work\MSS_FLAC_PLAYER\mss_tshell.vhd changed - recompiling File D:\temp4\A2F500_dac4\SmartFusion_FLAC_HW\hdl\player.vhd changed - recompiling File D:\temp4\A2F500_dac4\SmartFusion_FLAC_HW\smartgen\multi16\multi16.vhd changed - recompiling File D:\temp4\A2F500_dac4\SmartFusion_FLAC_HW\hdl\shifter_r.vhd changed - recompiling File D:\temp4\A2F500_dac4\SmartFusion_FLAC_HW\hdl\shifter.vhd changed - recompiling File D:\temp4\A2F500_dac4\SmartFusion_FLAC_HW\component\work\MSS_FLAC_PLAYER\MSS_CCC_0\MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd changed - recompiling File D:\temp4\A2F500_dac4\SmartFusion_FLAC_HW\component\work\MSS_FLAC_PLAYER\MSS_FLAC_PLAYER.vhd changed - recompiling File D:\temp4\A2F500_dac4\SmartFusion_FLAC_HW\hdl\LPC.vhd changed - recompiling File D:\temp4\A2F500_dac4\SmartFusion_FLAC_HW\hdl\RICE.vhd changed - recompiling File D:\temp4\A2F500_dac4\SmartFusion_FLAC_HW\hdl\FLAC_DECODER.vhd changed - recompiling File D:\temp4\A2F500_dac4\SmartFusion_FLAC_HW\component\work\TOP_FLAC_PLAYER\TOP_FLAC_PLAYER.vhd changed - recompiling @N:CD630 : TOP_FLAC_PLAYER.vhd(8) | Synthesizing work.top_flac_player.def_arch @N:CD630 : smartfusion.vhd(1784) | Synthesizing smartfusion.gnd.syn_black_box Post processing for smartfusion.gnd.syn_black_box @N:CD630 : FLAC_DECODER.vhd(22) | Synthesizing work.flac_decoder.struct @N:CD630 : player.vhd(21) | Synthesizing work.player.beh @N:CD231 : player.vhd(57) | Using onehot encoding for type state_type (idle="100000000") @W:CD604 : player.vhd(164) | OTHERS clause is not synthesized Post processing for work.player.beh @W:CL240 : player.vhd(35) | SPSLVERR is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : player.vhd(34) | SPRDATA is not assigned a value (floating) - a simulation mismatch is possible @A: : player.vhd(74) | Feedback mux created for signal rx_data_0[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : player.vhd(74) | Feedback mux created for signal wsample[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : player.vhd(74) | Feedback mux created for signal SPREADY. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : player.vhd(74) | Feedback mux created for signal samplerate[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : player.vhd(197) | Feedback mux created for signal clkdriven. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(16) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(17) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(18) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(19) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(20) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(21) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(22) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(23) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(24) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(25) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(26) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(27) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(28) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(29) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(30) to a constant 0 @W:CL190 : player.vhd(74) | Optimizing register bit MPWDATA(31) to a constant 0 @W:CL260 : player.vhd(74) | Pruning Register bit 31 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 30 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 29 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 28 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 27 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 26 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 25 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 24 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 23 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 22 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 21 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 20 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 19 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 18 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 17 of MPWDATA(31 downto 0) @W:CL260 : player.vhd(74) | Pruning Register bit 16 of MPWDATA(31 downto 0) @N:CD630 : LPC.vhd(26) | Synthesizing work.lpc.behav @N:CD231 : LPC.vhd(81) | Using onehot encoding for type state_type (srl2="1000000000000000") @W:CD612 : LPC.vhd(177) | Index value 8 downto 0 could be out of prefix range 7 downto 0 @W:CD612 : LPC.vhd(252) | Index value 8 downto 0 could be out of prefix range 7 downto 0 @W:CD612 : LPC.vhd(253) | Index value 8 downto 0 could be out of prefix range 7 downto 0 @N:CD630 : shifter_r.vhd(21) | Synthesizing work.shifter_r.shift_right @W:CD604 : shifter_r.vhd(54) | OTHERS clause is not synthesized Post processing for work.shifter_r.shift_right @W:CL117 : shifter_r.vhd(35) | Latch generated from process for signal OUTPUT(29 downto 0), probably caused by a missing assignment in an if or case stmt @N:CD630 : multi16.vhd(8) | Synthesizing work.multi16.def_arch @N:CD630 : smartfusion.vhd(2845) | Synthesizing smartfusion.xor3.syn_black_box Post processing for smartfusion.xor3.syn_black_box @N:CD630 : smartfusion.vhd(13) | Synthesizing smartfusion.and2.syn_black_box Post processing for smartfusion.and2.syn_black_box @N:CD630 : smartfusion.vhd(2104) | Synthesizing smartfusion.nor2.syn_black_box Post processing for smartfusion.nor2.syn_black_box @N:CD630 : smartfusion.vhd(136) | Synthesizing smartfusion.ao1.syn_black_box Post processing for smartfusion.ao1.syn_black_box @N:CD630 : smartfusion.vhd(2837) | Synthesizing smartfusion.xor2.syn_black_box Post processing for smartfusion.xor2.syn_black_box @N:CD630 : smartfusion.vhd(2007) | Synthesizing smartfusion.mx2.syn_black_box Post processing for smartfusion.mx2.syn_black_box @N:CD630 : smartfusion.vhd(37) | Synthesizing smartfusion.and3.syn_black_box Post processing for smartfusion.and3.syn_black_box @N:CD630 : smartfusion.vhd(190) | Synthesizing smartfusion.aoi1.syn_black_box Post processing for smartfusion.aoi1.syn_black_box @N:CD630 : smartfusion.vhd(2872) | Synthesizing smartfusion.buff.syn_black_box Post processing for smartfusion.buff.syn_black_box @N:CD630 : smartfusion.vhd(1953) | Synthesizing smartfusion.maj3.syn_black_box Post processing for smartfusion.maj3.syn_black_box @N:CD630 : smartfusion.vhd(2233) | Synthesizing smartfusion.or3.syn_black_box Post processing for smartfusion.or3.syn_black_box @N:CD630 : smartfusion.vhd(2802) | Synthesizing smartfusion.xnor2.syn_black_box Post processing for smartfusion.xnor2.syn_black_box @N:CD630 : smartfusion.vhd(21) | Synthesizing smartfusion.and2a.syn_black_box Post processing for smartfusion.and2a.syn_black_box @N:CD630 : smartfusion.vhd(2742) | Synthesizing smartfusion.vcc.syn_black_box Post processing for smartfusion.vcc.syn_black_box Post processing for work.multi16.def_arch @W:CL168 : multi16.vhd(2507) | Pruning instance AND2_219 - not in use ... @W:CL168 : multi16.vhd(2481) | Pruning instance AND2_143 - not in use ... @W:CL168 : multi16.vhd(2479) | Pruning instance AND2_61 - not in use ... @W:CL168 : multi16.vhd(2465) | Pruning instance AND2_107 - not in use ... @W:CL168 : multi16.vhd(2443) | Pruning instance AND2_41 - not in use ... @W:CL168 : multi16.vhd(2388) | Pruning instance AND2_54 - not in use ... @W:CL168 : multi16.vhd(2328) | Pruning instance AND2_197 - not in use ... @W:CL168 : multi16.vhd(2267) | Pruning instance AND2_92 - not in use ... @W:CL168 : multi16.vhd(2265) | Pruning instance AND2_5 - not in use ... @W:CL168 : multi16.vhd(2215) | Pruning instance AND2_139 - not in use ... @W:CL168 : multi16.vhd(2132) | Pruning instance AND2_80 - not in use ... @W:CL168 : multi16.vhd(1889) | Pruning instance AND2_187 - not in use ... @W:CL168 : multi16.vhd(1879) | Pruning instance XOR2_100 - not in use ... @W:CL168 : multi16.vhd(1837) | Pruning instance AND2_198 - not in use ... @W:CL168 : multi16.vhd(1790) | Pruning instance AND2_113 - not in use ... @W:CL168 : multi16.vhd(1760) | Pruning instance AND2_87 - not in use ... @W:CL168 : multi16.vhd(1737) | Pruning instance AND2_213 - not in use ... @W:CL168 : multi16.vhd(1713) | Pruning instance AND2_206 - not in use ... @W:CL168 : multi16.vhd(1604) | Pruning instance AO1_2 - not in use ... @W:CL168 : multi16.vhd(1602) | Pruning instance AND2_102 - not in use ... @W:CL168 : multi16.vhd(1512) | Pruning instance AND2_220 - not in use ... @W:CL168 : multi16.vhd(1468) | Pruning instance AND2_212 - not in use ... @W:CL168 : multi16.vhd(1384) | Pruning instance AND2_141 - not in use ... @W:CL168 : multi16.vhd(1310) | Pruning instance AND2_223 - not in use ... @W:CL168 : multi16.vhd(1190) | Pruning instance AND2_28 - not in use ... @W:CL168 : multi16.vhd(1180) | Pruning instance AND2_30 - not in use ... @W:CL168 : multi16.vhd(1155) | Pruning instance AND2_190 - not in use ... @W:CL168 : multi16.vhd(1143) | Pruning instance AND2_45 - not in use ... @W:CL168 : multi16.vhd(1115) | Pruning instance AND2_169 - not in use ... @W:CL168 : multi16.vhd(1031) | Pruning instance AO1_48 - not in use ... @W:CL168 : multi16.vhd(999) | Pruning instance AND2_137 - not in use ... @W:CL168 : multi16.vhd(949) | Pruning instance AND2_36 - not in use ... @W:CL168 : multi16.vhd(923) | Pruning instance XOR2_37 - not in use ... @W:CL168 : multi16.vhd(900) | Pruning instance AND2_170 - not in use ... @W:CL168 : multi16.vhd(898) | Pruning instance AND2_136 - not in use ... @W:CL168 : multi16.vhd(866) | Pruning instance AND2_175 - not in use ... @W:CL168 : multi16.vhd(793) | Pruning instance AO1_17 - not in use ... @W:CL168 : multi16.vhd(770) | Pruning instance AND2_156 - not in use ... @W:CL168 : multi16.vhd(635) | Pruning instance AND2_38 - not in use ... @W:CL168 : multi16.vhd(534) | Pruning instance AND2_125 - not in use ... @W:CL168 : multi16.vhd(357) | Pruning instance AND2_184 - not in use ... @W:CL168 : multi16.vhd(290) | Pruning instance AND2_158 - not in use ... Post processing for work.lpc.behav @W:CL240 : LPC.vhd(40) | SPSLVERR is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : LPC.vhd(39) | SPRDATA is not assigned a value (floating) - a simulation mismatch is possible @N:CL134 : LPC.vhd(86) | Found RAM coeff, depth=8, width=14 @W:CL169 : LPC.vhd(84) | Pruning Register coeff_1(13 downto 0) @W:CL169 : LPC.vhd(84) | Pruning Register coeff_2(13 downto 0) @W:CL169 : LPC.vhd(84) | Pruning Register coeff_3(13 downto 0) @W:CL169 : LPC.vhd(84) | Pruning Register coeff_4(13 downto 0) @W:CL169 : LPC.vhd(84) | Pruning Register coeff_5(13 downto 0) @W:CL169 : LPC.vhd(84) | Pruning Register coeff_6(13 downto 0) @W:CL169 : LPC.vhd(84) | Pruning Register coeff_7(13 downto 0) @W:CL265 : LPC.vhd(120) | Pruning bit 31 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 30 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 29 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 28 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 27 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 26 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 25 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 24 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 23 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 22 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 21 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 20 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 19 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 18 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 17 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 16 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 15 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 14 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 13 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 12 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 31 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 30 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 29 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 28 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 27 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 26 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 25 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 24 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 23 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 22 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 21 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 20 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 19 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 18 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 17 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 16 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 15 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 14 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 13 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 12 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 11 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 10 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 9 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 8 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 7 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 6 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 5 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : LPC.vhd(120) | Pruning bit 4 of rx_data_3_3(31 downto 0) - not in use ... @A: : LPC.vhd(108) | Feedback mux created for signal rx_data_2[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal rx_data_1[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal rx_data_0[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal SPREADY. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal data_7[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal data_6[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal data_5[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal data_4[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal data_3[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal data_2[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal data_1[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal data_0[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal re[29:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal i_mul[3:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal d1[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal c1[13:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal residue[29:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal sample[29:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal rx_data_4[11:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal rx_data_3[3:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal s_start. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal s_re[29:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : LPC.vhd(108) | Feedback mux created for signal out_sample[29:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @N:CD630 : RICE.vhd(28) | Synthesizing work.rice.beh @N:CD231 : RICE.vhd(73) | Using onehot encoding for type state_type (start_rice="1000000000000") @W:CD604 : RICE.vhd(319) | OTHERS clause is not synthesized @N:CD630 : shifter.vhd(21) | Synthesizing work.shifter.shift_left Post processing for work.shifter.shift_left @W:CL189 : shifter.vhd(35) | Register bit OUTPUT(31) is always 0, optimizing ... @W:CL260 : shifter.vhd(35) | Pruning Register bit 31 of OUTPUT(31 downto 0) Post processing for work.rice.beh @W:CL240 : RICE.vhd(42) | SPSLVERR is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : RICE.vhd(41) | SPRDATA is not assigned a value (floating) - a simulation mismatch is possible @W:CL265 : RICE.vhd(116) | Pruning bit 31 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 30 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 29 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 28 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 27 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 26 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 25 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 24 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 23 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 22 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 21 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 20 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 19 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 18 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 17 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 16 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 15 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 14 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 13 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 12 of rx_data_5_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 31 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 30 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 29 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 28 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 27 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 26 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 25 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 24 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 23 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 22 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 21 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 20 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 19 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 18 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 17 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 16 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 15 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 14 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 13 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 12 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 11 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 10 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 9 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 8 of rx_data_4_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 31 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 30 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 29 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 28 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 27 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 26 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 25 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 24 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 23 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 22 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 21 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 20 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 19 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 18 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 17 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 16 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 15 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 14 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 13 of rx_data_3_3(31 downto 0) - not in use ... @W:CL265 : RICE.vhd(116) | Pruning bit 12 of rx_data_3_3(31 downto 0) - not in use ... @A: : RICE.vhd(103) | Feedback mux created for signal cbits[7:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal rx_data_1[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal rx_data_0[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal nwords[11:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal rx_data_6[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal r[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal acbits[7:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal signbit. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal counts[3:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal residue[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal SPREADY. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal msbcount[4:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal word[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal rparam[3:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal rx_data_2[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal rx_data_5[11:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal rx_data_3[11:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal rx_data_4[7:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_3(0) assign '1', register removed by optimization @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_3(1) assign '0', register removed by optimization @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_3(2) assign '1', register removed by optimization @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_3(3) assign '0', register removed by optimization @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_3(4) assign '0', register removed by optimization @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_3(5) assign '1', register removed by optimization @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_3(6) assign '0', register removed by optimization @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_3(7) assign '1', register removed by optimization @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_3(8) assign '1', register removed by optimization @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_3(9) assign '0', register removed by optimization @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_3(10) assign '1', register removed by optimization @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_3(11) assign '0', register removed by optimization @A: : RICE.vhd(103) | Feedback mux created for signal tx_data_2[11:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : RICE.vhd(103) | Feedback mux created for signal tx_data_1[11:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_0(8) assign '0', register removed by optimization @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_0(9) assign '0', register removed by optimization @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_0(10) assign '0', register removed by optimization @W:CL111 : RICE.vhd(103) | All reachable assignments to tx_data_0(11) assign '0', register removed by optimization @A: : RICE.vhd(103) | Feedback mux created for signal tx_data_0[7:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area Post processing for work.flac_decoder.struct @N:CD630 : MSS_FLAC_PLAYER.vhd(8) | Synthesizing work.mss_flac_player.def_arch @N:CD630 : mss_comps.vhd(4) | Synthesizing work.inbuf_mss.def_arch Post processing for work.inbuf_mss.def_arch @N:CD630 : mss_comps.vhd(65) | Synthesizing work.bibuf_mss.def_arch Post processing for work.bibuf_mss.def_arch @N:CD630 : mss_comps.vhd(24) | Synthesizing work.outbuf_mss.def_arch Post processing for work.outbuf_mss.def_arch @N:CD630 : mss_comps.vhd(168) | Synthesizing work.mssint.def_arch Post processing for work.mssint.def_arch @N:CD630 : mss_comps.vhd(44) | Synthesizing work.tribuff_mss.def_arch Post processing for work.tribuff_mss.def_arch @N:CD630 : mss_tshell.vhd(4) | Synthesizing work.mss_apb.def_arch Post processing for work.mss_apb.def_arch @N:CD630 : smartfusion.vhd(2276) | Synthesizing smartfusion.outbuf_a.syn_black_box Post processing for smartfusion.outbuf_a.syn_black_box @N:CD630 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(8) | Synthesizing work.mss_flac_player_tmp_mss_ccc_0_mss_ccc.def_arch @N:CD630 : mss_comps.vhd(432) | Synthesizing work.mss_xtlosc.def_arch Post processing for work.mss_xtlosc.def_arch @N:CD630 : mss_comps.vhd(472) | Synthesizing work.mss_ccc.def_arch Post processing for work.mss_ccc.def_arch Post processing for work.mss_flac_player_tmp_mss_ccc_0_mss_ccc.def_arch @W:CL240 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(38) | LPXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(37) | MAINXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(36) | RCOSC_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @N:CD630 : smartfusion.vhd(1797) | Synthesizing smartfusion.inbuf_a.syn_black_box Post processing for smartfusion.inbuf_a.syn_black_box Post processing for work.mss_flac_player.def_arch Post processing for work.top_flac_player.def_arch @W:CL168 : TOP_FLAC_PLAYER.vhd(857) | Pruning instance GND - not in use ... @W:CL168 : TOP_FLAC_PLAYER.vhd(291) | Pruning instance VCC - not in use ... @W:CL159 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(10) | Input CLKA is unused @W:CL159 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(11) | Input CLKA_PAD is unused @W:CL159 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(12) | Input CLKA_PADP is unused @W:CL159 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(13) | Input CLKA_PADN is unused @W:CL159 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(14) | Input CLKB is unused @W:CL159 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(15) | Input CLKB_PAD is unused @W:CL159 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(16) | Input CLKB_PADP is unused @W:CL159 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(17) | Input CLKB_PADN is unused @W:CL159 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(18) | Input CLKC is unused @W:CL159 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(19) | Input CLKC_PAD is unused @W:CL159 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(20) | Input CLKC_PADP is unused @W:CL159 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(21) | Input CLKC_PADN is unused @W:CL159 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(23) | Input LPXIN is unused @W:CL159 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC.vhd(24) | Input MAC_CLK is unused @N:CL201 : RICE.vhd(103) | Trying to extract state machine for register state Extracted state machine for register state State machine has 13 reachable states with original encodings of: 0000000000001 0000000000010 0000000000100 0000000001000 0000000010000 0000000100000 0000001000000 0000010000000 0000100000000 0001000000000 0010000000000 0100000000000 1000000000000 @W:CL159 : RICE.vhd(52) | Input PSLVERR is unused @N:CL201 : LPC.vhd(108) | Trying to extract state machine for register state Extracted state machine for register state State machine has 15 reachable states with original encodings of: 0000000000000001 0000000000000010 0000000000000100 0000000000001000 0000000000100000 0000000001000000 0000000010000000 0000000100000000 0000001000000000 0000010000000000 0000100000000000 0001000000000000 0010000000000000 0100000000000000 1000000000000000 @W:CL260 : LPC.vhd(108) | Pruning Register bit 31 of MPWDATA(31 downto 0) @W:CL260 : LPC.vhd(108) | Pruning Register bit 30 of MPWDATA(31 downto 0) @W:CL246 : LPC.vhd(49) | Input port bits 31 to 30 of mprdata(31 downto 0) are unused @W:CL159 : LPC.vhd(50) | Input PSLVERR is unused @N:CL201 : player.vhd(74) | Trying to extract state machine for register state Extracted state machine for register state State machine has 9 reachable states with original encodings of: 000000001 000000010 000000100 000001000 000010000 000100000 001000000 010000000 100000000 @W:CL246 : player.vhd(44) | Input port bits 31 to 16 of mprdata(31 downto 0) are unused @W:CL159 : player.vhd(45) | Input PSLVERR is unused @END Process took 0h:00m:06s realtime, 0h:00m:05s cputime # Wed Aug 03 16:48:28 2011 ###########################################################] Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 Reading constraint file: D:\temp4\A2F500\SmartFusion_FLAC_HW\constraint\FLAC_PLAYER.sdc Adding property syn_replicate, value 0 to view:work.TOP_FLAC_PLAYER(def_arch) Adding property *, value "syn_maxfan" to view:work.TOP_FLAC_PLAYER(def_arch) @W:BN298 : | Ignoring invalid option "10000" of constraint "define_global_attribute". @W:BN309 : | One or more non-fatal issues found in constraints; Please run Constraint Check for analysis @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled Available hyper_sources - for debug and ip models None Found @W: : mss_flac_player_tmp_mss_ccc_0_mss_ccc.vhd(118) | Net MSS_FLAC_PLAYER_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. @W: : mss_flac_player_tmp_mss_ccc_0_mss_ccc.vhd(118) | Net FLAC_DECODER_0.PLAYER_0/PCLK appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:02s; Memory used current: 80MB peak: 81MB) @N: : rice.vhd(103) | Found counter in view:work.RICE(beh) inst nmsbs[15:0] @N: : rice.vhd(103) | Found updn counter in view:work.RICE(beh) inst length[11:0] @N: : rice.vhd(103) | Found counter in view:work.RICE(beh) inst msbcount[4:0] @N: : rice.vhd(103) | Found counter in view:work.RICE(beh) inst nwords[11:0] Encoding state machine work.RICE(beh)-state[0:12] original code -> new code 0000000000001 -> 0000000000001 0000000000010 -> 0000000000010 0000000000100 -> 0000000000100 0000000001000 -> 0000000001000 0000000010000 -> 0000000010000 0000000100000 -> 0000000100000 0000001000000 -> 0000001000000 0000010000000 -> 0000010000000 0000100000000 -> 0000100000000 0001000000000 -> 0001000000000 0010000000000 -> 0010000000000 0100000000000 -> 0100000000000 1000000000000 -> 1000000000000 @N:MF176 : | Default generator successful @N:MF239 : rice.vhd(153) | Found 4 bit decrementor, 'rparam_1[3:0]' @N:MF238 : rice.vhd(231) | Found 8 bit incrementor, 'un23_cbits[7:0]' @N:MF179 : rice.vhd(252) | Found 4 bit by 4 bit '<' comparator, 'un1_rparam' Ram Decomposition Statistics for coeff[13:0] RAM 512x9 : 0 RAM 512x9 : 0 Encoding state machine work.LPC(behav)-state[0:14] original code -> new code 0000000000000001 -> 000000000000001 0000000000000010 -> 000000000000010 0000000000000100 -> 000000000000100 0000000000001000 -> 000000000001000 0000000000100000 -> 000000000010000 0000000001000000 -> 000000000100000 0000000010000000 -> 000000001000000 0000000100000000 -> 000000010000000 0000001000000000 -> 000000100000000 0000010000000000 -> 000001000000000 0000100000000000 -> 000010000000000 0001000000000000 -> 000100000000000 0010000000000000 -> 001000000000000 0100000000000000 -> 010000000000000 1000000000000000 -> 100000000000000 @N:MF176 : | Default generator successful @N:MF176 : | Default generator successful @N: : player.vhd(197) | Found counter in view:work.PLAYER(beh) inst count[15:0] @N: : player.vhd(74) | Found counter in view:work.PLAYER(beh) inst length[11:0] Encoding state machine work.PLAYER(beh)-state[0:8] original code -> new code 000000001 -> 000000001 000000010 -> 000000010 000000100 -> 000000100 000001000 -> 000001000 000010000 -> 000010000 000100000 -> 000100000 001000000 -> 001000000 010000000 -> 010000000 100000000 -> 100000000 @W:MO171 : lpc.vhd(86) | Sequential instance coeff_tile.RADDR_REG1[3] has been reduced to a combinational gate by constant propagation @W:MO171 : lpc.vhd(86) | Sequential instance coeff_tile.RADDR_REG1[4] has been reduced to a combinational gate by constant propagation @W:MO171 : lpc.vhd(86) | Sequential instance coeff_tile.RADDR_REG1[5] has been reduced to a combinational gate by constant propagation @W:MO171 : lpc.vhd(86) | Sequential instance coeff_tile.RADDR_REG1[6] has been reduced to a combinational gate by constant propagation @W:MO171 : lpc.vhd(86) | Sequential instance coeff_tile.RADDR_REG1[7] has been reduced to a combinational gate by constant propagation @W:MO171 : lpc.vhd(86) | Sequential instance coeff_tile.WADDR_REG1[3] has been reduced to a combinational gate by constant propagation @W:MO171 : lpc.vhd(86) | Sequential instance coeff_tile.WADDR_REG1[4] has been reduced to a combinational gate by constant propagation @W:MO171 : lpc.vhd(86) | Sequential instance coeff_tile.WADDR_REG1[5] has been reduced to a combinational gate by constant propagation @W:MO171 : lpc.vhd(86) | Sequential instance coeff_tile.WADDR_REG1[6] has been reduced to a combinational gate by constant propagation @W:MO171 : lpc.vhd(86) | Sequential instance coeff_tile.WADDR_REG1[7] has been reduced to a combinational gate by constant propagation @W:MO171 : lpc.vhd(86) | Sequential instance coeff_tile.DIN_REG1[14] has been reduced to a combinational gate by constant propagation @W:MO171 : lpc.vhd(86) | Sequential instance coeff_tile.DIN_REG1[15] has been reduced to a combinational gate by constant propagation @W:MO171 : lpc.vhd(86) | Sequential instance coeff_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation @W:MO171 : lpc.vhd(86) | Sequential instance coeff_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation Finished factoring (Time elapsed 0h:00m:10s; Memory used current: 85MB peak: 93MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:10s; Memory used current: 85MB peak: 93MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:12s; Memory used current: 86MB peak: 93MB) Starting Early Timing Optimization (Time elapsed 0h:00m:13s; Memory used current: 87MB peak: 93MB) Finished Early Timing Optimization (Time elapsed 0h:00m:29s; Memory used current: 89MB peak: 93MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:29s; Memory used current: 88MB peak: 93MB) Finished preparing to map (Time elapsed 0h:00m:32s; Memory used current: 99MB peak: 99MB) @N:FP130 : | Promoting Net FLAC_DECODER_0.RICE_0.N_88 on CLKINT I_64 @N:FP130 : | Promoting Net FLAC_DECODER_0.LPC_0.state[3] on CLKINT I_65 @N:FP130 : | Promoting Net FLAC_DECODER_0.LPC_0.N_102 on CLKINT I_66 Finished technology mapping (Time elapsed 0h:00m:33s; Memory used current: 105MB peak: 108MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:34s; Memory used current: 105MB peak: 108MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:34s; Memory used current: 106MB peak: 108MB) Writing Analyst data base D:\temp4\A2F500\SmartFusion_FLAC_HW\synthesis\TOP_FLAC_PLAYER.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:35s; Memory used current: 102MB peak: 108MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:37s; Memory used current: 105MB peak: 108MB) @W:MT246 : mss_flac_player.vhd(1003) | Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_flac_player.vhd(958) | Blackbox TRIBUFF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_flac_player_tmp_mss_ccc_0_mss_ccc.vhd(156) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock LPC|s_start_inferred_clock with period 25.00ns. A user-defined clock should be declared on object "n:FLAC_DECODER_0.LPC_0.s_start" @W:MT420 : | Found inferred clock MSS_FLAC_PLAYER|MSS_EMI_0_CLK_D_inferred_clock with period 25.00ns. A user-defined clock should be declared on object "n:MSS_FLAC_PLAYER_0.MSS_EMI_0_CLK_D" @W:MT420 : | Found inferred clock MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock with period 25.00ns. A user-defined clock should be declared on object "n:MSS_FLAC_PLAYER_0_FAB_CLK" @W:MT420 : | Found inferred clock MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock with period 25.00ns. A user-defined clock should be declared on object "n:MSS_FLAC_PLAYER_0.MSS_ADLIB_INST_FCLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Aug 03 16:49:15 2011 # Top view: TOP_FLAC_PLAYER Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 40.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): D:\temp4\A2F500\SmartFusion_FLAC_HW\constraint\FLAC_PLAYER.sdc @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -11.244 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- LPC|s_start_inferred_clock 40.0 MHz NA 25.000 NA NA inferred Inferred_clkgroup_1 MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock 40.0 MHz 201.4 MHz 25.000 4.965 20.035 inferred Inferred_clkgroup_2 MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock 40.0 MHz 27.6 MHz 25.000 36.244 -11.244 inferred Inferred_clkgroup_3 System 40.0 MHz 45.8 MHz 25.000 21.855 3.145 system system_clkgroup ======================================================================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | 25.000 24.163 | No paths - | No paths - | No paths - System MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock | 25.000 3.145 | No paths - | 25.000 19.673 | No paths - LPC|s_start_inferred_clock MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock System | 25.000 20.036 | No paths - | No paths - | No paths - MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock | Diff grp - | No paths - | Diff grp - | No paths - MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock System | 25.000 23.877 | No paths - | No paths - | No paths - MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock LPC|s_start_inferred_clock | Diff grp - | No paths - | No paths - | No paths - MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock | 25.000 -11.244 | 25.000 11.273 | 12.500 3.227 | 12.500 7.033 ========================================================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSS_FLAC_PLAYER_0.MSS_ADLIB_INST MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB SPI1DO MSS_SPI_1_DO_D 4.643 20.035 MSS_FLAC_PLAYER_0.MSS_ADLIB_INST MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB SPI1DOE MSS_SPI_1_DO_E 4.318 20.361 MSS_FLAC_PLAYER_0.MSS_ADLIB_INST MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB GPO[1] MSSINT_GPO_1_A 4.132 20.547 MSS_FLAC_PLAYER_0.MSS_ADLIB_INST MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB GPO[3] MSSINT_GPO_3_A 4.132 20.547 MSS_FLAC_PLAYER_0.MSS_ADLIB_INST MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB GPO[4] MSSINT_GPO_4_A 4.132 20.547 =============================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ MSS_FLAC_PLAYER_0.MSS_SPI_1_DO MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock TRIBUFF_MSS D MSS_SPI_1_DO_D 25.000 20.035 MSS_FLAC_PLAYER_0.MSS_SPI_1_DO MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock TRIBUFF_MSS E MSS_SPI_1_DO_E 25.000 20.361 MSS_FLAC_PLAYER_0.MSSINT_GPO_1 MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSSINT A MSSINT_GPO_1_A 25.000 20.547 MSS_FLAC_PLAYER_0.MSSINT_GPO_3 MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSSINT A MSSINT_GPO_3_A 25.000 20.547 MSS_FLAC_PLAYER_0.MSSINT_GPO_4 MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSSINT A MSSINT_GPO_4_A 25.000 20.547 ============================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 25.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 25.000 - Propagation time: 4.965 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 20.035 Number of logic level(s): 0 Starting point: MSS_FLAC_PLAYER_0.MSS_ADLIB_INST / SPI1DO Ending point: MSS_FLAC_PLAYER_0.MSS_SPI_1_DO / D The start point is clocked by MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- MSS_FLAC_PLAYER_0.MSS_ADLIB_INST MSS_APB SPI1DO Out 4.643 4.643 - MSS_SPI_1_DO_D Net - - 0.322 - 1 MSS_FLAC_PLAYER_0.MSS_SPI_1_DO TRIBUFF_MSS D In - 4.965 - ======================================================================================================== Total path delay (propagation time + setup) of 4.965 is 4.643(93.5%) logic and 0.322(6.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------- FLAC_DECODER_0.LPC_0.c1[5] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 Q c1[5] 0.737 -11.244 FLAC_DECODER_0.LPC_0.c1[3] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 Q c1[3] 0.737 -11.140 FLAC_DECODER_0.LPC_0.c1[7] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 Q c1[7] 0.737 -10.592 FLAC_DECODER_0.LPC_0.c1[1] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 Q c1[1] 0.737 -10.443 FLAC_DECODER_0.LPC_0.c1[9] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 Q c1[9] 0.737 -10.000 FLAC_DECODER_0.LPC_0.c1[4] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 Q c1[4] 0.737 -9.874 FLAC_DECODER_0.LPC_0.c1[2] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 Q c1[2] 0.737 -9.770 FLAC_DECODER_0.LPC_0.c1[11] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 Q c1[11] 0.737 -9.624 FLAC_DECODER_0.LPC_0.c1[6] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 Q c1[6] 0.737 -9.223 FLAC_DECODER_0.LPC_0.c1[13] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 Q c1[13] 0.737 -8.875 ==================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- FLAC_DECODER_0.LPC_0.re[28] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 D un1_re[28] 24.461 -11.244 FLAC_DECODER_0.LPC_0.re[23] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 D un1_re[23] 24.427 -10.521 FLAC_DECODER_0.LPC_0.re[27] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 D un1_re[27] 24.427 -10.460 FLAC_DECODER_0.LPC_0.re[29] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 D un1_re[29] 24.427 -10.441 FLAC_DECODER_0.LPC_0.re[21] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 D un1_re[21] 24.427 -9.960 FLAC_DECODER_0.LPC_0.re[19] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 D un1_re[19] 24.427 -9.729 FLAC_DECODER_0.LPC_0.re[25] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 D un1_re[25] 24.427 -9.694 FLAC_DECODER_0.LPC_0.re[24] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 D un1_re_0_a2_24_N_7 24.427 -9.671 FLAC_DECODER_0.LPC_0.re[20] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 D un1_re[20] 24.427 -9.525 FLAC_DECODER_0.LPC_0.re[26] MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock DFN1E1 D un1_re[26] 24.427 -9.247 ================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 25.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 24.461 - Propagation time: 35.705 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -11.244 Number of logic level(s): 24 Starting point: FLAC_DECODER_0.LPC_0.c1[5] / Q Ending point: FLAC_DECODER_0.LPC_0.re[28] / D The start point is clocked by MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------- FLAC_DECODER_0.LPC_0.c1[5] DFN1E1 Q Out 0.737 0.737 - c1[5] Net - - 2.037 - 13 FLAC_DECODER_0.LPC_0.mult_i.BUFF_32 BUFF A In - 2.774 - FLAC_DECODER_0.LPC_0.mult_i.BUFF_32 BUFF Y Out 0.499 3.273 - BUFF_32_Y Net - - 1.526 - 7 FLAC_DECODER_0.LPC_0.mult_i.XNOR2_10 XNOR2 B In - 4.799 - FLAC_DECODER_0.LPC_0.mult_i.XNOR2_10 XNOR2 Y Out 0.937 5.735 - XNOR2_10_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.NOR2_9 NOR2 B In - 6.057 - FLAC_DECODER_0.LPC_0.mult_i.NOR2_9 NOR2 Y Out 0.514 6.571 - NOR2_9_Y Net - - 1.423 - 6 FLAC_DECODER_0.LPC_0.mult_i.MX2_72 MX2 S In - 7.995 - FLAC_DECODER_0.LPC_0.mult_i.MX2_72 MX2 Y Out 0.480 8.474 - MX2_72_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.XOR2_PP2_8_inst XOR2 A In - 8.796 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_PP2_8_inst XOR2 Y Out 0.488 9.284 - PP2_8_net Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_25 XOR3 C In - 9.670 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_25 XOR3 Y Out 0.985 10.655 - XOR3_25_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_22 XOR3 C In - 11.041 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_22 XOR3 Y Out 0.985 12.026 - XOR3_22_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_46 XOR3 C In - 12.412 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_46 XOR3 Y Out 0.985 13.398 - XOR3_46_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_SumB_11_inst XOR3 C In - 13.783 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_SumB_11_inst XOR3 Y Out 0.985 14.769 - SumB_11_net Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.mult_i.XOR2_102 XOR2 B In - 15.575 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_102 XOR2 Y Out 0.937 16.512 - XOR2_102_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.AND2_121 AND2 B In - 16.898 - FLAC_DECODER_0.LPC_0.mult_i.AND2_121 AND2 Y Out 0.516 17.414 - AND2_121_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AO1_10 AO1 A In - 18.597 - FLAC_DECODER_0.LPC_0.mult_i.AO1_10 AO1 Y Out 0.520 19.117 - AO1_10_Y Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.mult_i.AO1_25 AO1 B In - 19.923 - FLAC_DECODER_0.LPC_0.mult_i.AO1_25 AO1 Y Out 0.567 20.490 - AO1_25_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AO1_41 AO1 C In - 21.674 - FLAC_DECODER_0.LPC_0.mult_i.AO1_41 AO1 Y Out 0.655 22.329 - AO1_41_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AO1_72 AO1 B In - 23.512 - FLAC_DECODER_0.LPC_0.mult_i.AO1_72 AO1 Y Out 0.567 24.079 - AO1_72_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.XOR2_Mult_23_inst XOR2 B In - 24.400 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_Mult_23_inst XOR2 Y Out 0.937 25.337 - m_re[23] Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I23_P0N OR2 B In - 26.143 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I23_P0N OR2 Y Out 0.514 26.658 - N428 Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I39_Y OA1 C In - 27.464 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I39_Y OA1 Y Out 0.666 28.130 - N456 Net - - 1.279 - 5 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I91_Y NOR2B A In - 29.409 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I91_Y NOR2B Y Out 0.488 29.897 - N511 Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I233_Y_0_a3_0_0 OR2B A In - 30.704 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I233_Y_0_a3_0_0 OR2B Y Out 0.488 31.192 - ADD_30x30_fast_I233_Y_0_a3_0 Net - - 0.386 - 2 d_m5_i_o5 AO1A C In - 31.578 - d_m5_i_o5 AO1A Y Out 0.633 32.210 - d_N_8_1 Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.re_RNO_3[28] AOI1B B In - 32.596 - FLAC_DECODER_0.LPC_0.re_RNO_3[28] AOI1B Y Out 0.911 33.507 - d_m5_i_2_1 Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re_RNO_0[28] OAI1 C In - 33.828 - FLAC_DECODER_0.LPC_0.re_RNO_0[28] OAI1 Y Out 0.655 34.484 - d_N_6_2 Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re_RNO[28] MX2C A In - 34.805 - FLAC_DECODER_0.LPC_0.re_RNO[28] MX2C Y Out 0.579 35.384 - un1_re[28] Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re[28] DFN1E1 D In - 35.705 - =========================================================================================================================== Total path delay (propagation time + setup) of 36.244 is 17.766(49.0%) logic and 18.478(51.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 25.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 24.461 - Propagation time: 35.601 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -11.140 Number of logic level(s): 24 Starting point: FLAC_DECODER_0.LPC_0.c1[3] / Q Ending point: FLAC_DECODER_0.LPC_0.re[28] / D The start point is clocked by MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------- FLAC_DECODER_0.LPC_0.c1[3] DFN1E1 Q Out 0.737 0.737 - c1[3] Net - - 2.037 - 13 FLAC_DECODER_0.LPC_0.mult_i.BUFF_14 BUFF A In - 2.774 - FLAC_DECODER_0.LPC_0.mult_i.BUFF_14 BUFF Y Out 0.499 3.273 - BUFF_14_Y Net - - 1.526 - 7 FLAC_DECODER_0.LPC_0.mult_i.XNOR2_17 XNOR2 B In - 4.799 - FLAC_DECODER_0.LPC_0.mult_i.XNOR2_17 XNOR2 Y Out 0.937 5.735 - XNOR2_17_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.NOR2_13 NOR2 B In - 6.057 - FLAC_DECODER_0.LPC_0.mult_i.NOR2_13 NOR2 Y Out 0.514 6.571 - NOR2_13_Y Net - - 1.423 - 6 FLAC_DECODER_0.LPC_0.mult_i.MX2_76 MX2 S In - 7.995 - FLAC_DECODER_0.LPC_0.mult_i.MX2_76 MX2 Y Out 0.480 8.474 - MX2_76_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.XOR2_PP1_9_inst XOR2 A In - 8.796 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_PP1_9_inst XOR2 Y Out 0.488 9.284 - PP1_9_net Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR2_23 XOR2 A In - 9.670 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_23 XOR2 Y Out 0.488 10.158 - XOR2_23_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_12 XOR3 C In - 10.544 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_12 XOR3 Y Out 0.985 11.529 - XOR3_12_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_31 XOR3 C In - 11.915 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_31 XOR3 Y Out 0.985 12.900 - XOR3_31_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_SumB_10_inst XOR3 C In - 13.286 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_SumB_10_inst XOR3 Y Out 0.985 14.272 - SumB_10_net Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.mult_i.XOR2_39 XOR2 B In - 15.078 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_39 XOR2 Y Out 0.937 16.015 - XOR2_39_Y Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.mult_i.AND2_121 AND2 A In - 16.821 - FLAC_DECODER_0.LPC_0.mult_i.AND2_121 AND2 Y Out 0.488 17.310 - AND2_121_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AO1_10 AO1 A In - 18.493 - FLAC_DECODER_0.LPC_0.mult_i.AO1_10 AO1 Y Out 0.520 19.013 - AO1_10_Y Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.mult_i.AO1_25 AO1 B In - 19.819 - FLAC_DECODER_0.LPC_0.mult_i.AO1_25 AO1 Y Out 0.567 20.386 - AO1_25_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AO1_41 AO1 C In - 21.569 - FLAC_DECODER_0.LPC_0.mult_i.AO1_41 AO1 Y Out 0.655 22.224 - AO1_41_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AO1_72 AO1 B In - 23.408 - FLAC_DECODER_0.LPC_0.mult_i.AO1_72 AO1 Y Out 0.567 23.974 - AO1_72_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.XOR2_Mult_23_inst XOR2 B In - 24.296 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_Mult_23_inst XOR2 Y Out 0.937 25.233 - m_re[23] Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I23_P0N OR2 B In - 26.039 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I23_P0N OR2 Y Out 0.514 26.554 - N428 Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I39_Y OA1 C In - 27.360 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I39_Y OA1 Y Out 0.666 28.026 - N456 Net - - 1.279 - 5 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I91_Y NOR2B A In - 29.305 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I91_Y NOR2B Y Out 0.488 29.793 - N511 Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I233_Y_0_a3_0_0 OR2B A In - 30.599 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I233_Y_0_a3_0_0 OR2B Y Out 0.488 31.088 - ADD_30x30_fast_I233_Y_0_a3_0 Net - - 0.386 - 2 d_m5_i_o5 AO1A C In - 31.474 - d_m5_i_o5 AO1A Y Out 0.633 32.106 - d_N_8_1 Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.re_RNO_3[28] AOI1B B In - 32.492 - FLAC_DECODER_0.LPC_0.re_RNO_3[28] AOI1B Y Out 0.911 33.403 - d_m5_i_2_1 Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re_RNO_0[28] OAI1 C In - 33.724 - FLAC_DECODER_0.LPC_0.re_RNO_0[28] OAI1 Y Out 0.655 34.379 - d_N_6_2 Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re_RNO[28] MX2C A In - 34.701 - FLAC_DECODER_0.LPC_0.re_RNO[28] MX2C Y Out 0.579 35.279 - un1_re[28] Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re[28] DFN1E1 D In - 35.601 - =========================================================================================================================== Total path delay (propagation time + setup) of 36.140 is 17.241(47.7%) logic and 18.899(52.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 25.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 24.461 - Propagation time: 35.599 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -11.138 Number of logic level(s): 24 Starting point: FLAC_DECODER_0.LPC_0.c1[5] / Q Ending point: FLAC_DECODER_0.LPC_0.re[28] / D The start point is clocked by MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------- FLAC_DECODER_0.LPC_0.c1[5] DFN1E1 Q Out 0.737 0.737 - c1[5] Net - - 2.037 - 13 FLAC_DECODER_0.LPC_0.mult_i.BUFF_32 BUFF A In - 2.774 - FLAC_DECODER_0.LPC_0.mult_i.BUFF_32 BUFF Y Out 0.499 3.273 - BUFF_32_Y Net - - 1.526 - 7 FLAC_DECODER_0.LPC_0.mult_i.XNOR2_10 XNOR2 B In - 4.799 - FLAC_DECODER_0.LPC_0.mult_i.XNOR2_10 XNOR2 Y Out 0.937 5.735 - XNOR2_10_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.NOR2_9 NOR2 B In - 6.057 - FLAC_DECODER_0.LPC_0.mult_i.NOR2_9 NOR2 Y Out 0.514 6.571 - NOR2_9_Y Net - - 1.423 - 6 FLAC_DECODER_0.LPC_0.mult_i.MX2_22 MX2 S In - 7.995 - FLAC_DECODER_0.LPC_0.mult_i.MX2_22 MX2 Y Out 0.480 8.474 - MX2_22_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.XOR2_PP2_9_inst XOR2 A In - 8.796 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_PP2_9_inst XOR2 Y Out 0.488 9.284 - PP2_9_net Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_13 XOR3 C In - 9.670 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_13 XOR3 Y Out 0.985 10.655 - XOR3_13_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_27 XOR3 C In - 11.041 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_27 XOR3 Y Out 0.985 12.026 - XOR3_27_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_2 XOR3 C In - 12.412 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_2 XOR3 Y Out 0.985 13.398 - XOR3_2_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_SumB_12_inst XOR3 C In - 13.783 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_SumB_12_inst XOR3 Y Out 0.985 14.769 - SumB_12_net Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.mult_i.XOR2_92 XOR2 B In - 15.575 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_92 XOR2 Y Out 0.937 16.512 - XOR2_92_Y Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.mult_i.AND2_150 AND2 A In - 17.318 - FLAC_DECODER_0.LPC_0.mult_i.AND2_150 AND2 Y Out 0.488 17.807 - AND2_150_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AND2_83 AND2 A In - 18.990 - FLAC_DECODER_0.LPC_0.mult_i.AND2_83 AND2 Y Out 0.488 19.479 - AND2_83_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.AO1_25 AO1 A In - 19.864 - FLAC_DECODER_0.LPC_0.mult_i.AO1_25 AO1 Y Out 0.520 20.384 - AO1_25_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AO1_41 AO1 C In - 21.567 - FLAC_DECODER_0.LPC_0.mult_i.AO1_41 AO1 Y Out 0.655 22.223 - AO1_41_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AO1_72 AO1 B In - 23.406 - FLAC_DECODER_0.LPC_0.mult_i.AO1_72 AO1 Y Out 0.567 23.973 - AO1_72_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.XOR2_Mult_23_inst XOR2 B In - 24.294 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_Mult_23_inst XOR2 Y Out 0.937 25.231 - m_re[23] Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I23_P0N OR2 B In - 26.037 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I23_P0N OR2 Y Out 0.514 26.552 - N428 Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I39_Y OA1 C In - 27.358 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I39_Y OA1 Y Out 0.666 28.024 - N456 Net - - 1.279 - 5 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I91_Y NOR2B A In - 29.303 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I91_Y NOR2B Y Out 0.488 29.791 - N511 Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I233_Y_0_a3_0_0 OR2B A In - 30.598 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I233_Y_0_a3_0_0 OR2B Y Out 0.488 31.086 - ADD_30x30_fast_I233_Y_0_a3_0 Net - - 0.386 - 2 d_m5_i_o5 AO1A C In - 31.472 - d_m5_i_o5 AO1A Y Out 0.633 32.104 - d_N_8_1 Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.re_RNO_3[28] AOI1B B In - 32.490 - FLAC_DECODER_0.LPC_0.re_RNO_3[28] AOI1B Y Out 0.911 33.401 - d_m5_i_2_1 Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re_RNO_0[28] OAI1 C In - 33.722 - FLAC_DECODER_0.LPC_0.re_RNO_0[28] OAI1 Y Out 0.655 34.378 - d_N_6_2 Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re_RNO[28] MX2C A In - 34.699 - FLAC_DECODER_0.LPC_0.re_RNO[28] MX2C Y Out 0.579 35.278 - un1_re[28] Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re[28] DFN1E1 D In - 35.599 - =========================================================================================================================== Total path delay (propagation time + setup) of 36.138 is 17.660(48.9%) logic and 18.478(51.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 25.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 24.461 - Propagation time: 35.488 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -11.027 Number of logic level(s): 24 Starting point: FLAC_DECODER_0.LPC_0.c1[5] / Q Ending point: FLAC_DECODER_0.LPC_0.re[28] / D The start point is clocked by MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------- FLAC_DECODER_0.LPC_0.c1[5] DFN1E1 Q Out 0.737 0.737 - c1[5] Net - - 2.037 - 13 FLAC_DECODER_0.LPC_0.mult_i.BUFF_32 BUFF A In - 2.774 - FLAC_DECODER_0.LPC_0.mult_i.BUFF_32 BUFF Y Out 0.499 3.273 - BUFF_32_Y Net - - 1.526 - 7 FLAC_DECODER_0.LPC_0.mult_i.XNOR2_10 XNOR2 B In - 4.799 - FLAC_DECODER_0.LPC_0.mult_i.XNOR2_10 XNOR2 Y Out 0.937 5.735 - XNOR2_10_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.NOR2_9 NOR2 B In - 6.057 - FLAC_DECODER_0.LPC_0.mult_i.NOR2_9 NOR2 Y Out 0.514 6.571 - NOR2_9_Y Net - - 1.423 - 6 FLAC_DECODER_0.LPC_0.mult_i.MX2_72 MX2 S In - 7.995 - FLAC_DECODER_0.LPC_0.mult_i.MX2_72 MX2 Y Out 0.480 8.474 - MX2_72_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.XOR2_PP2_8_inst XOR2 A In - 8.796 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_PP2_8_inst XOR2 Y Out 0.488 9.284 - PP2_8_net Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_25 XOR3 C In - 9.670 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_25 XOR3 Y Out 0.985 10.655 - XOR3_25_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_22 XOR3 C In - 11.041 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_22 XOR3 Y Out 0.985 12.026 - XOR3_22_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_46 XOR3 C In - 12.412 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_46 XOR3 Y Out 0.985 13.398 - XOR3_46_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_SumB_11_inst XOR3 C In - 13.783 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_SumB_11_inst XOR3 Y Out 0.985 14.769 - SumB_11_net Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.mult_i.XOR2_102 XOR2 B In - 15.575 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_102 XOR2 Y Out 0.937 16.512 - XOR2_102_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.AND2_121 AND2 B In - 16.898 - FLAC_DECODER_0.LPC_0.mult_i.AND2_121 AND2 Y Out 0.516 17.414 - AND2_121_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AND2_222 AND2 B In - 18.597 - FLAC_DECODER_0.LPC_0.mult_i.AND2_222 AND2 Y Out 0.516 19.113 - AND2_222_Y Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.mult_i.AND2_209 AND2 A In - 19.920 - FLAC_DECODER_0.LPC_0.mult_i.AND2_209 AND2 Y Out 0.488 20.408 - AND2_209_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AO1_41 AO1 A In - 21.592 - FLAC_DECODER_0.LPC_0.mult_i.AO1_41 AO1 Y Out 0.520 22.111 - AO1_41_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AO1_72 AO1 B In - 23.295 - FLAC_DECODER_0.LPC_0.mult_i.AO1_72 AO1 Y Out 0.567 23.861 - AO1_72_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.XOR2_Mult_23_inst XOR2 B In - 24.183 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_Mult_23_inst XOR2 Y Out 0.937 25.120 - m_re[23] Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I23_P0N OR2 B In - 25.926 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I23_P0N OR2 Y Out 0.514 26.441 - N428 Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I39_Y OA1 C In - 27.247 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I39_Y OA1 Y Out 0.666 27.913 - N456 Net - - 1.279 - 5 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I91_Y NOR2B A In - 29.192 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I91_Y NOR2B Y Out 0.488 29.680 - N511 Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I233_Y_0_a3_0_0 OR2B A In - 30.486 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I233_Y_0_a3_0_0 OR2B Y Out 0.488 30.975 - ADD_30x30_fast_I233_Y_0_a3_0 Net - - 0.386 - 2 d_m5_i_o5 AO1A C In - 31.360 - d_m5_i_o5 AO1A Y Out 0.633 31.993 - d_N_8_1 Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.re_RNO_3[28] AOI1B B In - 32.379 - FLAC_DECODER_0.LPC_0.re_RNO_3[28] AOI1B Y Out 0.911 33.290 - d_m5_i_2_1 Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re_RNO_0[28] OAI1 C In - 33.611 - FLAC_DECODER_0.LPC_0.re_RNO_0[28] OAI1 Y Out 0.655 34.266 - d_N_6_2 Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re_RNO[28] MX2C A In - 34.588 - FLAC_DECODER_0.LPC_0.re_RNO[28] MX2C Y Out 0.579 35.166 - un1_re[28] Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re[28] DFN1E1 D In - 35.488 - =========================================================================================================================== Total path delay (propagation time + setup) of 36.027 is 17.549(48.7%) logic and 18.478(51.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 25.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 24.461 - Propagation time: 35.460 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -10.999 Number of logic level(s): 24 Starting point: FLAC_DECODER_0.LPC_0.c1[5] / Q Ending point: FLAC_DECODER_0.LPC_0.re[28] / D The start point is clocked by MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------- FLAC_DECODER_0.LPC_0.c1[5] DFN1E1 Q Out 0.737 0.737 - c1[5] Net - - 2.037 - 13 FLAC_DECODER_0.LPC_0.mult_i.BUFF_32 BUFF A In - 2.774 - FLAC_DECODER_0.LPC_0.mult_i.BUFF_32 BUFF Y Out 0.499 3.273 - BUFF_32_Y Net - - 1.526 - 7 FLAC_DECODER_0.LPC_0.mult_i.XNOR2_10 XNOR2 B In - 4.799 - FLAC_DECODER_0.LPC_0.mult_i.XNOR2_10 XNOR2 Y Out 0.937 5.735 - XNOR2_10_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.NOR2_9 NOR2 B In - 6.057 - FLAC_DECODER_0.LPC_0.mult_i.NOR2_9 NOR2 Y Out 0.514 6.571 - NOR2_9_Y Net - - 1.423 - 6 FLAC_DECODER_0.LPC_0.mult_i.MX2_22 MX2 S In - 7.995 - FLAC_DECODER_0.LPC_0.mult_i.MX2_22 MX2 Y Out 0.480 8.474 - MX2_22_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.XOR2_PP2_9_inst XOR2 A In - 8.796 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_PP2_9_inst XOR2 Y Out 0.488 9.284 - PP2_9_net Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_13 XOR3 C In - 9.670 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_13 XOR3 Y Out 0.985 10.655 - XOR3_13_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_27 XOR3 C In - 11.041 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_27 XOR3 Y Out 0.985 12.026 - XOR3_27_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_2 XOR3 C In - 12.412 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_2 XOR3 Y Out 0.985 13.398 - XOR3_2_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.XOR3_SumB_12_inst XOR3 C In - 13.783 - FLAC_DECODER_0.LPC_0.mult_i.XOR3_SumB_12_inst XOR3 Y Out 0.985 14.769 - SumB_12_net Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.mult_i.XOR2_92 XOR2 B In - 15.575 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_92 XOR2 Y Out 0.937 16.512 - XOR2_92_Y Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.mult_i.AND2_150 AND2 A In - 17.318 - FLAC_DECODER_0.LPC_0.mult_i.AND2_150 AND2 Y Out 0.488 17.807 - AND2_150_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AND2_83 AND2 A In - 18.990 - FLAC_DECODER_0.LPC_0.mult_i.AND2_83 AND2 Y Out 0.488 19.479 - AND2_83_Y Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.mult_i.AND2_209 AND2 B In - 19.864 - FLAC_DECODER_0.LPC_0.mult_i.AND2_209 AND2 Y Out 0.516 20.380 - AND2_209_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AO1_41 AO1 A In - 21.564 - FLAC_DECODER_0.LPC_0.mult_i.AO1_41 AO1 Y Out 0.520 22.084 - AO1_41_Y Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.mult_i.AO1_72 AO1 B In - 23.267 - FLAC_DECODER_0.LPC_0.mult_i.AO1_72 AO1 Y Out 0.567 23.834 - AO1_72_Y Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.mult_i.XOR2_Mult_23_inst XOR2 B In - 24.155 - FLAC_DECODER_0.LPC_0.mult_i.XOR2_Mult_23_inst XOR2 Y Out 0.937 25.092 - m_re[23] Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I23_P0N OR2 B In - 25.898 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I23_P0N OR2 Y Out 0.514 26.413 - N428 Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I39_Y OA1 C In - 27.219 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I39_Y OA1 Y Out 0.666 27.885 - N456 Net - - 1.279 - 5 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I91_Y NOR2B A In - 29.164 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I91_Y NOR2B Y Out 0.488 29.652 - N511 Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I233_Y_0_a3_0_0 OR2B A In - 30.459 - FLAC_DECODER_0.LPC_0.un7_re.ADD_30x30_fast_I233_Y_0_a3_0_0 OR2B Y Out 0.488 30.947 - ADD_30x30_fast_I233_Y_0_a3_0 Net - - 0.386 - 2 d_m5_i_o5 AO1A C In - 31.333 - d_m5_i_o5 AO1A Y Out 0.633 31.965 - d_N_8_1 Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.re_RNO_3[28] AOI1B B In - 32.351 - FLAC_DECODER_0.LPC_0.re_RNO_3[28] AOI1B Y Out 0.911 33.262 - d_m5_i_2_1 Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re_RNO_0[28] OAI1 C In - 33.583 - FLAC_DECODER_0.LPC_0.re_RNO_0[28] OAI1 Y Out 0.655 34.239 - d_N_6_2 Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re_RNO[28] MX2C A In - 34.560 - FLAC_DECODER_0.LPC_0.re_RNO[28] MX2C Y Out 0.579 35.139 - un1_re[28] Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.re[28] DFN1E1 D In - 35.460 - =========================================================================================================================== Total path delay (propagation time + setup) of 35.999 is 17.521(48.7%) logic and 18.478(51.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------- MSS_FLAC_PLAYER_0.MSSINT_GPO_4 System MSSINT Y MSS_FLAC_PLAYER_0_M2F_GPO_4 0.000 3.145 MSS_FLAC_PLAYER_0.MSSINT_GPO_1 System MSSINT Y MSS_FLAC_PLAYER_0_M2F_GPO_1 0.000 4.140 MSS_FLAC_PLAYER_0.MSSINT_GPO_3 System MSSINT Y MSS_FLAC_PLAYER_0_M2F_GPO_3 0.000 5.718 MSS_FLAC_PLAYER_0.MSSINT_GPI_0 System MSSINT Y MSSINT_GPI_0_Y 0.000 24.163 MSS_FLAC_PLAYER_0.MSSINT_GPI_2 System MSSINT Y MSSINT_GPI_2_Y 0.000 24.163 MSS_FLAC_PLAYER_0.MSSINT_GPI_5 System MSSINT Y MSSINT_GPI_5_Y 0.000 24.163 ====================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------- FLAC_DECODER_0.LPC_0.rx_data_1[29] System DFN1 D rx_data_1_RNO_0[29] 24.461 3.145 FLAC_DECODER_0.LPC_0.rx_data_1[31] System DFN1 D rx_data_1_RNO_0[31] 24.461 3.145 FLAC_DECODER_0.LPC_0.rx_data_1[25] System DFN1 D rx_data_1_RNO_0[25] 24.461 3.523 FLAC_DECODER_0.LPC_0.rx_data_2[29] System DFN1 D rx_data_2_RNO[29] 24.461 3.714 FLAC_DECODER_0.LPC_0.rx_data_2[31] System DFN1 D rx_data_2_RNO[31] 24.461 3.714 FLAC_DECODER_0.LPC_0.rx_data_1[28] System DFN1 D rx_data_1_RNO_0[28] 24.461 3.981 FLAC_DECODER_0.LPC_0.rx_data_1[30] System DFN1 D rx_data_1_RNO_0[30] 24.461 3.981 FLAC_DECODER_0.LPC_0.rx_data_1[27] System DFN1 D rx_data_1_RNO_0[27] 24.461 4.046 FLAC_DECODER_0.LPC_0.rx_data_2[25] System DFN1 D rx_data_2_RNO[25] 24.461 4.091 FLAC_DECODER_0.PLAYER_0.rx_data_0[29] System DFN1 D un1_rx_data_0_1[29] 24.461 4.140 =================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 25.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 24.461 - Propagation time: 21.316 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 3.145 Number of logic level(s): 15 Starting point: MSS_FLAC_PLAYER_0.MSSINT_GPO_4 / Y Ending point: FLAC_DECODER_0.LPC_0.rx_data_1[29] / D The start point is clocked by System [rising] The end point is clocked by MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC|MSS_FLAC_PLAYER_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- MSS_FLAC_PLAYER_0.MSSINT_GPO_4 MSSINT Y Out 0.000 0.000 - MSS_FLAC_PLAYER_0_M2F_GPO_4 Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.N_102_i_i_o2 OR2B B In - 0.322 - FLAC_DECODER_0.LPC_0.N_102_i_i_o2 OR2B Y Out 0.627 0.949 - N_102_i_i_o2 Net - - 0.322 - 1 I_66 CLKINT A In - 1.270 - I_66 CLKINT Y Out 0.174 1.444 - FLAC_DECODER_0.LPC_0.N_102 Net - - 1.601 - 113 FLAC_DECODER_0.LPC_0.un1_start_inv_2_0_0_o2 NOR2 B In - 3.045 - FLAC_DECODER_0.LPC_0.un1_start_inv_2_0_0_o2 NOR2 Y Out 0.514 3.559 - N_531 Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.state_RNIUTCQ[3] OR2B B In - 4.366 - FLAC_DECODER_0.LPC_0.state_RNIUTCQ[3] OR2B Y Out 0.627 4.993 - N_870 Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.warmup_samples_RNIS69V[3] NOR3A C In - 6.177 - FLAC_DECODER_0.LPC_0.warmup_samples_RNIS69V[3] NOR3A Y Out 0.641 6.818 - warmup_samples_RNIS69V[3] Net - - 1.279 - 5 FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_1 AND2 B In - 8.097 - FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_1 AND2 Y Out 0.627 8.725 - DWACT_ADD_CI_0_TMP_1[0] Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_123 NOR2B A In - 9.110 - FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_123 NOR2B Y Out 0.514 9.625 - DWACT_ADD_CI_0_g_array_1_0[0] Net - - 0.806 - 3 FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_167 NOR2B A In - 10.431 - FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_167 NOR2B Y Out 0.514 10.946 - DWACT_ADD_CI_0_g_array_2_0[0] Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_127 NOR2B A In - 12.129 - FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_127 NOR2B Y Out 0.514 12.644 - DWACT_ADD_CI_0_g_array_3[0] Net - - 1.279 - 5 FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_169 NOR2B A In - 13.923 - FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_169 NOR2B Y Out 0.514 14.437 - DWACT_ADD_CI_0_g_array_4[0] Net - - 1.279 - 5 FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_135 NOR2B A In - 15.716 - FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_135 NOR2B Y Out 0.514 16.231 - DWACT_ADD_CI_0_g_array_9[0] Net - - 1.184 - 4 FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_158 NOR2B A In - 17.414 - FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_158 NOR2B Y Out 0.514 17.929 - DWACT_ADD_CI_0_g_array_11_5[0] Net - - 0.386 - 2 FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_131 NOR2B A In - 18.315 - FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_131 NOR2B Y Out 0.514 18.829 - DWACT_ADD_CI_0_g_array_12_12[0] Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_99 XOR2 B In - 19.151 - FLAC_DECODER_0.LPC_0.un1_rx_data_1.I_99 XOR2 Y Out 0.937 20.087 - I_99_3 Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.rx_data_1_RNO[29] MX2 B In - 20.409 - FLAC_DECODER_0.LPC_0.rx_data_1_RNO[29] MX2 Y Out 0.586 20.994 - rx_data_1_RNO_0[29] Net - - 0.322 - 1 FLAC_DECODER_0.LPC_0.rx_data_1[29] DFN1 D In - 21.316 - =============================================================================================================== Total path delay (propagation time + setup) of 21.855 is 8.874(40.6%) logic and 12.981(59.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F500M3G_FBGA484_Std Report for cell TOP_FLAC_PLAYER.def_arch Core Cell usage: cell count area count*area AND2 369 1.0 369.0 AND2A 4 1.0 4.0 AND3 13 1.0 13.0 AO1 125 1.0 125.0 AO13 4 1.0 4.0 AO18 2 1.0 2.0 AO1A 10 1.0 10.0 AO1B 32 1.0 32.0 AO1C 19 1.0 19.0 AO1D 19 1.0 19.0 AOI1 28 1.0 28.0 AOI1A 3 1.0 3.0 AOI1B 51 1.0 51.0 AX1 4 1.0 4.0 AX1A 3 1.0 3.0 AX1C 14 1.0 14.0 AX1D 5 1.0 5.0 AX1E 6 1.0 6.0 AXOI4 1 1.0 1.0 BUFF 53 1.0 53.0 CLKINT 3 0.0 0.0 GND 10 0.0 0.0 INV 2 1.0 2.0 MAJ3 141 1.0 141.0 MIN3 12 1.0 12.0 MSSINT 6 0.0 0.0 MSS_CCC 1 0.0 0.0 MX2 835 1.0 835.0 MX2A 5 1.0 5.0 MX2B 6 1.0 6.0 MX2C 27 1.0 27.0 NAND2 3 1.0 3.0 NOR2 88 1.0 88.0 NOR2A 104 1.0 104.0 NOR2B 402 1.0 402.0 NOR3 38 1.0 38.0 NOR3A 33 1.0 33.0 NOR3B 29 1.0 29.0 NOR3C 63 1.0 63.0 OA1 30 1.0 30.0 OA1A 19 1.0 19.0 OA1B 8 1.0 8.0 OA1C 14 1.0 14.0 OAI1 19 1.0 19.0 OR2 74 1.0 74.0 OR2A 84 1.0 84.0 OR2B 200 1.0 200.0 OR3 80 1.0 80.0 OR3A 12 1.0 12.0 OR3B 18 1.0 18.0 OR3C 96 1.0 96.0 VCC 10 0.0 0.0 XA1 13 1.0 13.0 XA1A 24 1.0 24.0 XA1B 20 1.0 20.0 XA1C 15 1.0 15.0 XAI1 4 1.0 4.0 XNOR2 79 1.0 79.0 XNOR3 7 1.0 7.0 XO1 20 1.0 20.0 XO1A 20 1.0 20.0 XOR2 577 1.0 577.0 XOR3 96 1.0 96.0 DFN0C1 16 1.0 16.0 DFN0E0 1 1.0 1.0 DFN1 277 1.0 277.0 DFN1C1 74 1.0 74.0 DFN1E0 163 1.0 163.0 DFN1E0C1 121 1.0 121.0 DFN1E0P1 1 1.0 1.0 DFN1E1 438 1.0 438.0 DFN1E1C1 83 1.0 83.0 DFN1P1 8 1.0 8.0 DLN1 30 1.0 30.0 MSS_APB 1 0.0 0.0 RAM512X18 1 0.0 0.0 ----- ---------- TOTAL 5326 5294.0 IO Cell usage: cell count BIBUF_MSS 18 INBUF_A 1 INBUF_MSS 3 MSS_XTLOSC 1 OUTBUF_A 1 OUTBUF_MSS 35 TRIBUFF_MSS 1 ----- TOTAL 60 Core Cells : 5294 of 11520 (46%) IO Cells : 60 RAM/ROM Usage Summary Block Rams : 1 of 24 (4%) Mapper successful! Process took 0h:00m:45s realtime, 0h:00m:37s cputime # Wed Aug 03 16:49:16 2011 ###########################################################]