-------------------------------------------------------------------------------
-- Title      : FLAC_DECODER
-------------------------------------------------------------------------------
-- File       : FLAC_DECODER.vhd
-- Author     : Sathishkumar Donthu
--              Sathish.Donthu@microsemi.com
-- Company    : Microsemi Corporation
-- Device     : SmartFusion 
-- Standard   : VHDL
-------------------------------------------------------------------------------
-- Description: The FLAC_DECODER has RICE decoder and LPC decoder 
--              and a custom-made APB3 interface.
-------------------------------------------------------------------------------
-- Copyright (c) 2011   Actel Corporation
--                      All rights reserved.
-------------------------------------------------------------------------------

library   IEEE;
use       IEEE.std_logic_1164.all;
use       IEEE.std_logic_unsigned.all;

entity FLAC_DECODER is
port ( 
       PCLK                    : in  std_logic;
       PRESET                  : in  std_logic;
       
       --APB3 slave signals 
       
       SPENABLE                : in  std_logic;
       SPSEL                   : in  std_logic;
       SPWRITE                 : in  std_logic;
       SPWDATA                 : in  std_logic_vector(31 downto 0);
       SPADDR                  : in  std_logic_vector(19 downto 0);
       SPRDATA                 : out std_logic_vector(31 downto 0);
       SPREADY,SPSLVERR        : out std_logic;

       --APB3 master signals

       MPENABLE                : out std_logic;
       MPSEL                   : out std_logic;
       MPWRITE                 : out std_logic;
       MPWDATA                 : out std_logic_vector(31 downto 0);
       MPADDR                  : out std_logic_vector(31 downto 0);
       MPRDATA                 : in  std_logic_vector(31 downto 0);
       MPREADY,PSLVERR         : in  std_logic;

       --Signals for connecting to GPIO's of MSS

       START1                  : in std_logic;
       START2                  : in std_logic;
       START3                  : in std_logic;
       STOP1                   : out std_logic;
       STOP2                   : out std_logic;
       STOP3                   : out std_logic       
       );
      end FLAC_DECODER;

architecture struct of FLAC_DECODER is

component LPC
port ( 
       PCLK                    : in  std_logic;
       PRESET                  : in  std_logic;
       P_VALID                 : in  std_logic;       

       --APB3 slave signals 
       
       SPENABLE                : in  std_logic;
       SPSEL                   : in  std_logic;
       SPWRITE                 : in  std_logic;
       SPWDATA                 : in  std_logic_vector(31 downto 0);
       SPADDR                  : in  std_logic_vector(19 downto 0);
       SPRDATA                 : out std_logic_vector(31 downto 0);
       SPREADY,SPSLVERR        : out std_logic;

       --APB3 master signals

       MPENABLE                : out std_logic;
       MPSEL                   : out std_logic;
       MPWRITE                 : out std_logic;
       MPWDATA                 : out std_logic_vector(31 downto 0);
       MPADDR                  : out std_logic_vector(31 downto 0);
       MPRDATA                 : in  std_logic_vector(31 downto 0);
       MPREADY,PSLVERR         : in  std_logic;

       --Signals for connecting to GPIO's of MSS

       START                   : in  std_logic;
       STOP                    : out std_logic
       );
end component;

component RICE 
port ( 
       PCLK                    : in  std_logic;
       PRESET                  : in  std_logic;
       P_VALID                 : in  std_logic;
       
       --APB3 slave signals 
       
       SPENABLE                : in  std_logic;
       SPSEL                   : in  std_logic;
       SPWRITE                 : in  std_logic;
       SPWDATA                 : in  std_logic_vector(31 downto 0);
       SPADDR                  : in  std_logic_vector(19 downto 0);
       SPRDATA                 : out std_logic_vector(31 downto 0);
       SPREADY,SPSLVERR        : out std_logic;

       --APB3 master signals

       MPENABLE                : out std_logic;
       MPSEL                   : out std_logic;
       MPWRITE                 : out std_logic;
       MPWDATA                 : out std_logic_vector(31 downto 0);
       MPADDR                  : out std_logic_vector(31 downto 0);
       MPRDATA                 : in  std_logic_vector(31 downto 0);
       MPREADY,PSLVERR         : in  std_logic;

       --Signals for conncting to GPIO's of MSS

       START                   : in  std_logic;
       STOP                    : out std_logic
       );
end component;

component PLAYER
port ( 
       PCLK                    : in  std_logic;
       PRESET                  : in  std_logic;
       P_VALID                 : out  std_logic;

       --APB3 slave signals 
       
       SPENABLE                : in  std_logic;
       SPSEL                   : in  std_logic;
       SPWRITE                 : in  std_logic;
       SPWDATA                 : in  std_logic_vector(31 downto 0);
       SPADDR                  : in  std_logic_vector(19 downto 0);
       SPRDATA                 : out std_logic_vector(31 downto 0);
       SPREADY,SPSLVERR        : out std_logic;

       --APB3 master signals

       MPENABLE                : out std_logic;
       MPSEL                   : out std_logic;
       MPWRITE                 : out std_logic;
       MPWDATA                 : out std_logic_vector(31 downto 0);
       MPADDR                  : out std_logic_vector(31 downto 0);
       MPRDATA                 : in  std_logic_vector(31 downto 0);
       MPREADY,PSLVERR         : in  std_logic;

       --Signals for conncting to GPIO's of MSS

       START                   : in  std_logic;
       STOP                    : out std_logic
       );
end component;

signal MPENABLE1  : std_logic;
signal MPSEL1     : std_logic;
signal MPWRITE1   : std_logic;
signal SPREADY1   : std_logic;
signal MPWDATA1   : std_logic_vector(31 downto 0);
signal MPADDR1    : std_logic_vector(31 downto 0);
signal MPENABLE2  : std_logic;
signal MPSEL2     : std_logic;
signal MPWRITE2   : std_logic;
signal SPREADY2   : std_logic;
signal MPWDATA2   : std_logic_vector(31 downto 0);
signal MPADDR2    : std_logic_vector(31 downto 0);
signal MPENABLE3  : std_logic;
signal MPSEL3     : std_logic;
signal MPWRITE3   : std_logic;
signal SPREADY3   : std_logic;
signal MPWDATA3   : std_logic_vector(31 downto 0);
signal MPADDR3    : std_logic_vector(31 downto 0);
signal P_VALID    : std_logic;


begin

--Muxing APB Master signals

SPREADY     <=   SPREADY1 or SPREADY2 or SPREADY3;
MPENABLE    <=   MPENABLE1 or MPENABLE2 or MPENABLE3 ;
MPSEL       <=   MPSEL1 or MPSEL2 or MPSEL3;
MPWRITE     <=   MPWRITE1 or MPWRITE2 or MPWRITE3;
MPWDATA     <=   MPWDATA1 or MPWDATA2 or MPWDATA3;
MPADDR      <=   MPADDR1 or MPADDR2 or MPADDR3;
--******************************************************************************
-- Instantiation of RICE decoder
--******************************************************************************


RICE_0:RICE 
port map(
                     PCLK       =>      PCLK,
                     PRESET     =>      PRESET,
                     P_VALID    =>      P_VALID,                     
                     SPENABLE   =>      SPENABLE,
                     SPSEL      =>      SPSEL,
                     SPWRITE    =>      SPWRITE,
                     SPWDATA    =>      SPWDATA,
                     SPADDR     =>      SPADDR,
                     SPRDATA    =>      SPRDATA,
                     SPREADY    =>      SPREADY1,
                     SPSLVERR   =>      SPSLVERR,
                     MPENABLE   =>      MPENABLE1,
                     MPSEL      =>      MPSEL1,
                     MPWRITE    =>      MPWRITE1,
                     MPWDATA    =>      MPWDATA1,
                     MPADDR     =>      MPADDR1,
                     MPRDATA    =>      MPRDATA,
                     MPREADY    =>      MPREADY,
                     PSLVERR    =>      PSLVERR,
                     START      =>      START1,
                     STOP       =>      STOP1
                     );

--******************************************************************************
-- Instantiation of LPC decoder
--******************************************************************************

LPC_0 : LPC 
    port map(
                     PCLK       =>      PCLK,
                     PRESET     =>      PRESET,
                     P_VALID    =>      P_VALID,                    
                     SPENABLE   =>      SPENABLE,
                     SPSEL      =>      SPSEL,
                     SPWRITE    =>      SPWRITE,
                     SPWDATA    =>      SPWDATA,
                     SPADDR     =>      SPADDR,
                     SPRDATA    =>      SPRDATA,
                     SPREADY    =>      SPREADY2,
                     SPSLVERR   =>      SPSLVERR,
                     MPENABLE   =>      MPENABLE2,
                     MPSEL      =>      MPSEL2,
                     MPWRITE    =>      MPWRITE2,
                     MPWDATA    =>      MPWDATA2,
                     MPADDR     =>      MPADDR2,
                     MPRDATA    =>      MPRDATA,
                     MPREADY    =>      MPREADY,
                     PSLVERR    =>      PSLVERR,
                     START      =>      START2,
                     STOP       =>      STOP2
                     );

--******************************************************************************
-- Instantiation of PLAYER
--******************************************************************************

PLAYER_0 : PLAYER
    port map(
                     PCLK       =>      PCLK,
                     PRESET     =>      PRESET,                     
                     P_VALID    =>      P_VALID,
                     SPENABLE   =>      SPENABLE,
                     SPSEL      =>      SPSEL,
                     SPWRITE    =>      SPWRITE,
                     SPWDATA    =>      SPWDATA,
                     SPADDR     =>      SPADDR,
                     SPRDATA    =>      SPRDATA,
                     SPREADY    =>      SPREADY3,
                     SPSLVERR   =>      SPSLVERR,
                     MPENABLE   =>      MPENABLE3,
                     MPSEL      =>      MPSEL3,
                     MPWRITE    =>      MPWRITE3,
                     MPWDATA    =>      MPWDATA3,
                     MPADDR     =>      MPADDR3,
                     MPRDATA    =>      MPRDATA,
                     MPREADY    =>      MPREADY,
                     PSLVERR    =>      PSLVERR,
                     START      =>      START3,
                     STOP       =>      STOP3
                     );

end struct;
