-- FLAC_DECODER_testbench.vhd
library ieee;
use ieee.std_logic_1164.all;

entity flac_decoder_testbench is
end flac_decoder_testbench;

architecture test of flac_decoder_testbench is

component FLAC_DECODER is
port ( 
       PCLK                    : in  std_logic;
       PRESET                  : in  std_logic;
       
       --APB3 slave signals 
       
       SPENABLE                : in  std_logic;
       SPSEL                   : in  std_logic;
       SPWRITE                 : in  std_logic;
       SPWDATA                 : in  std_logic_vector(31 downto 0);
       SPADDR                  : in  std_logic_vector(19 downto 0);
       SPRDATA                 : out std_logic_vector(31 downto 0);
       SPREADY,SPSLVERR        : out std_logic;

       --APB3 master signals

       MPENABLE                : out std_logic;
       MPSEL                   : out std_logic;
       MPWRITE                 : out std_logic;
       MPWDATA                 : out std_logic_vector(31 downto 0);
       MPADDR                  : out std_logic_vector(31 downto 0);
       MPRDATA                 : in  std_logic_vector(31 downto 0);
       MPREADY,PSLVERR         : in  std_logic;

       --Signals for conncting to GPIO's of MSS

       START1                  : in std_logic;
       START2                  : in std_logic;
       START3                  : in std_logic;
       STOP1                   : out std_logic;
       STOP2                   : out std_logic;
       STOP3                   : out std_logic       
       );
      end component;

signal      pclk:std_logic:='0';
signal      preset,spenable,spsel,spwrite:std_logic;
signal      spwdata:std_logic_vector(31 downto 0);
signal      spaddr: std_logic_vector(19 downto 0);
signal      sprdata:std_logic_vector(31 downto 0);
signal      spready,spslverr:std_logic;
signal      mpenable,mpsel,mpwrite:std_logic;
signal      mpwdata:std_logic_vector(31 downto 0);
signal      mpaddr:std_logic_vector(31 downto 0);
signal      mprdata:std_logic_vector(31 downto 0);
signal      mpready,pslverr:std_logic;
signal      start1:std_logic;
signal      start2:std_logic;
signal      stop1: std_logic;
signal      stop2: std_logic;
signal      start3:std_logic;
signal      stop3: std_logic;
signal state:std_logic_vector (3 downto 0);
begin

preset<='1';
start2<='0';
pclk<= not pclk after 25 ns;
spwrite<='1';spsel<='1';
mpready<=mpenable and mpsel;
mprdata<=x"0aab85c5" when mpwrite<='0' else
         "00000000000000000000000000000000";
process(pclk,state)
begin
if (pclk'event and pclk='1') then
      case state is
        when "1111" =>start1<='0';
                      start3<='0';
                       state<="0000";
        when "0000" =>start1<='1';                      
                      spenable<='0';
                       spwdata<=x"20000000";
                       state<="0001";
        when "0001" =>spenable<='1';
                       if spready='1' then
                       state<="0010";
                       end if;
        when "0010" =>spenable<='0';
                       spwdata<=x"20002000";
                       state<="0011";
        when "0011" =>spenable<='1';
                       if spready='1' then
                       state<="0100";
                       end if;
        when "0100" =>spenable<='0';
                       spwdata<=x"00000004";
                       state<="0101";
        when "0101" =>spenable<='1';
                       if spready='1' then
                       state<="0110";
                       end if;
        when "0110" =>spenable<='0';
                       spwdata<=x"00000fff";
                       state<="0111";
        when "0111" =>spenable<='1';
                       if spready<='1' then
                       state<="1000";
                       end if;
        when "1000" =>spenable<='0';
                       spwdata<=x"00000000";
                       state<="1001";
        when "1001" =>spenable<='1';
                       if spready='1' then
                       state<="1010";
                       end if;
        when "1010" =>spenable<='0';
                       spwdata<=x"00000fff";
                       state<="1011";
        when "1011" =>spenable<='1';
                       if spready='1' then
                       state<="1100";
                       end if;
        when "1100" =>spenable<='0';
                       spwdata<=x"20004000";
                       state<="1101";
        when "1101" =>spenable<='1';
                       if spready='1' then
                       state<="1110";
                       start3<='1';
                       end if;
        when "1110" =>if (stop1='1') then
                       state<="1111";
                       end if;
        when others  =>state<="1111";
        end case;

end if;
end process;
FLAC_DECODER0:FLAC_DECODER port map( pclk,preset,spenable,spsel,spwrite,spwdata,
                                    spaddr,sprdata,spready,spslverr,mpenable,
                                    mpsel,mpwrite,mpwdata,mpaddr,mprdata,mpready,
                                    pslverr,start1,start2,start3,stop1,stop2,stop3);
end test;