-------------------------------------------------------------------------------
-- Title      : FLAC_DECODER
-------------------------------------------------------------------------------
-- File       : FLAC_DECODER.vhd
-- Author     : Sathishkumar Donthu
--              Sathish.Donthu@microsemi.com
-- Company    : Microsemi Corporation
-- Device     : SmartFusion 
-- Standard   : VHDL
-------------------------------------------------------------------------------
-- Description: -- shifter_r.vhd
-- Signed 32-bit right shifter
-------------------------------------------------------------------------------
-- Copyright (c) 2011   Actel Corporation
--                      All rights reserved.
-------------------------------------------------------------------------------

library IEEE;
use     IEEE.std_logic_1164.all;

entity shifter_r is
port (
      INPUT  : in  std_logic_vector(29 downto 0);
      CLK    : in  std_logic;
      SHIFT  : in  std_logic_vector(3 downto 0);
      OUTPUT : out std_logic_vector(29 downto 0)
      );
end shifter_r;

architecture shift_right of shifter_r is
begin

process(CLK,SHIFT,INPUT)
begin
   if (CLK = '1') then
       case SHIFT is

        when "0000" => OUTPUT<=INPUT;
        when "0001" => OUTPUT<=INPUT(29)&INPUT(29 downto 1);
        when "0010" => OUTPUT<=INPUT(29)&INPUT(29)&INPUT(29 downto 2);
        when "0011" => OUTPUT<=INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29 downto 3);
        when "0100" => OUTPUT<=INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29 downto 4);
        when "0101" => OUTPUT<=INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29 downto 5);
        when "0110" => OUTPUT<=INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29 downto 6);
        when "0111" => OUTPUT<=INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29 downto 7);
        when "1000" => OUTPUT<=INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29 downto 8);
        when "1001" => OUTPUT<=INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29 downto 9);
        when "1010" => OUTPUT<=INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29 downto 10);
        when "1011" => OUTPUT<=INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29 downto 11);
        when "1100" => OUTPUT<=INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29 downto 12);
        when "1101" => OUTPUT<=INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29 downto 13);
        when "1110" => OUTPUT<=INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29 downto 14);
        when "1111" => OUTPUT<=INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29)&INPUT(29 downto 15);
        when others => OUTPUT<=INPUT;        
      end case;
   end if;
end process;

end shift_right;