-- Version: 9.1 9.1.0.18

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity MSS_FLAC_PLAYER is

    port( FAB_CLK     : out   std_logic;
          MAINXIN     : in    std_logic;
          MSSPSEL     : out   std_logic;
          MSSPENABLE  : out   std_logic;
          MSSPWRITE   : out   std_logic;
          MSSPREADY   : in    std_logic;
          MSSPSLVERR  : in    std_logic;
          FABPSEL     : in    std_logic;
          FABPENABLE  : in    std_logic;
          FABPWRITE   : in    std_logic;
          FABPREADY   : out   std_logic;
          FABPSLVERR  : out   std_logic;
          M2F_RESET_N : out   std_logic;
          F2M_GPI_5   : in    std_logic;
          M2F_GPO_4   : out   std_logic;
          M2F_GPO_3   : out   std_logic;
          F2M_GPI_2   : in    std_logic;
          M2F_GPO_1   : out   std_logic;
          F2M_GPI_0   : in    std_logic;
          MSSPADDR    : out   std_logic_vector(19 downto 0);
          MSSPRDATA   : in    std_logic_vector(31 downto 0);
          MSSPWDATA   : out   std_logic_vector(31 downto 0);
          FABPADDR    : in    std_logic_vector(31 downto 0);
          FABPRDATA   : out   std_logic_vector(31 downto 0);
          FABPWDATA   : in    std_logic_vector(31 downto 0);
          UART_0_TXD  : out   std_logic;
          UART_0_RXD  : in    std_logic;
          SPI_1_DI    : in    std_logic;
          SPI_1_DO    : out   std_logic;
          SPI_1_CLK   : inout std_logic := 'Z';
          SPI_1_SS    : inout std_logic := 'Z';
          EMC_DB      : inout std_logic_vector(15 downto 0) := (others => 'Z');
          EMC_AB      : out   std_logic_vector(25 downto 0);
          EMC_BYTEN   : out   std_logic_vector(1 downto 0);
          EMC_CS0_N   : out   std_logic;
          EMC_CS1_N   : out   std_logic;
          EMC_OEN0_N  : out   std_logic;
          EMC_OEN1_N  : out   std_logic;
          EMC_CLK     : out   std_logic;
          EMC_RW_N    : out   std_logic;
          SDD_0       : out   std_logic;
          VAREF0      : in    std_logic;
          MSS_RESET_N : in    std_logic
        );

end MSS_FLAC_PLAYER;

architecture DEF_ARCH of MSS_FLAC_PLAYER is 

  component BIBUF_MSS
    generic (ACT_CONFIG:integer := 0; ACT_PIN:string := "");

    port( PAD : inout   std_logic;
          D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component OUTBUF_MSS
    generic (ACT_CONFIG:integer := 0; ACT_PIN:string := "");

    port( D   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component INBUF_A
    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component MSSINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component INBUF_MSS
    generic (ACT_CONFIG:integer := 0; ACT_PIN:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC
    port( CLKA           : in    std_logic := 'U';
          CLKA_PAD       : in    std_logic := 'U';
          CLKA_PADP      : in    std_logic := 'U';
          CLKA_PADN      : in    std_logic := 'U';
          CLKB           : in    std_logic := 'U';
          CLKB_PAD       : in    std_logic := 'U';
          CLKB_PADP      : in    std_logic := 'U';
          CLKB_PADN      : in    std_logic := 'U';
          CLKC           : in    std_logic := 'U';
          CLKC_PAD       : in    std_logic := 'U';
          CLKC_PADP      : in    std_logic := 'U';
          CLKC_PADN      : in    std_logic := 'U';
          GLA            : out   std_logic;
          GLB            : out   std_logic;
          GLC            : out   std_logic;
          FAB_CLK        : out   std_logic;
          YB             : out   std_logic;
          YC             : out   std_logic;
          MAINXIN        : in    std_logic := 'U';
          LPXIN          : in    std_logic := 'U';
          FAB_LOCK       : out   std_logic;
          MAC_CLK        : in    std_logic := 'U';
          RCOSC_CLKOUT   : out   std_logic;
          MAINXIN_CLKOUT : out   std_logic;
          LPXIN_CLKOUT   : out   std_logic;
          GLA0           : out   std_logic;
          MSS_LOCK       : out   std_logic;
          MAC_CLK_CCC    : out   std_logic;
          MAC_CLK_IO     : out   std_logic
        );
  end component;

  component OUTBUF_A
    port( D   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component MSS_APB
    generic (ACT_CONFIG:integer := 0; ACT_DIE:string := ""; 
        ACT_FCLK:integer := 0; ACT_PKG:string := "");

    port( MSSPADDR       : out   std_logic_vector(19 downto 0);
          MSSPWDATA      : out   std_logic_vector(31 downto 0);
          MSSPWRITE      : out   std_logic;
          MSSPSEL        : out   std_logic;
          MSSPENABLE     : out   std_logic;
          MSSPRDATA      : in    std_logic_vector(31 downto 0) := (others => 'U');
          MSSPREADY      : in    std_logic := 'U';
          MSSPSLVERR     : in    std_logic := 'U';
          FABPADDR       : in    std_logic_vector(31 downto 0) := (others => 'U');
          FABPWDATA      : in    std_logic_vector(31 downto 0) := (others => 'U');
          FABPWRITE      : in    std_logic := 'U';
          FABPSEL        : in    std_logic := 'U';
          FABPENABLE     : in    std_logic := 'U';
          FABPRDATA      : out   std_logic_vector(31 downto 0);
          FABPREADY      : out   std_logic;
          FABPSLVERR     : out   std_logic;
          SYNCCLKFDBK    : in    std_logic := 'U';
          CALIBOUT       : out   std_logic;
          CALIBIN        : in    std_logic := 'U';
          FABINT         : in    std_logic := 'U';
          MSSINT         : out   std_logic_vector(7 downto 0);
          WDINT          : out   std_logic;
          F2MRESETn      : in    std_logic := 'U';
          DMAREADY       : in    std_logic_vector(1 downto 0) := (others => 'U');
          RXEV           : in    std_logic := 'U';
          VRON           : in    std_logic := 'U';
          M2FRESETn      : out   std_logic;
          DEEPSLEEP      : out   std_logic;
          SLEEP          : out   std_logic;
          TXEV           : out   std_logic;
          GPI            : in    std_logic_vector(31 downto 0) := (others => 'U');
          GPO            : out   std_logic_vector(31 downto 0);
          UART0CTSn      : in    std_logic := 'U';
          UART0DSRn      : in    std_logic := 'U';
          UART0RIn       : in    std_logic := 'U';
          UART0DCDn      : in    std_logic := 'U';
          UART0RTSn      : out   std_logic;
          UART0DTRn      : out   std_logic;
          UART1CTSn      : in    std_logic := 'U';
          UART1DSRn      : in    std_logic := 'U';
          UART1RIn       : in    std_logic := 'U';
          UART1DCDn      : in    std_logic := 'U';
          UART1RTSn      : out   std_logic;
          UART1DTRn      : out   std_logic;
          I2C0SMBUSNI    : in    std_logic := 'U';
          I2C0SMBALERTNI : in    std_logic := 'U';
          I2C0BCLK       : in    std_logic := 'U';
          I2C0SMBUSNO    : out   std_logic;
          I2C0SMBALERTNO : out   std_logic;
          I2C1SMBUSNI    : in    std_logic := 'U';
          I2C1SMBALERTNI : in    std_logic := 'U';
          I2C1BCLK       : in    std_logic := 'U';
          I2C1SMBUSNO    : out   std_logic;
          I2C1SMBALERTNO : out   std_logic;
          MACM2FTXD      : out   std_logic_vector(1 downto 0);
          MACF2MRXD      : in    std_logic_vector(1 downto 0) := (others => 'U');
          MACM2FTXEN     : out   std_logic;
          MACF2MCRSDV    : in    std_logic := 'U';
          MACF2MRXER     : in    std_logic := 'U';
          MACF2MMDI      : in    std_logic := 'U';
          MACM2FMDO      : out   std_logic;
          MACM2FMDEN     : out   std_logic;
          MACM2FMDC      : out   std_logic;
          FABSDD0D       : in    std_logic := 'U';
          FABSDD1D       : in    std_logic := 'U';
          FABSDD2D       : in    std_logic := 'U';
          FABSDD0CLK     : in    std_logic := 'U';
          FABSDD1CLK     : in    std_logic := 'U';
          FABSDD2CLK     : in    std_logic := 'U';
          FABACETRIG     : in    std_logic := 'U';
          ACEFLAGS       : out   std_logic_vector(31 downto 0);
          CMP0           : out   std_logic;
          CMP1           : out   std_logic;
          CMP2           : out   std_logic;
          CMP3           : out   std_logic;
          CMP4           : out   std_logic;
          CMP5           : out   std_logic;
          CMP6           : out   std_logic;
          CMP7           : out   std_logic;
          CMP8           : out   std_logic;
          CMP9           : out   std_logic;
          CMP10          : out   std_logic;
          CMP11          : out   std_logic;
          LVTTL0EN       : in    std_logic := 'U';
          LVTTL1EN       : in    std_logic := 'U';
          LVTTL2EN       : in    std_logic := 'U';
          LVTTL3EN       : in    std_logic := 'U';
          LVTTL4EN       : in    std_logic := 'U';
          LVTTL5EN       : in    std_logic := 'U';
          LVTTL6EN       : in    std_logic := 'U';
          LVTTL7EN       : in    std_logic := 'U';
          LVTTL8EN       : in    std_logic := 'U';
          LVTTL9EN       : in    std_logic := 'U';
          LVTTL10EN      : in    std_logic := 'U';
          LVTTL11EN      : in    std_logic := 'U';
          LVTTL0         : out   std_logic;
          LVTTL1         : out   std_logic;
          LVTTL2         : out   std_logic;
          LVTTL3         : out   std_logic;
          LVTTL4         : out   std_logic;
          LVTTL5         : out   std_logic;
          LVTTL6         : out   std_logic;
          LVTTL7         : out   std_logic;
          LVTTL8         : out   std_logic;
          LVTTL9         : out   std_logic;
          LVTTL10        : out   std_logic;
          LVTTL11        : out   std_logic;
          PUFABn         : out   std_logic;
          VCC15GOOD      : out   std_logic;
          VCC33GOOD      : out   std_logic;
          FCLK           : in    std_logic := 'U';
          MACCLKCCC      : in    std_logic := 'U';
          RCOSC          : in    std_logic := 'U';
          MACCLK         : in    std_logic := 'U';
          PLLLOCK        : in    std_logic := 'U';
          MSSRESETn      : in    std_logic := 'U';
          GPOE           : out   std_logic_vector(31 downto 0);
          SPI0DO         : out   std_logic;
          SPI0DOE        : out   std_logic;
          SPI0DI         : in    std_logic := 'U';
          SPI0CLKI       : in    std_logic := 'U';
          SPI0CLKO       : out   std_logic;
          SPI0MODE       : out   std_logic;
          SPI0SSI        : in    std_logic := 'U';
          SPI0SSO        : out   std_logic_vector(7 downto 0);
          UART0TXD       : out   std_logic;
          UART0RXD       : in    std_logic := 'U';
          I2C0SDAI       : in    std_logic := 'U';
          I2C0SDAO       : out   std_logic;
          I2C0SCLI       : in    std_logic := 'U';
          I2C0SCLO       : out   std_logic;
          SPI1DO         : out   std_logic;
          SPI1DOE        : out   std_logic;
          SPI1DI         : in    std_logic := 'U';
          SPI1CLKI       : in    std_logic := 'U';
          SPI1CLKO       : out   std_logic;
          SPI1MODE       : out   std_logic;
          SPI1SSI        : in    std_logic := 'U';
          SPI1SSO        : out   std_logic_vector(7 downto 0);
          UART1TXD       : out   std_logic;
          UART1RXD       : in    std_logic := 'U';
          I2C1SDAI       : in    std_logic := 'U';
          I2C1SDAO       : out   std_logic;
          I2C1SCLI       : in    std_logic := 'U';
          I2C1SCLO       : out   std_logic;
          MACTXD         : out   std_logic_vector(1 downto 0);
          MACRXD         : in    std_logic_vector(1 downto 0) := (others => 'U');
          MACTXEN        : out   std_logic;
          MACCRSDV       : in    std_logic := 'U';
          MACRXER        : in    std_logic := 'U';
          MACMDI         : in    std_logic := 'U';
          MACMDO         : out   std_logic;
          MACMDEN        : out   std_logic;
          MACMDC         : out   std_logic;
          EMCCLK         : out   std_logic;
          EMCCLKRTN      : in    std_logic := 'U';
          EMCRDB         : in    std_logic_vector(15 downto 0) := (others => 'U');
          EMCAB          : out   std_logic_vector(25 downto 0);
          EMCWDB         : out   std_logic_vector(15 downto 0);
          EMCRWn         : out   std_logic;
          EMCCS0n        : out   std_logic;
          EMCCS1n        : out   std_logic;
          EMCOEN0n       : out   std_logic;
          EMCOEN1n       : out   std_logic;
          EMCBYTEN       : out   std_logic_vector(1 downto 0);
          EMCDBOE        : out   std_logic;
          ADC0           : in    std_logic := 'U';
          ADC1           : in    std_logic := 'U';
          ADC2           : in    std_logic := 'U';
          ADC3           : in    std_logic := 'U';
          ADC4           : in    std_logic := 'U';
          ADC5           : in    std_logic := 'U';
          ADC6           : in    std_logic := 'U';
          ADC7           : in    std_logic := 'U';
          ADC8           : in    std_logic := 'U';
          ADC9           : in    std_logic := 'U';
          ADC10          : in    std_logic := 'U';
          ADC11          : in    std_logic := 'U';
          SDD0           : out   std_logic;
          SDD1           : out   std_logic;
          SDD2           : out   std_logic;
          ABPS0          : in    std_logic := 'U';
          ABPS1          : in    std_logic := 'U';
          ABPS2          : in    std_logic := 'U';
          ABPS3          : in    std_logic := 'U';
          ABPS4          : in    std_logic := 'U';
          ABPS5          : in    std_logic := 'U';
          ABPS6          : in    std_logic := 'U';
          ABPS7          : in    std_logic := 'U';
          ABPS8          : in    std_logic := 'U';
          ABPS9          : in    std_logic := 'U';
          ABPS10         : in    std_logic := 'U';
          ABPS11         : in    std_logic := 'U';
          TM0            : in    std_logic := 'U';
          TM1            : in    std_logic := 'U';
          TM2            : in    std_logic := 'U';
          TM3            : in    std_logic := 'U';
          TM4            : in    std_logic := 'U';
          TM5            : in    std_logic := 'U';
          CM0            : in    std_logic := 'U';
          CM1            : in    std_logic := 'U';
          CM2            : in    std_logic := 'U';
          CM3            : in    std_logic := 'U';
          CM4            : in    std_logic := 'U';
          CM5            : in    std_logic := 'U';
          GNDTM0         : in    std_logic := 'U';
          GNDTM1         : in    std_logic := 'U';
          GNDTM2         : in    std_logic := 'U';
          VAREF0         : in    std_logic := 'U';
          VAREF1         : in    std_logic := 'U';
          VAREF2         : in    std_logic := 'U';
          VAREFOUT       : out   std_logic;
          GNDVAREF       : in    std_logic := 'U';
          PUn            : in    std_logic := 'U'
        );
  end component;

  component TRIBUFF_MSS
    generic (ACT_CONFIG:integer := 0; ACT_PIN:string := "");

    port( D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

    signal MSSINT_GPI_0_Y, MSSINT_GPI_2_Y, MSSINT_GPI_5_Y, 
        MSSINT_GPO_1_A, MSSINT_GPO_3_A, MSSINT_GPO_4_A, 
        MSS_ACE_0_SDD0_D, MSS_ACE_0_VAREF0_Y, MSS_ADLIB_INST_FCLK, 
        MSS_ADLIB_INST_MACCLK, MSS_ADLIB_INST_MACCLKCCC, 
        MSS_ADLIB_INST_PLLLOCK, MSS_ADLIB_INST_SYNCCLKFDBK, 
        MSS_EMI_0_AB_0_D, MSS_EMI_0_AB_10_D, MSS_EMI_0_AB_11_D, 
        MSS_EMI_0_AB_12_D, MSS_EMI_0_AB_13_D, MSS_EMI_0_AB_14_D, 
        MSS_EMI_0_AB_15_D, MSS_EMI_0_AB_16_D, MSS_EMI_0_AB_17_D, 
        MSS_EMI_0_AB_18_D, MSS_EMI_0_AB_19_D, MSS_EMI_0_AB_1_D, 
        MSS_EMI_0_AB_20_D, MSS_EMI_0_AB_21_D, MSS_EMI_0_AB_22_D, 
        MSS_EMI_0_AB_23_D, MSS_EMI_0_AB_24_D, MSS_EMI_0_AB_25_D, 
        MSS_EMI_0_AB_2_D, MSS_EMI_0_AB_3_D, MSS_EMI_0_AB_4_D, 
        MSS_EMI_0_AB_5_D, MSS_EMI_0_AB_6_D, MSS_EMI_0_AB_7_D, 
        MSS_EMI_0_AB_8_D, MSS_EMI_0_AB_9_D, MSS_EMI_0_BYTEN_0_D, 
        MSS_EMI_0_BYTEN_1_D, MSS_EMI_0_CLK_D, MSS_EMI_0_CS0_N_D, 
        MSS_EMI_0_CS1_N_D, MSS_EMI_0_DB_0_D, MSS_EMI_0_DB_0_Y, 
        MSS_EMI_0_DB_10_D, MSS_EMI_0_DB_10_Y, MSS_EMI_0_DB_11_D, 
        MSS_EMI_0_DB_11_Y, MSS_EMI_0_DB_12_D, MSS_EMI_0_DB_12_Y, 
        MSS_EMI_0_DB_13_D, MSS_EMI_0_DB_13_Y, MSS_EMI_0_DB_14_D, 
        MSS_EMI_0_DB_14_Y, MSS_EMI_0_DB_15_D, MSS_EMI_0_DB_15_E, 
        MSS_EMI_0_DB_15_Y, MSS_EMI_0_DB_1_D, MSS_EMI_0_DB_1_Y, 
        MSS_EMI_0_DB_2_D, MSS_EMI_0_DB_2_Y, MSS_EMI_0_DB_3_D, 
        MSS_EMI_0_DB_3_Y, MSS_EMI_0_DB_4_D, MSS_EMI_0_DB_4_Y, 
        MSS_EMI_0_DB_5_D, MSS_EMI_0_DB_5_Y, MSS_EMI_0_DB_6_D, 
        MSS_EMI_0_DB_6_Y, MSS_EMI_0_DB_7_D, MSS_EMI_0_DB_7_Y, 
        MSS_EMI_0_DB_8_D, MSS_EMI_0_DB_8_Y, MSS_EMI_0_DB_9_D, 
        MSS_EMI_0_DB_9_Y, MSS_EMI_0_OEN0_N_D, MSS_EMI_0_OEN1_N_D, 
        MSS_EMI_0_RW_N_D, MSS_RESET_0_MSS_RESET_N_Y, 
        MSS_SPI_1_CLK_D, MSS_SPI_1_CLK_Y, MSS_SPI_1_DI_Y, 
        MSS_SPI_1_DO_D, MSS_SPI_1_DO_E, MSS_SPI_1_SS_D, 
        MSS_SPI_1_SS_E, MSS_SPI_1_SS_Y, MSS_UART_0_RXD_Y, 
        MSS_UART_0_TXD_D, GND_net, VCC_net : std_logic;
    signal nc47, nc113, nc111, nc34, nc98, nc89, nc70, nc60, 
        nc105, nc74, nc120, nc119, nc64, nc110, nc9, nc92, nc91, 
        nc13, nc23, nc55, nc80, nc33, nc84, nc16, nc26, nc45, 
        nc73, nc58, nc63, nc27, nc17, nc99, nc117, nc36, nc116, 
        nc48, nc37, nc5, nc103, nc101, nc52, nc76, nc51, nc66, 
        nc77, nc67, nc4, nc109, nc42, nc114, nc100, nc83, nc41, 
        nc90, nc94, nc112, nc86, nc59, nc25, nc15, nc87, nc35, 
        nc49, nc28, nc18, nc107, nc118, nc106, nc75, nc65, nc38, 
        nc93, nc1, nc2, nc50, nc22, nc12, nc21, nc11, nc78, nc54, 
        nc68, nc3, nc32, nc104, nc40, nc31, nc96, nc44, nc7, nc97, 
        nc85, nc72, nc6, nc71, nc62, nc61, nc115, nc102, nc19, 
        nc29, nc88, nc53, nc39, nc8, nc82, nc108, nc81, nc79, 
        nc43, nc69, nc56, nc20, nc10, nc57, nc95, nc24, nc14, 
        nc46, nc30 : std_logic;

begin 

    FAB_CLK <= MSS_ADLIB_INST_SYNCCLKFDBK;

    MSS_EMI_0_DB_12 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D2")

      port map(PAD => EMC_DB(12), D => MSS_EMI_0_DB_12_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_12_Y);
    
    MSS_EMI_0_AB_24 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C16")

      port map(D => MSS_EMI_0_AB_24_D, PAD => EMC_AB(24));
    
    MSS_EMI_0_AB_4 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "E11")

      port map(D => MSS_EMI_0_AB_4_D, PAD => EMC_AB(4));
    
    MSS_EMI_0_AB_22 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C17")

      port map(D => MSS_EMI_0_AB_22_D, PAD => EMC_AB(22));
    
    MSS_EMI_0_OEN0_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D10")

      port map(D => MSS_EMI_0_OEN0_N_D, PAD => EMC_OEN0_N);
    
    MSS_EMI_0_CS1_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A6")

      port map(D => MSS_EMI_0_CS1_N_D, PAD => EMC_CS1_N);
    
    MSS_EMI_0_AB_7 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A12")

      port map(D => MSS_EMI_0_AB_7_D, PAD => EMC_AB(7));
    
    MSS_EMI_0_AB_23 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C18")

      port map(D => MSS_EMI_0_AB_23_D, PAD => EMC_AB(23));
    
    MSS_EMI_0_DB_10 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "F4")

      port map(PAD => EMC_DB(10), D => MSS_EMI_0_DB_10_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_10_Y);
    
    MSS_EMI_0_DB_2 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "K5")

      port map(PAD => EMC_DB(2), D => MSS_EMI_0_DB_2_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_2_Y);
    
    MSS_EMI_0_BYTEN_0 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B9")

      port map(D => MSS_EMI_0_BYTEN_0_D, PAD => EMC_BYTEN(0));
    
    MSS_ACE_0_VAREF0 : INBUF_A
      port map(PAD => VAREF0, Y => MSS_ACE_0_VAREF0_Y);
    
    MSSINT_GPO_1 : MSSINT
      port map(A => MSSINT_GPO_1_A, Y => M2F_GPO_1);
    
    MSS_EMI_0_AB_25 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D16")

      port map(D => MSS_EMI_0_AB_25_D, PAD => EMC_AB(25));
    
    MSS_EMI_0_AB_19 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B17")

      port map(D => MSS_EMI_0_AB_19_D, PAD => EMC_AB(19));
    
    \VCC\ : VCC
      port map(Y => VCC_net);
    
    MSS_EMI_0_OEN1_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C10")

      port map(D => MSS_EMI_0_OEN1_N_D, PAD => EMC_OEN1_N);
    
    MSS_EMI_0_AB_14 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B13")

      port map(D => MSS_EMI_0_AB_14_D, PAD => EMC_AB(14));
    
    MSS_EMI_0_AB_2 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B10")

      port map(D => MSS_EMI_0_AB_2_D, PAD => EMC_AB(2));
    
    MSS_EMI_0_AB_12 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A14")

      port map(D => MSS_EMI_0_AB_12_D, PAD => EMC_AB(12));
    
    MSS_SPI_1_CLK : BIBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "AA22")

      port map(PAD => SPI_1_CLK, D => MSS_SPI_1_CLK_D, E => 
        MSS_SPI_1_SS_E, Y => MSS_SPI_1_CLK_Y);
    
    MSS_EMI_0_AB_20 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "F13")

      port map(D => MSS_EMI_0_AB_20_D, PAD => EMC_AB(20));
    
    MSS_EMI_0_DB_3 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "J4")

      port map(PAD => EMC_DB(3), D => MSS_EMI_0_DB_3_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_3_Y);
    
    MSS_EMI_0_AB_17 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C15")

      port map(D => MSS_EMI_0_AB_17_D, PAD => EMC_AB(17));
    
    MSS_EMI_0_DB_8 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "H3")

      port map(PAD => EMC_DB(8), D => MSS_EMI_0_DB_8_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_8_Y);
    
    MSS_EMI_0_DB_6 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "J1")

      port map(PAD => EMC_DB(6), D => MSS_EMI_0_DB_6_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_6_Y);
    
    MSS_EMI_0_AB_13 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A15")

      port map(D => MSS_EMI_0_AB_13_D, PAD => EMC_AB(13));
    
    MSS_EMI_0_AB_21 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "F14")

      port map(D => MSS_EMI_0_AB_21_D, PAD => EMC_AB(21));
    
    MSS_EMI_0_DB_1 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "K3")

      port map(PAD => EMC_DB(1), D => MSS_EMI_0_DB_1_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_1_Y);
    
    MSS_EMI_0_AB_16 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C14")

      port map(D => MSS_EMI_0_AB_16_D, PAD => EMC_AB(16));
    
    MSS_EMI_0_DB_11 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "G5")

      port map(PAD => EMC_DB(11), D => MSS_EMI_0_DB_11_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_11_Y);
    
    \GND\ : GND
      port map(Y => GND_net);
    
    MSS_RESET_0_MSS_RESET_N : INBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "R1")

      port map(PAD => MSS_RESET_N, Y => MSS_RESET_0_MSS_RESET_N_Y);
    
    MSS_EMI_0_DB_0 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "K2")

      port map(PAD => EMC_DB(0), D => MSS_EMI_0_DB_0_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_0_Y);
    
    MSS_EMI_0_AB_15 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B14")

      port map(D => MSS_EMI_0_AB_15_D, PAD => EMC_AB(15));
    
    MSS_CCC_0 : MSS_FLAC_PLAYER_tmp_MSS_CCC_0_MSS_CCC
      port map(CLKA => GND_net, CLKA_PAD => GND_net, CLKA_PADP
         => GND_net, CLKA_PADN => GND_net, CLKB => GND_net, 
        CLKB_PAD => GND_net, CLKB_PADP => GND_net, CLKB_PADN => 
        GND_net, CLKC => GND_net, CLKC_PAD => GND_net, CLKC_PADP
         => GND_net, CLKC_PADN => GND_net, GLA => OPEN, GLB => 
        OPEN, GLC => OPEN, FAB_CLK => MSS_ADLIB_INST_SYNCCLKFDBK, 
        YB => OPEN, YC => OPEN, MAINXIN => MAINXIN, LPXIN => 
        GND_net, FAB_LOCK => OPEN, MAC_CLK => GND_net, 
        RCOSC_CLKOUT => OPEN, MAINXIN_CLKOUT => OPEN, 
        LPXIN_CLKOUT => OPEN, GLA0 => MSS_ADLIB_INST_FCLK, 
        MSS_LOCK => MSS_ADLIB_INST_PLLLOCK, MAC_CLK_CCC => 
        MSS_ADLIB_INST_MACCLKCCC, MAC_CLK_IO => 
        MSS_ADLIB_INST_MACCLK);
    
    MSS_EMI_0_AB_3 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B11")

      port map(D => MSS_EMI_0_AB_3_D, PAD => EMC_AB(3));
    
    MSS_EMI_0_AB_8 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C13")

      port map(D => MSS_EMI_0_AB_8_D, PAD => EMC_AB(8));
    
    MSS_ACE_0_SDD0 : OUTBUF_A
      port map(D => MSS_ACE_0_SDD0_D, PAD => SDD_0);
    
    MSS_EMI_0_AB_6 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B12")

      port map(D => MSS_EMI_0_AB_6_D, PAD => EMC_AB(6));
    
    MSS_ADLIB_INST : MSS_APB
      generic map(ACT_CONFIG => 640, ACT_DIE => "IP6X5M2",
         ACT_FCLK => 80000000, ACT_PKG => "fg484")

      port map(MSSPADDR(19) => MSSPADDR(19), MSSPADDR(18) => 
        MSSPADDR(18), MSSPADDR(17) => MSSPADDR(17), MSSPADDR(16)
         => MSSPADDR(16), MSSPADDR(15) => MSSPADDR(15), 
        MSSPADDR(14) => MSSPADDR(14), MSSPADDR(13) => 
        MSSPADDR(13), MSSPADDR(12) => MSSPADDR(12), MSSPADDR(11)
         => MSSPADDR(11), MSSPADDR(10) => MSSPADDR(10), 
        MSSPADDR(9) => MSSPADDR(9), MSSPADDR(8) => MSSPADDR(8), 
        MSSPADDR(7) => MSSPADDR(7), MSSPADDR(6) => MSSPADDR(6), 
        MSSPADDR(5) => MSSPADDR(5), MSSPADDR(4) => MSSPADDR(4), 
        MSSPADDR(3) => MSSPADDR(3), MSSPADDR(2) => MSSPADDR(2), 
        MSSPADDR(1) => MSSPADDR(1), MSSPADDR(0) => MSSPADDR(0), 
        MSSPWDATA(31) => MSSPWDATA(31), MSSPWDATA(30) => 
        MSSPWDATA(30), MSSPWDATA(29) => MSSPWDATA(29), 
        MSSPWDATA(28) => MSSPWDATA(28), MSSPWDATA(27) => 
        MSSPWDATA(27), MSSPWDATA(26) => MSSPWDATA(26), 
        MSSPWDATA(25) => MSSPWDATA(25), MSSPWDATA(24) => 
        MSSPWDATA(24), MSSPWDATA(23) => MSSPWDATA(23), 
        MSSPWDATA(22) => MSSPWDATA(22), MSSPWDATA(21) => 
        MSSPWDATA(21), MSSPWDATA(20) => MSSPWDATA(20), 
        MSSPWDATA(19) => MSSPWDATA(19), MSSPWDATA(18) => 
        MSSPWDATA(18), MSSPWDATA(17) => MSSPWDATA(17), 
        MSSPWDATA(16) => MSSPWDATA(16), MSSPWDATA(15) => 
        MSSPWDATA(15), MSSPWDATA(14) => MSSPWDATA(14), 
        MSSPWDATA(13) => MSSPWDATA(13), MSSPWDATA(12) => 
        MSSPWDATA(12), MSSPWDATA(11) => MSSPWDATA(11), 
        MSSPWDATA(10) => MSSPWDATA(10), MSSPWDATA(9) => 
        MSSPWDATA(9), MSSPWDATA(8) => MSSPWDATA(8), MSSPWDATA(7)
         => MSSPWDATA(7), MSSPWDATA(6) => MSSPWDATA(6), 
        MSSPWDATA(5) => MSSPWDATA(5), MSSPWDATA(4) => 
        MSSPWDATA(4), MSSPWDATA(3) => MSSPWDATA(3), MSSPWDATA(2)
         => MSSPWDATA(2), MSSPWDATA(1) => MSSPWDATA(1), 
        MSSPWDATA(0) => MSSPWDATA(0), MSSPWRITE => MSSPWRITE, 
        MSSPSEL => MSSPSEL, MSSPENABLE => MSSPENABLE, 
        MSSPRDATA(31) => MSSPRDATA(31), MSSPRDATA(30) => 
        MSSPRDATA(30), MSSPRDATA(29) => MSSPRDATA(29), 
        MSSPRDATA(28) => MSSPRDATA(28), MSSPRDATA(27) => 
        MSSPRDATA(27), MSSPRDATA(26) => MSSPRDATA(26), 
        MSSPRDATA(25) => MSSPRDATA(25), MSSPRDATA(24) => 
        MSSPRDATA(24), MSSPRDATA(23) => MSSPRDATA(23), 
        MSSPRDATA(22) => MSSPRDATA(22), MSSPRDATA(21) => 
        MSSPRDATA(21), MSSPRDATA(20) => MSSPRDATA(20), 
        MSSPRDATA(19) => MSSPRDATA(19), MSSPRDATA(18) => 
        MSSPRDATA(18), MSSPRDATA(17) => MSSPRDATA(17), 
        MSSPRDATA(16) => MSSPRDATA(16), MSSPRDATA(15) => 
        MSSPRDATA(15), MSSPRDATA(14) => MSSPRDATA(14), 
        MSSPRDATA(13) => MSSPRDATA(13), MSSPRDATA(12) => 
        MSSPRDATA(12), MSSPRDATA(11) => MSSPRDATA(11), 
        MSSPRDATA(10) => MSSPRDATA(10), MSSPRDATA(9) => 
        MSSPRDATA(9), MSSPRDATA(8) => MSSPRDATA(8), MSSPRDATA(7)
         => MSSPRDATA(7), MSSPRDATA(6) => MSSPRDATA(6), 
        MSSPRDATA(5) => MSSPRDATA(5), MSSPRDATA(4) => 
        MSSPRDATA(4), MSSPRDATA(3) => MSSPRDATA(3), MSSPRDATA(2)
         => MSSPRDATA(2), MSSPRDATA(1) => MSSPRDATA(1), 
        MSSPRDATA(0) => MSSPRDATA(0), MSSPREADY => MSSPREADY, 
        MSSPSLVERR => MSSPSLVERR, FABPADDR(31) => FABPADDR(31), 
        FABPADDR(30) => FABPADDR(30), FABPADDR(29) => 
        FABPADDR(29), FABPADDR(28) => FABPADDR(28), FABPADDR(27)
         => FABPADDR(27), FABPADDR(26) => FABPADDR(26), 
        FABPADDR(25) => FABPADDR(25), FABPADDR(24) => 
        FABPADDR(24), FABPADDR(23) => FABPADDR(23), FABPADDR(22)
         => FABPADDR(22), FABPADDR(21) => FABPADDR(21), 
        FABPADDR(20) => FABPADDR(20), FABPADDR(19) => 
        FABPADDR(19), FABPADDR(18) => FABPADDR(18), FABPADDR(17)
         => FABPADDR(17), FABPADDR(16) => FABPADDR(16), 
        FABPADDR(15) => FABPADDR(15), FABPADDR(14) => 
        FABPADDR(14), FABPADDR(13) => FABPADDR(13), FABPADDR(12)
         => FABPADDR(12), FABPADDR(11) => FABPADDR(11), 
        FABPADDR(10) => FABPADDR(10), FABPADDR(9) => FABPADDR(9), 
        FABPADDR(8) => FABPADDR(8), FABPADDR(7) => FABPADDR(7), 
        FABPADDR(6) => FABPADDR(6), FABPADDR(5) => FABPADDR(5), 
        FABPADDR(4) => FABPADDR(4), FABPADDR(3) => FABPADDR(3), 
        FABPADDR(2) => FABPADDR(2), FABPADDR(1) => FABPADDR(1), 
        FABPADDR(0) => FABPADDR(0), FABPWDATA(31) => 
        FABPWDATA(31), FABPWDATA(30) => FABPWDATA(30), 
        FABPWDATA(29) => FABPWDATA(29), FABPWDATA(28) => 
        FABPWDATA(28), FABPWDATA(27) => FABPWDATA(27), 
        FABPWDATA(26) => FABPWDATA(26), FABPWDATA(25) => 
        FABPWDATA(25), FABPWDATA(24) => FABPWDATA(24), 
        FABPWDATA(23) => FABPWDATA(23), FABPWDATA(22) => 
        FABPWDATA(22), FABPWDATA(21) => FABPWDATA(21), 
        FABPWDATA(20) => FABPWDATA(20), FABPWDATA(19) => 
        FABPWDATA(19), FABPWDATA(18) => FABPWDATA(18), 
        FABPWDATA(17) => FABPWDATA(17), FABPWDATA(16) => 
        FABPWDATA(16), FABPWDATA(15) => FABPWDATA(15), 
        FABPWDATA(14) => FABPWDATA(14), FABPWDATA(13) => 
        FABPWDATA(13), FABPWDATA(12) => FABPWDATA(12), 
        FABPWDATA(11) => FABPWDATA(11), FABPWDATA(10) => 
        FABPWDATA(10), FABPWDATA(9) => FABPWDATA(9), FABPWDATA(8)
         => FABPWDATA(8), FABPWDATA(7) => FABPWDATA(7), 
        FABPWDATA(6) => FABPWDATA(6), FABPWDATA(5) => 
        FABPWDATA(5), FABPWDATA(4) => FABPWDATA(4), FABPWDATA(3)
         => FABPWDATA(3), FABPWDATA(2) => FABPWDATA(2), 
        FABPWDATA(1) => FABPWDATA(1), FABPWDATA(0) => 
        FABPWDATA(0), FABPWRITE => FABPWRITE, FABPSEL => FABPSEL, 
        FABPENABLE => FABPENABLE, FABPRDATA(31) => FABPRDATA(31), 
        FABPRDATA(30) => FABPRDATA(30), FABPRDATA(29) => 
        FABPRDATA(29), FABPRDATA(28) => FABPRDATA(28), 
        FABPRDATA(27) => FABPRDATA(27), FABPRDATA(26) => 
        FABPRDATA(26), FABPRDATA(25) => FABPRDATA(25), 
        FABPRDATA(24) => FABPRDATA(24), FABPRDATA(23) => 
        FABPRDATA(23), FABPRDATA(22) => FABPRDATA(22), 
        FABPRDATA(21) => FABPRDATA(21), FABPRDATA(20) => 
        FABPRDATA(20), FABPRDATA(19) => FABPRDATA(19), 
        FABPRDATA(18) => FABPRDATA(18), FABPRDATA(17) => 
        FABPRDATA(17), FABPRDATA(16) => FABPRDATA(16), 
        FABPRDATA(15) => FABPRDATA(15), FABPRDATA(14) => 
        FABPRDATA(14), FABPRDATA(13) => FABPRDATA(13), 
        FABPRDATA(12) => FABPRDATA(12), FABPRDATA(11) => 
        FABPRDATA(11), FABPRDATA(10) => FABPRDATA(10), 
        FABPRDATA(9) => FABPRDATA(9), FABPRDATA(8) => 
        FABPRDATA(8), FABPRDATA(7) => FABPRDATA(7), FABPRDATA(6)
         => FABPRDATA(6), FABPRDATA(5) => FABPRDATA(5), 
        FABPRDATA(4) => FABPRDATA(4), FABPRDATA(3) => 
        FABPRDATA(3), FABPRDATA(2) => FABPRDATA(2), FABPRDATA(1)
         => FABPRDATA(1), FABPRDATA(0) => FABPRDATA(0), FABPREADY
         => FABPREADY, FABPSLVERR => FABPSLVERR, SYNCCLKFDBK => 
        MSS_ADLIB_INST_SYNCCLKFDBK, CALIBOUT => OPEN, CALIBIN => 
        GND_net, FABINT => GND_net, MSSINT(7) => nc47, MSSINT(6)
         => nc113, MSSINT(5) => nc111, MSSINT(4) => nc34, 
        MSSINT(3) => nc98, MSSINT(2) => nc89, MSSINT(1) => nc70, 
        MSSINT(0) => nc60, WDINT => OPEN, F2MRESETn => VCC_net, 
        DMAREADY(1) => GND_net, DMAREADY(0) => GND_net, RXEV => 
        GND_net, VRON => GND_net, M2FRESETn => M2F_RESET_N, 
        DEEPSLEEP => OPEN, SLEEP => OPEN, TXEV => OPEN, GPI(31)
         => GND_net, GPI(30) => GND_net, GPI(29) => GND_net, 
        GPI(28) => GND_net, GPI(27) => GND_net, GPI(26) => 
        GND_net, GPI(25) => GND_net, GPI(24) => GND_net, GPI(23)
         => GND_net, GPI(22) => GND_net, GPI(21) => GND_net, 
        GPI(20) => GND_net, GPI(19) => GND_net, GPI(18) => 
        GND_net, GPI(17) => GND_net, GPI(16) => GND_net, GPI(15)
         => GND_net, GPI(14) => GND_net, GPI(13) => GND_net, 
        GPI(12) => GND_net, GPI(11) => GND_net, GPI(10) => 
        GND_net, GPI(9) => GND_net, GPI(8) => GND_net, GPI(7) => 
        GND_net, GPI(6) => GND_net, GPI(5) => MSSINT_GPI_5_Y, 
        GPI(4) => GND_net, GPI(3) => GND_net, GPI(2) => 
        MSSINT_GPI_2_Y, GPI(1) => GND_net, GPI(0) => 
        MSSINT_GPI_0_Y, GPO(31) => nc105, GPO(30) => nc74, 
        GPO(29) => nc120, GPO(28) => nc119, GPO(27) => nc64, 
        GPO(26) => nc110, GPO(25) => nc9, GPO(24) => nc92, 
        GPO(23) => nc91, GPO(22) => nc13, GPO(21) => nc23, 
        GPO(20) => nc55, GPO(19) => nc80, GPO(18) => nc33, 
        GPO(17) => nc84, GPO(16) => nc16, GPO(15) => nc26, 
        GPO(14) => nc45, GPO(13) => nc73, GPO(12) => nc58, 
        GPO(11) => nc63, GPO(10) => nc27, GPO(9) => nc17, GPO(8)
         => nc99, GPO(7) => nc117, GPO(6) => nc36, GPO(5) => 
        nc116, GPO(4) => MSSINT_GPO_4_A, GPO(3) => MSSINT_GPO_3_A, 
        GPO(2) => nc48, GPO(1) => MSSINT_GPO_1_A, GPO(0) => nc37, 
        UART0CTSn => GND_net, UART0DSRn => GND_net, UART0RIn => 
        GND_net, UART0DCDn => GND_net, UART0RTSn => OPEN, 
        UART0DTRn => OPEN, UART1CTSn => GND_net, UART1DSRn => 
        GND_net, UART1RIn => GND_net, UART1DCDn => GND_net, 
        UART1RTSn => OPEN, UART1DTRn => OPEN, I2C0SMBUSNI => 
        GND_net, I2C0SMBALERTNI => GND_net, I2C0BCLK => GND_net, 
        I2C0SMBUSNO => OPEN, I2C0SMBALERTNO => OPEN, I2C1SMBUSNI
         => GND_net, I2C1SMBALERTNI => GND_net, I2C1BCLK => 
        GND_net, I2C1SMBUSNO => OPEN, I2C1SMBALERTNO => OPEN, 
        MACM2FTXD(1) => nc5, MACM2FTXD(0) => nc103, MACF2MRXD(1)
         => GND_net, MACF2MRXD(0) => GND_net, MACM2FTXEN => OPEN, 
        MACF2MCRSDV => GND_net, MACF2MRXER => GND_net, MACF2MMDI
         => GND_net, MACM2FMDO => OPEN, MACM2FMDEN => OPEN, 
        MACM2FMDC => OPEN, FABSDD0D => GND_net, FABSDD1D => 
        GND_net, FABSDD2D => GND_net, FABSDD0CLK => GND_net, 
        FABSDD1CLK => GND_net, FABSDD2CLK => GND_net, FABACETRIG
         => GND_net, ACEFLAGS(31) => nc101, ACEFLAGS(30) => nc52, 
        ACEFLAGS(29) => nc76, ACEFLAGS(28) => nc51, ACEFLAGS(27)
         => nc66, ACEFLAGS(26) => nc77, ACEFLAGS(25) => nc67, 
        ACEFLAGS(24) => nc4, ACEFLAGS(23) => nc109, ACEFLAGS(22)
         => nc42, ACEFLAGS(21) => nc114, ACEFLAGS(20) => nc100, 
        ACEFLAGS(19) => nc83, ACEFLAGS(18) => nc41, ACEFLAGS(17)
         => nc90, ACEFLAGS(16) => nc94, ACEFLAGS(15) => nc112, 
        ACEFLAGS(14) => nc86, ACEFLAGS(13) => nc59, ACEFLAGS(12)
         => nc25, ACEFLAGS(11) => nc15, ACEFLAGS(10) => nc87, 
        ACEFLAGS(9) => nc35, ACEFLAGS(8) => nc49, ACEFLAGS(7) => 
        nc28, ACEFLAGS(6) => nc18, ACEFLAGS(5) => nc107, 
        ACEFLAGS(4) => nc118, ACEFLAGS(3) => nc106, ACEFLAGS(2)
         => nc75, ACEFLAGS(1) => nc65, ACEFLAGS(0) => nc38, CMP0
         => OPEN, CMP1 => OPEN, CMP2 => OPEN, CMP3 => OPEN, CMP4
         => OPEN, CMP5 => OPEN, CMP6 => OPEN, CMP7 => OPEN, CMP8
         => OPEN, CMP9 => OPEN, CMP10 => OPEN, CMP11 => OPEN, 
        LVTTL0EN => GND_net, LVTTL1EN => GND_net, LVTTL2EN => 
        GND_net, LVTTL3EN => GND_net, LVTTL4EN => GND_net, 
        LVTTL5EN => GND_net, LVTTL6EN => GND_net, LVTTL7EN => 
        GND_net, LVTTL8EN => GND_net, LVTTL9EN => GND_net, 
        LVTTL10EN => GND_net, LVTTL11EN => GND_net, LVTTL0 => 
        OPEN, LVTTL1 => OPEN, LVTTL2 => OPEN, LVTTL3 => OPEN, 
        LVTTL4 => OPEN, LVTTL5 => OPEN, LVTTL6 => OPEN, LVTTL7
         => OPEN, LVTTL8 => OPEN, LVTTL9 => OPEN, LVTTL10 => OPEN, 
        LVTTL11 => OPEN, PUFABn => OPEN, VCC15GOOD => OPEN, 
        VCC33GOOD => OPEN, FCLK => MSS_ADLIB_INST_FCLK, MACCLKCCC
         => MSS_ADLIB_INST_MACCLKCCC, RCOSC => GND_net, MACCLK
         => MSS_ADLIB_INST_MACCLK, PLLLOCK => 
        MSS_ADLIB_INST_PLLLOCK, MSSRESETn => 
        MSS_RESET_0_MSS_RESET_N_Y, GPOE(31) => nc93, GPOE(30) => 
        nc1, GPOE(29) => nc2, GPOE(28) => nc50, GPOE(27) => nc22, 
        GPOE(26) => nc12, GPOE(25) => nc21, GPOE(24) => nc11, 
        GPOE(23) => nc78, GPOE(22) => nc54, GPOE(21) => nc68, 
        GPOE(20) => nc3, GPOE(19) => nc32, GPOE(18) => nc104, 
        GPOE(17) => nc40, GPOE(16) => nc31, GPOE(15) => nc96, 
        GPOE(14) => nc44, GPOE(13) => nc7, GPOE(12) => nc97, 
        GPOE(11) => nc85, GPOE(10) => nc72, GPOE(9) => nc6, 
        GPOE(8) => nc71, GPOE(7) => nc62, GPOE(6) => nc61, 
        GPOE(5) => nc115, GPOE(4) => nc102, GPOE(3) => nc19, 
        GPOE(2) => nc29, GPOE(1) => nc88, GPOE(0) => nc53, SPI0DO
         => OPEN, SPI0DOE => OPEN, SPI0DI => GND_net, SPI0CLKI
         => GND_net, SPI0CLKO => OPEN, SPI0MODE => OPEN, SPI0SSI
         => GND_net, SPI0SSO(7) => nc39, SPI0SSO(6) => nc8, 
        SPI0SSO(5) => nc82, SPI0SSO(4) => nc108, SPI0SSO(3) => 
        nc81, SPI0SSO(2) => nc79, SPI0SSO(1) => nc43, SPI0SSO(0)
         => nc69, UART0TXD => MSS_UART_0_TXD_D, UART0RXD => 
        MSS_UART_0_RXD_Y, I2C0SDAI => GND_net, I2C0SDAO => OPEN, 
        I2C0SCLI => GND_net, I2C0SCLO => OPEN, SPI1DO => 
        MSS_SPI_1_DO_D, SPI1DOE => MSS_SPI_1_DO_E, SPI1DI => 
        MSS_SPI_1_DI_Y, SPI1CLKI => MSS_SPI_1_CLK_Y, SPI1CLKO => 
        MSS_SPI_1_CLK_D, SPI1MODE => MSS_SPI_1_SS_E, SPI1SSI => 
        MSS_SPI_1_SS_Y, SPI1SSO(7) => nc56, SPI1SSO(6) => nc20, 
        SPI1SSO(5) => nc10, SPI1SSO(4) => nc57, SPI1SSO(3) => 
        nc95, SPI1SSO(2) => nc24, SPI1SSO(1) => nc14, SPI1SSO(0)
         => MSS_SPI_1_SS_D, UART1TXD => OPEN, UART1RXD => GND_net, 
        I2C1SDAI => GND_net, I2C1SDAO => OPEN, I2C1SCLI => 
        GND_net, I2C1SCLO => OPEN, MACTXD(1) => nc46, MACTXD(0)
         => nc30, MACRXD(1) => GND_net, MACRXD(0) => GND_net, 
        MACTXEN => OPEN, MACCRSDV => GND_net, MACRXER => GND_net, 
        MACMDI => GND_net, MACMDO => OPEN, MACMDEN => OPEN, 
        MACMDC => OPEN, EMCCLK => MSS_EMI_0_CLK_D, EMCCLKRTN => 
        MSS_EMI_0_CLK_D, EMCRDB(15) => MSS_EMI_0_DB_15_Y, 
        EMCRDB(14) => MSS_EMI_0_DB_14_Y, EMCRDB(13) => 
        MSS_EMI_0_DB_13_Y, EMCRDB(12) => MSS_EMI_0_DB_12_Y, 
        EMCRDB(11) => MSS_EMI_0_DB_11_Y, EMCRDB(10) => 
        MSS_EMI_0_DB_10_Y, EMCRDB(9) => MSS_EMI_0_DB_9_Y, 
        EMCRDB(8) => MSS_EMI_0_DB_8_Y, EMCRDB(7) => 
        MSS_EMI_0_DB_7_Y, EMCRDB(6) => MSS_EMI_0_DB_6_Y, 
        EMCRDB(5) => MSS_EMI_0_DB_5_Y, EMCRDB(4) => 
        MSS_EMI_0_DB_4_Y, EMCRDB(3) => MSS_EMI_0_DB_3_Y, 
        EMCRDB(2) => MSS_EMI_0_DB_2_Y, EMCRDB(1) => 
        MSS_EMI_0_DB_1_Y, EMCRDB(0) => MSS_EMI_0_DB_0_Y, 
        EMCAB(25) => MSS_EMI_0_AB_25_D, EMCAB(24) => 
        MSS_EMI_0_AB_24_D, EMCAB(23) => MSS_EMI_0_AB_23_D, 
        EMCAB(22) => MSS_EMI_0_AB_22_D, EMCAB(21) => 
        MSS_EMI_0_AB_21_D, EMCAB(20) => MSS_EMI_0_AB_20_D, 
        EMCAB(19) => MSS_EMI_0_AB_19_D, EMCAB(18) => 
        MSS_EMI_0_AB_18_D, EMCAB(17) => MSS_EMI_0_AB_17_D, 
        EMCAB(16) => MSS_EMI_0_AB_16_D, EMCAB(15) => 
        MSS_EMI_0_AB_15_D, EMCAB(14) => MSS_EMI_0_AB_14_D, 
        EMCAB(13) => MSS_EMI_0_AB_13_D, EMCAB(12) => 
        MSS_EMI_0_AB_12_D, EMCAB(11) => MSS_EMI_0_AB_11_D, 
        EMCAB(10) => MSS_EMI_0_AB_10_D, EMCAB(9) => 
        MSS_EMI_0_AB_9_D, EMCAB(8) => MSS_EMI_0_AB_8_D, EMCAB(7)
         => MSS_EMI_0_AB_7_D, EMCAB(6) => MSS_EMI_0_AB_6_D, 
        EMCAB(5) => MSS_EMI_0_AB_5_D, EMCAB(4) => 
        MSS_EMI_0_AB_4_D, EMCAB(3) => MSS_EMI_0_AB_3_D, EMCAB(2)
         => MSS_EMI_0_AB_2_D, EMCAB(1) => MSS_EMI_0_AB_1_D, 
        EMCAB(0) => MSS_EMI_0_AB_0_D, EMCWDB(15) => 
        MSS_EMI_0_DB_15_D, EMCWDB(14) => MSS_EMI_0_DB_14_D, 
        EMCWDB(13) => MSS_EMI_0_DB_13_D, EMCWDB(12) => 
        MSS_EMI_0_DB_12_D, EMCWDB(11) => MSS_EMI_0_DB_11_D, 
        EMCWDB(10) => MSS_EMI_0_DB_10_D, EMCWDB(9) => 
        MSS_EMI_0_DB_9_D, EMCWDB(8) => MSS_EMI_0_DB_8_D, 
        EMCWDB(7) => MSS_EMI_0_DB_7_D, EMCWDB(6) => 
        MSS_EMI_0_DB_6_D, EMCWDB(5) => MSS_EMI_0_DB_5_D, 
        EMCWDB(4) => MSS_EMI_0_DB_4_D, EMCWDB(3) => 
        MSS_EMI_0_DB_3_D, EMCWDB(2) => MSS_EMI_0_DB_2_D, 
        EMCWDB(1) => MSS_EMI_0_DB_1_D, EMCWDB(0) => 
        MSS_EMI_0_DB_0_D, EMCRWn => MSS_EMI_0_RW_N_D, EMCCS0n => 
        MSS_EMI_0_CS0_N_D, EMCCS1n => MSS_EMI_0_CS1_N_D, EMCOEN0n
         => MSS_EMI_0_OEN0_N_D, EMCOEN1n => MSS_EMI_0_OEN1_N_D, 
        EMCBYTEN(1) => MSS_EMI_0_BYTEN_1_D, EMCBYTEN(0) => 
        MSS_EMI_0_BYTEN_0_D, EMCDBOE => MSS_EMI_0_DB_15_E, ADC0
         => GND_net, ADC1 => GND_net, ADC2 => GND_net, ADC3 => 
        GND_net, ADC4 => GND_net, ADC5 => GND_net, ADC6 => 
        GND_net, ADC7 => GND_net, ADC8 => GND_net, ADC9 => 
        GND_net, ADC10 => GND_net, ADC11 => GND_net, SDD0 => 
        MSS_ACE_0_SDD0_D, SDD1 => OPEN, SDD2 => OPEN, ABPS0 => 
        GND_net, ABPS1 => GND_net, ABPS2 => GND_net, ABPS3 => 
        GND_net, ABPS4 => GND_net, ABPS5 => GND_net, ABPS6 => 
        GND_net, ABPS7 => GND_net, ABPS8 => GND_net, ABPS9 => 
        GND_net, ABPS10 => GND_net, ABPS11 => GND_net, TM0 => 
        GND_net, TM1 => GND_net, TM2 => GND_net, TM3 => GND_net, 
        TM4 => GND_net, TM5 => GND_net, CM0 => GND_net, CM1 => 
        GND_net, CM2 => GND_net, CM3 => GND_net, CM4 => GND_net, 
        CM5 => GND_net, GNDTM0 => GND_net, GNDTM1 => GND_net, 
        GNDTM2 => GND_net, VAREF0 => MSS_ACE_0_VAREF0_Y, VAREF1
         => GND_net, VAREF2 => GND_net, VAREFOUT => OPEN, 
        GNDVAREF => GND_net, PUn => GND_net);
    
    MSS_EMI_0_AB_1 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A9")

      port map(D => MSS_EMI_0_AB_1_D, PAD => EMC_AB(1));
    
    MSS_EMI_0_AB_0 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A8")

      port map(D => MSS_EMI_0_AB_0_D, PAD => EMC_AB(0));
    
    MSS_EMI_0_DB_15 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B1")

      port map(PAD => EMC_DB(15), D => MSS_EMI_0_DB_15_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_15_Y);
    
    MSS_EMI_0_DB_14 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C1")

      port map(PAD => EMC_DB(14), D => MSS_EMI_0_DB_14_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_14_Y);
    
    MSSINT_GPI_2 : MSSINT
      port map(A => F2M_GPI_2, Y => MSSINT_GPI_2_Y);
    
    MSSINT_GPI_0 : MSSINT
      port map(A => F2M_GPI_0, Y => MSSINT_GPI_0_Y);
    
    MSS_EMI_0_AB_10 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D11")

      port map(D => MSS_EMI_0_AB_10_D, PAD => EMC_AB(10));
    
    MSS_SPI_1_DO : TRIBUFF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "T17")

      port map(D => MSS_SPI_1_DO_D, E => MSS_SPI_1_DO_E, PAD => 
        SPI_1_DO);
    
    MSS_EMI_0_AB_11 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D12")

      port map(D => MSS_EMI_0_AB_11_D, PAD => EMC_AB(11));
    
    MSS_EMI_0_DB_9 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "G3")

      port map(PAD => EMC_DB(9), D => MSS_EMI_0_DB_9_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_9_Y);
    
    MSS_EMI_0_BYTEN_1 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C9")

      port map(D => MSS_EMI_0_BYTEN_1_D, PAD => EMC_BYTEN(1));
    
    MSS_EMI_0_AB_18 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B16")

      port map(D => MSS_EMI_0_AB_18_D, PAD => EMC_AB(18));
    
    MSSINT_GPI_5 : MSSINT
      port map(A => F2M_GPI_5, Y => MSSINT_GPI_5_Y);
    
    MSS_EMI_0_DB_5 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "J2")

      port map(PAD => EMC_DB(5), D => MSS_EMI_0_DB_5_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_5_Y);
    
    MSS_SPI_1_SS : BIBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "W21")

      port map(PAD => SPI_1_SS, D => MSS_SPI_1_SS_D, E => 
        MSS_SPI_1_SS_E, Y => MSS_SPI_1_SS_Y);
    
    MSSINT_GPO_3 : MSSINT
      port map(A => MSSINT_GPO_3_A, Y => M2F_GPO_3);
    
    MSSINT_GPO_4 : MSSINT
      port map(A => MSSINT_GPO_4_A, Y => M2F_GPO_4);
    
    MSS_EMI_0_DB_4 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "J3")

      port map(PAD => EMC_DB(4), D => MSS_EMI_0_DB_4_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_4_Y);
    
    MSS_UART_0_RXD : INBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "U18")

      port map(PAD => UART_0_RXD, Y => MSS_UART_0_RXD_Y);
    
    MSS_EMI_0_AB_9 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D13")

      port map(D => MSS_EMI_0_AB_9_D, PAD => EMC_AB(9));
    
    MSS_EMI_0_CLK : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C6")

      port map(D => MSS_EMI_0_CLK_D, PAD => EMC_CLK);
    
    MSS_EMI_0_DB_13 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D3")

      port map(PAD => EMC_DB(13), D => MSS_EMI_0_DB_13_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_13_Y);
    
    MSS_UART_0_TXD : OUTBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "Y22")

      port map(D => MSS_UART_0_TXD_D, PAD => UART_0_TXD);
    
    MSS_EMI_0_CS0_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A5")

      port map(D => MSS_EMI_0_CS0_N_D, PAD => EMC_CS0_N);
    
    MSS_EMI_0_RW_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B6")

      port map(D => MSS_EMI_0_RW_N_D, PAD => EMC_RW_N);
    
    MSS_EMI_0_AB_5 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "E12")

      port map(D => MSS_EMI_0_AB_5_D, PAD => EMC_AB(5));
    
    MSS_EMI_0_DB_7 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "H1")

      port map(PAD => EMC_DB(7), D => MSS_EMI_0_DB_7_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_7_Y);
    
    MSS_SPI_1_DI : INBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "V19")

      port map(PAD => SPI_1_DI, Y => MSS_SPI_1_DI_Y);
    

end DEF_ARCH; 
