-- FLAC_DECODER_testbench.vhd
library ieee;
use ieee.std_logic_1164.all;

entity Ftestbench is
end Ftestbench;

architecture test of Ftestbench is

component FLAC_DECODER is
port ( 
       PCLK                    : in  std_logic;
       PRESET                  : in  std_logic;
       
       --APB3 slave signals 
       
       SPENABLE                : in  std_logic;
       SPSEL                   : in  std_logic;
       SPWRITE                 : in  std_logic;
       SPWDATA                 : in  std_logic_vector(31 downto 0);
       SPADDR                  : in  std_logic_vector(19 downto 0);
       SPRDATA                 : out std_logic_vector(31 downto 0);
       SPREADY,SPSLVERR        : out std_logic;

       --APB3 master signals

       MPENABLE                : out std_logic;
       MPSEL                   : out std_logic;
       MPWRITE                 : out std_logic;
       MPWDATA                 : out std_logic_vector(31 downto 0);
       MPADDR                  : out std_logic_vector(31 downto 0);
       MPRDATA                 : in  std_logic_vector(31 downto 0);
       MPREADY,PSLVERR         : in  std_logic;

       --Signals for conncting to GPIO's of MSS

       START1                  : in std_logic;
       START2                  : in std_logic;
       START3                  : in std_logic;
       STOP1                   : out std_logic;
       STOP2                   : out std_logic;
       STOP3                   : out std_logic       
       );
      end component;

type array64 is array (63  downto  0) of std_logic_vector(31  downto   0 ) ;
signal      Mreg:array64;
signal      pclk:std_logic:='0';
signal      preset,spenable,spsel,spwrite:std_logic;
signal      spwdata:std_logic_vector(31 downto 0);
signal      spaddr: std_logic_vector(19 downto 0);
signal      sprdata:std_logic_vector(31 downto 0);
signal      spready,spslverr:std_logic;
signal      mpenable,mpsel,mpwrite:std_logic;
signal      mpwdata:std_logic_vector(31 downto 0);
signal      mpaddr:std_logic_vector(31 downto 0);
signal      mprdata:std_logic_vector(31 downto 0);
signal      mpready,pslverr:std_logic;
signal      start1:std_logic;
signal      stop1: std_logic;
signal      start2:std_logic;
signal      stop2: std_logic;
signal      start3:std_logic;
signal      stop3: std_logic;

signal state:std_logic_vector (3 downto 0);
signal state2:std_logic;
signal i:integer:=0;
begin

preset<='1';
pclk<= not pclk after 25 ns;
spwrite<='1';spsel<='1';
mpready<=(mpenable and mpsel);

mprdata<=Mreg(i) when i<=27 else
         x"00000000";
start2<='0';
start1<='0';
master:process(pclk,mpwrite)

variable j:std_logic;
begin
if (pclk'event and pclk='1') then
  case state2 is
    when '0' => if (mpenable='1'and mpwrite='0') then                
                j:='1';
                state2<='1';                
                i<=i+1;                                               
                end if;                
    when '1' => if(j='1' and mpenable='0') then       
                j:='0';
                state2<='0';
                end if;
    when others=>state2<='0'; 
  end case;
end if;
end process master;

slave:process(pclk,state)
begin
if (pclk'event and pclk='1') then
      case state is
        when "1111" =>start3<='0';
                       state<="0000";
        when "0000" =>start3<='1';                 
                       state<="0010";        
        when "0010" =>spenable<='0';
                       spwdata<=x"20000000";
                       state<="0011";
        when "0011" =>spenable<='1';
                       if spready='1' then
                       state<="0100";
                       end if;
        when "0100" =>spenable<='0';
                       spwdata<=x"0000038b";
                       state<="0101";
        when "0101" =>spenable<='1';
                       if spready='1' then
                       state<="0110";
                       end if;
                
        when "0110" =>if (stop3='1') then
                       state<="1111";
                       end if;
        when others  =>state<="1111";
        end case;

end if;
end process slave;
FLAC_DECODER0:FLAC_DECODER port map( pclk,preset,spenable,spsel,spwrite,spwdata,
                                     spaddr,sprdata,spready,spslverr,mpenable,
                                     mpsel,mpwrite,mpwdata,mpaddr,mprdata,mpready,
                                     pslverr,start1,start2,start3,stop1,stop2,stop3);

Mreg(0)<=x"00000003";
Mreg(1)<=x"00000001";
Mreg(2)<=x"00000001";
Mreg(3)<=x"00000004";
Mreg(4)<=x"00000003";
Mreg(5)<=x"00000002";
Mreg(6)<=x"00000002";
Mreg(7)<=x"00000001";
Mreg(8)<=x"00000504";
Mreg(9)<=x"fffffc5f";
Mreg(10)<=x"000001b4";
Mreg(11)<=x"fffffe3b";
Mreg(12)<=x"00000246";
Mreg(13)<=x"fffffde8";
Mreg(14)<=x"00000156";
Mreg(15)<=x"ffffff67";
Mreg(16)<=x"00000003";
Mreg(17)<=x"00000000";
Mreg(18)<=x"00000001";
Mreg(19)<=x"00000003";
Mreg(20)<=x"00000000";
Mreg(21)<=x"00000003";
Mreg(22)<=x"fffffffe";
Mreg(23)<=x"00000007";
Mreg(24)<=x"fffffffc";
Mreg(25)<=x"00000002";
Mreg(26)<=x"00000003";
Mreg(27)<=x"00000001";
end test;