#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 #install: D:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1 #OS: Windows XP 5.1 #Hostname: WXPL-ODIGAS #Implementation: synthesis #Tue Aug 02 16:51:19 2011 $ Start of Compile #Tue Aug 02 16:51:19 2011 Synopsys Verilog Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 @N: : | Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @I::"D:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v" @I::"D:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v" @I::"D:\DATA\PROJECTS\SmartFusion\Synthetic ADC\simplewire\Simplewire_modified\apbmaster_adc_to_dac\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v" @I::"D:\DATA\PROJECTS\SmartFusion\Synthetic ADC\simplewire\Simplewire_modified\apbmaster_adc_to_dac\component\work\M3_PROC_ADC_DAC\MSS_CCC_0\M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v" @I::"D:\DATA\PROJECTS\SmartFusion\Synthetic ADC\simplewire\Simplewire_modified\apbmaster_adc_to_dac\component\work\M3_PROC_ADC_DAC\mss_tshell.v" @I::"D:\DATA\PROJECTS\SmartFusion\Synthetic ADC\simplewire\Simplewire_modified\apbmaster_adc_to_dac\component\work\M3_PROC_ADC_DAC\M3_PROC_ADC_DAC.v" @I::"D:\DATA\PROJECTS\SmartFusion\Synthetic ADC\simplewire\Simplewire_modified\apbmaster_adc_to_dac\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v" @I::"D:\DATA\PROJECTS\SmartFusion\Synthetic ADC\simplewire\Simplewire_modified\apbmaster_adc_to_dac\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v" @I::"D:\DATA\PROJECTS\SmartFusion\Synthetic ADC\simplewire\Simplewire_modified\apbmaster_adc_to_dac\component\work\CoreAPB3_Master_Side\CoreAPB3_Master_Side.v" @I::"D:\DATA\PROJECTS\SmartFusion\Synthetic ADC\simplewire\Simplewire_modified\apbmaster_adc_to_dac\hdl\APB_MEM_CTRL.v" @N:CG347 : APB_MEM_CTRL.v(68) | Read parallel_case directive @I::"D:\DATA\PROJECTS\SmartFusion\Synthetic ADC\simplewire\Simplewire_modified\apbmaster_adc_to_dac\component\work\Top_Level\Top_Level.v" Verilog syntax check successful! Options changed - recompiling Selecting top level module Top_Level @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC @N:CG364 : smartfusion.v(1133) | Synthesizing module GND @N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS @N:CG364 : smartfusion.v(2614) | Synthesizing module OUTBUF_A @N:CG364 : smartfusion.v(2609) | Synthesizing module INBUF_A @N:CG364 : mss_comps.v(37) | Synthesizing module OUTBUF_MSS @N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC @N:CG364 : mss_comps.v(1) | Synthesizing module MSS_XTLOSC @N:CG364 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC @N:CG364 : mss_tshell.v(1) | Synthesizing module MSS_APB @N:CG364 : M3_PROC_ADC_DAC.v(5) | Synthesizing module M3_PROC_ADC_DAC @W:CG775 : coreapb3.v(30) | Found Component CoreAPB3 in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 @N:CG364 : coreapb3.v(30) | Synthesizing module CoreAPB3 APB_DWIDTH=6'b100000 RANGESIZE=21'b000010000000000000000 IADDR_ENABLE=1'b1 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b1 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 RANGEBITS=32'b00000000000000000000000000010000 RANGEBITS_LT16=32'b00000000000000000000000000001111 IADDR_31_24_8B_A=16'b0000000000001100 IADDR_23_16_8B_A=16'b0000000000001000 IADDR_15_8_8B_A=16'b0000000000000100 IADDR_7_0_8B_A=16'b0000000000000000 IADDR_31_16_16B_A=16'b0000000000000100 IADDR_15_0_16B_A=16'b0000000000000000 IADDR_31_0_32B_A=16'b0000000000000000 SL0=16'b0000000000000001 SL1=16'b0000000000000010 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 Generated name = CoreAPB3_Z1 @W:CL113 : coreapb3.v(276) | Feedback mux created for signal g_iaddr.genblk0.g_ia1.genblk2.genblk4.IADDR[15:0]. @W:CL251 : coreapb3.v(276) | All reachable assignments to g_iaddr.genblk0.g_ia1.genblk2.genblk4.IADDR[15:0] assign 0, register removed by optimization @N:CG364 : CoreAPB3_Master_Side.v(5) | Synthesizing module CoreAPB3_Master_Side @N:CG364 : APB_MEM_CTRL.v(2) | Synthesizing module APB_MEM_CTRL @W:CG133 : APB_MEM_CTRL.v(17) | No assignment to Adc0_Shift_Reg @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 31 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 30 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 29 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 28 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 27 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 26 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 25 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 24 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 23 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 22 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 21 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 20 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 19 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 18 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 17 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 16 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 15 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 14 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 13 of Adc0_poll_Reg[31:0] - not in use ... @W:CL265 : APB_MEM_CTRL.v(48) | Pruning bit 12 of Adc0_poll_Reg[31:0] - not in use ... @A: : APB_MEM_CTRL.v(48) | Feedback mux created for signal Adc0_poll_Reg[11:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[0] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[1] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[2] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[3] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[4] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[5] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[6] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[7] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[9] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[11] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[13] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[14] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[15] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[17] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[18] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[19] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[20] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[21] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[22] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PADDR[23] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[0] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[1] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[2] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[3] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[16] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[18] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[19] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[20] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[21] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[22] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[23] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[24] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[25] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[26] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[27] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[28] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[29] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit PWDATA[31] to a constant 0 @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 31 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 29 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 28 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 27 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 26 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 25 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 24 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 23 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 22 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 21 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 20 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 19 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 18 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 16 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 3 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 2 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 1 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 0 of PWDATA[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 23 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 22 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 21 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 20 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 19 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 18 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 17 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 15 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 14 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 13 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 11 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 9 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 7 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 6 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 5 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 4 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 3 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 2 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 1 of PADDR[23:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 0 of PADDR[23:0] @N:CG364 : Top_Level.v(5) | Synthesizing module Top_Level @W:CL168 : Top_Level.v(226) | Pruning instance GND - not in use ... @W:CL168 : Top_Level.v(225) | Pruning instance VCC - not in use ... @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[15] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[16] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[17] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[18] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[19] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[20] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[21] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[22] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[23] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[24] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[25] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[26] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[27] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[28] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[29] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[30] to a constant 0 @W:CL190 : APB_MEM_CTRL.v(48) | Optimizing register bit delay_start[31] to a constant 0 @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 31 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 30 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 29 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 28 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 27 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 26 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 25 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 24 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 23 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 22 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 21 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 20 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 19 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 18 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 17 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 16 of delay_start[31:0] @W:CL260 : APB_MEM_CTRL.v(48) | Pruning Register bit 15 of delay_start[31:0] @N:CL201 : APB_MEM_CTRL.v(48) | Trying to extract state machine for register current_state Extracted state machine for register current_state State machine has 10 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 @W:CL246 : APB_MEM_CTRL.v(5) | Input port bits 31 to 14 of PRDATA[31:0] are unused @W:CL159 : APB_MEM_CTRL.v(4) | Input PSLVERR is unused @W:CL246 : coreapb3.v(54) | Input port bits 23 to 20 of PADDR[23:0] are unused @W:CL159 : coreapb3.v(84) | Input PRDATAS1 is unused @W:CL159 : coreapb3.v(85) | Input PRDATAS2 is unused @W:CL159 : coreapb3.v(86) | Input PRDATAS3 is unused @W:CL159 : coreapb3.v(87) | Input PRDATAS4 is unused @W:CL159 : coreapb3.v(88) | Input PRDATAS5 is unused @W:CL159 : coreapb3.v(89) | Input PRDATAS6 is unused @W:CL159 : coreapb3.v(90) | Input PRDATAS7 is unused @W:CL159 : coreapb3.v(91) | Input PRDATAS8 is unused @W:CL159 : coreapb3.v(92) | Input PRDATAS9 is unused @W:CL159 : coreapb3.v(93) | Input PRDATAS10 is unused @W:CL159 : coreapb3.v(94) | Input PRDATAS11 is unused @W:CL159 : coreapb3.v(95) | Input PRDATAS12 is unused @W:CL159 : coreapb3.v(96) | Input PRDATAS13 is unused @W:CL159 : coreapb3.v(97) | Input PRDATAS14 is unused @W:CL159 : coreapb3.v(98) | Input PRDATAS15 is unused @W:CL159 : coreapb3.v(100) | Input PREADYS1 is unused @W:CL159 : coreapb3.v(101) | Input PREADYS2 is unused @W:CL159 : coreapb3.v(102) | Input PREADYS3 is unused @W:CL159 : coreapb3.v(103) | Input PREADYS4 is unused @W:CL159 : coreapb3.v(104) | Input PREADYS5 is unused @W:CL159 : coreapb3.v(105) | Input PREADYS6 is unused @W:CL159 : coreapb3.v(106) | Input PREADYS7 is unused @W:CL159 : coreapb3.v(107) | Input PREADYS8 is unused @W:CL159 : coreapb3.v(108) | Input PREADYS9 is unused @W:CL159 : coreapb3.v(109) | Input PREADYS10 is unused @W:CL159 : coreapb3.v(110) | Input PREADYS11 is unused @W:CL159 : coreapb3.v(111) | Input PREADYS12 is unused @W:CL159 : coreapb3.v(112) | Input PREADYS13 is unused @W:CL159 : coreapb3.v(113) | Input PREADYS14 is unused @W:CL159 : coreapb3.v(114) | Input PREADYS15 is unused @W:CL159 : coreapb3.v(116) | Input PSLVERRS1 is unused @W:CL159 : coreapb3.v(117) | Input PSLVERRS2 is unused @W:CL159 : coreapb3.v(118) | Input PSLVERRS3 is unused @W:CL159 : coreapb3.v(119) | Input PSLVERRS4 is unused @W:CL159 : coreapb3.v(120) | Input PSLVERRS5 is unused @W:CL159 : coreapb3.v(121) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.v(122) | Input PSLVERRS7 is unused @W:CL159 : coreapb3.v(123) | Input PSLVERRS8 is unused @W:CL159 : coreapb3.v(124) | Input PSLVERRS9 is unused @W:CL159 : coreapb3.v(125) | Input PSLVERRS10 is unused @W:CL159 : coreapb3.v(126) | Input PSLVERRS11 is unused @W:CL159 : coreapb3.v(127) | Input PSLVERRS12 is unused @W:CL159 : coreapb3.v(128) | Input PSLVERRS13 is unused @W:CL159 : coreapb3.v(129) | Input PSLVERRS14 is unused @W:CL159 : coreapb3.v(130) | Input PSLVERRS15 is unused @W:CL157 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL159 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused @W:CL159 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused @W:CL159 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused @W:CL159 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused @W:CL159 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused @W:CL159 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused @W:CL159 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused @W:CL159 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused @W:CL159 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused @W:CL159 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused @W:CL159 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused @W:CL159 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused @W:CL159 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused @W:CL159 : M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused @END Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Tue Aug 02 16:51:21 2011 ###########################################################] Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO111 : m3_proc_adc_dac_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : m3_proc_adc_dac_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : m3_proc_adc_dac_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC) @W:BN132 : apb_mem_ctrl.v(48) | Removing sequential instance APB_MEM_CTRL_0.PWDATA_1[30], because it is equivalent to instance APB_MEM_CTRL_0.PWDATA_1[17] @W:BN132 : apb_mem_ctrl.v(48) | Removing sequential instance APB_MEM_CTRL_0.PADDR_1[8], because it is equivalent to instance APB_MEM_CTRL_0.PADDR_1[10] Available hyper_sources - for debug and ip models None Found @W: : m3_proc_adc_dac_tmp_mss_ccc_0_mss_ccc.v(79) | Net M3_PROC_ADC_DAC_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. @W: : m3_proc_adc_dac_tmp_mss_ccc_0_mss_ccc.v(79) | Net FAB_CLK_80MHz appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:02s; Memory used current: 56MB peak: 57MB) @W:MO161 : coreapb3.v(276) | Register bit CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.g_iaddr\.genblk0\.g_ia1\.genblk2\.genblk4\.IADDR[31] is always 0, optimizing ... @W:MO161 : coreapb3.v(276) | Register bit CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.g_iaddr\.genblk0\.g_ia1\.genblk2\.genblk4\.IADDR[29] is always 0, optimizing ... @W:MO161 : coreapb3.v(276) | Register bit CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.g_iaddr\.genblk0\.g_ia1\.genblk2\.genblk4\.IADDR[28] is always 0, optimizing ... @W:MO161 : coreapb3.v(276) | Register bit CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.g_iaddr\.genblk0\.g_ia1\.genblk2\.genblk4\.IADDR[27] is always 0, optimizing ... @W:MO161 : coreapb3.v(276) | Register bit CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.g_iaddr\.genblk0\.g_ia1\.genblk2\.genblk4\.IADDR[26] is always 0, optimizing ... @W:MO161 : coreapb3.v(276) | Register bit CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.g_iaddr\.genblk0\.g_ia1\.genblk2\.genblk4\.IADDR[25] is always 0, optimizing ... @W:MO161 : coreapb3.v(276) | Register bit CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.g_iaddr\.genblk0\.g_ia1\.genblk2\.genblk4\.IADDR[24] is always 0, optimizing ... @W:MO161 : coreapb3.v(276) | Register bit CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.g_iaddr\.genblk0\.g_ia1\.genblk2\.genblk4\.IADDR[23] is always 0, optimizing ... @W:MO161 : coreapb3.v(276) | Register bit CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.g_iaddr\.genblk0\.g_ia1\.genblk2\.genblk4\.IADDR[22] is always 0, optimizing ... @W:MO161 : coreapb3.v(276) | Register bit CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.g_iaddr\.genblk0\.g_ia1\.genblk2\.genblk4\.IADDR[21] is always 0, optimizing ... @W:MO161 : coreapb3.v(276) | Register bit CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.g_iaddr\.genblk0\.g_ia1\.genblk2\.genblk4\.IADDR[20] is always 0, optimizing ... @W:MO161 : coreapb3.v(276) | Register bit CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.g_iaddr\.genblk0\.g_ia1\.genblk2\.genblk4\.IADDR[19] is always 0, optimizing ... @W:MO161 : coreapb3.v(276) | Register bit CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.g_iaddr\.genblk0\.g_ia1\.genblk2\.genblk4\.IADDR[18] is always 0, optimizing ... @W:MO161 : coreapb3.v(276) | Register bit CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.g_iaddr\.genblk0\.g_ia1\.genblk2\.genblk4\.IADDR[16] is always 0, optimizing ... @N: : apb_mem_ctrl.v(48) | Found counter in view:work.APB_MEM_CTRL(verilog) inst delay_start[14:0] Encoding state machine work.APB_MEM_CTRL(verilog)-current_state[9:0] original code -> new code 0000 -> 0000000001 0001 -> 0000000010 0010 -> 0000000100 0011 -> 0000001000 0100 -> 0000010000 0101 -> 0000100000 0110 -> 0001000000 0111 -> 0010000000 1000 -> 0100000000 1001 -> 1000000000 Finished factoring (Time elapsed 0h:00m:02s; Memory used current: 57MB peak: 57MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:02s; Memory used current: 57MB peak: 57MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:03s; Memory used current: 57MB peak: 57MB) Starting Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 57MB peak: 57MB) Finished Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 57MB peak: 58MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:03s; Memory used current: 57MB peak: 58MB) Finished preparing to map (Time elapsed 0h:00m:04s; Memory used current: 58MB peak: 58MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ------------------------------------------------------------------------------- M3_PROC_ADC_DAC_0.MSS_ADLIB_INST / M2FRESETn 53 : 52 asynchronous set/reset =============================================================================== Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 58MB peak: 58MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 58MB peak: 58MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 58MB peak: 58MB) Writing Analyst data base D:\DATA\PROJECTS\SmartFusion\Synthetic ADC\simplewire\Simplewire_modified\apbmaster_adc_to_dac\synthesis\Top_Level.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:05s; Memory used current: 57MB peak: 58MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:05s; Memory used current: 58MB peak: 58MB) @W:MT246 : m3_proc_adc_dac_tmp_mss_ccc_0_mss_ccc.v(97) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock M3_PROC_ADC_DAC|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:M3_PROC_ADC_DAC_0.MSS_ADLIB_INST_EMCCLK" @W:MT420 : | Found inferred clock M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:FAB_CLK_80MHz" @W:MT420 : | Found inferred clock M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:M3_PROC_ADC_DAC_0.MSS_ADLIB_INST_FCLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Aug 02 16:51:33 2011 # Top view: Top_Level Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -0.629 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock 100.0 MHz 94.1 MHz 10.000 10.629 -0.629 inferred Inferred_clkgroup_2 M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_1 ================================================================================================================================================================================ Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock | Diff grp - | No paths - | No paths - | No paths - M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock | 10.000 -0.629 | No paths - | No paths - | No paths - =========================================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- APB_MEM_CTRL_0.delay_start[0] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 Q delay_start_c0 0.737 -0.629 APB_MEM_CTRL_0.delay_start[1] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 Q delay_start[1] 0.737 -0.096 APB_MEM_CTRL_0.PSEL M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E0C0 Q APB_MEM_CTRL_0_APB_bif_PSELx 0.580 -0.012 APB_MEM_CTRL_0.delay_start[7] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 Q delay_start[7] 0.737 0.047 APB_MEM_CTRL_0.delay_start[9] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 Q delay_start[9] 0.737 0.165 APB_MEM_CTRL_0.delay_start[8] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 Q delay_start[8] 0.737 0.304 APB_MEM_CTRL_0.delay_start[11] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 Q delay_start[11] 0.737 0.330 APB_MEM_CTRL_0.PADDR_1[16] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E0C0 Q PADDR_1[16] 0.737 0.420 APB_MEM_CTRL_0.delay_start[12] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 Q delay_start[12] 0.737 0.427 APB_MEM_CTRL_0.delay_start[14] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 Q delay_start[14] 0.737 0.567 ================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------ APB_MEM_CTRL_0.delay_start[9] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 D N_56 9.496 -0.629 APB_MEM_CTRL_0.delay_start[0] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 E delay_starte 9.392 -0.012 APB_MEM_CTRL_0.delay_start[1] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 E delay_starte 9.392 -0.012 APB_MEM_CTRL_0.delay_start[2] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 E delay_starte 9.392 -0.012 APB_MEM_CTRL_0.delay_start[3] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 E delay_starte 9.392 -0.012 APB_MEM_CTRL_0.delay_start[4] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 E delay_starte 9.392 -0.012 APB_MEM_CTRL_0.delay_start[5] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 E delay_starte 9.392 -0.012 APB_MEM_CTRL_0.delay_start[6] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 E delay_starte 9.392 -0.012 APB_MEM_CTRL_0.delay_start[7] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 E delay_starte 9.392 -0.012 APB_MEM_CTRL_0.delay_start[8] M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock DFN1E1C0 E delay_starte 9.392 -0.012 ================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.504 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.496 - Propagation time: 10.125 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.629 Number of logic level(s): 6 Starting point: APB_MEM_CTRL_0.delay_start[0] / Q Ending point: APB_MEM_CTRL_0.delay_start[9] / D The start point is clocked by M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock [rising] on pin CLK The end point is clocked by M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------- APB_MEM_CTRL_0.delay_start[0] DFN1E1C0 Q Out 0.737 0.737 - delay_start_c0 Net - - 0.806 - 3 APB_MEM_CTRL_0.delay_start_RNI993[1] NOR2B B In - 1.543 - APB_MEM_CTRL_0.delay_start_RNI993[1] NOR2B Y Out 0.627 2.171 - N_370 Net - - 1.184 - 4 APB_MEM_CTRL_0.delay_start_RNIVT4[2] NOR2B B In - 3.354 - APB_MEM_CTRL_0.delay_start_RNIVT4[2] NOR2B Y Out 0.627 3.982 - N_15_i_0 Net - - 1.279 - 5 APB_MEM_CTRL_0.delay_start_RNI1HB[6] NOR3C C In - 5.261 - APB_MEM_CTRL_0.delay_start_RNI1HB[6] NOR3C Y Out 0.641 5.902 - N_19 Net - - 1.279 - 5 APB_MEM_CTRL_0.delay_start_RNIOQE[8] NOR2B B In - 7.181 - APB_MEM_CTRL_0.delay_start_RNIOQE[8] NOR2B Y Out 0.627 7.809 - N_74 Net - - 0.386 - 2 APB_MEM_CTRL_0.delay_start_RNO_1[9] NOR2 B In - 8.195 - APB_MEM_CTRL_0.delay_start_RNO_1[9] NOR2 Y Out 0.646 8.841 - N_112 Net - - 0.322 - 1 APB_MEM_CTRL_0.delay_start_RNO[9] NOR3A C In - 9.163 - APB_MEM_CTRL_0.delay_start_RNO[9] NOR3A Y Out 0.641 9.804 - N_56 Net - - 0.322 - 1 APB_MEM_CTRL_0.delay_start[9] DFN1E1C0 D In - 10.125 - ======================================================================================================= Total path delay (propagation time + setup) of 10.629 is 5.052(47.5%) logic and 5.577(52.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.504 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.496 - Propagation time: 9.592 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.096 Number of logic level(s): 6 Starting point: APB_MEM_CTRL_0.delay_start[1] / Q Ending point: APB_MEM_CTRL_0.delay_start[9] / D The start point is clocked by M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock [rising] on pin CLK The end point is clocked by M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------- APB_MEM_CTRL_0.delay_start[1] DFN1E1C0 Q Out 0.737 0.737 - delay_start[1] Net - - 0.386 - 2 APB_MEM_CTRL_0.delay_start_RNI993[1] NOR2B A In - 1.123 - APB_MEM_CTRL_0.delay_start_RNI993[1] NOR2B Y Out 0.514 1.637 - N_370 Net - - 1.184 - 4 APB_MEM_CTRL_0.delay_start_RNIVT4[2] NOR2B B In - 2.821 - APB_MEM_CTRL_0.delay_start_RNIVT4[2] NOR2B Y Out 0.627 3.448 - N_15_i_0 Net - - 1.279 - 5 APB_MEM_CTRL_0.delay_start_RNI1HB[6] NOR3C C In - 4.727 - APB_MEM_CTRL_0.delay_start_RNI1HB[6] NOR3C Y Out 0.641 5.369 - N_19 Net - - 1.279 - 5 APB_MEM_CTRL_0.delay_start_RNIOQE[8] NOR2B B In - 6.648 - APB_MEM_CTRL_0.delay_start_RNIOQE[8] NOR2B Y Out 0.627 7.275 - N_74 Net - - 0.386 - 2 APB_MEM_CTRL_0.delay_start_RNO_1[9] NOR2 B In - 7.661 - APB_MEM_CTRL_0.delay_start_RNO_1[9] NOR2 Y Out 0.646 8.307 - N_112 Net - - 0.322 - 1 APB_MEM_CTRL_0.delay_start_RNO[9] NOR3A C In - 8.629 - APB_MEM_CTRL_0.delay_start_RNO[9] NOR3A Y Out 0.641 9.270 - N_56 Net - - 0.322 - 1 APB_MEM_CTRL_0.delay_start[9] DFN1E1C0 D In - 9.592 - ======================================================================================================= Total path delay (propagation time + setup) of 10.096 is 4.939(48.9%) logic and 5.157(51.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.608 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.392 - Propagation time: 9.404 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.012 Number of logic level(s): 5 Starting point: APB_MEM_CTRL_0.PSEL / Q Ending point: APB_MEM_CTRL_0.delay_start[0] / E The start point is clocked by M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock [rising] on pin CLK The end point is clocked by M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------ APB_MEM_CTRL_0.PSEL DFN1E0C0 Q Out 0.580 0.580 - APB_MEM_CTRL_0_APB_bif_PSELx Net - - 0.806 - 3 APB_MEM_CTRL_0.PSEL_RNITS26 OR2A A In - 1.387 - APB_MEM_CTRL_0.PSEL_RNITS26 OR2A Y Out 0.537 1.924 - delay_startlde_0_o3_a0_0 Net - - 0.386 - 2 CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.u_mux_p_to_b3.PREADY_i_a2 NOR2 B In - 2.310 - CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.u_mux_p_to_b3.PREADY_i_a2 NOR2 Y Out 0.646 2.956 - N_62 Net - - 1.669 - 9 APB_MEM_CTRL_0.current_state_RNIFCIF[9] NOR2A B In - 4.625 - APB_MEM_CTRL_0.current_state_RNIFCIF[9] NOR2A Y Out 0.386 5.010 - N_140 Net - - 0.806 - 3 APB_MEM_CTRL_0.current_state_RNIP76E1[9] OR2B A In - 5.817 - APB_MEM_CTRL_0.current_state_RNIP76E1[9] OR2B Y Out 0.514 6.331 - N_102 Net - - 0.322 - 1 APB_MEM_CTRL_0.delay_start_RNI69964[14] OR3B B In - 6.653 - APB_MEM_CTRL_0.delay_start_RNI69964[14] OR3B Y Out 0.624 7.277 - delay_starte Net - - 2.127 - 15 APB_MEM_CTRL_0.delay_start[0] DFN1E1C0 E In - 9.404 - ========================================================================================================================================== Total path delay (propagation time + setup) of 10.012 is 3.896(38.9%) logic and 6.116(61.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.608 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.392 - Propagation time: 9.404 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.012 Number of logic level(s): 5 Starting point: APB_MEM_CTRL_0.PSEL / Q Ending point: APB_MEM_CTRL_0.delay_start[14] / E The start point is clocked by M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock [rising] on pin CLK The end point is clocked by M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------ APB_MEM_CTRL_0.PSEL DFN1E0C0 Q Out 0.580 0.580 - APB_MEM_CTRL_0_APB_bif_PSELx Net - - 0.806 - 3 APB_MEM_CTRL_0.PSEL_RNITS26 OR2A A In - 1.387 - APB_MEM_CTRL_0.PSEL_RNITS26 OR2A Y Out 0.537 1.924 - delay_startlde_0_o3_a0_0 Net - - 0.386 - 2 CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.u_mux_p_to_b3.PREADY_i_a2 NOR2 B In - 2.310 - CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.u_mux_p_to_b3.PREADY_i_a2 NOR2 Y Out 0.646 2.956 - N_62 Net - - 1.669 - 9 APB_MEM_CTRL_0.current_state_RNIFCIF[9] NOR2A B In - 4.625 - APB_MEM_CTRL_0.current_state_RNIFCIF[9] NOR2A Y Out 0.386 5.010 - N_140 Net - - 0.806 - 3 APB_MEM_CTRL_0.current_state_RNIP76E1[9] OR2B A In - 5.817 - APB_MEM_CTRL_0.current_state_RNIP76E1[9] OR2B Y Out 0.514 6.331 - N_102 Net - - 0.322 - 1 APB_MEM_CTRL_0.delay_start_RNI69964[14] OR3B B In - 6.653 - APB_MEM_CTRL_0.delay_start_RNI69964[14] OR3B Y Out 0.624 7.277 - delay_starte Net - - 2.127 - 15 APB_MEM_CTRL_0.delay_start[14] DFN1E1C0 E In - 9.404 - ========================================================================================================================================== Total path delay (propagation time + setup) of 10.012 is 3.896(38.9%) logic and 6.116(61.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.608 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.392 - Propagation time: 9.404 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.012 Number of logic level(s): 5 Starting point: APB_MEM_CTRL_0.PSEL / Q Ending point: APB_MEM_CTRL_0.delay_start[13] / E The start point is clocked by M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock [rising] on pin CLK The end point is clocked by M3_PROC_ADC_DAC_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_80MHz_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------ APB_MEM_CTRL_0.PSEL DFN1E0C0 Q Out 0.580 0.580 - APB_MEM_CTRL_0_APB_bif_PSELx Net - - 0.806 - 3 APB_MEM_CTRL_0.PSEL_RNITS26 OR2A A In - 1.387 - APB_MEM_CTRL_0.PSEL_RNITS26 OR2A Y Out 0.537 1.924 - delay_startlde_0_o3_a0_0 Net - - 0.386 - 2 CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.u_mux_p_to_b3.PREADY_i_a2 NOR2 B In - 2.310 - CoreAPB3_Master_Side_0.CoreAPB3_Master_Side_0.u_mux_p_to_b3.PREADY_i_a2 NOR2 Y Out 0.646 2.956 - N_62 Net - - 1.669 - 9 APB_MEM_CTRL_0.current_state_RNIFCIF[9] NOR2A B In - 4.625 - APB_MEM_CTRL_0.current_state_RNIFCIF[9] NOR2A Y Out 0.386 5.010 - N_140 Net - - 0.806 - 3 APB_MEM_CTRL_0.current_state_RNIP76E1[9] OR2B A In - 5.817 - APB_MEM_CTRL_0.current_state_RNIP76E1[9] OR2B Y Out 0.514 6.331 - N_102 Net - - 0.322 - 1 APB_MEM_CTRL_0.delay_start_RNI69964[14] OR3B B In - 6.653 - APB_MEM_CTRL_0.delay_start_RNI69964[14] OR3B Y Out 0.624 7.277 - delay_starte Net - - 2.127 - 15 APB_MEM_CTRL_0.delay_start[13] DFN1E1C0 E In - 9.404 - ========================================================================================================================================== Total path delay (propagation time + setup) of 10.012 is 3.896(38.9%) logic and 6.116(61.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F500M3G_FBGA256_Std Report for cell Top_Level.verilog Core Cell usage: cell count area count*area AO1 5 1.0 5.0 AO1B 1 1.0 1.0 AOI1 3 1.0 3.0 AOI1B 1 1.0 1.0 AX1E 1 1.0 1.0 GND 7 0.0 0.0 INV 2 1.0 2.0 MSS_CCC 1 0.0 0.0 NOR2 10 1.0 10.0 NOR2A 21 1.0 21.0 NOR2B 28 1.0 28.0 NOR3 1 1.0 1.0 NOR3A 7 1.0 7.0 NOR3C 13 1.0 13.0 OA1 2 1.0 2.0 OA1A 1 1.0 1.0 OR2 8 1.0 8.0 OR2A 4 1.0 4.0 OR2B 2 1.0 2.0 OR3 4 1.0 4.0 OR3A 2 1.0 2.0 OR3B 4 1.0 4.0 OR3C 1 1.0 1.0 VCC 7 0.0 0.0 XA1 6 1.0 6.0 XA1A 1 1.0 1.0 DFN1C0 13 1.0 13.0 DFN1E0 12 1.0 12.0 DFN1E0C0 8 1.0 8.0 DFN1E1C0 30 1.0 30.0 DFN1P0 1 1.0 1.0 MSS_APB 1 0.0 0.0 ----- ---------- TOTAL 208 192.0 IO Cell usage: cell count INBUF_A 2 INBUF_MSS 2 MSS_XTLOSC 1 OUTBUF 7 OUTBUF_A 1 OUTBUF_MSS 1 ----- TOTAL 14 Core Cells : 192 of 11520 (2%) IO Cells : 14 RAM/ROM Usage Summary Block Rams : 0 of 24 (0%) Mapper successful! Process took 0h:00m:09s realtime, 0h:00m:06s cputime # Tue Aug 02 16:51:33 2011 ###########################################################]