Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Fri Dec 16 20:26:40 2011


Design: Top_Level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                9.222
Frequency (MHz):            108.436
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.513
Max Clock-To-Out (ns):      5.777

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.383
External Hold (ns):         1.283
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               SimpleWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      5.862
Max Clock-To-Out (ns):      9.350

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        APB_MEM_CTRL_0/delay_start[7]/U1:CLK
  To:                          APB_MEM_CTRL_0/delay_start[9]/U1:D
  Delay (ns):                  8.802
  Slack (ns):
  Arrival (ns):                9.361
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         9.222

Path 2
  From:                        APB_MEM_CTRL_0/delay_start[7]/U1:CLK
  To:                          APB_MEM_CTRL_0/delay_start[4]/U1:D
  Delay (ns):                  8.767
  Slack (ns):
  Arrival (ns):                9.326
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         9.205

Path 3
  From:                        APB_MEM_CTRL_0/delay_start[7]/U1:CLK
  To:                          APB_MEM_CTRL_0/delay_start[1]/U1:D
  Delay (ns):                  8.681
  Slack (ns):
  Arrival (ns):                9.240
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         9.101

Path 4
  From:                        APB_MEM_CTRL_0/delay_start[10]/U1:CLK
  To:                          APB_MEM_CTRL_0/delay_start[9]/U1:D
  Delay (ns):                  8.526
  Slack (ns):
  Arrival (ns):                9.086
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         8.947

Path 5
  From:                        APB_MEM_CTRL_0/delay_start[10]/U1:CLK
  To:                          APB_MEM_CTRL_0/delay_start[4]/U1:D
  Delay (ns):                  8.491
  Slack (ns):
  Arrival (ns):                9.051
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         8.930


Expanded Path 1
  From: APB_MEM_CTRL_0/delay_start[7]/U1:CLK
  To: APB_MEM_CTRL_0/delay_start[9]/U1:D
  data required time                             N/C
  data arrival time                          -   9.361
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: SimpleWire_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.559          net: FAB_CLK
  0.559                        APB_MEM_CTRL_0/delay_start[7]/U1:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  0.999                        APB_MEM_CTRL_0/delay_start[7]/U1:Q (r)
               +     1.252          net: APB_MEM_CTRL_0/delay_start[7]
  2.251                        APB_MEM_CTRL_0/delay_start_RNIL93[6]:B (r)
               +     0.390          cell: ADLIB:NOR2
  2.641                        APB_MEM_CTRL_0/delay_start_RNIL93[6]:Y (f)
               +     0.247          net: APB_MEM_CTRL_0/un1_current_state_0_sqmuxa_1_i_i_a3_3
  2.888                        APB_MEM_CTRL_0/delay_start_RNING76[14]:A (f)
               +     0.486          cell: ADLIB:NOR3A
  3.374                        APB_MEM_CTRL_0/delay_start_RNING76[14]:Y (f)
               +     0.247          net: APB_MEM_CTRL_0/un1_current_state_0_sqmuxa_1_i_i_a3_6
  3.621                        APB_MEM_CTRL_0/delay_start_RNIARJU[14]:B (f)
               +     0.476          cell: ADLIB:OR2B
  4.097                        APB_MEM_CTRL_0/delay_start_RNIARJU[14]:Y (r)
               +     1.319          net: APB_MEM_CTRL_0/N_134
  5.416                        APB_MEM_CTRL_0/current_state_RNI34GD1[9]:B (r)
               +     0.390          cell: ADLIB:OR2A
  5.806                        APB_MEM_CTRL_0/current_state_RNI34GD1[9]:Y (r)
               +     0.670          net: APB_MEM_CTRL_0/N_102_i
  6.476                        APB_MEM_CTRL_0/delay_start_RNI8QGT3[14]:A (r)
               +     0.370          cell: ADLIB:OR3B
  6.846                        APB_MEM_CTRL_0/delay_start_RNI8QGT3[14]:Y (f)
               +     1.874          net: APB_MEM_CTRL_0/delay_starte
  8.720                        APB_MEM_CTRL_0/delay_start[9]/U0:S (f)
               +     0.394          cell: ADLIB:MX2
  9.114                        APB_MEM_CTRL_0/delay_start[9]/U0:Y (f)
               +     0.247          net: APB_MEM_CTRL_0/delay_start[9]/Y
  9.361                        APB_MEM_CTRL_0/delay_start[9]/U1:D (f)
                                    
  9.361                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: SimpleWire_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.574          net: FAB_CLK
  N/C                          APB_MEM_CTRL_0/delay_start[9]/U1:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  N/C                          APB_MEM_CTRL_0/delay_start[9]/U1:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        APB_MEM_CTRL_0/cur_state[0]:CLK
  To:                          cur_state[0]
  Delay (ns):                  5.203
  Slack (ns):
  Arrival (ns):                5.777
  Required (ns):
  Clock to Out (ns):           5.777

Path 2
  From:                        APB_MEM_CTRL_0/dac_out_enable/U1:CLK
  To:                          dac_out_enable
  Delay (ns):                  4.936
  Slack (ns):
  Arrival (ns):                5.487
  Required (ns):
  Clock to Out (ns):           5.487

Path 3
  From:                        APB_MEM_CTRL_0/cur_state[3]:CLK
  To:                          cur_state[3]
  Delay (ns):                  4.787
  Slack (ns):
  Arrival (ns):                5.345
  Required (ns):
  Clock to Out (ns):           5.345

Path 4
  From:                        APB_MEM_CTRL_0/cur_state[1]:CLK
  To:                          cur_state[1]
  Delay (ns):                  4.727
  Slack (ns):
  Arrival (ns):                5.301
  Required (ns):
  Clock to Out (ns):           5.301

Path 5
  From:                        APB_MEM_CTRL_0/busy/U1:CLK
  To:                          busy
  Delay (ns):                  4.710
  Slack (ns):
  Arrival (ns):                5.285
  Required (ns):
  Clock to Out (ns):           5.285


Expanded Path 1
  From: APB_MEM_CTRL_0/cur_state[0]:CLK
  To: cur_state[0]
  data required time                             N/C
  data arrival time                          -   5.777
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: SimpleWire_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.574          net: FAB_CLK
  0.574                        APB_MEM_CTRL_0/cur_state[0]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.133                        APB_MEM_CTRL_0/cur_state[0]:Q (f)
               +     1.336          net: cur_state_c[0]
  2.469                        cur_state_pad[0]/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  2.969                        cur_state_pad[0]/U0/U1:DOUT (f)
               +     0.000          net: cur_state_pad[0]/U0/NET1
  2.969                        cur_state_pad[0]/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  5.777                        cur_state_pad[0]/U0/U0:PAD (f)
               +     0.000          net: cur_state[0]
  5.777                        cur_state[0] (f)
                                    
  5.777                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
                                    
  N/C                          cur_state[0] (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin SimpleWire_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          SimpleWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.782
  External Setup (ns):         -1.383


Expanded Path 1
  From: MSS_RESET_N
  To: SimpleWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        SimpleWire_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        SimpleWire_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: SimpleWire_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        SimpleWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.382          net: SimpleWire_0/GLA0
  N/C                          SimpleWire_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.782          Library setup time: ADLIB:MSS_APB_IP
  N/C                          SimpleWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain SimpleWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          FAB_CLK_80MHz
  Delay (ns):                  9.350
  Slack (ns):
  Arrival (ns):                9.350
  Required (ns):
  Clock to Out (ns):           9.350


Expanded Path 1
  From: SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: FAB_CLK_80MHz
  data required time                             N/C
  data arrival time                          -   9.350
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        SimpleWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  0.000                        SimpleWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: SimpleWire_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     5.249          cell: ADLIB:MSS_CCC_IP
  5.249                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (f)
               +     0.000          net: SimpleWire_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (f)
               +     0.793          net: FAB_CLK
  6.042                        FAB_CLK_80MHz_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  6.542                        FAB_CLK_80MHz_pad/U0/U1:DOUT (f)
               +     0.000          net: FAB_CLK_80MHz_pad/U0/NET1
  6.542                        FAB_CLK_80MHz_pad/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  9.350                        FAB_CLK_80MHz_pad/U0/U0:PAD (f)
               +     0.000          net: FAB_CLK_80MHz
  9.350                        FAB_CLK_80MHz (f)
                                    
  9.350                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          SimpleWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  N/C                          SimpleWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          FAB_CLK_80MHz (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

