Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Fri Dec 16 18:54:29 2011


Design: Top_Level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                7.971
Frequency (MHz):            125.455
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.383
External Hold (ns):         1.283
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                14.880
Frequency (MHz):            67.204
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      3.416
Max Clock-To-Out (ns):      8.355

Clock Domain:               mss_ccc_glc
Period (ns):                29.501
Frequency (MHz):            33.897
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.832
Max Clock-To-Out (ns):      11.229

Clock Domain:               ImprovedWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      3.386
Max Clock-To-Out (ns):      11.380

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[13]
  Delay (ns):                  9.789
  Slack (ns):
  Arrival (ns):                9.789
  Required (ns):
  Setup (ns):                  -1.818
  Minimum Period (ns):         7.971

Path 2
  From:                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  Delay (ns):                  9.359
  Slack (ns):
  Arrival (ns):                9.359
  Required (ns):
  Setup (ns):                  -1.818
  Minimum Period (ns):         7.541

Path 3
  From:                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  8.509
  Slack (ns):
  Arrival (ns):                8.509
  Required (ns):
  Setup (ns):                  -1.070
  Minimum Period (ns):         7.439

Path 4
  From:                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
  Delay (ns):                  9.169
  Slack (ns):
  Arrival (ns):                9.169
  Required (ns):
  Setup (ns):                  -1.814
  Minimum Period (ns):         7.355

Path 5
  From:                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[1]
  Delay (ns):                  8.989
  Slack (ns):
  Arrival (ns):                8.989
  Required (ns):
  Setup (ns):                  -1.814
  Minimum Period (ns):         7.175


Expanded Path 1
  From: ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB
  To: ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[13]
  data required time                             N/C
  data arrival time                          -   9.789
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.381          cell: ADLIB:MSS_APB_IP
  2.381                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[11] (f)
               +     0.131          net: ImprovedWire_0/MSS_ADLIB_INST/MSSPADDR[11]INT_NET
  2.512                        ImprovedWire_0/MSS_ADLIB_INST/U_33:PIN3INT (f)
               +     0.072          cell: ADLIB:MSS_IF
  2.584                        ImprovedWire_0/MSS_ADLIB_INST/U_33:PIN3 (f)
               +     1.089          net: M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[11]
  3.673                        CoreAPB3_Slave_Side_0/CoreAPB3_Slave_Side_0/iPSELS_2[0]:C (f)
               +     0.543          cell: ADLIB:NOR3A
  4.216                        CoreAPB3_Slave_Side_0/CoreAPB3_Slave_Side_0/iPSELS_2[0]:Y (r)
               +     0.255          net: CoreAPB3_Slave_Side_0/CoreAPB3_Slave_Side_0/iPSELS_2[0]
  4.471                        CoreAPB3_Slave_Side_0/CoreAPB3_Slave_Side_0/iPSELS[0]:A (r)
               +     0.398          cell: ADLIB:OR3A
  4.869                        CoreAPB3_Slave_Side_0/CoreAPB3_Slave_Side_0/iPSELS[0]:Y (f)
               +     1.950          net: CoreAPB3_Slave_Side_0_APBmslave0_PSELx
  6.819                        CoreAPB3_Slave_Side_0/CoreAPB3_Slave_Side_0/u_mux_p_to_b3/PRDATA_13:B (f)
               +     0.370          cell: ADLIB:NOR2A
  7.189                        CoreAPB3_Slave_Side_0/CoreAPB3_Slave_Side_0/u_mux_p_to_b3/PRDATA_13:Y (r)
               +     2.065          net: PRDATA_13
  9.254                        ImprovedWire_0/MSS_ADLIB_INST/U_41:PIN5 (r)
               +     0.180          cell: ADLIB:MSS_IF
  9.434                        ImprovedWire_0/MSS_ADLIB_INST/U_41:PIN5INT (r)
               +     0.355          net: ImprovedWire_0/MSS_ADLIB_INST/MSSPRDATA[13]INT_NET
  9.789                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[13] (r)
                                    
  9.789                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               -    -1.818          Library setup time: ADLIB:MSS_APB_IP
  N/C                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[13]


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin ImprovedWire_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.782
  External Setup (ns):         -1.383


Expanded Path 1
  From: MSS_RESET_N
  To: ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        ImprovedWire_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        ImprovedWire_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: ImprovedWire_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.382          net: ImprovedWire_0/GLA0
  N/C                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.782          Library setup time: ADLIB:MSS_APB_IP
  N/C                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        APB_MEM_CTRL_0/delay_start[0]:CLK
  To:                          APB_MEM_CTRL_0/delay_start[31]:D
  Delay (ns):                  14.445
  Slack (ns):
  Arrival (ns):                15.056
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         14.880

Path 2
  From:                        APB_MEM_CTRL_0/delay_start[0]:CLK
  To:                          APB_MEM_CTRL_0/delay_start[30]:D
  Delay (ns):                  14.269
  Slack (ns):
  Arrival (ns):                14.880
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         14.692

Path 3
  From:                        APB_MEM_CTRL_0/delay_start[1]:CLK
  To:                          APB_MEM_CTRL_0/delay_start[31]:D
  Delay (ns):                  14.252
  Slack (ns):
  Arrival (ns):                14.849
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         14.673

Path 4
  From:                        APB_MEM_CTRL_0/delay_start[2]:CLK
  To:                          APB_MEM_CTRL_0/delay_start[31]:D
  Delay (ns):                  14.226
  Slack (ns):
  Arrival (ns):                14.823
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         14.647

Path 5
  From:                        APB_MEM_CTRL_0/delay_start[1]:CLK
  To:                          APB_MEM_CTRL_0/delay_start[30]:D
  Delay (ns):                  14.076
  Slack (ns):
  Arrival (ns):                14.673
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         14.485


Expanded Path 1
  From: APB_MEM_CTRL_0/delay_start[0]:CLK
  To: APB_MEM_CTRL_0/delay_start[31]:D
  data required time                             N/C
  data arrival time                          -   15.056
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.611          net: FAB_CLK
  0.611                        APB_MEM_CTRL_0/delay_start[0]:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  1.051                        APB_MEM_CTRL_0/delay_start[0]:Q (r)
               +     0.632          net: APB_MEM_CTRL_0/delay_start[0]
  1.683                        APB_MEM_CTRL_0/delay_start_RNIVT4[2]:A (r)
               +     0.398          cell: ADLIB:NOR3C
  2.081                        APB_MEM_CTRL_0/delay_start_RNIVT4[2]:Y (r)
               +     0.364          net: APB_MEM_CTRL_0/N_345
  2.445                        APB_MEM_CTRL_0/delay_start_RNIE78[4]:A (r)
               +     0.398          cell: ADLIB:NOR3C
  2.843                        APB_MEM_CTRL_0/delay_start_RNIE78[4]:Y (r)
               +     1.135          net: APB_MEM_CTRL_0/N_347
  3.978                        APB_MEM_CTRL_0/delay_start_RNI1HB[6]:A (r)
               +     0.398          cell: ADLIB:NOR3C
  4.376                        APB_MEM_CTRL_0/delay_start_RNI1HB[6]:Y (r)
               +     0.360          net: APB_MEM_CTRL_0/delay_start_c6
  4.736                        APB_MEM_CTRL_0/delay_start_RNIOQE[8]:B (r)
               +     0.473          cell: ADLIB:NOR3C
  5.209                        APB_MEM_CTRL_0/delay_start_RNIOQE[8]:Y (r)
               +     0.360          net: APB_MEM_CTRL_0/delay_start_c8
  5.569                        APB_MEM_CTRL_0/delay_start_RNIQHI6[10]:B (r)
               +     0.473          cell: ADLIB:NOR3C
  6.042                        APB_MEM_CTRL_0/delay_start_RNIQHI6[10]:Y (r)
               +     1.363          net: APB_MEM_CTRL_0/delay_start_c10
  7.405                        APB_MEM_CTRL_0/delay_start_RNIQSC32[11]:B (r)
               +     0.473          cell: ADLIB:NOR3C
  7.878                        APB_MEM_CTRL_0/delay_start_RNIQSC32[11]:Y (r)
               +     0.758          net: APB_MEM_CTRL_0/delay_start_c20
  8.636                        APB_MEM_CTRL_0/delay_start_RNI9DHF2[22]:B (r)
               +     0.473          cell: ADLIB:NOR3C
  9.109                        APB_MEM_CTRL_0/delay_start_RNI9DHF2[22]:Y (r)
               +     0.360          net: APB_MEM_CTRL_0/delay_start_c22
  9.469                        APB_MEM_CTRL_0/delay_start_RNISDMR2[24]:B (r)
               +     0.473          cell: ADLIB:NOR3C
  9.942                        APB_MEM_CTRL_0/delay_start_RNISDMR2[24]:Y (r)
               +     0.822          net: APB_MEM_CTRL_0/delay_start_c24
  10.764                       APB_MEM_CTRL_0/delay_start_RNIJUR73[26]:B (r)
               +     0.473          cell: ADLIB:NOR3C
  11.237                       APB_MEM_CTRL_0/delay_start_RNIJUR73[26]:Y (r)
               +     1.362          net: APB_MEM_CTRL_0/delay_start_c26
  12.599                       APB_MEM_CTRL_0/delay_start_RNIEV1K3[28]:B (r)
               +     0.473          cell: ADLIB:NOR3C
  13.072                       APB_MEM_CTRL_0/delay_start_RNIEV1K3[28]:Y (r)
               +     0.505          net: APB_MEM_CTRL_0/delay_start_c28
  13.577                       APB_MEM_CTRL_0/delay_start_RNIT55Q3[29]:A (r)
               +     0.370          cell: ADLIB:NOR2B
  13.947                       APB_MEM_CTRL_0/delay_start_RNIT55Q3[29]:Y (r)
               +     0.291          net: APB_MEM_CTRL_0/delay_start_c29
  14.238                       APB_MEM_CTRL_0/delay_start_RNO[31]:B (r)
               +     0.571          cell: ADLIB:AX1C
  14.809                       APB_MEM_CTRL_0/delay_start_RNO[31]:Y (f)
               +     0.247          net: APB_MEM_CTRL_0/delay_start_n31
  15.056                       APB_MEM_CTRL_0/delay_start[31]:D (f)
                                    
  15.056                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.611          net: FAB_CLK
  N/C                          APB_MEM_CTRL_0/delay_start[31]:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  N/C                          APB_MEM_CTRL_0/delay_start[31]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        APB_MEM_CTRL_0/data[7]/U1:CLK
  To:                          adc_data_to_mod[7]
  Delay (ns):                  7.770
  Slack (ns):
  Arrival (ns):                8.355
  Required (ns):
  Clock to Out (ns):           8.355

Path 2
  From:                        APB_MEM_CTRL_0/data[4]/U1:CLK
  To:                          adc_data_to_mod[4]
  Delay (ns):                  7.366
  Slack (ns):
  Arrival (ns):                7.911
  Required (ns):
  Clock to Out (ns):           7.911

Path 3
  From:                        APB_MEM_CTRL_0/data[5]/U1:CLK
  To:                          adc_data_to_mod[5]
  Delay (ns):                  7.254
  Slack (ns):
  Arrival (ns):                7.816
  Required (ns):
  Clock to Out (ns):           7.816

Path 4
  From:                        APB_MEM_CTRL_0/data[2]/U1:CLK
  To:                          adc_data_to_mod[2]
  Delay (ns):                  7.200
  Slack (ns):
  Arrival (ns):                7.762
  Required (ns):
  Clock to Out (ns):           7.762

Path 5
  From:                        APB_MEM_CTRL_0/data[6]/U1:CLK
  To:                          adc_data_to_mod[6]
  Delay (ns):                  7.093
  Slack (ns):
  Arrival (ns):                7.647
  Required (ns):
  Clock to Out (ns):           7.647


Expanded Path 1
  From: APB_MEM_CTRL_0/data[7]/U1:CLK
  To: adc_data_to_mod[7]
  data required time                             N/C
  data arrival time                          -   8.355
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.585          net: FAB_CLK
  0.585                        APB_MEM_CTRL_0/data[7]/U1:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.144                        APB_MEM_CTRL_0/data[7]/U1:Q (f)
               +     4.002          net: adc_data_to_mod_c[7]
  5.146                        adc_data_to_mod_pad[7]/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  5.646                        adc_data_to_mod_pad[7]/U0/U1:DOUT (f)
               +     0.000          net: adc_data_to_mod_pad[7]/U0/NET1
  5.646                        adc_data_to_mod_pad[7]/U0/U0:D (f)
               +     2.709          cell: ADLIB:IOPAD_TRI
  8.355                        adc_data_to_mod_pad[7]/U0/U0:PAD (f)
               +     0.000          net: adc_data_to_mod[7]
  8.355                        adc_data_to_mod[7] (f)
                                    
  8.355                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
                                    
  N/C                          adc_data_to_mod[7] (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glc

SET Register to Register

Path 1
  From:                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/myRegister1/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[3]:CLK
  To:                          Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_ret_16_Z:D
  Delay (ns):                  29.097
  Slack (ns):
  Arrival (ns):                29.651
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         29.501

Path 2
  From:                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/myRegister1/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[3]:CLK
  To:                          Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_ret_11_Z:D
  Delay (ns):                  28.975
  Slack (ns):
  Arrival (ns):                29.529
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         29.383

Path 3
  From:                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/myRegister1/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[3]:CLK
  To:                          Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_ret_18_Z:D
  Delay (ns):                  28.867
  Slack (ns):
  Arrival (ns):                29.421
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         29.271

Path 4
  From:                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/myRegister1/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[0]:CLK
  To:                          Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_ret_16_Z:D
  Delay (ns):                  28.827
  Slack (ns):
  Arrival (ns):                29.389
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         29.239

Path 5
  From:                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[5]:CLK
  To:                          Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_ret_16_Z:D
  Delay (ns):                  28.728
  Slack (ns):
  Arrival (ns):                29.286
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         29.136


Expanded Path 1
  From: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/myRegister1/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[3]:CLK
  To: Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_ret_16_Z:D
  data required time                             N/C
  data arrival time                          -   29.651
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.554          net: M3_PROC_ADC_DAC_0_GLC
  0.554                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/myRegister1/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[3]:CLK (r)
               +     0.559          cell: ADLIB:DFN1
  1.113                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/myRegister1/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[3]:Q (f)
               +     0.806          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/N_7[3]
  1.919                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_RNIMCSB[5]:B (f)
               +     0.749          cell: ADLIB:XOR2
  2.668                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_RNIMCSB[5]:Y (f)
               +     0.278          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/N_194
  2.946                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_2_95.ADD_25x25_medium_area_I2_S_0:A (f)
               +     0.370          cell: ADLIB:XOR2
  3.316                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_2_95.ADD_25x25_medium_area_I2_S_0:Y (r)
               +     0.453          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/N309
  3.769                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_2_95.ADD_25x25_medium_area_I58_un1_Y:A (r)
               +     0.398          cell: ADLIB:OR3C
  4.167                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_2_95.ADD_25x25_medium_area_I58_un1_Y:Y (f)
               +     0.255          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/I58_un1_Y
  4.422                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_2_95.ADD_25x25_medium_area_I58_Y:B (f)
               +     0.479          cell: ADLIB:OR2B
  4.901                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_2_95.ADD_25x25_medium_area_I58_Y:Y (r)
               +     0.982          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/N475
  5.883                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_2_95.ADD_25x25_medium_area_I131_un1_Y:A (r)
               +     0.407          cell: ADLIB:OR2A
  6.290                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_2_95.ADD_25x25_medium_area_I131_un1_Y:Y (f)
               +     0.255          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/I131_un1_Y_0
  6.545                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_2_95.ADD_25x25_medium_area_I137_Y_0:A (f)
               +     0.753          cell: ADLIB:AX1C
  7.298                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_2_95.ADD_25x25_medium_area_I137_Y_0:Y (f)
               +     0.896          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/N_6[3]
  8.194                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I5_S_0:B (f)
               +     0.711          cell: ADLIB:XOR2
  8.905                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I5_S_0:Y (r)
               +     0.294          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/N334_1
  9.199                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I48_Y:A (r)
               +     0.370          cell: ADLIB:NOR2B
  9.569                        Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I48_Y:Y (r)
               +     0.750          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/N507
  10.319                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I67_un1_Y_0:B (r)
               +     0.448          cell: ADLIB:NOR2B
  10.767                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I67_un1_Y_0:Y (r)
               +     0.247          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/ADD_27x27_medium_area_I67_un1_Y_0
  11.014                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I67_un1_Y:C (r)
               +     0.570          cell: ADLIB:OR3C
  11.584                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I67_un1_Y:Y (f)
               +     0.255          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/I67_un1_Y
  11.839                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I67_Y:C (f)
               +     0.517          cell: ADLIB:OR3C
  12.356                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I67_Y:Y (r)
               +     1.252          net: Synthetic_ADC_v2_0/myDecimate_by_ten/N500
  13.608                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I68_un1_Y_0:A (r)
               +     0.570          cell: ADLIB:NOR3A
  14.178                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I68_un1_Y_0:Y (r)
               +     0.969          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/ADD_27x27_medium_area_I68_un1_Y_0
  15.147                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I68_un1_Y_1:A (r)
               +     0.370          cell: ADLIB:NOR2B
  15.517                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I68_un1_Y_1:Y (r)
               +     0.259          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/ADD_27x27_medium_area_I68_un1_Y_1
  15.776                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I68_Y_2:B (r)
               +     0.452          cell: ADLIB:OAI1
  16.228                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I68_Y_2:Y (f)
               +     0.257          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/ADD_27x27_medium_area_I68_Y_2
  16.485                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I68_Y:A (f)
               +     0.293          cell: ADLIB:OR2B
  16.778                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I68_Y:Y (r)
               +     1.028          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/N480
  17.806                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I159_Y_0:A (r)
               +     0.301          cell: ADLIB:XOR2
  18.107                       Synthetic_ADC_v2_0/myDecimate_by_ten/myIIR_2nd_order/tmpOutPre_3_0_0.ADD_27x27_medium_area_I159_Y_0:Y (f)
               +     1.080          net: Synthetic_ADC_v2_0/myDecimate_by_ten/IIR_filter_out[14]
  19.187                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I14_S_0:B (f)
               +     0.711          cell: ADLIB:XOR2
  19.898                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I14_S_0:Y (r)
               +     0.358          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/N418
  20.256                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I73_Y_0:A (r)
               +     0.407          cell: ADLIB:OR2A
  20.663                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I73_Y_0:Y (f)
               +     0.252          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/ADD_33x33_medium_area_I73_Y_0
  20.915                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I73_Y:C (f)
               +     0.399          cell: ADLIB:XA1C
  21.314                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I73_Y:Y (r)
               +     0.255          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/N497
  21.569                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I88_Y_2:C (r)
               +     0.497          cell: ADLIB:OAI1
  22.066                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I88_Y_2:Y (f)
               +     0.255          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/ADD_33x33_medium_area_I88_Y_2
  22.321                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I88_Y:C (f)
               +     0.517          cell: ADLIB:OR3C
  22.838                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I88_Y:Y (r)
               +     1.311          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/N594
  24.149                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I96_Y_2_tz:A (r)
               +     0.364          cell: ADLIB:AO1
  24.513                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I96_Y_2_tz:Y (r)
               +     0.970          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/ADD_33x33_medium_area_I96_Y_2_tz
  25.483                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I96_Y_2:C (r)
               +     0.505          cell: ADLIB:OR3C
  25.988                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I96_Y_2:Y (f)
               +     0.435          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/ADD_33x33_medium_area_I96_Y_2
  26.423                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I103_un1_Y:B (f)
               +     0.461          cell: ADLIB:AO1B
  26.884                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I103_un1_Y:Y (f)
               +     1.038          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/I103_un1_Y
  27.922                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I209_Y_0:A (f)
               +     0.758          cell: ADLIB:AX1E
  28.680                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/tmpOutPre_3.ADD_33x33_medium_area_I209_Y_0:Y (f)
               +     0.255          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/N_2[28]
  28.935                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_ret_16_RNO:B (f)
               +     0.469          cell: ADLIB:MX2
  29.404                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_ret_16_RNO:Y (f)
               +     0.247          net: Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/myRegister_syn/Register_syn_block_myRegister_syn/Delay0_block/GenBlock_genblk58_genblk59_theDelay/N_29
  29.651                       Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_ret_16_Z:D (f)
                                    
  29.651                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.585          net: M3_PROC_ADC_DAC_0_GLC
  N/C                          Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_ret_16_Z:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1
  N/C                          Synthetic_ADC_v2_0/myDecimate_by_ten/myCIC_2nd_Order/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_ret_16_Z:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/myRegister1/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[0]:CLK
  To:                          Load_SR
  Delay (ns):                  10.705
  Slack (ns):
  Arrival (ns):                11.229
  Required (ns):
  Clock to Out (ns):           11.229

Path 2
  From:                        Synthetic_ADC_v2_0/myP2S/myBitclk_Edges/myRegister2/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[0]:CLK
  To:                          Load_SR
  Delay (ns):                  10.466
  Slack (ns):
  Arrival (ns):                11.003
  Required (ns):
  Clock to Out (ns):           11.003

Path 3
  From:                        Synthetic_ADC_v2_0/Delay_syn_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[0]:CLK
  To:                          En_50K_pulse
  Delay (ns):                  9.344
  Slack (ns):
  Arrival (ns):                9.877
  Required (ns):
  Clock to Out (ns):           9.877

Path 4
  From:                        Synthetic_ADC_v2_0/mySigma_Delta_Modulator/myClkdiv_and_RTZ_Modulator/mycounter/myRegister_syn/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[2]:CLK
  To:                          En_out
  Delay (ns):                  9.223
  Slack (ns):
  Arrival (ns):                9.829
  Required (ns):
  Clock to Out (ns):           9.829

Path 5
  From:                        Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/myRegister2/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[0]:CLK
  To:                          Load_SR
  Delay (ns):                  9.242
  Slack (ns):
  Arrival (ns):                9.777
  Required (ns):
  Clock to Out (ns):           9.777


Expanded Path 1
  From: Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/myRegister1/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[0]:CLK
  To: Load_SR
  data required time                             N/C
  data arrival time                          -   11.229
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.524          net: M3_PROC_ADC_DAC_0_GLC
  0.524                        Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/myRegister1/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[0]:CLK (r)
               +     0.559          cell: ADLIB:DFN1
  1.083                        Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/myRegister1/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[0]:Q (f)
               +     1.428          net: Synthetic_ADC_v2_0/myP2S/N_9[0]
  2.511                        Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/myRegister2/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_RNI55A7[0]:B (f)
               +     0.749          cell: ADLIB:XOR2
  3.260                        Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/myRegister2/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_RNI55A7[0]:Y (f)
               +     0.803          net: Synthetic_ADC_v2_0/myP2S/outreg_RNI55A7[0]
  4.063                        Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/N_2[0]:A (f)
               +     0.390          cell: ADLIB:OR2B
  4.453                        Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/N_2[0]:Y (r)
               +     1.525          net: Synthetic_ADC_v2_0/myP2S/N_30[0]
  5.978                        Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/N_2_RNIE172[0]:A (r)
               +     0.276          cell: ADLIB:INV
  6.254                        Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/N_2_RNIE172[0]:Y (f)
               +     1.766          net: Load_SR_c
  8.020                        Load_SR_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  8.520                        Load_SR_pad/U0/U1:DOUT (f)
               +     0.000          net: Load_SR_pad/U0/NET1
  8.520                        Load_SR_pad/U0/U0:D (f)
               +     2.709          cell: ADLIB:IOPAD_TRI
  11.229                       Load_SR_pad/U0/U0:PAD (f)
               +     0.000          net: Load_SR
  11.229                       Load_SR (f)
                                    
  11.229                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
                                    
  N/C                          Load_SR (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        reg_apb_wrp_0/reg4x20_inst/mem[1][14]:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/mem[1][14]:CLR
  Delay (ns):                  2.850
  Slack (ns):
  Arrival (ns):                3.423
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.075
  Skew (ns):                   0.000

Path 2
  From:                        reg_apb_wrp_0/reg4x20_inst/mem[0][12]:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/mem[0][12]:PRE
  Delay (ns):                  2.674
  Slack (ns):
  Arrival (ns):                3.260
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         2.933
  Skew (ns):                   0.034

Path 3
  From:                        reg_apb_wrp_0/reg4x20_inst/mem[1][0]:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/mem[1][0]:PRE
  Delay (ns):                  2.603
  Slack (ns):
  Arrival (ns):                3.176
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         2.828
  Skew (ns):                   0.000

Path 4
  From:                        reg_apb_wrp_0/reg4x20_inst/mem[0][11]:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/mem[0][11]:PRE
  Delay (ns):                  2.499
  Slack (ns):
  Arrival (ns):                3.095
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         2.763
  Skew (ns):                   0.039

Path 5
  From:                        reg_apb_wrp_0/reg4x20_inst/mem[0][17]:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/mem[0][17]:PRE
  Delay (ns):                  2.514
  Slack (ns):
  Arrival (ns):                3.104
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         2.761
  Skew (ns):                   0.022


Expanded Path 1
  From: reg_apb_wrp_0/reg4x20_inst/mem[1][14]:CLK
  To: reg_apb_wrp_0/reg4x20_inst/mem[1][14]:CLR
  data required time                             N/C
  data arrival time                          -   3.423
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.573          net: M3_PROC_ADC_DAC_0_GLC
  0.573                        reg_apb_wrp_0/reg4x20_inst/mem[1][14]:CLK (r)
               +     1.272          cell: ADLIB:DFN1P1C1
  1.845                        reg_apb_wrp_0/reg4x20_inst/mem[1][14]:Q (r)
               +     0.840          net: reg_apb_wrp_0/reg4x20_inst/mem[1][14]
  2.685                        reg_apb_wrp_0/reg4x20_inst/mem[1]_RNO[14]:A (r)
               +     0.460          cell: ADLIB:AOI1
  3.145                        reg_apb_wrp_0/reg4x20_inst/mem[1]_RNO[14]:Y (f)
               +     0.278          net: reg_apb_wrp_0/reg4x20_inst/mem[1]_RNO[14]
  3.423                        reg_apb_wrp_0/reg4x20_inst/mem[1][14]:CLR (f)
                                    
  3.423                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.573          net: M3_PROC_ADC_DAC_0_GLC
  N/C                          reg_apb_wrp_0/reg4x20_inst/mem[1][14]:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1P1C1
  N/C                          reg_apb_wrp_0/reg4x20_inst/mem[1][14]:CLR


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain ImprovedWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          Load_SR
  Delay (ns):                  11.380
  Slack (ns):
  Arrival (ns):                11.380
  Required (ns):
  Clock to Out (ns):           11.380

Path 2
  From:                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          P2S_bitclk_falling
  Delay (ns):                  9.444
  Slack (ns):
  Arrival (ns):                9.444
  Required (ns):
  Clock to Out (ns):           9.444

Path 3
  From:                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          P2S_bitclk_rising
  Delay (ns):                  8.507
  Slack (ns):
  Arrival (ns):                8.507
  Required (ns):
  Clock to Out (ns):           8.507

Path 4
  From:                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          bit_clk_out
  Delay (ns):                  6.843
  Slack (ns):
  Arrival (ns):                6.843
  Required (ns):
  Clock to Out (ns):           6.843

Path 5
  From:                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          clk_24MHz_out
  Delay (ns):                  6.843
  Slack (ns):
  Arrival (ns):                6.843
  Required (ns):
  Clock to Out (ns):           6.843


Expanded Path 1
  From: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: Load_SR
  data required time                             N/C
  data arrival time                          -   11.380
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        ImprovedWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  0.000                        ImprovedWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     2.141          cell: ADLIB:MSS_CCC_IP
  2.141                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  2.141                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  2.141                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.534          net: M3_PROC_ADC_DAC_0_GLC
  2.675                        Synthetic_ADC_v2_0/myP2S/myBitclk_Edges/myRegister2/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_RNILK07[0]:B (r)
               +     0.293          cell: ADLIB:NOR2A
  2.968                        Synthetic_ADC_v2_0/myP2S/myBitclk_Edges/myRegister2/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_RNILK07[0]:Y (f)
               +     1.157          net: P2S_bitclk_falling_c
  4.125                        Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/N_2[0]:B (f)
               +     0.479          cell: ADLIB:OR2B
  4.604                        Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/N_2[0]:Y (r)
               +     1.525          net: Synthetic_ADC_v2_0/myP2S/N_30[0]
  6.129                        Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/N_2_RNIE172[0]:A (r)
               +     0.276          cell: ADLIB:INV
  6.405                        Synthetic_ADC_v2_0/myP2S/myFrameclk_Edges/N_2_RNIE172[0]:Y (f)
               +     1.766          net: Load_SR_c
  8.171                        Load_SR_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  8.671                        Load_SR_pad/U0/U1:DOUT (f)
               +     0.000          net: Load_SR_pad/U0/NET1
  8.671                        Load_SR_pad/U0/U0:D (f)
               +     2.709          cell: ADLIB:IOPAD_TRI
  11.380                       Load_SR_pad/U0/U0:PAD (f)
               +     0.000          net: Load_SR
  11.380                       Load_SR (f)
                                    
  11.380                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          ImprovedWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          Load_SR (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

