********************************************************************
                            Global Net Report
********************************************************************
  
Product: Designer
Release: v10.0
Version: 10.0.9.37
Date: Fri Dec 16 18:54:16 2011
Design Name: Top_Level  Family: SmartFusion  Die: A2F500M3G  Package: 484 FBGA


Automatic Global Net Placement Result:
Status: Global net placement completed successfully


Global Nets Information:

        |-------------------------------------------------------------|
        |Global Nets                 |Loads                           |
        |-------------------------------------------------------------|
        |Name                        |Core      |IO        |RAM       |
        |-------------------------------------------------------------|
        |FAB_CLK                     |       85 |        0 |        0 |
        |-------------------------------------------------------------|
        |INVD_0_Y                    |      412 |        0 |        0 |
        |-------------------------------------------------------------|
        |M3_PROC_ADC_DAC_0_GLC       |      605 |        1 |        0 |
        |-------------------------------------------------------------|
        |Synthetic_ADC_v2_0/en       |      109 |        0 |        0 |
        |-------------------------------------------------------------|
        |Synthetic_ADC_v2_0/enab     |       81 |        0 |        0 |
        |-------------------------------------------------------------|
        |Synthetic_ADC_v2_0/rst_1    |      134 |        0 |        0 |
        |-------------------------------------------------------------|
        |Synthetic_ADC_v2_0/un1_rst_1|      157 |        0 |        0 |
        |-------------------------------------------------------------|

Nets Sharing Loads:

        |---------------------------------------------------------|
        |Global Net                  |Shares Loads With ...       |
        |---------------------------------------------------------|
        |INVD_0_Y                    |M3_PROC_ADC_DAC_0_GLC       |
        |                            |Synthetic_ADC_v2_0/un1_rst_1|
        |---------------------------------------------------------|
        |M3_PROC_ADC_DAC_0_GLC       |INVD_0_Y                    |
        |                            |Synthetic_ADC_v2_0/en       |
        |---------------------------------------------------------|
        |Synthetic_ADC_v2_0/en       |M3_PROC_ADC_DAC_0_GLC       |
        |---------------------------------------------------------|
        |Synthetic_ADC_v2_0/un1_rst_1|INVD_0_Y                    |
        |---------------------------------------------------------|

Summary of Global Net Placement:

        |--------------------------------------------------------------------------------|
        |Global Net                  |Assignment          |Violation                     |
        |--------------------------------------------------------------------------------|
        |FAB_CLK                     |MIDDLE_LEFT         |                              |
        |--------------------------------------------------------------------------------|
        |INVD_0_Y                    |MIDDLE_RIGHT        |                              |
        |--------------------------------------------------------------------------------|
        |M3_PROC_ADC_DAC_0_GLC       |MIDDLE_LEFT         |                              |
        |--------------------------------------------------------------------------------|
        |Synthetic_ADC_v2_0/en       |LOWER_LEFT          |                              |
        |--------------------------------------------------------------------------------|
        |Synthetic_ADC_v2_0/enab     |LOWER_LEFT          |                              |
        |--------------------------------------------------------------------------------|
        |Synthetic_ADC_v2_0/rst_1    |MIDDLE_RIGHT        |                              |
        |--------------------------------------------------------------------------------|
        |Synthetic_ADC_v2_0/un1_rst_1|MIDDLE_RIGHT        |                              |
        |--------------------------------------------------------------------------------|
