library verilog;
use verilog.vl_types.all;
entity Top_Level is
    port(
        UART_0_TXD      : out    vl_logic;
        UART_0_RXD      : in     vl_logic;
        MSS_RESET_N     : in     vl_logic;
        SDD_0           : out    vl_logic;
        ADCDirectInput_0: in     vl_logic;
        VAREF0          : in     vl_logic;
        Bit_Clk         : in     vl_logic;
        Frame_Clk       : in     vl_logic;
        DAC_out         : out    vl_logic;
        Serial_Data_out : out    vl_logic;
        En_out          : out    vl_logic;
        nDAC_out        : out    vl_logic;
        Load_SR         : out    vl_logic;
        P2S_bitclk_rising: out    vl_logic;
        P2S_bitclk_falling: out    vl_logic;
        En_50K_pulse    : out    vl_logic;
        clk_24MHz_out   : out    vl_logic;
        frame_clk_out   : out    vl_logic;
        bit_clk_out     : out    vl_logic;
        En_400K_pulse   : out    vl_logic;
        adc_data_ready  : out    vl_logic;
        CLKA            : in     vl_logic;
        clk_25MHz_out   : out    vl_logic;
        adc_data_to_mod : out    vl_logic_vector(11 downto 0)
    );
end Top_Level;
