library verilog;
use verilog.vl_types.all;
entity synP2S_Shift_Register_Shift_Register_Register is
    port(
        Ser_Dat_out     : out    vl_logic_vector(0 downto 0);
        N_2             : in     vl_logic_vector(23 downto 0);
        N_8             : out    vl_logic_vector(22 downto 0);
        clk             : in     vl_logic;
        GlobalReset     : in     vl_logic;
        enab            : in     vl_logic
    );
end synP2S_Shift_Register_Shift_Register_Register;
