library verilog;
use verilog.vl_types.all;
entity Sigma_Delta_Modulator_Sigma_Delta_Modulator_4th_order is
    port(
        N_6_1           : out    vl_logic;
        N_10            : in     vl_logic_vector(20 downto 5);
        N_9_0_1z        : in     vl_logic;
        rst_1_0         : out    vl_logic;
        Reset           : in     vl_logic;
        GlobalEnable1   : in     vl_logic;
        clk             : in     vl_logic;
        un1_rst_1_0     : out    vl_logic;
        rst_1           : in     vl_logic;
        GlobalReset     : in     vl_logic;
        un1_rst_1       : in     vl_logic
    );
end Sigma_Delta_Modulator_Sigma_Delta_Modulator_4th_order;
