library verilog;
use verilog.vl_types.all;
entity synSigma_Delta_Modulator_Sigma_Delta_Modulator_4th_order_D2_Register is
    port(
        SUM1_i          : in     vl_logic_vector(24 downto 24);
        N_3             : in     vl_logic_vector(9 downto 0);
        N_4             : out    vl_logic_vector(9 downto 9);
        SUM1            : in     vl_logic_vector(17 downto 14);
        N_13            : in     vl_logic_vector(3 downto 1);
        N_15_0          : out    vl_logic;
        N_15_7          : out    vl_logic;
        N_15_5          : out    vl_logic;
        N_21            : in     vl_logic_vector(6 downto 0);
        N_9             : in     vl_logic_vector(23 downto 8);
        clk             : in     vl_logic;
        N_366           : out    vl_logic;
        N_365           : out    vl_logic;
        N_355           : out    vl_logic;
        N_356           : out    vl_logic;
        N_358_1         : out    vl_logic;
        N_417_i         : out    vl_logic;
        N_418           : out    vl_logic;
        N_189_i         : out    vl_logic;
        tmpOutPre_1_96_9: out    vl_logic;
        tmpOutPre_2_10  : out    vl_logic;
        rst_1           : in     vl_logic;
        GlobalReset     : in     vl_logic;
        un1_rst_1       : in     vl_logic;
        N_466           : out    vl_logic;
        N_454           : out    vl_logic;
        N_430           : out    vl_logic;
        N_408           : out    vl_logic;
        N_402_i         : out    vl_logic;
        tmpOutPre_2_151 : in     vl_logic;
        tmpOutPre_2_255_0_tz: in     vl_logic;
        N_288           : out    vl_logic;
        N_276_i         : out    vl_logic;
        N_274_i         : out    vl_logic;
        N_266           : out    vl_logic;
        N_258           : out    vl_logic;
        N_246           : out    vl_logic;
        N_236           : out    vl_logic;
        N_216           : in     vl_logic;
        N_226           : out    vl_logic;
        N_194           : in     vl_logic;
        N_204           : out    vl_logic;
        N_186           : out    vl_logic;
        N_256_i_0       : out    vl_logic;
        N_344           : in     vl_logic;
        N_298           : out    vl_logic;
        N_458           : out    vl_logic;
        N_270           : out    vl_logic;
        N_260           : out    vl_logic;
        tmpOutPre_2_138 : out    vl_logic;
        N_362           : out    vl_logic;
        N_364           : out    vl_logic;
        N_308           : out    vl_logic;
        tmpOutPre_2_34  : in     vl_logic;
        tmpOutPre_2_18_0_tz: out    vl_logic;
        tmpOutPre_2_429_0: out    vl_logic;
        tmpOutPre_2_429_0_tz: out    vl_logic;
        N_275           : out    vl_logic;
        N_202           : in     vl_logic;
        N_213           : out    vl_logic;
        N_271           : in     vl_logic;
        N_185           : out    vl_logic;
        N_287           : out    vl_logic;
        N_307           : out    vl_logic;
        N_320           : in     vl_logic;
        N_331           : out    vl_logic;
        N_401           : out    vl_logic;
        N_407           : out    vl_logic;
        N_429           : out    vl_logic;
        N_465           : out    vl_logic;
        N_255           : out    vl_logic;
        N_444           : in     vl_logic;
        N_457           : out    vl_logic;
        N_441           : out    vl_logic;
        N_297           : out    vl_logic;
        N_317           : out    vl_logic;
        N_197           : out    vl_logic;
        N_190           : out    vl_logic;
        tmpOutPre_2_44_4_0: out    vl_logic;
        N_201           : in     vl_logic;
        tmpOutPre_2_44_0_0: out    vl_logic;
        tmpOutPre_2_386_0_0: out    vl_logic;
        N_332           : out    vl_logic;
        N_341           : in     vl_logic;
        tmpOutPre_2_391_0_0: out    vl_logic;
        tmpOutPre_2_96_0_0: out    vl_logic;
        tmpOutPre_2_121_0_0: out    vl_logic;
        tmpOutPre_2_413_0_0: out    vl_logic;
        tmpOutPre_2_146_0_0: out    vl_logic;
        tmpOutPre_2_196_0_0: out    vl_logic
    );
end synSigma_Delta_Modulator_Sigma_Delta_Modulator_4th_order_D2_Register;
