library verilog;
use verilog.vl_types.all;
entity Sigma_Delta_Modulator_ISI_Compensation is
    port(
        tmpOut          : in     vl_logic_vector(0 downto 0);
        Quadratic_Comp  : in     vl_logic_vector(14 downto 0);
        Cubic_Comp      : in     vl_logic_vector(14 downto 0);
        Out1_0_0_2      : out    vl_logic;
        Out1_0_0_0      : out    vl_logic;
        N_8_14          : out    vl_logic;
        N_8_13          : out    vl_logic;
        N_8_12          : out    vl_logic;
        N_8_11          : out    vl_logic;
        N_8_6           : out    vl_logic;
        N_8_0           : out    vl_logic;
        N_8_1           : out    vl_logic;
        N_8_2           : out    vl_logic;
        N_8_4           : out    vl_logic;
        N_8_7           : out    vl_logic;
        N_8_8           : out    vl_logic;
        N_8_9           : out    vl_logic;
        N_8_10          : out    vl_logic;
        GlobalReset     : in     vl_logic;
        N_9             : in     vl_logic;
        clk             : in     vl_logic;
        N_67            : out    vl_logic;
        N_73            : out    vl_logic
    );
end Sigma_Delta_Modulator_ISI_Compensation;
