library verilog;
use verilog.vl_types.all;
entity Decimate_by_ten_CIC_2nd_Order_Register1_3 is
    port(
        N_5             : out    vl_logic_vector(25 downto 0);
        N_3             : in     vl_logic_vector(25 downto 1);
        N_4             : in     vl_logic_vector(5 downto 5);
        en              : in     vl_logic;
        GlobalReset     : in     vl_logic;
        clk             : in     vl_logic
    );
end Decimate_by_ten_CIC_2nd_Order_Register1_3;
