library verilog;
use verilog.vl_types.all;
entity synComparator_4s_unsign_equ is
    generic(
        bitwidth        : integer := 4;
        datatype        : string  := "unsign";
        opr             : string  := "equ"
    );
    port(
        N_8_i_0         : out    vl_logic_vector(0 downto 0);
        N_5             : in     vl_logic_vector(3 downto 0)
    );
end synComparator_4s_unsign_equ;
