library verilog;
use verilog.vl_types.all;
entity Synthetic_ADC_v2 is
    port(
        clk             : in     vl_logic;
        GlobalReset     : in     vl_logic;
        GlobalEnable1   : in     vl_logic;
        P2S_bitclk_falling: out    vl_logic;
        P2S_bitclk_rising: out    vl_logic;
        nDAC_out        : out    vl_logic;
        clk_div         : in     vl_logic_vector(3 downto 0);
        Serial_Data_out : out    vl_logic;
        SD_Mod_Select   : in     vl_logic_vector(1 downto 0);
        Reset           : in     vl_logic;
        RTZ_Mode        : in     vl_logic_vector(1 downto 0);
        Quadratic_Comp  : in     vl_logic_vector(14 downto 0);
        Load_SR         : out    vl_logic;
        Frame_Clk       : in     vl_logic;
        En_out          : out    vl_logic;
        En_50K_pulse    : out    vl_logic;
        En_400K_pulse   : out    vl_logic;
        En_400KHz       : in     vl_logic;
        Direct_Bitstream: in     vl_logic;
        DAC_out         : out    vl_logic;
        Cubic_Comp      : in     vl_logic_vector(14 downto 0);
        Bit_Clk         : in     vl_logic;
        ADC             : in     vl_logic_vector(11 downto 0)
    );
end Synthetic_ADC_v2;
