library verilog;
use verilog.vl_types.all;
entity synDelayWithEnable_1s_24s_1s_2 is
    generic(
        bitwidth        : integer := 24;
        delaylength     : integer := 1
    );
    port(
        N_8             : out    vl_logic_vector(22 downto 0);
        N_2             : in     vl_logic_vector(23 downto 0);
        Ser_Dat_out     : out    vl_logic_vector(0 downto 0);
        enab            : in     vl_logic;
        GlobalReset     : in     vl_logic;
        clk             : in     vl_logic
    );
end synDelayWithEnable_1s_24s_1s_2;
