library verilog;
use verilog.vl_types.all;
entity synP2S_Bitclk_Edges_Register2_Register is
    port(
        clk             : in     vl_logic;
        GlobalEnable1   : in     vl_logic;
        Frame_Clk       : in     vl_logic;
        GlobalReset     : in     vl_logic;
        rst             : out    vl_logic
    );
end synP2S_Bitclk_Edges_Register2_Register;
