library verilog;
use verilog.vl_types.all;
entity Decimate_by_ten_CIC_2nd_Order_Register1 is
    port(
        N_13            : out    vl_logic_vector(25 downto 0);
        N_12            : in     vl_logic_vector(25 downto 1);
        enab            : in     vl_logic;
        GlobalReset     : in     vl_logic;
        N299_i_0        : in     vl_logic;
        clk             : in     vl_logic
    );
end Decimate_by_ten_CIC_2nd_Order_Register1;
