library verilog;
use verilog.vl_types.all;
entity Sigma_Delta_Modulator_Clkdiv_and_RTZ_Modulator_Toggle_FF is
    port(
        RTZ_Mode        : in     vl_logic_vector(1 downto 0);
        N_5             : out    vl_logic_vector(0 downto 0);
        N_8_i_0         : in     vl_logic_vector(0 downto 0);
        GlobalReset     : in     vl_logic;
        Reset           : in     vl_logic;
        un1_rst_1       : in     vl_logic;
        clk             : in     vl_logic;
        N_12            : in     vl_logic
    );
end Sigma_Delta_Modulator_Clkdiv_and_RTZ_Modulator_Toggle_FF;
