library verilog;
use verilog.vl_types.all;
entity synDelayWithEnable_1s_1s_1s is
    generic(
        bitwidth        : integer := 1;
        delaylength     : integer := 1
    );
    port(
        rst             : out    vl_logic;
        GlobalReset     : in     vl_logic;
        Frame_Clk       : in     vl_logic;
        GlobalEnable1   : in     vl_logic;
        clk             : in     vl_logic
    );
end synDelayWithEnable_1s_1s_1s;
