library verilog;
use verilog.vl_types.all;
entity synP2S_Bitclk_Edges_Register2_Register_3 is
    port(
        N_4             : in     vl_logic_vector(0 downto 0);
        N_1             : out    vl_logic_vector(0 downto 0);
        clk             : in     vl_logic;
        GlobalReset     : in     vl_logic;
        GlobalEnable1   : in     vl_logic
    );
end synP2S_Bitclk_Edges_Register2_Register_3;
