library verilog;
use verilog.vl_types.all;
entity synDelayWithEnable_1s_25s_1s is
    generic(
        bitwidth        : integer := 25;
        delaylength     : integer := 1
    );
    port(
        N_7             : out    vl_logic_vector(24 downto 0);
        outreg_RNIJBTD8 : out    vl_logic_vector(2 downto 2);
        outreg_RNIHQ5G4 : out    vl_logic_vector(1 downto 1);
        outreg_RNIGRHK1 : out    vl_logic_vector(0 downto 0);
        N_44            : in     vl_logic_vector(11 downto 11);
        N_8_19          : in     vl_logic;
        N_8_0           : in     vl_logic;
        N_1             : in     vl_logic_vector(24 downto 1);
        N_6_23          : in     vl_logic;
        N_6_0           : in     vl_logic;
        clk             : in     vl_logic;
        N_220_i         : out    vl_logic;
        tmpOutPre_2_49_0_0: in     vl_logic;
        N_236           : out    vl_logic;
        N_216           : out    vl_logic;
        tmpOutPre_2_39_0_0: in     vl_logic;
        N_226           : out    vl_logic;
        tmpOutPre_2_64_0_0: in     vl_logic;
        en              : in     vl_logic;
        GlobalReset     : in     vl_logic;
        N_197           : out    vl_logic;
        N_157_0         : out    vl_logic
    );
end synDelayWithEnable_1s_25s_1s;
