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                            Global Usage Report
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Product: Designer
Release: v10.0
Version: 10.0.9.37
Date: Fri Dec 16 18:54:17 2011
Design Name: Top_Level  Family: SmartFusion  Die: A2F500M3G  Package: 484 FBGA
Design State: Post-Layout

The following nets have been routed to a chip global resource:

    Fanout            Name
    ----------------------
    686               Net   : M3_PROC_ADC_DAC_0_GLC
                      Driver: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3
    86                Net   : FAB_CLK
                      Driver: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE2
    413               Net   : INVD_0_Y
                      Driver: INVD_0_RNIKLE5/U_CLKSRC/U_GL
    157               Net   : Synthetic_ADC_v2_0/un1_rst_1
                      Driver: Synthetic_ADC_v2_0/I_125/U_CLKSRC/U_GL
    134               Net   : Synthetic_ADC_v2_0/rst_1
                      Driver: Synthetic_ADC_v2_0/I_126/U_CLKSRC/U_GL


The following nets have been routed to a quadrant global resource:

    Fanout            Name
    ----------------------
    81                Net   : Synthetic_ADC_v2_0/enab
                      Driver: Synthetic_ADC_v2_0/mySync_logic/Counter_block_myCounter/CounterGen_genblk61_cntU_RNIOJ44_0[2]/U_CLKSRC/U_GL
                      Region : quadrant_LL
    109               Net   : Synthetic_ADC_v2_0/en
                      Driver: Synthetic_ADC_v2_0/I_127/U_CLKSRC/U_GL
                      Region : quadrant_LL



