library verilog;
use verilog.vl_types.all;
entity synP2S_Frameclk_Edges_Register1_Register_2 is
    port(
        N_9             : out    vl_logic_vector(0 downto 0);
        N_9_0           : out    vl_logic_vector(0 downto 0);
        enab            : in     vl_logic;
        Frame_Clk       : in     vl_logic;
        GlobalReset     : in     vl_logic;
        clk             : in     vl_logic
    );
end synP2S_Frameclk_Edges_Register1_Register_2;
