library verilog;
use verilog.vl_types.all;
entity reg_apb_wrp is
    port(
        PCLK            : in     vl_logic;
        PENABLE         : in     vl_logic;
        PSEL            : in     vl_logic;
        PRESETN         : in     vl_logic;
        PWRITE          : in     vl_logic;
        PREADY          : out    vl_logic;
        PSLVERR         : out    vl_logic;
        PADDR           : in     vl_logic_vector(19 downto 0);
        PWDATA          : in     vl_logic_vector(19 downto 0);
        PRDATA          : out    vl_logic_vector(19 downto 0);
        Direct_Out      : out    vl_logic_vector(19 downto 0);
        Quadratic_Comp  : out    vl_logic_vector(14 downto 0);
        Cubic_Comp      : out    vl_logic_vector(14 downto 0);
        Clk_Div         : out    vl_logic_vector(3 downto 0);
        RTZ_Mode        : out    vl_logic_vector(1 downto 0);
        SD_Mod          : out    vl_logic_vector(1 downto 0)
    );
end reg_apb_wrp;
