//////////////////////////////////////////////////////////////////////
// Created by Actel SmartDesign Wed Oct 13 10:26:23 2010
// Testbench Template
// This is a basic testbench that instantiates your design with basic 
// clock and reset pins connected.  If your design has special
// clock/reset or testbench driver requirements then you should 
// copy this file and modify it. 
//////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps

module testbench;

parameter SYSCLK_PERIOD = 40; // 25MHz
parameter BITCLK_PERIOD = 1000; // 1MHz
parameter FRMCLK_PERIOD = 10000; // 100 KHz

real adc_direct_ana = 0.0;
wire adc_direct_dig;

reg SYSCLK, BIT_CLK, FRAME_CLK;
reg NSYSRESET;

integer i;


initial
begin
    SYSCLK = 1'b0;
    BIT_CLK = 1'b0;
    FRAME_CLK = 1'b0;
    NSYSRESET = 1'b0;
end

//////////////////////////////////////////////////////////////////////
// Reset Pulse
//////////////////////////////////////////////////////////////////////
initial
begin
    #(SYSCLK_PERIOD * 10 )
        NSYSRESET = 1'b1;
end

//analog input to ADC
drive_analog_input inst0 ( $realtobits(adc_direct_ana), adc_direct_dig);

//////////////////////////////////////////////////////////////////////
// change analog input
//////////////////////////////////////////////////////////////////////
initial
begin
#100;
   for (i=0; i < 256; i = i+1)
   begin
        #(SYSCLK_PERIOD * 500 )
            adc_direct_ana = 0.25 + (i * 0.01);
   end
   for (i=0; i < 256; i = i+1)
   begin
        #(SYSCLK_PERIOD * 500 )
            adc_direct_ana = 3.0 - (i * 0.01);
   end
end


//////////////////////////////////////////////////////////////////////
// 10MHz Clock Driver
//////////////////////////////////////////////////////////////////////
always @(SYSCLK)
    #(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;

always @(BIT_CLK)
    #(BITCLK_PERIOD / 2.0) BIT_CLK <= !BIT_CLK;

always @(FRAME_CLK)
    #(FRMCLK_PERIOD / 2.0) FRAME_CLK <= !FRAME_CLK;

//////////////////////////////////////////////////////////////////////
// Instantiate Unit Under Test:  Top_Level
//////////////////////////////////////////////////////////////////////
/*
Top_Level Top_Level_0 (
    // Inputs
    .UART_0_RXD({1{1'b0}}),
    .MSS_RESET_N(NSYSRESET),
    .ADCDirectInput_0(adc_direct_dig),
    .VAREF0(),
    .CLKA(SYSCLK),

    // Outputs
    .UART_0_TXD( ),
    .SDD_0( ),
    .data( ),
    .dataout_enable( )

    // Inouts

);
*/

Top_Level Top_Level_0 (
    // Inputs
    .UART_0_RXD({1{1'b0}}),
    .MSS_RESET_N(NSYSRESET),
    .ADCDirectInput_0(adc_direct_dig),
    .VAREF0(),
    .CLKA(SYSCLK),
    .Bit_Clk(BIT_CLK),
    .Frame_Clk(FRAME_CLK),

       // Outputs
    .UART_0_TXD( ),
    .SDD_0( ),
    .DAC_out( ),
    .Serial_Data_out( ),
    .En_out( ),
    .nDAC_out( ),
    .Load_SR( ),
    .P2S_bitclk_rising( ),
    .P2S_bitclk_falling( ),
    .En_50K_pulse( ),
    .clk_24MHz_out( ),
    .frame_clk_out( ),
    .bit_clk_out( ),
    .adc_data_to_mod( ),
    .En_400K_pulse( ),
    .adc_data_ready( ),
    .clk_25MHz_out( )

    // Inouts

);

endmodule

