Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Fri Dec 16 20:26:40 2011


Design: Top_Level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                9.222
Frequency (MHz):            108.436
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.513
Max Clock-To-Out (ns):      5.777

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.383
External Hold (ns):         1.283
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               SimpleWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      5.862
Max Clock-To-Out (ns):      9.350

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        APB_MEM_CTRL_0/current_state[1]:CLK
  To:                          APB_MEM_CTRL_0/current_state[2]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.733
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        APB_MEM_CTRL_0/current_state[7]:CLK
  To:                          APB_MEM_CTRL_0/current_state[8]:D
  Delay (ns):                  0.453
  Slack (ns):
  Arrival (ns):                0.790
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        APB_MEM_CTRL_0/PWDATA_1[14]/U1:CLK
  To:                          APB_MEM_CTRL_0/PWDATA_1[14]/U1:D
  Delay (ns):                  0.789
  Slack (ns):
  Arrival (ns):                1.150
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        APB_MEM_CTRL_0/PWDATA_1[6]/U1:CLK
  To:                          APB_MEM_CTRL_0/PWDATA_1[6]/U1:D
  Delay (ns):                  0.789
  Slack (ns):
  Arrival (ns):                1.150
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        APB_MEM_CTRL_0/PWDATA_1[9]/U1:CLK
  To:                          APB_MEM_CTRL_0/PWDATA_1[9]/U1:D
  Delay (ns):                  0.789
  Slack (ns):
  Arrival (ns):                1.150
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: APB_MEM_CTRL_0/current_state[1]:CLK
  To: APB_MEM_CTRL_0/current_state[2]:D
  data arrival time                              0.733
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: SimpleWire_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.336          net: FAB_CLK
  0.336                        APB_MEM_CTRL_0/current_state[1]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.584                        APB_MEM_CTRL_0/current_state[1]:Q (r)
               +     0.149          net: APB_MEM_CTRL_0/current_state[1]
  0.733                        APB_MEM_CTRL_0/current_state[2]:D (r)
                                    
  0.733                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: SimpleWire_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.354          net: FAB_CLK
  N/C                          APB_MEM_CTRL_0/current_state[2]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          APB_MEM_CTRL_0/current_state[2]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        APB_MEM_CTRL_0/busy/U1:CLK
  To:                          busy
  Delay (ns):                  2.177
  Slack (ns):
  Arrival (ns):                2.513
  Required (ns):
  Clock to Out (ns):           2.513

Path 2
  From:                        APB_MEM_CTRL_0/cur_state[2]:CLK
  To:                          cur_state[2]
  Delay (ns):                  2.177
  Slack (ns):
  Arrival (ns):                2.513
  Required (ns):
  Clock to Out (ns):           2.513

Path 3
  From:                        APB_MEM_CTRL_0/cur_state[1]:CLK
  To:                          cur_state[1]
  Delay (ns):                  2.188
  Slack (ns):
  Arrival (ns):                2.524
  Required (ns):
  Clock to Out (ns):           2.524

Path 4
  From:                        APB_MEM_CTRL_0/cur_state[3]:CLK
  To:                          cur_state[3]
  Delay (ns):                  2.198
  Slack (ns):
  Arrival (ns):                2.525
  Required (ns):
  Clock to Out (ns):           2.525

Path 5
  From:                        APB_MEM_CTRL_0/dac_out_enable/U1:CLK
  To:                          dac_out_enable
  Delay (ns):                  2.297
  Slack (ns):
  Arrival (ns):                2.620
  Required (ns):
  Clock to Out (ns):           2.620


Expanded Path 1
  From: APB_MEM_CTRL_0/busy/U1:CLK
  To: busy
  data arrival time                              2.513
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: SimpleWire_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.336          net: FAB_CLK
  0.336                        APB_MEM_CTRL_0/busy/U1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.584                        APB_MEM_CTRL_0/busy/U1:Q (r)
               +     0.534          net: busy_c
  1.118                        busy_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  1.397                        busy_pad/U0/U1:DOUT (r)
               +     0.000          net: busy_pad/U0/NET1
  1.397                        busy_pad/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  2.513                        busy_pad/U0/U0:PAD (r)
               +     0.000          net: busy
  2.513                        busy (r)
                                    
  2.513                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
                                    
  N/C                          busy (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin SimpleWire_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          SimpleWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   1.289
  External Hold (ns):          1.283


Expanded Path 1
  From: MSS_RESET_N
  To: SimpleWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        SimpleWire_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        SimpleWire_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: SimpleWire_0/MSS_RESET_0_MSS_RESET_N_Y
  0.276                        SimpleWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.270          net: SimpleWire_0/GLA0
  N/C                          SimpleWire_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.289          Library hold time: ADLIB:MSS_APB_IP
  N/C                          SimpleWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain SimpleWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          FAB_CLK_80MHz
  Delay (ns):                  5.862
  Slack (ns):
  Arrival (ns):                5.862
  Required (ns):
  Clock to Out (ns):           5.862


Expanded Path 1
  From: SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: FAB_CLK_80MHz
  data arrival time                              5.862
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        SimpleWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  0.000                        SimpleWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: SimpleWire_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     4.035          cell: ADLIB:MSS_CCC_IP
  4.035                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: SimpleWire_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        SimpleWire_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.432          net: FAB_CLK
  4.467                        FAB_CLK_80MHz_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  4.746                        FAB_CLK_80MHz_pad/U0/U1:DOUT (r)
               +     0.000          net: FAB_CLK_80MHz_pad/U0/NET1
  4.746                        FAB_CLK_80MHz_pad/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  5.862                        FAB_CLK_80MHz_pad/U0/U0:PAD (r)
               +     0.000          net: FAB_CLK_80MHz
  5.862                        FAB_CLK_80MHz (r)
                                    
  5.862                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          SimpleWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  N/C                          SimpleWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          FAB_CLK_80MHz (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

