library verilog;
use verilog.vl_types.all;
entity synBusSatRnd_Z13 is
    generic(
        inp_width       : integer := 29;
        out_width       : integer := 24;
        infrac          : integer := 19;
        outfrac         : integer := 16;
        round           : integer := 1;
        sat             : integer := 1;
        datatype        : string  := "SS"
    );
    port(
        tmpOutPre       : in     vl_logic_vector(28 downto 15);
        N_30            : out    vl_logic;
        N_32            : out    vl_logic;
        N_34            : out    vl_logic;
        N_36_i_0        : out    vl_logic;
        N_453           : out    vl_logic;
        N_455           : out    vl_logic;
        N_456           : out    vl_logic;
        N_451           : out    vl_logic;
        N_457_i         : out    vl_logic;
        N_473           : out    vl_logic;
        N_481           : out    vl_logic;
        N_454_i         : out    vl_logic;
        N_479           : out    vl_logic;
        N_460           : out    vl_logic;
        N_452           : out    vl_logic
    );
end synBusSatRnd_Z13;
