library verilog;
use verilog.vl_types.all;
entity M3_PROC_ADC_DAC is
    port(
        M2F_RESET_N     : out    vl_logic;
        MSSPSEL         : out    vl_logic;
        MSSPENABLE      : out    vl_logic;
        MSSPWRITE       : out    vl_logic;
        MSSPREADY       : in     vl_logic;
        MSSPSLVERR      : in     vl_logic;
        FABPSEL         : in     vl_logic;
        FABPENABLE      : in     vl_logic;
        FABPWRITE       : in     vl_logic;
        FABPREADY       : out    vl_logic;
        FABPSLVERR      : out    vl_logic;
        CLKA            : in     vl_logic;
        FAB_CLK_40MHz   : out    vl_logic;
        FABSDD0D        : in     vl_logic;
        FABSDD0CLK      : in     vl_logic;
        GLC             : out    vl_logic;
        MSSPADDR        : out    vl_logic_vector(19 downto 0);
        MSSPRDATA       : in     vl_logic_vector(31 downto 0);
        MSSPWDATA       : out    vl_logic_vector(31 downto 0);
        FABPADDR        : in     vl_logic_vector(31 downto 0);
        FABPRDATA       : out    vl_logic_vector(31 downto 0);
        FABPWDATA       : in     vl_logic_vector(31 downto 0);
        UART_0_TXD      : out    vl_logic;
        UART_0_RXD      : in     vl_logic;
        SDD_0           : out    vl_logic;
        ADCDirectInput_0: in     vl_logic;
        VAREF0          : in     vl_logic;
        MSS_RESET_N     : in     vl_logic
    );
end M3_PROC_ADC_DAC;
