library verilog;
use verilog.vl_types.all;
entity synDelayWithEnable_1s_1s_1s_6 is
    generic(
        bitwidth        : integer := 1;
        delaylength     : integer := 1
    );
    port(
        Quadratic_Comp  : in     vl_logic_vector(14 downto 0);
        outBuf0         : in     vl_logic_vector(0 downto 0);
        outBuf1         : out    vl_logic_vector(0 downto 0);
        N_57            : out    vl_logic;
        N_56            : out    vl_logic;
        N_62            : out    vl_logic;
        N_65            : out    vl_logic;
        N_68            : out    vl_logic;
        N_71            : out    vl_logic;
        N_77            : out    vl_logic;
        N_80            : out    vl_logic;
        N_83            : out    vl_logic;
        N_86            : out    vl_logic;
        GlobalReset     : in     vl_logic;
        N_9             : in     vl_logic;
        N_74            : out    vl_logic;
        N_98            : out    vl_logic;
        N_95            : out    vl_logic;
        N_92            : out    vl_logic;
        N_89            : out    vl_logic;
        clk             : in     vl_logic
    );
end synDelayWithEnable_1s_1s_1s_6;
