library verilog;
use verilog.vl_types.all;
entity P2S_Frameclk_Edges is
    port(
        P2S_N_bitclk_rising_1_301: in     vl_logic_vector(0 downto 0);
        N_9_0           : out    vl_logic_vector(0 downto 0);
        N_9             : out    vl_logic_vector(0 downto 0);
        P2S_N_bitclk_falling_1_300: in     vl_logic_vector(0 downto 0);
        N_30            : out    vl_logic_vector(0 downto 0);
        N_30_i          : out    vl_logic_vector(0 downto 0);
        GlobalEnable1   : in     vl_logic;
        Frame_Clk       : in     vl_logic;
        clk             : in     vl_logic;
        GlobalReset     : in     vl_logic;
        un1_N_2         : out    vl_logic
    );
end P2S_Frameclk_Edges;
