library verilog;
use verilog.vl_types.all;
entity synDelayWithEnable_1s_28s_1s_3 is
    generic(
        bitwidth        : integer := 28;
        delaylength     : integer := 1
    );
    port(
        N_5             : out    vl_logic_vector(25 downto 0);
        N_3             : in     vl_logic_vector(25 downto 1);
        N_4             : in     vl_logic_vector(5 downto 5);
        en              : in     vl_logic;
        GlobalReset     : in     vl_logic;
        clk             : in     vl_logic
    );
end synDelayWithEnable_1s_28s_1s_3;
