library verilog;
use verilog.vl_types.all;
entity synDelayWithEnable_1s_12s_1s is
    generic(
        bitwidth        : integer := 12;
        delaylength     : integer := 1
    );
    port(
        N_44            : out    vl_logic_vector(11 downto 0);
        ADC             : in     vl_logic_vector(11 downto 0);
        enab            : in     vl_logic;
        GlobalReset     : in     vl_logic;
        clk             : in     vl_logic
    );
end synDelayWithEnable_1s_12s_1s;
