library verilog;
use verilog.vl_types.all;
entity synDelayWithEnable_1s_1s_1s_10 is
    generic(
        bitwidth        : integer := 1;
        delaylength     : integer := 1
    );
    port(
        P2S_N_bitclk_falling_1_300: out    vl_logic_vector(0 downto 0);
        N_1             : out    vl_logic_vector(0 downto 0);
        Bit_Clk         : in     vl_logic;
        GlobalReset     : in     vl_logic;
        GlobalEnable1   : in     vl_logic;
        clk             : in     vl_logic
    );
end synDelayWithEnable_1s_1s_1s_10;
