library verilog;
use verilog.vl_types.all;
entity APB_MEM_CTRL is
    generic(
        AD0POLL_DATA_OFFSET: integer := 4096;
        DAC_DATA_OFFSET : integer := 1280;
        IDLE            : integer := 0;
        FIC_UPPER_ACCESS_0: integer := 1;
        FIC_UPPER_ACCESS_1: integer := 2;
        FIC_UPPER_ACCESS_2: integer := 3;
        FIC_READPOLL_0  : integer := 4;
        FIC_READPOLL_1  : integer := 5;
        FIC_READPOLL_2  : integer := 6;
        FIC_WRITE_0     : integer := 7;
        FIC_WRITE_1     : integer := 8;
        FIC_WRITE_2     : integer := 9
    );
    port(
        PRESETn         : in     vl_logic;
        PCLK            : in     vl_logic;
        PREADY          : in     vl_logic;
        PSLVERR         : in     vl_logic;
        PRDATA          : in     vl_logic_vector(31 downto 0);
        PENABLE         : out    vl_logic;
        PSEL            : out    vl_logic;
        PWRITE          : out    vl_logic;
        PADDR           : out    vl_logic_vector(23 downto 0);
        PWDATA          : out    vl_logic_vector(31 downto 0);
        busy            : out    vl_logic;
        dac_out_enable  : out    vl_logic;
        cur_state       : out    vl_logic_vector(3 downto 0)
    );
end APB_MEM_CTRL;
