library verilog;
use verilog.vl_types.all;
entity Sigma_Delta_Modulator_Clkdiv_and_RTZ_Modulator_counter_Register is
    port(
        N_5             : out    vl_logic_vector(3 downto 0);
        clk_div         : in     vl_logic_vector(3 downto 0);
        N_2             : in     vl_logic_vector(0 downto 0);
        N_7             : in     vl_logic_vector(3 downto 1);
        GlobalEnable1   : in     vl_logic;
        GlobalReset     : in     vl_logic;
        clk             : in     vl_logic
    );
end Sigma_Delta_Modulator_Clkdiv_and_RTZ_Modulator_counter_Register;
