library verilog;
use verilog.vl_types.all;
entity singleDelayWithEnableGeneric_24s_2 is
    generic(
        bitwidth        : integer := 24
    );
    port(
        Ser_Dat_out     : out    vl_logic_vector(0 downto 0);
        N_2             : in     vl_logic_vector(23 downto 0);
        N_8             : out    vl_logic_vector(22 downto 0);
        clk             : in     vl_logic;
        GlobalReset     : in     vl_logic;
        enab            : in     vl_logic
    );
end singleDelayWithEnableGeneric_24s_2;
