library verilog;
use verilog.vl_types.all;
entity Top_Level is
    port(
        UART_0_TXD      : out    vl_logic;
        UART_0_RXD      : in     vl_logic;
        MSS_RESET_N     : in     vl_logic;
        SDD_0           : out    vl_logic;
        ADCDirectInput_0: in     vl_logic;
        VAREF0          : in     vl_logic;
        busy            : out    vl_logic;
        dac_out_enable  : out    vl_logic;
        FAB_CLK_80MHz   : out    vl_logic;
        cur_state       : out    vl_logic_vector(3 downto 0)
    );
end Top_Level;
