library verilog;
use verilog.vl_types.all;
entity singleDelayWithEnableGeneric_1s_7 is
    generic(
        bitwidth        : integer := 1
    );
    port(
        outBuf1         : in     vl_logic_vector(0 downto 0);
        outBuf0         : in     vl_logic_vector(0 downto 0);
        N_8_10          : out    vl_logic;
        N_8_9           : out    vl_logic;
        N_8_8           : out    vl_logic;
        N_8_7           : out    vl_logic;
        N_8_4           : out    vl_logic;
        N_8_2           : out    vl_logic;
        N_8_1           : out    vl_logic;
        N_8_0           : out    vl_logic;
        N_8_6           : out    vl_logic;
        N_8_11          : out    vl_logic;
        N_8_12          : out    vl_logic;
        N_8_13          : out    vl_logic;
        N_8_14          : out    vl_logic;
        Out1_0_0_3      : out    vl_logic;
        Out1_0_0_5      : out    vl_logic;
        Cubic_Comp      : in     vl_logic_vector(14 downto 0);
        clk             : in     vl_logic;
        N_9             : in     vl_logic;
        GlobalReset     : in     vl_logic;
        N_73            : out    vl_logic;
        N_67            : out    vl_logic;
        N_80            : in     vl_logic;
        N_77            : in     vl_logic;
        N_68            : in     vl_logic;
        N_62            : in     vl_logic;
        N_56            : in     vl_logic;
        N_95            : in     vl_logic;
        N_92            : in     vl_logic;
        N_89            : in     vl_logic;
        N_98            : in     vl_logic;
        N_74            : in     vl_logic;
        N_57            : in     vl_logic;
        N_65            : in     vl_logic;
        N_71            : in     vl_logic;
        N_83            : in     vl_logic;
        N_86            : in     vl_logic
    );
end singleDelayWithEnableGeneric_1s_7;
