# (OPEN DESIGN)

open_design "C:/A2F_AC375_DF/A2F500/verilog/ADC_DAC_SimpleWire/designer/impl1/Top_Level.adb"
export -format "FDB" {C:/A2F_AC375_DF/A2F500/verilog/ADC_DAC_SimpleWire/designer/impl1/Top_Level.fdb}

save_design "C:/A2F_AC375_DF/A2F500/verilog/ADC_DAC_SimpleWire/designer/impl1/Top_Level.adb"

