library verilog;
use verilog.vl_types.all;
entity P2S_Bitclk_Edges_Register2_5 is
    port(
        P2S_N_bitclk_falling_1_300: out    vl_logic_vector(0 downto 0);
        N_1             : out    vl_logic_vector(0 downto 0);
        Bit_Clk         : in     vl_logic;
        GlobalReset     : in     vl_logic;
        GlobalEnable1   : in     vl_logic;
        clk             : in     vl_logic
    );
end P2S_Bitclk_Edges_Register2_5;
