`timescale 1 ns/100 ps
/*-------------------------------------------------------------------------------
-- Title      : 4x20 memory block
-------------------------------------------------------------------------------
-- File       : reg8x20.v
-- Author     : Mir Ali
-- Company    : Microsemi Corporation
-- Device     : SmartFusion 
-- Standard   : Verilog
-------------------------------------------------------------------------------
-- Description: 4x20 memory block
-------------------------------------------------------------------------------
-- Copyright (c) 2011   Microsemi Corporation
--                      All rights reserved.
-------------------------------------------------------------------------------
-- Revisions  : V1.0 
-------------------------------------------------------------------------------*/

// 
`timescale  1 ns /  1 ps

module reg4x20( clk, nreset, wr_en, rd_en, addr, data_in, data_out,
Direct_Out, Quadratic_Comp, Cubic_Comp, Clk_Div, RTZ_Mode, SD_Mod ); 
  
  
//Inputs Declarations 
input  clk;             //Clock
input  nreset;          //active low reset  
input  wr_en;           //Write Enable 
input  rd_en;           //Read Enable 
input  [1:0] addr;      //Address Width 
input  [19:0] data_in;   //Data Input 
  
//output Declarations 
output [19:0]  data_out; 
output reg [19:0]  Direct_Out;  //Data Output
output reg [14:0]  Quadratic_Comp, Cubic_Comp;
output reg [3:0]    Clk_Div;
output reg [1:0]    RTZ_Mode, SD_Mod;

reg [19:0] temp_data; //hold data to add delay
  
//reg Declarations 
reg [19:0] mem [3:0];    //Memory 
reg [19:0] data_out;     //Data Output 

//Generation Writing data into memory 
always @(posedge clk, negedge nreset) 
    begin : WRITE_GEN 
        if(nreset == 1'b0)
            begin
                mem[addr] <= 20'h00000;
            end
        else if(wr_en)
            begin  
               	mem[addr] <= data_in;
            end
  	 
end
  
//Generation of data_out 
always @(posedge clk, negedge nreset) 
    begin : READ_GEN 
        if(nreset == 1'b0)
            begin
                temp_data <= 20'h00000;
            end
        else if(rd_en)
            begin  
                temp_data <= mem[addr]; 
end           end 


always @(posedge clk) 
begin
    data_out            <=  temp_data; 	 
    Direct_Out          <=  mem[0];
    Quadratic_Comp      <=  mem[1];
    Cubic_Comp          <=  mem[2];
    SD_Mod              <=  mem[3][1:0];
    RTZ_Mode            <=  mem[3][3:2];
    Clk_Div             <=  mem[3][7:4];
end
  
endmodule