library verilog;
use verilog.vl_types.all;
entity Sigma_Delta_Modulator_Clkdiv_and_RTZ_Modulator is
    port(
        tmpOut          : in     vl_logic_vector(0 downto 0);
        SD_mod          : out    vl_logic_vector(0 downto 0);
        N_16            : out    vl_logic_vector(0 downto 0);
        N_8_i_0         : out    vl_logic_vector(0 downto 0);
        clk_div         : in     vl_logic_vector(3 downto 0);
        RTZ_Mode        : in     vl_logic_vector(1 downto 0);
        N_9             : out    vl_logic;
        un1_rst_1       : in     vl_logic;
        Reset           : in     vl_logic;
        GlobalEnable1   : in     vl_logic;
        GlobalReset     : in     vl_logic;
        clk             : in     vl_logic
    );
end Sigma_Delta_Modulator_Clkdiv_and_RTZ_Modulator;
