library verilog;
use verilog.vl_types.all;
entity singleDelayWithEnableGeneric_20s_1 is
    generic(
        bitwidth        : integer := 20
    );
    port(
        SUM2_i          : in     vl_logic_vector(6 downto 6);
        N_5_i_0         : in     vl_logic_vector(7 downto 7);
        N_4             : in     vl_logic_vector(9 downto 9);
        N_15            : in     vl_logic_vector(0 downto 0);
        N_9_7           : in     vl_logic;
        N_9_0           : in     vl_logic;
        N_9_8           : in     vl_logic;
        N_3             : out    vl_logic_vector(9 downto 0);
        N_13            : out    vl_logic_vector(3 downto 1);
        N_21            : out    vl_logic_vector(6 downto 0);
        N_5             : in     vl_logic_vector(6 downto 0);
        N_16            : in     vl_logic_vector(3 downto 2);
        clk             : in     vl_logic;
        ADD_28x28_fast_I253_Y_0_0: in     vl_logic;
        N705            : in     vl_logic;
        N_405           : out    vl_logic;
        N_401           : in     vl_logic;
        ADD_28x28_fast_I262_Y_0_0: in     vl_logic;
        N679_i          : in     vl_logic;
        N_2_0           : in     vl_logic;
        ADD_28x28_fast_I260_Y_0_0: in     vl_logic;
        N684            : in     vl_logic;
        ADD_28x28_fast_I258_Y_0_0: in     vl_logic;
        N_73            : in     vl_logic;
        ADD_28x28_fast_I257_Y_0_0: in     vl_logic;
        N693_i          : in     vl_logic;
        ADD_28x28_fast_I256_Y_0_0: in     vl_logic;
        N696            : in     vl_logic;
        ADD_28x28_fast_I255_Y_0_0: in     vl_logic;
        N_41            : in     vl_logic;
        rst_1           : in     vl_logic;
        ADD_28x28_fast_I254_Y_0_0: in     vl_logic;
        N_121_i_0       : in     vl_logic;
        GlobalReset     : in     vl_logic;
        un1_rst_1       : in     vl_logic;
        N_476           : out    vl_logic;
        N_474           : out    vl_logic;
        N_470           : out    vl_logic;
        N_468           : out    vl_logic;
        N_464           : out    vl_logic;
        N_452           : out    vl_logic;
        N_440           : out    vl_logic;
        N_406           : out    vl_logic;
        N_292           : out    vl_logic;
        N_272           : out    vl_logic;
        N_197           : in     vl_logic;
        N_190           : in     vl_logic;
        N_202           : out    vl_logic;
        N_196           : out    vl_logic;
        tmpOutPre_2_10  : in     vl_logic;
        tmpOutPre_2_18_0_tz: in     vl_logic;
        N_282           : out    vl_logic;
        N_444           : out    vl_logic;
        N_472           : out    vl_logic;
        N_193           : in     vl_logic;
        N_195_i         : out    vl_logic;
        N_439           : out    vl_logic;
        N_451           : out    vl_logic;
        N_463           : out    vl_logic;
        N_475           : out    vl_logic;
        N_425           : out    vl_logic;
        N_457           : in     vl_logic;
        tmpOutPre_2_44_4_0: in     vl_logic;
        N_201           : out    vl_logic;
        N_260           : in     vl_logic;
        N_258           : in     vl_logic;
        N_271           : out    vl_logic;
        N_185           : in     vl_logic;
        N_187           : out    vl_logic;
        N_270           : in     vl_logic;
        N_281           : out    vl_logic;
        N_280           : in     vl_logic;
        N_287           : in     vl_logic;
        N_291           : out    vl_logic;
        N_407           : in     vl_logic;
        N_402_i         : in     vl_logic;
        N_411           : out    vl_logic;
        N_409           : out    vl_logic;
        N_408           : in     vl_logic;
        N_418           : in     vl_logic;
        N_429           : in     vl_logic;
        N_441           : in     vl_logic;
        N_430           : in     vl_logic;
        N_465           : in     vl_logic;
        N_454           : in     vl_logic;
        N_458           : in     vl_logic;
        N_417_i         : in     vl_logic
    );
end singleDelayWithEnableGeneric_20s_1;
