library verilog;
use verilog.vl_types.all;
entity synDelayWithEnable_1s_2s_1s is
    generic(
        bitwidth        : integer := 2;
        delaylength     : integer := 1
    );
    port(
        N_6             : in     vl_logic_vector(15 downto 15);
        N_3             : out    vl_logic_vector(1 downto 1);
        N_10_7          : in     vl_logic;
        N_10_0          : in     vl_logic;
        N_10_5          : in     vl_logic;
        N_7_2           : in     vl_logic;
        N_7_0           : in     vl_logic;
        SD_Mod_Select   : in     vl_logic_vector(1 downto 1);
        N_233           : out    vl_logic;
        N_214           : in     vl_logic;
        N_170           : out    vl_logic;
        N_168           : in     vl_logic;
        N_161           : in     vl_logic;
        N_210           : out    vl_logic;
        N_208           : in     vl_logic;
        N_201           : in     vl_logic;
        N_205           : in     vl_logic;
        N_226           : out    vl_logic;
        tmpOutPre_295_0_0: in     vl_logic;
        N_176           : out    vl_logic;
        N_172           : in     vl_logic;
        N_165_1         : in     vl_logic;
        N_268           : out    vl_logic;
        N_266           : in     vl_logic;
        N_256           : out    vl_logic;
        N_259           : in     vl_logic;
        N_260           : out    vl_logic;
        N_258           : in     vl_logic;
        N_251           : in     vl_logic;
        N_252           : out    vl_logic;
        N_250           : in     vl_logic;
        N_243           : in     vl_logic;
        N_244           : out    vl_logic;
        N_242           : in     vl_logic;
        N_235           : in     vl_logic;
        N_220           : out    vl_logic;
        N_209           : in     vl_logic;
        N_219           : out    vl_logic;
        N_211           : out    vl_logic;
        N_171           : out    vl_logic;
        N_227           : out    vl_logic;
        N_215           : in     vl_logic;
        N_222           : in     vl_logic;
        N_177           : out    vl_logic;
        N_221           : out    vl_logic;
        N_245           : out    vl_logic;
        N_253           : out    vl_logic;
        N_261           : out    vl_logic;
        N_269           : out    vl_logic;
        N_277           : out    vl_logic;
        tmpOutPre_415_0_0: in     vl_logic;
        N_267           : in     vl_logic;
        N_9             : in     vl_logic;
        rst_1           : in     vl_logic;
        N_276           : out    vl_logic;
        GlobalReset     : in     vl_logic;
        N_89            : out    vl_logic;
        Direct_Bitstream: in     vl_logic;
        N_213           : out    vl_logic;
        N297            : in     vl_logic;
        ADD_13x13_fast_I102_Y_0_0: in     vl_logic;
        un1_rst_1       : in     vl_logic;
        clk             : in     vl_logic
    );
end synDelayWithEnable_1s_2s_1s;
