library verilog;
use verilog.vl_types.all;
entity singleDelayWithEnableGeneric_21s is
    generic(
        bitwidth        : integer := 21
    );
    port(
        tmpOutPre       : in     vl_logic_vector(20 downto 8);
        N_8             : in     vl_logic_vector(2 downto 0);
        N_10            : out    vl_logic_vector(20 downto 5);
        clk             : in     vl_logic;
        GlobalReset     : in     vl_logic;
        GlobalEnable1   : in     vl_logic
    );
end singleDelayWithEnableGeneric_21s;
