library verilog;
use verilog.vl_types.all;
entity Decimate_by_ten_IIR_2nd_order is
    port(
        N_44            : in     vl_logic_vector(11 downto 0);
        IIR_filter_out_i: out    vl_logic_vector(16 downto 16);
        IIR_filter_out_0: out    vl_logic;
        IIR_filter_out_22: out    vl_logic;
        IIR_filter_out_23: out    vl_logic;
        IIR_filter_out_3: out    vl_logic;
        IIR_filter_out_14: out    vl_logic;
        IIR_filter_out_15: out    vl_logic;
        IIR_filter_out_5: out    vl_logic;
        IIR_filter_out_2: out    vl_logic;
        IIR_filter_out_13: out    vl_logic;
        IIR_filter_out_11: out    vl_logic;
        IIR_filter_out_9: out    vl_logic;
        IIR_filter_out_7: out    vl_logic;
        IIR_filter_out_20: out    vl_logic;
        IIR_filter_out_19: out    vl_logic;
        IIR_filter_out_18: out    vl_logic;
        IIR_filter_out_17: out    vl_logic;
        IIR_filter_out_1: out    vl_logic;
        IIR_filter_out_24: out    vl_logic;
        GlobalReset     : in     vl_logic;
        en              : in     vl_logic;
        N522_i          : out    vl_logic;
        N_141           : out    vl_logic;
        N_140           : out    vl_logic;
        N512_0          : out    vl_logic;
        N352            : out    vl_logic;
        N492            : out    vl_logic;
        N502            : out    vl_logic;
        N340_0          : out    vl_logic;
        N348_0          : out    vl_logic;
        N516_i          : out    vl_logic;
        N490            : out    vl_logic;
        N344_0          : out    vl_logic;
        N370            : out    vl_logic;
        N336            : out    vl_logic;
        N500            : out    vl_logic;
        clk             : in     vl_logic
    );
end Decimate_by_ten_IIR_2nd_order;
