Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Fri Dec 16 18:54:30 2011


Design: Top_Level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                7.971
Frequency (MHz):            125.455
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.383
External Hold (ns):         1.283
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                14.880
Frequency (MHz):            67.204
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      3.416
Max Clock-To-Out (ns):      8.355

Clock Domain:               mss_ccc_glc
Period (ns):                29.501
Frequency (MHz):            33.897
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.832
Max Clock-To-Out (ns):      11.229

Clock Domain:               ImprovedWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      3.386
Max Clock-To-Out (ns):      11.380

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]
  Delay (ns):                  3.374
  Slack (ns):
  Arrival (ns):                3.374
  Required (ns):
  Hold (ns):                   1.308

Path 2
  From:                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[5]
  Delay (ns):                  3.446
  Slack (ns):
  Arrival (ns):                3.446
  Required (ns):
  Hold (ns):                   1.330

Path 3
  From:                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[14]
  Delay (ns):                  3.546
  Slack (ns):
  Arrival (ns):                3.546
  Required (ns):
  Hold (ns):                   1.310

Path 4
  From:                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[18]
  Delay (ns):                  3.731
  Slack (ns):
  Arrival (ns):                3.731
  Required (ns):
  Hold (ns):                   1.324

Path 5
  From:                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  3.740
  Slack (ns):
  Arrival (ns):                3.740
  Required (ns):
  Hold (ns):                   1.330


Expanded Path 1
  From: ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB
  To: ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]
  data arrival time                              3.374
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     1.320          cell: ADLIB:MSS_APB_IP
  1.320                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[9] (r)
               +     0.059          net: ImprovedWire_0/MSS_ADLIB_INST/MSSPADDR[9]INT_NET
  1.379                        ImprovedWire_0/MSS_ADLIB_INST/U_33:PIN1INT (r)
               +     0.041          cell: ADLIB:MSS_IF
  1.420                        ImprovedWire_0/MSS_ADLIB_INST/U_33:PIN1 (r)
               +     0.507          net: M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[9]
  1.927                        CoreAPB3_Slave_Side_0/CoreAPB3_Slave_Side_0/iPSELS[0]:C (r)
               +     0.291          cell: ADLIB:OR3A
  2.218                        CoreAPB3_Slave_Side_0/CoreAPB3_Slave_Side_0/iPSELS[0]:Y (r)
               +     0.264          net: CoreAPB3_Slave_Side_0_APBmslave0_PSELx
  2.482                        CoreAPB3_Slave_Side_0/CoreAPB3_Slave_Side_0/u_mux_p_to_b3/PRDATA_3:B (r)
               +     0.223          cell: ADLIB:NOR2A
  2.705                        CoreAPB3_Slave_Side_0/CoreAPB3_Slave_Side_0/u_mux_p_to_b3/PRDATA_3:Y (f)
               +     0.341          net: PRDATA_3
  3.046                        ImprovedWire_0/MSS_ADLIB_INST/U_37:PIN6 (f)
               +     0.083          cell: ADLIB:MSS_IF
  3.129                        ImprovedWire_0/MSS_ADLIB_INST/U_37:PIN6INT (f)
               +     0.245          net: ImprovedWire_0/MSS_ADLIB_INST/MSSPRDATA[3]INT_NET
  3.374                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3] (f)
                                    
  3.374                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     1.308          Library hold time: ADLIB:MSS_APB_IP
  N/C                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin ImprovedWire_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   1.289
  External Hold (ns):          1.283


Expanded Path 1
  From: MSS_RESET_N
  To: ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        ImprovedWire_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        ImprovedWire_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: ImprovedWire_0/MSS_RESET_0_MSS_RESET_N_Y
  0.276                        ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.270          net: ImprovedWire_0/GLA0
  N/C                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.289          Library hold time: ADLIB:MSS_APB_IP
  N/C                          ImprovedWire_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        APB_MEM_CTRL_0/current_state[4]:CLK
  To:                          APB_MEM_CTRL_0/current_state[5]:D
  Delay (ns):                  0.429
  Slack (ns):
  Arrival (ns):                0.761
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        APB_MEM_CTRL_0/delay_start[31]:CLK
  To:                          APB_MEM_CTRL_0/delay_start[31]:D
  Delay (ns):                  0.688
  Slack (ns):
  Arrival (ns):                1.046
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        APB_MEM_CTRL_0/delay_start[10]:CLK
  To:                          APB_MEM_CTRL_0/delay_start[10]:D
  Delay (ns):                  0.718
  Slack (ns):
  Arrival (ns):                1.076
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        APB_MEM_CTRL_0/delay_start[4]:CLK
  To:                          APB_MEM_CTRL_0/delay_start[4]:D
  Delay (ns):                  0.718
  Slack (ns):
  Arrival (ns):                1.072
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        APB_MEM_CTRL_0/delay_start[12]:CLK
  To:                          APB_MEM_CTRL_0/delay_start[12]:D
  Delay (ns):                  0.718
  Slack (ns):
  Arrival (ns):                1.076
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: APB_MEM_CTRL_0/current_state[4]:CLK
  To: APB_MEM_CTRL_0/current_state[5]:D
  data arrival time                              0.761
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.332          net: FAB_CLK
  0.332                        APB_MEM_CTRL_0/current_state[4]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.580                        APB_MEM_CTRL_0/current_state[4]:Q (r)
               +     0.181          net: APB_MEM_CTRL_0/current_state[4]
  0.761                        APB_MEM_CTRL_0/current_state[5]:D (r)
                                    
  0.761                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.349          net: FAB_CLK
  N/C                          APB_MEM_CTRL_0/current_state[5]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          APB_MEM_CTRL_0/current_state[5]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        APB_MEM_CTRL_0/data[9]/U1:CLK
  To:                          adc_data_to_mod[9]
  Delay (ns):                  3.086
  Slack (ns):
  Arrival (ns):                3.416
  Required (ns):
  Clock to Out (ns):           3.416

Path 2
  From:                        APB_MEM_CTRL_0/data[0]/U1:CLK
  To:                          adc_data_to_mod[0]
  Delay (ns):                  3.122
  Slack (ns):
  Arrival (ns):                3.480
  Required (ns):
  Clock to Out (ns):           3.480

Path 3
  From:                        APB_MEM_CTRL_0/data[11]/U1:CLK
  To:                          adc_data_to_mod[11]
  Delay (ns):                  3.186
  Slack (ns):
  Arrival (ns):                3.519
  Required (ns):
  Clock to Out (ns):           3.519

Path 4
  From:                        APB_MEM_CTRL_0/dataout_enable/U1:CLK
  To:                          adc_data_ready
  Delay (ns):                  3.219
  Slack (ns):
  Arrival (ns):                3.549
  Required (ns):
  Clock to Out (ns):           3.549

Path 5
  From:                        APB_MEM_CTRL_0/data[1]/U1:CLK
  To:                          adc_data_to_mod[1]
  Delay (ns):                  3.279
  Slack (ns):
  Arrival (ns):                3.611
  Required (ns):
  Clock to Out (ns):           3.611


Expanded Path 1
  From: APB_MEM_CTRL_0/data[9]/U1:CLK
  To: adc_data_to_mod[9]
  data arrival time                              3.416
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.330          net: FAB_CLK
  0.330                        APB_MEM_CTRL_0/data[9]/U1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.578                        APB_MEM_CTRL_0/data[9]/U1:Q (r)
               +     1.443          net: adc_data_to_mod_c[9]
  2.021                        adc_data_to_mod_pad[9]/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  2.300                        adc_data_to_mod_pad[9]/U0/U1:DOUT (r)
               +     0.000          net: adc_data_to_mod_pad[9]/U0/NET1
  2.300                        adc_data_to_mod_pad[9]/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  3.416                        adc_data_to_mod_pad[9]/U0/U0:PAD (r)
               +     0.000          net: adc_data_to_mod[9]
  3.416                        adc_data_to_mod[9] (r)
                                    
  3.416                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
                                    
  N/C                          adc_data_to_mod[9] (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glc

SET Register to Register

Path 1
  From:                        reg_apb_wrp_0/reg4x20_inst/temp_data[16]/U1:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/data_out[16]:D
  Delay (ns):                  0.429
  Slack (ns):
  Arrival (ns):                0.763
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        reg_apb_wrp_0/reg4x20_inst/temp_data[9]/U1:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/data_out[9]:D
  Delay (ns):                  0.429
  Slack (ns):
  Arrival (ns):                0.766
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        reg_apb_wrp_0/reg4x20_inst/temp_data[7]/U1:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/data_out[7]:D
  Delay (ns):                  0.429
  Slack (ns):
  Arrival (ns):                0.783
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        reg_apb_wrp_0/reg4x20_inst/temp_data[8]/U1:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/data_out[8]:D
  Delay (ns):                  0.427
  Slack (ns):
  Arrival (ns):                0.772
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        reg_apb_wrp_0/reg4x20_inst/temp_data[13]/U1:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/data_out[13]:D
  Delay (ns):                  0.429
  Slack (ns):
  Arrival (ns):                0.774
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: reg_apb_wrp_0/reg4x20_inst/temp_data[16]/U1:CLK
  To: reg_apb_wrp_0/reg4x20_inst/data_out[16]:D
  data arrival time                              0.763
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.334          net: M3_PROC_ADC_DAC_0_GLC
  0.334                        reg_apb_wrp_0/reg4x20_inst/temp_data[16]/U1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.582                        reg_apb_wrp_0/reg4x20_inst/temp_data[16]/U1:Q (r)
               +     0.181          net: reg_apb_wrp_0/reg4x20_inst/temp_data[16]
  0.763                        reg_apb_wrp_0/reg4x20_inst/data_out[16]:D (r)
                                    
  0.763                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.356          net: M3_PROC_ADC_DAC_0_GLC
  N/C                          reg_apb_wrp_0/reg4x20_inst/data_out[16]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1
  N/C                          reg_apb_wrp_0/reg4x20_inst/data_out[16]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        Synthetic_ADC_v2_0/myP2S/myShift_Register/myShift_Register/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[23]:CLK
  To:                          Serial_Data_out
  Delay (ns):                  2.512
  Slack (ns):
  Arrival (ns):                2.832
  Required (ns):
  Clock to Out (ns):           2.832

Path 2
  From:                        Synthetic_ADC_v2_0/mySigma_Delta_Modulator/myClkdiv_and_RTZ_Modulator/myRetime1/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[0]:CLK
  To:                          nDAC_out
  Delay (ns):                  2.660
  Slack (ns):
  Arrival (ns):                2.978
  Required (ns):
  Clock to Out (ns):           2.978

Path 3
  From:                        Synthetic_ADC_v2_0/mySigma_Delta_Modulator/myClkdiv_and_RTZ_Modulator/myRetime/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[0]:CLK
  To:                          DAC_out
  Delay (ns):                  2.733
  Slack (ns):
  Arrival (ns):                3.070
  Required (ns):
  Clock to Out (ns):           3.070

Path 4
  From:                        Synthetic_ADC_v2_0/myRising_Edge_Det/myRegister1/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[0]:CLK
  To:                          En_400K_pulse
  Delay (ns):                  3.130
  Slack (ns):
  Arrival (ns):                3.443
  Required (ns):
  Clock to Out (ns):           3.443

Path 5
  From:                        Synthetic_ADC_v2_0/myRising_Edge_Det/myRegister2/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[0]:CLK
  To:                          En_400K_pulse
  Delay (ns):                  3.133
  Slack (ns):
  Arrival (ns):                3.446
  Required (ns):
  Clock to Out (ns):           3.446


Expanded Path 1
  From: Synthetic_ADC_v2_0/myP2S/myShift_Register/myShift_Register/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[23]:CLK
  To: Serial_Data_out
  data arrival time                              2.832
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.320          net: M3_PROC_ADC_DAC_0_GLC
  0.320                        Synthetic_ADC_v2_0/myP2S/myShift_Register/myShift_Register/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[23]:CLK (r)
               +     0.248          cell: ADLIB:DFN1
  0.568                        Synthetic_ADC_v2_0/myP2S/myShift_Register/myShift_Register/Register_syn_block.myRegister_syn/Delay0_block/GenBlock.genblk58.genblk59.theDelay/outreg_Z[23]:Q (r)
               +     0.892          net: Serial_Data_out_c
  1.460                        Serial_Data_out_pad/U0/U1:D (r)
               +     0.256          cell: ADLIB:IOTRI_OB_EB
  1.716                        Serial_Data_out_pad/U0/U1:DOUT (r)
               +     0.000          net: Serial_Data_out_pad/U0/NET1
  1.716                        Serial_Data_out_pad/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  2.832                        Serial_Data_out_pad/U0/U0:PAD (r)
               +     0.000          net: Serial_Data_out
  2.832                        Serial_Data_out (r)
                                    
  2.832                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
                                    
  N/C                          Serial_Data_out (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        reg_apb_wrp_0/reg4x20_inst/mem[2][5]:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/mem[2][5]:CLR
  Delay (ns):                  1.360
  Slack (ns):
  Arrival (ns):                1.689
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.033

Path 2
  From:                        reg_apb_wrp_0/reg4x20_inst/mem[3][7]:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/mem[3][7]:CLR
  Delay (ns):                  1.358
  Slack (ns):
  Arrival (ns):                1.697
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.027

Path 3
  From:                        reg_apb_wrp_0/reg4x20_inst/mem[0][18]:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/mem[0][18]:CLR
  Delay (ns):                  1.360
  Slack (ns):
  Arrival (ns):                1.690
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.028

Path 4
  From:                        reg_apb_wrp_0/reg4x20_inst/mem[0][9]:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/mem[0][9]:CLR
  Delay (ns):                  1.360
  Slack (ns):
  Arrival (ns):                1.697
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.028

Path 5
  From:                        reg_apb_wrp_0/reg4x20_inst/mem[3][6]:CLK
  To:                          reg_apb_wrp_0/reg4x20_inst/mem[3][6]:CLR
  Delay (ns):                  1.360
  Slack (ns):
  Arrival (ns):                1.700
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.026


Expanded Path 1
  From: reg_apb_wrp_0/reg4x20_inst/mem[2][5]:CLK
  To: reg_apb_wrp_0/reg4x20_inst/mem[2][5]:CLR
  data arrival time                              1.689
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.329          net: M3_PROC_ADC_DAC_0_GLC
  0.329                        reg_apb_wrp_0/reg4x20_inst/mem[2][5]:CLK (r)
               +     0.717          cell: ADLIB:DFN1P1C1
  1.046                        reg_apb_wrp_0/reg4x20_inst/mem[2][5]:Q (r)
               +     0.213          net: reg_apb_wrp_0/reg4x20_inst/mem[2][5]
  1.259                        reg_apb_wrp_0/reg4x20_inst/mem[2]_RNO[5]:A (r)
               +     0.263          cell: ADLIB:AOI1
  1.522                        reg_apb_wrp_0/reg4x20_inst/mem[2]_RNO[5]:Y (f)
               +     0.167          net: reg_apb_wrp_0/reg4x20_inst/mem[2]_RNO[5]
  1.689                        reg_apb_wrp_0/reg4x20_inst/mem[2][5]:CLR (f)
                                    
  1.689                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.362          net: M3_PROC_ADC_DAC_0_GLC
  N/C                          reg_apb_wrp_0/reg4x20_inst/mem[2][5]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1P1C1
  N/C                          reg_apb_wrp_0/reg4x20_inst/mem[2][5]:CLR


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain ImprovedWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          clk_25MHz_out
  Delay (ns):                  3.386
  Slack (ns):
  Arrival (ns):                3.386
  Required (ns):
  Clock to Out (ns):           3.386

Path 2
  From:                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          frame_clk_out
  Delay (ns):                  3.605
  Slack (ns):
  Arrival (ns):                3.605
  Required (ns):
  Clock to Out (ns):           3.605

Path 3
  From:                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          bit_clk_out
  Delay (ns):                  3.786
  Slack (ns):
  Arrival (ns):                3.786
  Required (ns):
  Clock to Out (ns):           3.786

Path 4
  From:                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          clk_24MHz_out
  Delay (ns):                  3.786
  Slack (ns):
  Arrival (ns):                3.786
  Required (ns):
  Clock to Out (ns):           3.786

Path 5
  From:                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          P2S_bitclk_rising
  Delay (ns):                  4.734
  Slack (ns):
  Arrival (ns):                4.734
  Required (ns):
  Clock to Out (ns):           4.734


Expanded Path 1
  From: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: clk_25MHz_out
  data arrival time                              3.386
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        ImprovedWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  0.000                        ImprovedWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     1.645          cell: ADLIB:MSS_CCC_IP
  1.645                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: ImprovedWire_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  1.645                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  1.645                        ImprovedWire_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.346          net: M3_PROC_ADC_DAC_0_GLC
  1.991                        clk_25MHz_out_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  2.270                        clk_25MHz_out_pad/U0/U1:DOUT (r)
               +     0.000          net: clk_25MHz_out_pad/U0/NET1
  2.270                        clk_25MHz_out_pad/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  3.386                        clk_25MHz_out_pad/U0/U0:PAD (r)
               +     0.000          net: clk_25MHz_out
  3.386                        clk_25MHz_out (r)
                                    
  3.386                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          ImprovedWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  N/C                          ImprovedWire_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          clk_25MHz_out (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

