library verilog;
use verilog.vl_types.all;
entity CoreAPB3 is
    generic(
        APB_DWIDTH      : integer := 32;
        RANGESIZE       : integer := 256;
        IADDR_ENABLE    : integer := 0;
        APBSLOT0ENABLE  : integer := 1;
        APBSLOT1ENABLE  : integer := 1;
        APBSLOT2ENABLE  : integer := 1;
        APBSLOT3ENABLE  : integer := 1;
        APBSLOT4ENABLE  : integer := 1;
        APBSLOT5ENABLE  : integer := 1;
        APBSLOT6ENABLE  : integer := 1;
        APBSLOT7ENABLE  : integer := 1;
        APBSLOT8ENABLE  : integer := 1;
        APBSLOT9ENABLE  : integer := 1;
        APBSLOT10ENABLE : integer := 1;
        APBSLOT11ENABLE : integer := 1;
        APBSLOT12ENABLE : integer := 1;
        APBSLOT13ENABLE : integer := 1;
        APBSLOT14ENABLE : integer := 1;
        APBSLOT15ENABLE : integer := 1
    );
    port(
        PRESETN         : in     vl_logic;
        PCLK            : in     vl_logic;
        PADDR           : in     vl_logic_vector(23 downto 0);
        PWRITE          : in     vl_logic;
        PENABLE         : in     vl_logic;
        PSEL            : in     vl_logic;
        PWDATA          : in     vl_logic_vector(31 downto 0);
        PRDATA          : out    vl_logic_vector(31 downto 0);
        PREADY          : out    vl_logic;
        PSLVERR         : out    vl_logic;
        PADDRS          : out    vl_logic_vector(23 downto 0);
        PADDRS0         : out    vl_logic_vector;
        PWRITES         : out    vl_logic;
        PENABLES        : out    vl_logic;
        PWDATAS         : out    vl_logic_vector(31 downto 0);
        PSELS0          : out    vl_logic;
        PSELS1          : out    vl_logic;
        PSELS2          : out    vl_logic;
        PSELS3          : out    vl_logic;
        PSELS4          : out    vl_logic;
        PSELS5          : out    vl_logic;
        PSELS6          : out    vl_logic;
        PSELS7          : out    vl_logic;
        PSELS8          : out    vl_logic;
        PSELS9          : out    vl_logic;
        PSELS10         : out    vl_logic;
        PSELS11         : out    vl_logic;
        PSELS12         : out    vl_logic;
        PSELS13         : out    vl_logic;
        PSELS14         : out    vl_logic;
        PSELS15         : out    vl_logic;
        PRDATAS0        : in     vl_logic_vector(31 downto 0);
        PRDATAS1        : in     vl_logic_vector(31 downto 0);
        PRDATAS2        : in     vl_logic_vector(31 downto 0);
        PRDATAS3        : in     vl_logic_vector(31 downto 0);
        PRDATAS4        : in     vl_logic_vector(31 downto 0);
        PRDATAS5        : in     vl_logic_vector(31 downto 0);
        PRDATAS6        : in     vl_logic_vector(31 downto 0);
        PRDATAS7        : in     vl_logic_vector(31 downto 0);
        PRDATAS8        : in     vl_logic_vector(31 downto 0);
        PRDATAS9        : in     vl_logic_vector(31 downto 0);
        PRDATAS10       : in     vl_logic_vector(31 downto 0);
        PRDATAS11       : in     vl_logic_vector(31 downto 0);
        PRDATAS12       : in     vl_logic_vector(31 downto 0);
        PRDATAS13       : in     vl_logic_vector(31 downto 0);
        PRDATAS14       : in     vl_logic_vector(31 downto 0);
        PRDATAS15       : in     vl_logic_vector(31 downto 0);
        PREADYS0        : in     vl_logic;
        PREADYS1        : in     vl_logic;
        PREADYS2        : in     vl_logic;
        PREADYS3        : in     vl_logic;
        PREADYS4        : in     vl_logic;
        PREADYS5        : in     vl_logic;
        PREADYS6        : in     vl_logic;
        PREADYS7        : in     vl_logic;
        PREADYS8        : in     vl_logic;
        PREADYS9        : in     vl_logic;
        PREADYS10       : in     vl_logic;
        PREADYS11       : in     vl_logic;
        PREADYS12       : in     vl_logic;
        PREADYS13       : in     vl_logic;
        PREADYS14       : in     vl_logic;
        PREADYS15       : in     vl_logic;
        PSLVERRS0       : in     vl_logic;
        PSLVERRS1       : in     vl_logic;
        PSLVERRS2       : in     vl_logic;
        PSLVERRS3       : in     vl_logic;
        PSLVERRS4       : in     vl_logic;
        PSLVERRS5       : in     vl_logic;
        PSLVERRS6       : in     vl_logic;
        PSLVERRS7       : in     vl_logic;
        PSLVERRS8       : in     vl_logic;
        PSLVERRS9       : in     vl_logic;
        PSLVERRS10      : in     vl_logic;
        PSLVERRS11      : in     vl_logic;
        PSLVERRS12      : in     vl_logic;
        PSLVERRS13      : in     vl_logic;
        PSLVERRS14      : in     vl_logic;
        PSLVERRS15      : in     vl_logic
    );
end CoreAPB3;
