library verilog;
use verilog.vl_types.all;
entity reg4x20 is
    port(
        clk             : in     vl_logic;
        nreset          : in     vl_logic;
        wr_en           : in     vl_logic;
        rd_en           : in     vl_logic;
        addr            : in     vl_logic_vector(1 downto 0);
        data_in         : in     vl_logic_vector(19 downto 0);
        data_out        : out    vl_logic_vector(19 downto 0);
        Direct_Out      : out    vl_logic_vector(19 downto 0);
        Quadratic_Comp  : out    vl_logic_vector(14 downto 0);
        Cubic_Comp      : out    vl_logic_vector(14 downto 0);
        Clk_Div         : out    vl_logic_vector(3 downto 0);
        RTZ_Mode        : out    vl_logic_vector(1 downto 0);
        SD_Mod          : out    vl_logic_vector(1 downto 0)
    );
end reg4x20;
