library verilog;
use verilog.vl_types.all;
entity singleDelayWithEnableGeneric_28s_3 is
    generic(
        bitwidth        : integer := 28
    );
    port(
        N_4             : in     vl_logic_vector(5 downto 5);
        N_3             : in     vl_logic_vector(25 downto 1);
        N_5             : out    vl_logic_vector(25 downto 0);
        clk             : in     vl_logic;
        GlobalReset     : in     vl_logic;
        en              : in     vl_logic
    );
end singleDelayWithEnableGeneric_28s_3;
