library verilog;
use verilog.vl_types.all;
entity Sync_logic is
    port(
        En_50KHz_P      : out    vl_logic_vector(0 downto 0);
        N_47            : in     vl_logic_vector(0 downto 0);
        Frame_Clk       : in     vl_logic;
        enab            : out    vl_logic;
        en_0            : in     vl_logic;
        GlobalReset     : in     vl_logic;
        clk             : in     vl_logic;
        GlobalEnable1   : in     vl_logic;
        en              : out    vl_logic
    );
end Sync_logic;
