library verilog;
use verilog.vl_types.all;
entity synBusSatRnd_Z12 is
    generic(
        inp_width       : integer := 23;
        out_width       : integer := 17;
        infrac          : integer := 19;
        outfrac         : integer := 15;
        round           : integer := 0;
        sat             : integer := 1;
        datatype        : string  := "SS"
    );
    port(
        tmpOutPre       : in     vl_logic_vector(21 downto 20);
        N_35            : out    vl_logic
    );
end synBusSatRnd_Z12;
