library verilog;
use verilog.vl_types.all;
entity singleDelayWithEnableGeneric_12s is
    generic(
        bitwidth        : integer := 12
    );
    port(
        ADC             : in     vl_logic_vector(11 downto 0);
        N_44            : out    vl_logic_vector(11 downto 0);
        clk             : in     vl_logic;
        GlobalReset     : in     vl_logic;
        enab            : in     vl_logic
    );
end singleDelayWithEnableGeneric_12s;
