library verilog;
use verilog.vl_types.all;
entity synSigma_Delta_Modulator_Sigma_Delta_Modulator_2nd_order_D0_Register is
    port(
        N_8             : out    vl_logic_vector(0 downto 0);
        N_9             : in     vl_logic_vector(9 downto 5);
        N_7_8           : out    vl_logic;
        N_7_0           : out    vl_logic;
        N_7_10          : out    vl_logic;
        N_7_15          : out    vl_logic;
        N_6_15          : in     vl_logic;
        N_6_7           : in     vl_logic;
        N_6_1           : in     vl_logic;
        N_6_2           : in     vl_logic;
        N_6_3           : in     vl_logic;
        N_6_4           : in     vl_logic;
        N_6_5           : in     vl_logic;
        N_6_6           : in     vl_logic;
        N_6_9           : in     vl_logic;
        N_6_8           : in     vl_logic;
        N_6_0           : in     vl_logic;
        N_5             : in     vl_logic_vector(7 downto 0);
        clk             : in     vl_logic;
        N_111           : out    vl_logic;
        N_165_1         : out    vl_logic;
        N_164_i         : out    vl_logic;
        rst_1           : in     vl_logic;
        GlobalReset     : in     vl_logic;
        un1_rst_1       : in     vl_logic;
        N_267           : out    vl_logic;
        N_259           : out    vl_logic;
        N_251           : out    vl_logic;
        N_243           : out    vl_logic;
        N_235           : out    vl_logic;
        N_197           : out    vl_logic;
        N_189           : out    vl_logic;
        N_185           : out    vl_logic;
        N_181           : out    vl_logic;
        N_143           : in     vl_logic;
        N_151           : out    vl_logic;
        N_147           : out    vl_logic;
        N_137           : in     vl_logic;
        N_145           : out    vl_logic;
        N_141           : out    vl_logic;
        N_139           : out    vl_logic;
        N_135           : out    vl_logic;
        N_129           : out    vl_logic;
        N_127           : out    vl_logic;
        N_123           : out    vl_logic;
        N_121           : out    vl_logic;
        N_117           : out    vl_logic;
        N_112           : out    vl_logic;
        N_159           : out    vl_logic;
        N_163           : out    vl_logic;
        N_263           : out    vl_logic;
        tmpOutPre_244_0 : out    vl_logic;
        N_124           : in     vl_logic;
        N_119           : in     vl_logic;
        N_126           : out    vl_logic;
        N_131           : in     vl_logic;
        N_136           : in     vl_logic;
        N_138           : out    vl_logic;
        N_172           : out    vl_logic;
        N_175           : in     vl_logic;
        N_184           : out    vl_logic;
        N_188           : out    vl_logic;
        N_196           : out    vl_logic;
        N_204           : out    vl_logic;
        N_242           : out    vl_logic;
        N_250           : out    vl_logic;
        N_258           : out    vl_logic;
        N_233           : in     vl_logic;
        N_266           : out    vl_logic;
        N_120           : out    vl_logic;
        N_256           : in     vl_logic;
        N_234           : out    vl_logic;
        N_222           : out    vl_logic;
        N_155           : in     vl_logic;
        N_160           : in     vl_logic;
        N_162           : out    vl_logic;
        tmpOutPre_15_0_0: out    vl_logic;
        N_148           : in     vl_logic;
        tmpOutPre_105_0_0: out    vl_logic;
        N_142           : in     vl_logic;
        tmpOutPre_90_0_0: out    vl_logic;
        N_130           : in     vl_logic;
        N_128_i         : out    vl_logic;
        tmpOutPre_60_0_0: out    vl_logic
    );
end synSigma_Delta_Modulator_Sigma_Delta_Modulator_2nd_order_D0_Register;
