library verilog;
use verilog.vl_types.all;
entity synDecimate_by_ten_CIC_2nd_Order_Register1_Register_2 is
    port(
        N_5             : in     vl_logic_vector(25 downto 0);
        N_6             : out    vl_logic_vector(25 downto 0);
        clk             : in     vl_logic;
        GlobalReset     : in     vl_logic;
        enab            : in     vl_logic
    );
end synDecimate_by_ten_CIC_2nd_Order_Register1_Register_2;
