library verilog;
use verilog.vl_types.all;
entity singleDelayWithEnableGeneric_2s_1 is
    generic(
        bitwidth        : integer := 2
    );
    port(
        N_6             : out    vl_logic_vector(1 downto 0);
        clk             : in     vl_logic;
        N_129_1         : out    vl_logic;
        N_158_0_0_1     : in     vl_logic;
        N_138           : out    vl_logic;
        N_128_i         : out    vl_logic;
        N_9             : in     vl_logic;
        un1_rst_1_0     : out    vl_logic;
        rst_1           : in     vl_logic;
        ADD_8x8_fast_I49_Y_0_12: in     vl_logic;
        N177_i          : in     vl_logic;
        GlobalReset     : in     vl_logic;
        un1_rst_1       : in     vl_logic
    );
end singleDelayWithEnableGeneric_2s_1;
