library verilog;
use verilog.vl_types.all;
entity Sigma_Delta_Modulator_Sigma_Delta_Modulator_1st_order is
    port(
        N_6             : in     vl_logic_vector(1 downto 1);
        SD_Mod_Select   : in     vl_logic_vector(1 downto 0);
        tmpOut          : out    vl_logic_vector(0 downto 0);
        N_10            : in     vl_logic_vector(20 downto 5);
        clk             : in     vl_logic;
        N_89            : in     vl_logic;
        GlobalReset     : in     vl_logic;
        un1_rst_1       : in     vl_logic;
        rst_1           : in     vl_logic
    );
end Sigma_Delta_Modulator_Sigma_Delta_Modulator_1st_order;
