library verilog;
use verilog.vl_types.all;
entity synCounter_1_1_0_1_2s_0s_7s_3s_0 is
    generic(
        en_exists       : integer := 1;
        rst_exists      : integer := 1;
        ld_exists       : integer := 0;
        rdy_exists      : integer := 1;
        ctype           : integer := 2;
        ival            : integer := 0;
        tval            : integer := 7;
        bitwidth        : integer := 3;
        isSigned        : integer := 0
    );
    port(
        N_47            : in     vl_logic_vector(0 downto 0);
        En_50KHz_P      : out    vl_logic_vector(0 downto 0);
        clk             : in     vl_logic;
        GlobalReset     : in     vl_logic;
        rst             : in     vl_logic;
        en              : in     vl_logic;
        enab            : out    vl_logic
    );
end synCounter_1_1_0_1_2s_0s_7s_3s_0;
