library verilog;
use verilog.vl_types.all;
entity synP2S_Frameclk_Edges_Register1_Register is
    port(
        tmpOut          : in     vl_logic_vector(0 downto 0);
        N_8_i_0         : in     vl_logic_vector(0 downto 0);
        clk             : in     vl_logic;
        N_9             : in     vl_logic;
        N_6_i           : in     vl_logic;
        N_12            : out    vl_logic;
        GlobalReset     : in     vl_logic
    );
end synP2S_Frameclk_Edges_Register1_Register;
