library verilog;
use verilog.vl_types.all;
entity synDelayWithEnable_1s_33s_1s is
    generic(
        bitwidth        : integer := 33;
        delaylength     : integer := 1
    );
    port(
        N_4             : out    vl_logic_vector(30 downto 0);
        N_2_29          : in     vl_logic;
        N_2_0           : in     vl_logic;
        N_2_1           : in     vl_logic;
        N_2_2           : in     vl_logic;
        N_2_7           : in     vl_logic;
        N_2_8           : in     vl_logic;
        N_2_9           : in     vl_logic;
        N_2_10          : in     vl_logic;
        N_2_11          : in     vl_logic;
        N_2_12          : in     vl_logic;
        N_2_13          : in     vl_logic;
        N_2_14          : in     vl_logic;
        N_2_15          : in     vl_logic;
        N_2_16          : in     vl_logic;
        N_2_17          : in     vl_logic;
        N_2_18          : in     vl_logic;
        N_2_19          : in     vl_logic;
        N_2_20          : in     vl_logic;
        N_2_22          : in     vl_logic;
        N_2_23          : in     vl_logic;
        N_2_24          : in     vl_logic;
        N_2_25          : in     vl_logic;
        N_2_27          : in     vl_logic;
        N_2_4           : in     vl_logic;
        N_2_21          : in     vl_logic;
        N_2_3           : in     vl_logic;
        N_2_5           : in     vl_logic;
        N_2_6           : in     vl_logic;
        N_2_reto_0      : in     vl_logic;
        N_2_reto_2      : in     vl_logic;
        IIR_filter_out  : in     vl_logic_vector(0 downto 0);
        clk             : in     vl_logic;
        GlobalReset     : in     vl_logic;
        N444_reto       : out    vl_logic;
        N444            : in     vl_logic;
        N443_reto       : out    vl_logic;
        N443            : in     vl_logic;
        I169_un1_Y_reto : out    vl_logic;
        I169_un1_Y      : in     vl_logic;
        N448_reto       : out    vl_logic;
        N448            : in     vl_logic;
        N447_reto       : out    vl_logic;
        N447            : in     vl_logic;
        N_5290_reto     : out    vl_logic;
        ADD_33x33_medium_area_I168_un1_Y: in     vl_logic;
        en              : in     vl_logic
    );
end synDelayWithEnable_1s_33s_1s;
