library verilog;
use verilog.vl_types.all;
entity APB_MEM_CTRL is
    generic(
        AD0_STATUS_REG_OFFSET: integer := 4096;
        IDLE            : integer := 0;
        FIC_UPPER_ACCESS_0: integer := 1;
        FIC_UPPER_ACCESS_1: integer := 2;
        FIC_UPPER_ACCESS_2: integer := 3;
        FIC_READ_0      : integer := 4;
        FIC_READ_1      : integer := 5;
        FIC_READ_2      : integer := 6;
        EVAL_DATA_VALID : integer := 7;
        HOLD_DATA_ENABLE: integer := 8;
        WAIT_TILL_DATAVALID_LOW: integer := 9
    );
    port(
        PRESETn         : in     vl_logic;
        PCLK            : in     vl_logic;
        PREADY          : in     vl_logic;
        PSLVERR         : in     vl_logic;
        PRDATA          : in     vl_logic_vector(31 downto 0);
        PENABLE         : out    vl_logic;
        PSEL            : out    vl_logic;
        PWRITE          : out    vl_logic;
        PADDR           : out    vl_logic_vector(23 downto 0);
        PWDATA          : out    vl_logic_vector(31 downto 0);
        busy            : out    vl_logic;
        dataout_enable  : out    vl_logic;
        data            : out    vl_logic_vector(11 downto 0)
    );
end APB_MEM_CTRL;
