library verilog;
use verilog.vl_types.all;
entity synP2S_Frameclk_Edges_Register1_Register_1 is
    port(
        N_9             : in     vl_logic_vector(0 downto 0);
        clk             : in     vl_logic;
        enab            : in     vl_logic;
        un1_N_2         : out    vl_logic;
        GlobalReset     : in     vl_logic
    );
end synP2S_Frameclk_Edges_Register1_Register_1;
