library verilog;
use verilog.vl_types.all;
entity CoreAPB3_Master_Side is
    port(
        PADDR           : in     vl_logic_vector(23 downto 0);
        PSEL            : in     vl_logic;
        PENABLE         : in     vl_logic;
        PWRITE          : in     vl_logic;
        PRDATA          : out    vl_logic_vector(31 downto 0);
        PWDATA          : in     vl_logic_vector(31 downto 0);
        PREADY          : out    vl_logic;
        PSLVERR         : out    vl_logic;
        PRESETN         : in     vl_logic;
        PCLK            : in     vl_logic;
        PADDRS0         : out    vl_logic_vector(31 downto 0);
        PSELS0          : out    vl_logic;
        PENABLES        : out    vl_logic;
        PWRITES         : out    vl_logic;
        PRDATAS0        : in     vl_logic_vector(31 downto 0);
        PWDATAS         : out    vl_logic_vector(31 downto 0);
        PREADYS0        : in     vl_logic;
        PSLVERRS0       : in     vl_logic
    );
end CoreAPB3_Master_Side;
