library verilog;
use verilog.vl_types.all;
entity Register_syn is
    port(
        N_44            : out    vl_logic_vector(11 downto 0);
        ADC             : in     vl_logic_vector(11 downto 0);
        En_400KHz_P     : in     vl_logic_vector(0 downto 0);
        GlobalReset     : in     vl_logic;
        clk             : in     vl_logic;
        GlobalEnable1   : in     vl_logic
    );
end Register_syn;
