library verilog;
use verilog.vl_types.all;
entity synDelayWithEnable_1s_1s_1s_4 is
    generic(
        bitwidth        : integer := 1;
        delaylength     : integer := 1
    );
    port(
        N_8_i_0         : in     vl_logic_vector(0 downto 0);
        tmpOut          : in     vl_logic_vector(0 downto 0);
        GlobalReset     : in     vl_logic;
        N_12            : out    vl_logic;
        N_6_i           : in     vl_logic;
        N_9             : in     vl_logic;
        clk             : in     vl_logic
    );
end synDelayWithEnable_1s_1s_1s_4;
