`timescale 1 ns/100 ps
// Version: 10.0 10.0.9.37


module Top_Level(
       UART_0_TXD,
       UART_0_RXD,
       MSS_RESET_N,
       SDD_0,
       ADCDirectInput_0,
       VAREF0,
       DAC_out,
       Serial_Data_out,
       En_out,
       nDAC_out,
       Load_SR,
       P2S_bitclk_rising,
       P2S_bitclk_falling,
       En_50K_pulse,
       clk_24MHz_out,
       frame_clk_out,
       bit_clk_out,
       En_400K_pulse,
       adc_data_ready,
       clk_25MHz_out,
       MAINXIN,
       adc_data_to_mod
    );
output UART_0_TXD;
input  UART_0_RXD;
input  MSS_RESET_N;
output SDD_0;
input  ADCDirectInput_0;
input  VAREF0;
output DAC_out;
output Serial_Data_out;
output En_out;
output nDAC_out;
output Load_SR;
output P2S_bitclk_rising;
output P2S_bitclk_falling;
output En_50K_pulse;
output clk_24MHz_out;
output frame_clk_out;
output bit_clk_out;
output En_400K_pulse;
output adc_data_ready;
output clk_25MHz_out;
input  MAINXIN;
output [11:0] adc_data_to_mod;

    wire \APB_MEM_CTRL_0_APB_bif_PADDR_[0] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[1] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[2] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[3] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[4] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[5] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[6] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[7] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[8] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[9] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[10] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[11] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[12] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[13] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[14] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[15] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[16] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[17] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[18] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[19] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[20] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[21] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[22] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[23] , 
        APB_MEM_CTRL_0_APB_bif_PENABLE, 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[0] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[1] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[2] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[3] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[4] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[5] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[6] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[7] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[8] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[9] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[10] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[11] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[12] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[13] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[14] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[15] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[16] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[17] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[18] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[19] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[20] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[21] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[22] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[23] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[24] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[25] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[26] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[27] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[28] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[29] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[30] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[31] , 
        APB_MEM_CTRL_0_APB_bif_PREADY, APB_MEM_CTRL_0_APB_bif_PSELx, 
        APB_MEM_CTRL_0_APB_bif_PSLVERR, 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[0] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[1] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[2] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[3] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[4] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[5] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[6] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[7] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[8] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[9] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[10] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[11] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[12] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[13] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[14] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[15] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[16] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[17] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[18] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[19] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[20] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[21] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[22] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[23] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[24] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[25] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[26] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[27] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[28] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[29] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[30] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[31] , 
        APB_MEM_CTRL_0_APB_bif_PWRITE, 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[0] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[1] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[2] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[3] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[4] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[5] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[6] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[7] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[8] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[9] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[10] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[11] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[12] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[13] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[14] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[15] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[16] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[17] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[18] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[19] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[20] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[21] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[22] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[23] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[24] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[25] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[26] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[27] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[28] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[29] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[30] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[31] , 
        CoreAPB3_Master_Side_0_APBmslave0_PENABLE, 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[0] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[1] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[2] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[3] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[4] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[5] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[6] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[7] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[8] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[9] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[10] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[11] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[12] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[13] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[14] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[15] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[16] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[17] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[18] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[19] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[20] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[21] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[22] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[23] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[24] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[25] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[26] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[27] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[28] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[29] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[30] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[31] , 
        CoreAPB3_Master_Side_0_APBmslave0_PREADY, 
        CoreAPB3_Master_Side_0_APBmslave0_PSELx, 
        CoreAPB3_Master_Side_0_APBmslave0_PSLVERR, 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[0] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[1] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[2] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[3] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[4] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[5] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[6] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[7] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[8] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[9] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[10] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[11] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[12] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[13] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[14] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[15] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[16] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[17] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[18] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[19] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[20] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[21] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[22] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[23] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[24] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[25] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[26] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[27] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[28] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[29] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[30] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[31] , 
        CoreAPB3_Master_Side_0_APBmslave0_PWRITE, 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[0] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[1] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[2] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[3] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[4] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[5] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[6] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[7] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[8] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[9] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[10] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[11] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[12] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[13] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[14] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[15] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[16] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[17] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[18] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[19] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[20] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[21] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[22] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[23] , 
        CoreAPB3_Slave_Side_0_APBmslave0_PENABLE, 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[0] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[1] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[2] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[3] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[4] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[5] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[6] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[7] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[8] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[9] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[10] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[11] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[12] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[13] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[14] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[15] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[16] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[17] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[18] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[19] , 
        CoreAPB3_Slave_Side_0_APBmslave0_PREADY, 
        CoreAPB3_Slave_Side_0_APBmslave0_PSELx, 
        CoreAPB3_Slave_Side_0_APBmslave0_PSLVERR, 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[0] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[1] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[2] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[3] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[4] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[5] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[6] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[7] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[8] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[9] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[10] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[11] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[12] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[13] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[14] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[15] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[16] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[17] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[18] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[19] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[20] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[21] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[22] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[23] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[24] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[25] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[26] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[27] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[28] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[29] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[30] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[31] , 
        CoreAPB3_Slave_Side_0_APBmslave0_PWRITE, INVD_0_Y, 
        M3_PROC_ADC_DAC_0_FAB_CLK_40MHz, M3_PROC_ADC_DAC_0_GLC, 
        M3_PROC_ADC_DAC_0_M2F_RESET_N, 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[0] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[1] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[2] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[3] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[4] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[5] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[6] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[7] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[8] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[9] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[10] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[11] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[12] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[13] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[14] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[15] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[16] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[17] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[18] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[19] , 
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PENABLE, 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[0] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[1] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[2] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[3] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[4] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[5] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[6] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[7] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[8] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[9] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[10] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[11] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[12] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[13] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[14] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[15] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[16] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[17] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[18] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[19] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[20] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[21] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[22] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[23] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[24] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[25] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[26] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[27] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[28] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[29] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[30] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[31] , 
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PREADY, 
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PSELx, 
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PSLVERR, 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[0] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[1] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[2] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[3] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[4] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[5] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[6] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[7] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[8] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[9] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[10] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[11] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[12] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[13] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[14] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[15] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[16] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[17] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[18] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[19] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[20] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[21] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[22] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[23] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[24] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[25] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[26] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[27] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[28] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[29] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[30] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[31] , 
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWRITE, 
        \reg_apb_wrp_0_Clk_Div_[3] , \reg_apb_wrp_0_Clk_Div_[2] , 
        \reg_apb_wrp_0_Clk_Div_[1] , \reg_apb_wrp_0_Clk_Div_[0] , 
        \reg_apb_wrp_0_Cubic_Comp_[14] , 
        \reg_apb_wrp_0_Cubic_Comp_[13] , 
        \reg_apb_wrp_0_Cubic_Comp_[12] , 
        \reg_apb_wrp_0_Cubic_Comp_[11] , 
        \reg_apb_wrp_0_Cubic_Comp_[10] , 
        \reg_apb_wrp_0_Cubic_Comp_[9] , \reg_apb_wrp_0_Cubic_Comp_[8] , 
        \reg_apb_wrp_0_Cubic_Comp_[7] , \reg_apb_wrp_0_Cubic_Comp_[6] , 
        \reg_apb_wrp_0_Cubic_Comp_[5] , \reg_apb_wrp_0_Cubic_Comp_[4] , 
        \reg_apb_wrp_0_Cubic_Comp_[3] , \reg_apb_wrp_0_Cubic_Comp_[2] , 
        \reg_apb_wrp_0_Cubic_Comp_[1] , \reg_apb_wrp_0_Cubic_Comp_[0] , 
        \reg_apb_wrp_0_Quadratic_Comp_[14] , 
        \reg_apb_wrp_0_Quadratic_Comp_[13] , 
        \reg_apb_wrp_0_Quadratic_Comp_[12] , 
        \reg_apb_wrp_0_Quadratic_Comp_[11] , 
        \reg_apb_wrp_0_Quadratic_Comp_[10] , 
        \reg_apb_wrp_0_Quadratic_Comp_[9] , 
        \reg_apb_wrp_0_Quadratic_Comp_[8] , 
        \reg_apb_wrp_0_Quadratic_Comp_[7] , 
        \reg_apb_wrp_0_Quadratic_Comp_[6] , 
        \reg_apb_wrp_0_Quadratic_Comp_[5] , 
        \reg_apb_wrp_0_Quadratic_Comp_[4] , 
        \reg_apb_wrp_0_Quadratic_Comp_[3] , 
        \reg_apb_wrp_0_Quadratic_Comp_[2] , 
        \reg_apb_wrp_0_Quadratic_Comp_[1] , 
        \reg_apb_wrp_0_Quadratic_Comp_[0] , 
        \reg_apb_wrp_0_RTZ_Mode_[1] , \reg_apb_wrp_0_RTZ_Mode_[0] , 
        \reg_apb_wrp_0_SD_Mod_[1] , \reg_apb_wrp_0_SD_Mod_[0] , 
        GND_net, VCC_net;
    
    CLKINT CLKINT_0 (.A(M3_PROC_ADC_DAC_0_GLC), .Y(clk_25MHz_out));
    BUFD BUFD_0 (.A(clk_25MHz_out), .Y(clk_24MHz_out));
    BUFD BUFD_1 (.A(clk_25MHz_out), .Y(frame_clk_out));
    reg_apb_wrp reg_apb_wrp_0 (.PCLK(clk_25MHz_out), .PENABLE(
        CoreAPB3_Slave_Side_0_APBmslave0_PENABLE), .PSEL(
        CoreAPB3_Slave_Side_0_APBmslave0_PSELx), .PRESETN(
        M3_PROC_ADC_DAC_0_M2F_RESET_N), .PWRITE(
        CoreAPB3_Slave_Side_0_APBmslave0_PWRITE), .PREADY(
        CoreAPB3_Slave_Side_0_APBmslave0_PREADY), .PSLVERR(
        CoreAPB3_Slave_Side_0_APBmslave0_PSLVERR), .PADDR({
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[19] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[18] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[17] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[16] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[15] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[14] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[13] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[12] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[11] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[10] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[9] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[8] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[7] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[6] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[5] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[4] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[3] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[2] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[1] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[0] }), .PWDATA({
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[19] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[18] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[17] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[16] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[15] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[14] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[13] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[12] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[11] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[10] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[9] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[8] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[7] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[6] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[5] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[4] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[3] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[2] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[1] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[0] }), .PRDATA({
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[19] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[18] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[17] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[16] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[15] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[14] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[13] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[12] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[11] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[10] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[9] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[8] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[7] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[6] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[5] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[4] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[3] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[2] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[1] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[0] }), .Direct_Out({
        nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7, nc8, nc9, nc10, nc11, 
        nc12, nc13, nc14, nc15, nc16, nc17, nc18, nc19}), 
        .Quadratic_Comp({\reg_apb_wrp_0_Quadratic_Comp_[14] , 
        \reg_apb_wrp_0_Quadratic_Comp_[13] , 
        \reg_apb_wrp_0_Quadratic_Comp_[12] , 
        \reg_apb_wrp_0_Quadratic_Comp_[11] , 
        \reg_apb_wrp_0_Quadratic_Comp_[10] , 
        \reg_apb_wrp_0_Quadratic_Comp_[9] , 
        \reg_apb_wrp_0_Quadratic_Comp_[8] , 
        \reg_apb_wrp_0_Quadratic_Comp_[7] , 
        \reg_apb_wrp_0_Quadratic_Comp_[6] , 
        \reg_apb_wrp_0_Quadratic_Comp_[5] , 
        \reg_apb_wrp_0_Quadratic_Comp_[4] , 
        \reg_apb_wrp_0_Quadratic_Comp_[3] , 
        \reg_apb_wrp_0_Quadratic_Comp_[2] , 
        \reg_apb_wrp_0_Quadratic_Comp_[1] , 
        \reg_apb_wrp_0_Quadratic_Comp_[0] }), .Cubic_Comp({
        \reg_apb_wrp_0_Cubic_Comp_[14] , 
        \reg_apb_wrp_0_Cubic_Comp_[13] , 
        \reg_apb_wrp_0_Cubic_Comp_[12] , 
        \reg_apb_wrp_0_Cubic_Comp_[11] , 
        \reg_apb_wrp_0_Cubic_Comp_[10] , 
        \reg_apb_wrp_0_Cubic_Comp_[9] , \reg_apb_wrp_0_Cubic_Comp_[8] , 
        \reg_apb_wrp_0_Cubic_Comp_[7] , \reg_apb_wrp_0_Cubic_Comp_[6] , 
        \reg_apb_wrp_0_Cubic_Comp_[5] , \reg_apb_wrp_0_Cubic_Comp_[4] , 
        \reg_apb_wrp_0_Cubic_Comp_[3] , \reg_apb_wrp_0_Cubic_Comp_[2] , 
        \reg_apb_wrp_0_Cubic_Comp_[1] , \reg_apb_wrp_0_Cubic_Comp_[0] })
        , .Clk_Div({\reg_apb_wrp_0_Clk_Div_[3] , 
        \reg_apb_wrp_0_Clk_Div_[2] , \reg_apb_wrp_0_Clk_Div_[1] , 
        \reg_apb_wrp_0_Clk_Div_[0] }), .RTZ_Mode({
        \reg_apb_wrp_0_RTZ_Mode_[1] , \reg_apb_wrp_0_RTZ_Mode_[0] }), 
        .SD_Mod({\reg_apb_wrp_0_SD_Mod_[1] , 
        \reg_apb_wrp_0_SD_Mod_[0] }));
    GND GND (.Y(GND_net));
    CoreAPB3_Master_Side CoreAPB3_Master_Side_0 (.PSEL(
        APB_MEM_CTRL_0_APB_bif_PSELx), .PENABLE(
        APB_MEM_CTRL_0_APB_bif_PENABLE), .PWRITE(
        APB_MEM_CTRL_0_APB_bif_PWRITE), .PREADY(
        APB_MEM_CTRL_0_APB_bif_PREADY), .PSLVERR(
        APB_MEM_CTRL_0_APB_bif_PSLVERR), .PRESETN(
        M3_PROC_ADC_DAC_0_M2F_RESET_N), .PCLK(
        M3_PROC_ADC_DAC_0_FAB_CLK_40MHz), .PSELS0(
        CoreAPB3_Master_Side_0_APBmslave0_PSELx), .PENABLES(
        CoreAPB3_Master_Side_0_APBmslave0_PENABLE), .PWRITES(
        CoreAPB3_Master_Side_0_APBmslave0_PWRITE), .PREADYS0(
        CoreAPB3_Master_Side_0_APBmslave0_PREADY), .PSLVERRS0(
        CoreAPB3_Master_Side_0_APBmslave0_PSLVERR), .PADDR({
        \APB_MEM_CTRL_0_APB_bif_PADDR_[23] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[22] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[21] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[20] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[19] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[18] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[17] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[16] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[15] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[14] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[13] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[12] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[11] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[10] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[9] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[8] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[7] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[6] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[5] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[4] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[3] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[2] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[1] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[0] }), .PRDATA({
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[31] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[30] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[29] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[28] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[27] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[26] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[25] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[24] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[23] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[22] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[21] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[20] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[19] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[18] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[17] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[16] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[15] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[14] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[13] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[12] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[11] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[10] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[9] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[8] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[7] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[6] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[5] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[4] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[3] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[2] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[1] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[0] }), .PWDATA({
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[31] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[30] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[29] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[28] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[27] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[26] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[25] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[24] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[23] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[22] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[21] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[20] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[19] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[18] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[17] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[16] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[15] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[14] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[13] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[12] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[11] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[10] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[9] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[8] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[7] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[6] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[5] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[4] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[3] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[2] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[1] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[0] }), .PADDRS0({
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[31] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[30] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[29] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[28] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[27] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[26] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[25] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[24] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[23] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[22] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[21] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[20] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[19] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[18] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[17] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[16] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[15] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[14] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[13] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[12] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[11] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[10] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[9] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[8] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[7] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[6] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[5] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[4] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[3] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[2] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[1] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[0] }), .PRDATAS0({
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[31] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[30] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[29] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[28] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[27] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[26] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[25] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[24] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[23] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[22] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[21] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[20] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[19] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[18] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[17] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[16] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[15] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[14] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[13] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[12] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[11] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[10] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[9] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[8] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[7] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[6] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[5] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[4] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[3] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[2] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[1] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[0] }), .PWDATAS({
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[31] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[30] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[29] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[28] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[27] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[26] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[25] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[24] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[23] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[22] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[21] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[20] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[19] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[18] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[17] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[16] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[15] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[14] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[13] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[12] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[11] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[10] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[9] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[8] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[7] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[6] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[5] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[4] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[3] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[2] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[1] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[0] }));
    VCC VCC (.Y(VCC_net));
    INVD INVD_0 (.A(M3_PROC_ADC_DAC_0_M2F_RESET_N), .Y(INVD_0_Y));
    CoreAPB3_Slave_Side CoreAPB3_Slave_Side_0 (.PSEL(
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PSELx), .PENABLE(
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PENABLE), .PWRITE(
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWRITE), .PREADY(
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PREADY), .PSLVERR(
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PSLVERR), .PSELS0(
        CoreAPB3_Slave_Side_0_APBmslave0_PSELx), .PENABLES(
        CoreAPB3_Slave_Side_0_APBmslave0_PENABLE), .PWRITES(
        CoreAPB3_Slave_Side_0_APBmslave0_PWRITE), .PREADYS0(
        CoreAPB3_Slave_Side_0_APBmslave0_PREADY), .PSLVERRS0(
        CoreAPB3_Slave_Side_0_APBmslave0_PSLVERR), .PADDR({GND_net, 
        GND_net, GND_net, GND_net, 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[19] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[18] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[17] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[16] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[15] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[14] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[13] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[12] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[11] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[10] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[9] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[8] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[7] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[6] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[5] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[4] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[3] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[2] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[1] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[0] }), .PRDATA({
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[31] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[30] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[29] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[28] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[27] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[26] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[25] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[24] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[23] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[22] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[21] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[20] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[19] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[18] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[17] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[16] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[15] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[14] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[13] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[12] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[11] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[10] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[9] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[8] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[7] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[6] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[5] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[4] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[3] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[2] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[1] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[0] }), .PWDATA({
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[31] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[30] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[29] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[28] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[27] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[26] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[25] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[24] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[23] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[22] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[21] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[20] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[19] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[18] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[17] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[16] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[15] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[14] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[13] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[12] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[11] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[10] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[9] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[8] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[7] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[6] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[5] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[4] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[3] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[2] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[1] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[0] }), .PADDRS0({
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[23] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[22] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[21] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[20] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[19] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[18] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[17] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[16] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[15] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[14] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[13] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[12] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[11] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[10] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[9] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[8] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[7] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[6] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[5] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[4] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[3] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[2] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[1] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PADDR_[0] }), .PRDATAS0({
        GND_net, GND_net, GND_net, GND_net, GND_net, GND_net, GND_net, 
        GND_net, GND_net, GND_net, GND_net, GND_net, 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[19] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[18] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[17] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[16] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[15] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[14] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[13] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[12] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[11] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[10] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[9] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[8] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[7] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[6] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[5] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[4] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[3] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[2] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[1] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PRDATA_[0] }), .PWDATAS({
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[31] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[30] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[29] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[28] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[27] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[26] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[25] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[24] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[23] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[22] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[21] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[20] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[19] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[18] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[17] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[16] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[15] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[14] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[13] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[12] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[11] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[10] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[9] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[8] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[7] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[6] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[5] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[4] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[3] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[2] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[1] , 
        \CoreAPB3_Slave_Side_0_APBmslave0_PWDATA_[0] }));
    Synthetic_ADC_v2 Synthetic_ADC_v2_0 (.clk(clk_25MHz_out), 
        .GlobalReset(INVD_0_Y), .GlobalEnable1(VCC_net), 
        .P2S_bitclk_falling(P2S_bitclk_falling), .P2S_bitclk_rising(
        P2S_bitclk_rising), .nDAC_out(nDAC_out), .Serial_Data_out(
        Serial_Data_out), .Reset(INVD_0_Y), .Load_SR(Load_SR), 
        .Frame_Clk(clk_25MHz_out), .En_out(En_out), .En_50K_pulse(
        En_50K_pulse), .En_400K_pulse(En_400K_pulse), .En_400KHz(
        adc_data_ready), .Direct_Bitstream(VCC_net), .DAC_out(DAC_out), 
        .Bit_Clk(clk_25MHz_out), .clk_div({\reg_apb_wrp_0_Clk_Div_[3] , 
        \reg_apb_wrp_0_Clk_Div_[2] , \reg_apb_wrp_0_Clk_Div_[1] , 
        \reg_apb_wrp_0_Clk_Div_[0] }), .SD_Mod_Select({
        \reg_apb_wrp_0_SD_Mod_[1] , \reg_apb_wrp_0_SD_Mod_[0] }), 
        .RTZ_Mode({\reg_apb_wrp_0_RTZ_Mode_[1] , 
        \reg_apb_wrp_0_RTZ_Mode_[0] }), .Quadratic_Comp({
        \reg_apb_wrp_0_Quadratic_Comp_[14] , 
        \reg_apb_wrp_0_Quadratic_Comp_[13] , 
        \reg_apb_wrp_0_Quadratic_Comp_[12] , 
        \reg_apb_wrp_0_Quadratic_Comp_[11] , 
        \reg_apb_wrp_0_Quadratic_Comp_[10] , 
        \reg_apb_wrp_0_Quadratic_Comp_[9] , 
        \reg_apb_wrp_0_Quadratic_Comp_[8] , 
        \reg_apb_wrp_0_Quadratic_Comp_[7] , 
        \reg_apb_wrp_0_Quadratic_Comp_[6] , 
        \reg_apb_wrp_0_Quadratic_Comp_[5] , 
        \reg_apb_wrp_0_Quadratic_Comp_[4] , 
        \reg_apb_wrp_0_Quadratic_Comp_[3] , 
        \reg_apb_wrp_0_Quadratic_Comp_[2] , 
        \reg_apb_wrp_0_Quadratic_Comp_[1] , 
        \reg_apb_wrp_0_Quadratic_Comp_[0] }), .Cubic_Comp({
        \reg_apb_wrp_0_Cubic_Comp_[14] , 
        \reg_apb_wrp_0_Cubic_Comp_[13] , 
        \reg_apb_wrp_0_Cubic_Comp_[12] , 
        \reg_apb_wrp_0_Cubic_Comp_[11] , 
        \reg_apb_wrp_0_Cubic_Comp_[10] , 
        \reg_apb_wrp_0_Cubic_Comp_[9] , \reg_apb_wrp_0_Cubic_Comp_[8] , 
        \reg_apb_wrp_0_Cubic_Comp_[7] , \reg_apb_wrp_0_Cubic_Comp_[6] , 
        \reg_apb_wrp_0_Cubic_Comp_[5] , \reg_apb_wrp_0_Cubic_Comp_[4] , 
        \reg_apb_wrp_0_Cubic_Comp_[3] , \reg_apb_wrp_0_Cubic_Comp_[2] , 
        \reg_apb_wrp_0_Cubic_Comp_[1] , \reg_apb_wrp_0_Cubic_Comp_[0] })
        , .ADC({adc_data_to_mod[11], adc_data_to_mod[10], 
        adc_data_to_mod[9], adc_data_to_mod[8], adc_data_to_mod[7], 
        adc_data_to_mod[6], adc_data_to_mod[5], adc_data_to_mod[4], 
        adc_data_to_mod[3], adc_data_to_mod[2], adc_data_to_mod[1], 
        adc_data_to_mod[0]}));
    BUFD BUFD_2 (.A(clk_25MHz_out), .Y(bit_clk_out));
    ImprovedWire ImprovedWire_0 (.UART_0_TXD(UART_0_TXD), .UART_0_RXD(
        UART_0_RXD), .MSS_RESET_N(MSS_RESET_N), .M2F_RESET_N(
        M3_PROC_ADC_DAC_0_M2F_RESET_N), .MSSPSEL(
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PSELx), .MSSPENABLE(
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PENABLE), .MSSPWRITE(
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWRITE), .MSSPREADY(
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PREADY), .MSSPSLVERR(
        M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PSLVERR), .FABPSEL(
        CoreAPB3_Master_Side_0_APBmslave0_PSELx), .FABPENABLE(
        CoreAPB3_Master_Side_0_APBmslave0_PENABLE), .FABPWRITE(
        CoreAPB3_Master_Side_0_APBmslave0_PWRITE), .FABPREADY(
        CoreAPB3_Master_Side_0_APBmslave0_PREADY), .FABPSLVERR(
        CoreAPB3_Master_Side_0_APBmslave0_PSLVERR), .FAB_CLK_40MHz(
        M3_PROC_ADC_DAC_0_FAB_CLK_40MHz), .SDD_0(SDD_0), .FABSDD0D(
        DAC_out), .FABSDD0CLK(En_out), .VAREF0(VAREF0), .GLC(
        M3_PROC_ADC_DAC_0_GLC), .ADCDirectInput_0(ADCDirectInput_0), 
        .MAINXIN(MAINXIN), .MSSPADDR({
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[19] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[18] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[17] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[16] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[15] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[14] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[13] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[12] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[11] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[10] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[9] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[8] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[7] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[6] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[5] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[4] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[3] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[2] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[1] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PADDR_[0] }), .MSSPRDATA({
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[31] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[30] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[29] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[28] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[27] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[26] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[25] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[24] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[23] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[22] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[21] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[20] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[19] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[18] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[17] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[16] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[15] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[14] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[13] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[12] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[11] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[10] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[9] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[8] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[7] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[6] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[5] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[4] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[3] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[2] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[1] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PRDATA_[0] }), .MSSPWDATA({
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[31] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[30] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[29] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[28] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[27] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[26] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[25] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[24] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[23] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[22] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[21] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[20] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[19] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[18] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[17] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[16] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[15] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[14] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[13] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[12] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[11] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[10] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[9] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[8] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[7] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[6] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[5] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[4] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[3] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[2] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[1] , 
        \M3_PROC_ADC_DAC_0_MSS_MASTER_APB_PWDATA_[0] }), .FABPADDR({
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[31] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[30] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[29] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[28] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[27] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[26] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[25] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[24] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[23] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[22] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[21] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[20] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[19] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[18] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[17] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[16] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[15] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[14] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[13] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[12] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[11] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[10] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[9] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[8] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[7] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[6] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[5] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[4] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[3] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[2] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[1] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PADDR_[0] }), .FABPRDATA({
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[31] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[30] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[29] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[28] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[27] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[26] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[25] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[24] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[23] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[22] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[21] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[20] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[19] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[18] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[17] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[16] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[15] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[14] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[13] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[12] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[11] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[10] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[9] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[8] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[7] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[6] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[5] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[4] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[3] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[2] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[1] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PRDATA_[0] }), .FABPWDATA({
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[31] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[30] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[29] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[28] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[27] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[26] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[25] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[24] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[23] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[22] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[21] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[20] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[19] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[18] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[17] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[16] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[15] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[14] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[13] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[12] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[11] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[10] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[9] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[8] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[7] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[6] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[5] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[4] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[3] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[2] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[1] , 
        \CoreAPB3_Master_Side_0_APBmslave0_PWDATA_[0] }));
    APB_MEM_CTRL APB_MEM_CTRL_0 (.PRESETn(
        M3_PROC_ADC_DAC_0_M2F_RESET_N), .PCLK(
        M3_PROC_ADC_DAC_0_FAB_CLK_40MHz), .PREADY(
        APB_MEM_CTRL_0_APB_bif_PREADY), .PSLVERR(
        APB_MEM_CTRL_0_APB_bif_PSLVERR), .PENABLE(
        APB_MEM_CTRL_0_APB_bif_PENABLE), .PSEL(
        APB_MEM_CTRL_0_APB_bif_PSELx), .PWRITE(
        APB_MEM_CTRL_0_APB_bif_PWRITE), .busy(), .dataout_enable(
        adc_data_ready), .PRDATA({\APB_MEM_CTRL_0_APB_bif_PRDATA_[31] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[30] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[29] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[28] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[27] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[26] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[25] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[24] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[23] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[22] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[21] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[20] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[19] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[18] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[17] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[16] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[15] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[14] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[13] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[12] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[11] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[10] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[9] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[8] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[7] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[6] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[5] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[4] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[3] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[2] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[1] , 
        \APB_MEM_CTRL_0_APB_bif_PRDATA_[0] }), .PADDR({
        \APB_MEM_CTRL_0_APB_bif_PADDR_[23] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[22] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[21] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[20] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[19] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[18] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[17] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[16] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[15] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[14] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[13] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[12] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[11] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[10] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[9] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[8] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[7] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[6] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[5] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[4] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[3] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[2] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[1] , 
        \APB_MEM_CTRL_0_APB_bif_PADDR_[0] }), .PWDATA({
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[31] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[30] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[29] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[28] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[27] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[26] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[25] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[24] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[23] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[22] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[21] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[20] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[19] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[18] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[17] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[16] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[15] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[14] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[13] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[12] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[11] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[10] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[9] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[8] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[7] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[6] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[5] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[4] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[3] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[2] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[1] , 
        \APB_MEM_CTRL_0_APB_bif_PWDATA_[0] }), .data({
        adc_data_to_mod[11], adc_data_to_mod[10], adc_data_to_mod[9], 
        adc_data_to_mod[8], adc_data_to_mod[7], adc_data_to_mod[6], 
        adc_data_to_mod[5], adc_data_to_mod[4], adc_data_to_mod[3], 
        adc_data_to_mod[2], adc_data_to_mod[1], adc_data_to_mod[0]}));
    
endmodule
