library verilog;
use verilog.vl_types.all;
entity singleDelayWithEnableGeneric_1s_13 is
    generic(
        bitwidth        : integer := 1
    );
    port(
        En_400KHz_P     : in     vl_logic_vector(0 downto 0);
        N_47            : out    vl_logic_vector(0 downto 0);
        clk             : in     vl_logic;
        GlobalReset     : in     vl_logic;
        GlobalEnable1   : in     vl_logic
    );
end singleDelayWithEnableGeneric_1s_13;
