#-- Synopsys, Inc.
#-- Version E-2010.09A-1
#-- Project file D:\HANS\ACTEL\DESIGNS\Aerospace\RTAXS_ClockSourceSynchronousOutput\LIBERO_Project_RTAXS_ClockSourceSynchronousOutput\synthesis\run_options.txt

#project files
add_file -vhdl -lib work "D:/HANS/ACTEL/DESIGNS/Aerospace/RTAXS_ClockSourceSynchronousOutput/LIBERO_Project_RTAXS_ClockSourceSynchronousOutput/hdl/RTAXS_ClockSourceSynchronousOutput.vhd"


#implementation: "synthesis"
impl -add synthesis -type fpga

#device options
set_option -technology Axcelerator
set_option -part RTAX1000S
set_option -package CQFP352
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "work.RTAXS_ClockSourceSynchronousOutput"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0

# Actel 500K
set_option -run_prop_extract 1
set_option -maxfan 10
set_option -maxfan_hard3 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 0
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0

# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./RTAXS_ClockSourceSynchronousOutput.edn"
impl -active "synthesis"
