`

    #Build: Synplify Pro E-2010.09A-1, Build 006R, Oct  6 2010
    #install: D:\ACTEL_All_Software\Libero_v9.1\Synopsys\synplify_E201009A-1
    #OS: Windows XP 5.1
    #Hostname: WXPL-SCHMITZH

    #Implementation: synthesis

    #Mon May 16 18:04:27 2011

    $ Start of Compile
    #Mon May 16 18:04:27 2011

    Synopsys VHDL Compiler, version comp520rcp1, Build 028R, built Sep 23 2010
    @N: :  | Running in 32-bit mode
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    @N: : RTAXS_ClockSourceSynchronousOutput.vhd(42) | Top entity is set to RTAXS_ClockSourceSynchronousOutput.
    VHDL syntax check successful!

    Compiler output is up to date.  No re-compile necessary

    @N:CD630 : RTAXS_ClockSourceSynchronousOutput.vhd(42) | Synthesizing work.rtaxs_clocksourcesynchronousoutput.my_architecture
    @W:CD280 : RTAXS_ClockSourceSynchronousOutput.vhd(72) | Unbound component CLKBUF mapped to black box
    @N:CD630 : RTAXS_ClockSourceSynchronousOutput.vhd(72) | Synthesizing work.clkbuf.syn_black_box
    Post processing for work.clkbuf.syn_black_box
    Post processing for work.rtaxs_clocksourcesynchronousoutput.my_architecture
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Mon May 16 18:04:27 2011

    ###########################################################]

`
Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Writing Analyst data base D:\HANS\ACTEL\DESIGNS\Aerospace\RTAXS_ClockSourceSynchronousOutput\LIBERO_Project_RTAXS_ClockSourceSynchronousOutput\synthesis\RTAXS_ClockSourceSynchronousOutput.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 59MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 59MB) ##### START OF TIMING REPORT #####[ # Timing Report written on Mon May 16 18:04:12 2011 # Top view: RTAXS_ClockSourceSynchronousOutput Library name: adlib Operating conditions: COMWC-1 ( T = 70.0, V = 1.42, P = 1.31, tree_type = worst_case ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: ax125 Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: NA Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------- ======================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ##### END OF TIMING REPORT #####] --------------------------------------- Synthesized design as a chip Resource Usage Report of RTAXS_ClockSourceSynchronousOutput Target Part: rtax1000s_cqfp352-1 Combinational Cells: 0 of 12096 (0%) Sequential Cells: 1 of 6048 (0%) Total Cells: 1 of 18144 (1%) DSP Blocks: 0 Clock Buffers: 1 IO Cells: 4 Details: df1: 1 seq:1 clkbuf: 1 clock buffer inbuf: 1 outbuf: 2 false: 1 true: 1 RAM/ROM Usage Summary Block Rams : 0 of 36 (0%) Mapper successful! Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon May 16 18:04:12 2011 ###########################################################]