Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Jan 19 11:35:18 2012


Design: IAP_TOP
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.383
External Hold (ns):         1.283
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                7.209
Frequency (MHz):            138.715
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.651
Max Clock-To-Out (ns):      5.725

Clock Domain:               mss_ccc_macclk
Period (ns):                20.000
Frequency (MHz):            50.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.644
Max Clock-To-Out (ns):      5.005

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_IAP_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   1.289
  External Hold (ns):          1.283


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_IAP_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        MSS_IAP_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: MSS_IAP_0/MSS_RESET_0_MSS_RESET_N_Y
  0.276                        MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.270          net: MSS_IAP_0/GLA0
  N/C                          MSS_IAP_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.289          Library hold time: ADLIB:MSS_APB_IP
  N/C                          MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        BLINK_LED_0/LED2:CLK
  To:                          BLINK_LED_0/LED2:D
  Delay (ns):                  0.714
  Slack (ns):
  Arrival (ns):                1.072
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        BLINK_LED_0/LED1:CLK
  To:                          BLINK_LED_0/LED1:D
  Delay (ns):                  0.712
  Slack (ns):
  Arrival (ns):                1.043
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        BLINK_LED_0/counter[2]:CLK
  To:                          BLINK_LED_0/counter[2]:D
  Delay (ns):                  0.717
  Slack (ns):
  Arrival (ns):                1.054
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        BLINK_LED_0/counter[4]:CLK
  To:                          BLINK_LED_0/counter[4]:D
  Delay (ns):                  0.814
  Slack (ns):
  Arrival (ns):                1.151
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        BLINK_LED_0/counter[10]:CLK
  To:                          BLINK_LED_0/counter[10]:D
  Delay (ns):                  0.816
  Slack (ns):
  Arrival (ns):                1.161
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: BLINK_LED_0/LED2:CLK
  To: BLINK_LED_0/LED2:D
  data arrival time                              1.072
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_IAP_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.358          net: FAB_CLK
  0.358                        BLINK_LED_0/LED2:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.606                        BLINK_LED_0/LED2:Q (r)
               +     0.156          net: LED4_c_c
  0.762                        BLINK_LED_0/LED2_RNO:C (r)
               +     0.147          cell: ADLIB:AX1C
  0.909                        BLINK_LED_0/LED2_RNO:Y (r)
               +     0.163          net: BLINK_LED_0/LED2_RNO
  1.072                        BLINK_LED_0/LED2:D (r)
                                    
  1.072                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_IAP_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.380          net: FAB_CLK
  N/C                          BLINK_LED_0/LED2:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          BLINK_LED_0/LED2:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        BLINK_LED_0/LED1:CLK
  To:                          LED1
  Delay (ns):                  2.320
  Slack (ns):
  Arrival (ns):                2.651
  Required (ns):
  Clock to Out (ns):           2.651

Path 2
  From:                        BLINK_LED_0/LED2:CLK
  To:                          LED2
  Delay (ns):                  2.339
  Slack (ns):
  Arrival (ns):                2.697
  Required (ns):
  Clock to Out (ns):           2.697

Path 3
  From:                        BLINK_LED_0/LED1:CLK
  To:                          LED3
  Delay (ns):                  2.406
  Slack (ns):
  Arrival (ns):                2.737
  Required (ns):
  Clock to Out (ns):           2.737

Path 4
  From:                        BLINK_LED_0/LED2:CLK
  To:                          LED4
  Delay (ns):                  2.406
  Slack (ns):
  Arrival (ns):                2.764
  Required (ns):
  Clock to Out (ns):           2.764


Expanded Path 1
  From: BLINK_LED_0/LED1:CLK
  To: LED1
  data arrival time                              2.651
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_IAP_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.331          net: FAB_CLK
  0.331                        BLINK_LED_0/LED1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.579                        BLINK_LED_0/LED1:Q (r)
               +     0.677          net: LED3_c_c
  1.256                        LED1_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  1.535                        LED1_pad/U0/U1:DOUT (r)
               +     0.000          net: LED1_pad/U0/NET1
  1.535                        LED1_pad/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  2.651                        LED1_pad/U0/U0:PAD (r)
               +     0.000          net: LED1
  2.651                        LED1 (r)
                                    
  2.651                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
                                    
  N/C                          LED1 (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          GLC
  Delay (ns):                  2.644
  Slack (ns):
  Arrival (ns):                2.644
  Required (ns):
  Clock to Out (ns):           2.644


Expanded Path 1
  From: MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: GLC
  data arrival time                              2.644
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  0.000                        MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: MSS_IAP_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     0.957          cell: ADLIB:MSS_CCC_IP
  0.957                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.000          net: MSS_IAP_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.323          net: GLC_c
  1.280                        GLC_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  1.559                        GLC_pad/U0/U1:DOUT (r)
               +     0.000          net: GLC_pad/U0/NET1
  1.559                        GLC_pad/U0/U0:D (r)
               +     1.085          cell: ADLIB:IOPAD_TRI
  2.644                        GLC_pad/U0/U0:PAD (r)
               +     0.000          net: GLC
  2.644                        GLC (r)
                                    
  2.644                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  N/C                          MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          GLC (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

