Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Jan 19 11:35:18 2012


Design: IAP_TOP
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.383
External Hold (ns):         1.283
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                7.209
Frequency (MHz):            138.715
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.651
Max Clock-To-Out (ns):      5.725

Clock Domain:               mss_ccc_macclk
Period (ns):                20.000
Frequency (MHz):            50.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.644
Max Clock-To-Out (ns):      5.005

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_IAP_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.782
  External Setup (ns):         -1.383


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_IAP_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        MSS_IAP_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_IAP_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.382          net: MSS_IAP_0/GLA0
  N/C                          MSS_IAP_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.782          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        BLINK_LED_0/counter[30]:CLK
  To:                          BLINK_LED_0/counter[9]:D
  Delay (ns):                  6.833
  Slack (ns):
  Arrival (ns):                7.363
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.209

Path 2
  From:                        BLINK_LED_0/counter[19]:CLK
  To:                          BLINK_LED_0/counter[9]:D
  Delay (ns):                  6.748
  Slack (ns):
  Arrival (ns):                7.311
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.157

Path 3
  From:                        BLINK_LED_0/counter[29]:CLK
  To:                          BLINK_LED_0/counter[9]:D
  Delay (ns):                  6.768
  Slack (ns):
  Arrival (ns):                7.298
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.144

Path 4
  From:                        BLINK_LED_0/counter[30]:CLK
  To:                          BLINK_LED_0/counter[22]:D
  Delay (ns):                  6.704
  Slack (ns):
  Arrival (ns):                7.234
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.123

Path 5
  From:                        BLINK_LED_0/counter[30]:CLK
  To:                          BLINK_LED_0/counter[17]:D
  Delay (ns):                  6.676
  Slack (ns):
  Arrival (ns):                7.206
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.078


Expanded Path 1
  From: BLINK_LED_0/counter[30]:CLK
  To: BLINK_LED_0/counter[9]:D
  data required time                             N/C
  data arrival time                          -   7.363
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_IAP_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.530          net: FAB_CLK
  0.530                        BLINK_LED_0/counter[30]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.089                        BLINK_LED_0/counter[30]:Q (f)
               +     0.292          net: BLINK_LED_0/counter[30]
  1.381                        BLINK_LED_0/counter_RNIQTT3[29]:B (f)
               +     0.490          cell: ADLIB:NOR2
  1.871                        BLINK_LED_0/counter_RNIQTT3[29]:Y (r)
               +     0.255          net: BLINK_LED_0/m18_e_2
  2.126                        BLINK_LED_0/counter_RNIHNR7[23]:A (r)
               +     0.504          cell: ADLIB:NOR3A
  2.630                        BLINK_LED_0/counter_RNIHNR7[23]:Y (r)
               +     0.937          net: BLINK_LED_0/m18_e_10
  3.567                        BLINK_LED_0/counter_RNIAF3H1[15]:A (r)
               +     0.398          cell: ADLIB:NOR3C
  3.965                        BLINK_LED_0/counter_RNIAF3H1[15]:Y (r)
               +     0.747          net: BLINK_LED_0/m18_e_16
  4.712                        BLINK_LED_0/counter_RNIJHJ54[21]:C (r)
               +     0.505          cell: ADLIB:NOR3C
  5.217                        BLINK_LED_0/counter_RNIJHJ54[21]:Y (r)
               +     1.439          net: BLINK_LED_0/N_19
  6.656                        BLINK_LED_0/counter_RNO[9]:B (r)
               +     0.460          cell: ADLIB:AOI1B
  7.116                        BLINK_LED_0/counter_RNO[9]:Y (f)
               +     0.247          net: BLINK_LED_0/N_33
  7.363                        BLINK_LED_0/counter[9]:D (f)
                                    
  7.363                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_IAP_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.589          net: FAB_CLK
  N/C                          BLINK_LED_0/counter[9]:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  N/C                          BLINK_LED_0/counter[9]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        BLINK_LED_0/LED2:CLK
  To:                          LED4
  Delay (ns):                  5.114
  Slack (ns):
  Arrival (ns):                5.725
  Required (ns):
  Clock to Out (ns):           5.725

Path 2
  From:                        BLINK_LED_0/LED1:CLK
  To:                          LED3
  Delay (ns):                  5.079
  Slack (ns):
  Arrival (ns):                5.643
  Required (ns):
  Clock to Out (ns):           5.643

Path 3
  From:                        BLINK_LED_0/LED2:CLK
  To:                          LED2
  Delay (ns):                  4.998
  Slack (ns):
  Arrival (ns):                5.609
  Required (ns):
  Clock to Out (ns):           5.609

Path 4
  From:                        BLINK_LED_0/LED1:CLK
  To:                          LED1
  Delay (ns):                  4.971
  Slack (ns):
  Arrival (ns):                5.535
  Required (ns):
  Clock to Out (ns):           5.535


Expanded Path 1
  From: BLINK_LED_0/LED2:CLK
  To: LED4
  data required time                             N/C
  data arrival time                          -   5.725
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_IAP_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.611          net: FAB_CLK
  0.611                        BLINK_LED_0/LED2:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.170                        BLINK_LED_0/LED2:Q (f)
               +     1.247          net: LED4_c_c
  2.417                        LED4_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  2.917                        LED4_pad/U0/U1:DOUT (f)
               +     0.000          net: LED4_pad/U0/NET1
  2.917                        LED4_pad/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  5.725                        LED4_pad/U0/U0:PAD (f)
               +     0.000          net: LED4
  5.725                        LED4 (f)
                                    
  5.725                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
                                    
  N/C                          LED4 (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          GLC
  Delay (ns):                  5.005
  Slack (ns):
  Arrival (ns):                5.005
  Required (ns):
  Clock to Out (ns):           5.005


Expanded Path 1
  From: MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: GLC
  data required time                             N/C
  data arrival time                          -   5.005
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  0.000                        MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: MSS_IAP_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     1.246          cell: ADLIB:MSS_CCC_IP
  1.246                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (f)
               +     0.000          net: MSS_IAP_0/MSS_CCC_0/I_MSSCCC/GLC_INT
  1.246                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  1.246                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (f)
               +     0.550          net: GLC_c
  1.796                        GLC_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  2.296                        GLC_pad/U0/U1:DOUT (f)
               +     0.000          net: GLC_pad/U0/NET1
  2.296                        GLC_pad/U0/U0:D (f)
               +     2.709          cell: ADLIB:IOPAD_TRI
  5.005                        GLC_pad/U0/U0:PAD (f)
               +     0.000          net: GLC
  5.005                        GLC (f)
                                    
  5.005                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  N/C                          MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          GLC (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

