Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 20:18:03 2011


Design: ACE_Simul_Samp
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                11.214
Frequency (MHz):            89.174
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.661
External Hold (ns):         1.288
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        fab_logic_0/counter2[25]/U1:CLK
  To:                          fab_logic_0/counter2[6]/U1:D
  Delay (ns):                  10.692
  Slack (ns):
  Arrival (ns):                11.386
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         11.214

Path 2
  From:                        fab_logic_0/counter2[22]/U1:CLK
  To:                          fab_logic_0/counter2[6]/U1:D
  Delay (ns):                  10.547
  Slack (ns):
  Arrival (ns):                11.241
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         11.069

Path 3
  From:                        fab_logic_0/counter2[24]/U1:CLK
  To:                          fab_logic_0/counter2[6]/U1:D
  Delay (ns):                  10.331
  Slack (ns):
  Arrival (ns):                11.025
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         10.853

Path 4
  From:                        fab_logic_0/counter2[21]/U1:CLK
  To:                          fab_logic_0/counter2[6]/U1:D
  Delay (ns):                  10.300
  Slack (ns):
  Arrival (ns):                10.973
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         10.801

Path 5
  From:                        fab_logic_0/counter2[25]/U1:CLK
  To:                          fab_logic_0/Interrupt/U1:D
  Delay (ns):                  10.046
  Slack (ns):
  Arrival (ns):                10.740
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         10.568


Expanded Path 1
  From: fab_logic_0/counter2[25]/U1:CLK
  To: fab_logic_0/counter2[6]/U1:D
  data required time                             N/C
  data arrival time                          -   11.386
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.694          net: FAB_CLK
  0.694                        fab_logic_0/counter2[25]/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  1.365                        fab_logic_0/counter2[25]/U1:Q (f)
               +     0.526          net: fab_logic_0/counter2[25]
  1.891                        fab_logic_0/counter2_RNIHHRF[22]:B (f)
               +     0.588          cell: ADLIB:NOR2
  2.479                        fab_logic_0/counter2_RNIHHRF[22]:Y (r)
               +     0.978          net: fab_logic_0/counter2_3_i_o3_6[0]
  3.457                        fab_logic_0/counter2_RNI83OV[16]:A (r)
               +     0.604          cell: ADLIB:NOR3A
  4.061                        fab_logic_0/counter2_RNI83OV[16]:Y (r)
               +     0.306          net: fab_logic_0/counter2_3_i_o3_16[0]
  4.367                        fab_logic_0/counter2_RNI82FV1[30]:C (r)
               +     0.606          cell: ADLIB:NOR3C
  4.973                        fab_logic_0/counter2_RNI82FV1[30]:Y (r)
               +     0.966          net: fab_logic_0/counter2_3_i_o3_21[0]
  5.939                        fab_logic_0/counter2_RNIO51N5[2]:B (r)
               +     0.568          cell: ADLIB:OR3C
  6.507                        fab_logic_0/counter2_RNIO51N5[2]:Y (f)
               +     0.669          net: fab_logic_0/N_43
  7.176                        fab_logic_0/counter2_RNICDT96[0]:B (f)
               +     0.568          cell: ADLIB:OR3A
  7.744                        fab_logic_0/counter2_RNICDT96[0]:Y (f)
               +     1.788          net: fab_logic_0/N_53
  9.532                        fab_logic_0/counter2_RNO[6]:C (f)
               +     0.660          cell: ADLIB:XA1
  10.192                       fab_logic_0/counter2_RNO[6]:Y (f)
               +     0.320          net: fab_logic_0/N_16
  10.512                       fab_logic_0/counter2[6]/U0:B (f)
               +     0.563          cell: ADLIB:MX2
  11.075                       fab_logic_0/counter2[6]/U0:Y (f)
               +     0.311          net: fab_logic_0/counter2[6]/Y
  11.386                       fab_logic_0/counter2[6]/U1:D (f)
                                    
  11.386                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.694          net: FAB_CLK
  N/C                          fab_logic_0/counter2[6]/U1:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1C0
  N/C                          fab_logic_0/counter2[6]/U1:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin ACE_Simul_Samp_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          ACE_Simul_Samp_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.139
  External Setup (ns):         -1.661


Expanded Path 1
  From: MSS_RESET_N
  To: ACE_Simul_Samp_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        ACE_Simul_Samp_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        ACE_Simul_Samp_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: ACE_Simul_Samp_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        ACE_Simul_Samp_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.459          net: ACE_Simul_Samp_MSS_0/GLA0
  N/C                          ACE_Simul_Samp_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.139          Library setup time: ADLIB:MSS_APB_IP
  N/C                          ACE_Simul_Samp_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

