library verilog;
use verilog.vl_types.all;
entity MSSTOP is
    port(
        MSSPSEL         : out    vl_logic;
        MSSPENABLE      : out    vl_logic;
        MSSPWRITE       : out    vl_logic;
        MSSPREADY       : in     vl_logic;
        MSSPSLVERR      : in     vl_logic;
        FABPSEL         : in     vl_logic;
        FABPENABLE      : in     vl_logic;
        FABPWRITE       : in     vl_logic;
        FABPREADY       : out    vl_logic;
        FABPSLVERR      : out    vl_logic;
        FAB_CLK         : out    vl_logic;
        M2F_RESET_N     : out    vl_logic;
        FABACETRIG      : in     vl_logic;
        MSSPADDR        : out    vl_logic_vector(19 downto 0);
        MSSPRDATA       : in     vl_logic_vector(31 downto 0);
        MSSPWDATA       : out    vl_logic_vector(31 downto 0);
        FABPADDR        : in     vl_logic_vector(31 downto 0);
        FABPRDATA       : out    vl_logic_vector(31 downto 0);
        FABPWDATA       : in     vl_logic_vector(31 downto 0);
        ACEFLAGS        : out    vl_logic_vector(31 downto 0);
        ADCDirectInput_0: in     vl_logic;
        ADCDirectInput_1: in     vl_logic;
        ADCDirectInput_2: in     vl_logic;
        SDD_0           : out    vl_logic;
        SDD_1           : out    vl_logic;
        VAREF0          : in     vl_logic;
        VAREF1          : in     vl_logic;
        MSS_RESET_N_0   : in     vl_logic
    );
end MSSTOP;
