library verilog;
use verilog.vl_types.all;
entity tach_if is
    generic(
        TACH_NUM        : integer := 1
    );
    port(
        PCLK            : in     vl_logic;
        PRESETN         : in     vl_logic;
        TACHIN          : in     vl_logic;
        TACHMODE        : in     vl_logic;
        TACH_EDGE       : in     vl_logic;
        TACHSTATUS      : in     vl_logic;
        status_clear    : in     vl_logic;
        tach_cnt_clk    : in     vl_logic;
        TACHPULSEDUR    : out    vl_logic_vector(15 downto 0);
        update_status   : out    vl_logic
    );
end tach_if;
