library verilog;
use verilog.vl_types.all;
entity timebase is
    generic(
        APB_DWIDTH      : integer := 8
    );
    port(
        PRESETN         : in     vl_logic;
        PCLK            : in     vl_logic;
        period_reg      : in     vl_logic_vector;
        prescale_reg    : in     vl_logic_vector;
        period_cnt      : out    vl_logic_vector;
        sync_pulse      : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of APB_DWIDTH : constant is 1;
end timebase;
