Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 19:44:00 2011


Design: ACE_Simul_Samp
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                10.342
Frequency (MHz):            96.693
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.889
External Hold (ns):         1.452
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        fab_logic_0/counter2[22]/U1:CLK
  To:                          fab_logic_0/counter2[12]/U1:D
  Delay (ns):                  9.808
  Slack (ns):
  Arrival (ns):                10.438
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         10.342

Path 2
  From:                        fab_logic_0/counter2[26]/U1:CLK
  To:                          fab_logic_0/counter2[12]/U1:D
  Delay (ns):                  9.686
  Slack (ns):
  Arrival (ns):                10.304
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         10.208

Path 3
  From:                        fab_logic_0/counter2[22]/U1:CLK
  To:                          fab_logic_0/counter2[10]/U1:D
  Delay (ns):                  9.678
  Slack (ns):
  Arrival (ns):                10.308
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         10.205

Path 4
  From:                        fab_logic_0/counter2[26]/U1:CLK
  To:                          fab_logic_0/counter2[10]/U1:D
  Delay (ns):                  9.556
  Slack (ns):
  Arrival (ns):                10.174
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         10.071

Path 5
  From:                        fab_logic_0/counter2[23]/U1:CLK
  To:                          fab_logic_0/counter2[12]/U1:D
  Delay (ns):                  9.540
  Slack (ns):
  Arrival (ns):                10.165
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         10.069


Expanded Path 1
  From: fab_logic_0/counter2[22]/U1:CLK
  To: fab_logic_0/counter2[12]/U1:D
  data required time                             N/C
  data arrival time                          -   10.438
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.630          net: FAB_CLK
  0.630                        fab_logic_0/counter2[22]/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  1.301                        fab_logic_0/counter2[22]/U1:Q (f)
               +     0.838          net: fab_logic_0/counter2[22]
  2.139                        fab_logic_0/counter2_RNIHHRF[22]:A (f)
               +     0.462          cell: ADLIB:NOR2
  2.601                        fab_logic_0/counter2_RNIHHRF[22]:Y (r)
               +     0.306          net: fab_logic_0/counter2_3_i_o3_6[0]
  2.907                        fab_logic_0/counter2_RNI83OV[16]:A (r)
               +     0.604          cell: ADLIB:NOR3A
  3.511                        fab_logic_0/counter2_RNI83OV[16]:Y (r)
               +     0.889          net: fab_logic_0/counter2_3_i_o3_16[0]
  4.400                        fab_logic_0/counter2_RNI82FV1[30]:C (r)
               +     0.606          cell: ADLIB:NOR3C
  5.006                        fab_logic_0/counter2_RNI82FV1[30]:Y (r)
               +     0.306          net: fab_logic_0/counter2_3_i_o3_21[0]
  5.312                        fab_logic_0/counter2_RNIO51N5[2]:B (r)
               +     0.568          cell: ADLIB:OR3C
  5.880                        fab_logic_0/counter2_RNIO51N5[2]:Y (f)
               +     1.047          net: fab_logic_0/N_43
  6.927                        fab_logic_0/counter2_RNICDT96[0]:B (f)
               +     0.568          cell: ADLIB:OR3A
  7.495                        fab_logic_0/counter2_RNICDT96[0]:Y (f)
               +     1.204          net: fab_logic_0/N_53
  8.699                        fab_logic_0/counter2_RNO[12]:B (f)
               +     0.574          cell: ADLIB:NOR2B
  9.273                        fab_logic_0/counter2_RNO[12]:Y (f)
               +     0.306          net: fab_logic_0/N_29
  9.579                        fab_logic_0/counter2[12]/U0:B (f)
               +     0.563          cell: ADLIB:MX2
  10.142                       fab_logic_0/counter2[12]/U0:Y (f)
               +     0.296          net: fab_logic_0/counter2[12]/Y
  10.438                       fab_logic_0/counter2[12]/U1:D (f)
                                    
  10.438                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.618          net: FAB_CLK
  N/C                          fab_logic_0/counter2[12]/U1:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1C0
  N/C                          fab_logic_0/counter2[12]/U1:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin ACE_Simul_Samp_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          ACE_Simul_Samp_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.196
  External Setup (ns):         -1.889


Expanded Path 1
  From: MSS_RESET_N
  To: ACE_Simul_Samp_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        ACE_Simul_Samp_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        ACE_Simul_Samp_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: ACE_Simul_Samp_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        ACE_Simul_Samp_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.630          net: ACE_Simul_Samp_MSS_0/GLA0
  N/C                          ACE_Simul_Samp_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.196          Library setup time: ADLIB:MSS_APB_IP
  N/C                          ACE_Simul_Samp_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain ACE_Simul_Samp_MSS_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

