library verilog;
use verilog.vl_types.all;
entity pwm_gen is
    generic(
        PWM_NUM         : integer := 8;
        APB_DWIDTH      : integer := 8;
        DAC_MODE        : integer := 0
    );
    port(
        PRESETN         : in     vl_logic;
        PCLK            : in     vl_logic;
        PWM             : out    vl_logic_vector;
        period_cnt      : in     vl_logic_vector;
        pwm_enable_reg  : in     vl_logic_vector;
        pwm_posedge_reg : in     vl_logic_vector;
        pwm_negedge_reg : in     vl_logic_vector;
        sync_pulse      : in     vl_logic
    );
end pwm_gen;
