library verilog;
use verilog.vl_types.all;
entity reg_if is
    generic(
        PWM_NUM         : integer := 8;
        APB_DWIDTH      : integer := 8;
        FIXED_PRESCALE_EN: integer := 0;
        FIXED_PRESCALE  : integer := 8;
        FIXED_PERIOD_EN : integer := 0;
        FIXED_PERIOD    : integer := 8;
        DAC_MODE        : integer := 0;
        SHADOW_REG_EN   : integer := 0;
        FIXED_PWM_POS_EN: integer := 0;
        FIXED_PWM_POSEDGE: integer := 0;
        FIXED_PWM_NEG_EN: integer := 0;
        FIXED_PWM_NEGEDGE: integer := 0
    );
    port(
        PCLK            : in     vl_logic;
        PRESETN         : in     vl_logic;
        PSEL            : in     vl_logic;
        PENABLE         : in     vl_logic;
        PWRITE          : in     vl_logic;
        PADDR           : in     vl_logic_vector(5 downto 0);
        PWDATA          : in     vl_logic_vector;
        PRDATA_regif    : out    vl_logic_vector;
        period_cnt      : in     vl_logic_vector;
        sync_pulse      : in     vl_logic;
        PWM_STRETCH     : in     vl_logic_vector;
        period_out_wire : out    vl_logic_vector;
        prescale_out_wire: out    vl_logic_vector;
        pwm_enable_out_wire: out    vl_logic_vector;
        pwm_posedge_out_wire: out    vl_logic_vector;
        pwm_negedge_out_wire: out    vl_logic_vector
    );
end reg_if;
