Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 20:25:26 2011


Design: SDTOP
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                8.742
Frequency (MHz):            114.390
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                9.176
Frequency (MHz):            108.980
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      6.095
Max Clock-To-Out (ns):      10.992

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        -4.586
External Hold (ns):         3.536
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSSTOP_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_aclk

Path 1
  From:                        MyAPBFabricMaster_0/FPGA_TRIGGER/U1:CLK
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABACETRIG
  Delay (ns):                  3.051
  Slack (ns):                  6.636
  Arrival (ns):                8.354
  Required (ns):               14.990
  Setup (ns):                  -1.606


Expanded Path 1
  From: MyAPBFabricMaster_0/FPGA_TRIGGER/U1:CLK
  To: MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABACETRIG
  data required time                             14.990
  data arrival time                          -   8.354
  slack                                          6.636
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.630          Clock generation
  4.630
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.630                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.630                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.673          net: FAB_CLK
  5.303                        MyAPBFabricMaster_0/FPGA_TRIGGER/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  5.974                        MyAPBFabricMaster_0/FPGA_TRIGGER/U1:Q (f)
               +     1.797          net: MyAPBFabricMaster_0_FPGA_TRIGGER
  7.771                        MSSTOP_0/MSS_ADLIB_INST/U_73:PIN5 (f)
               +     0.095          cell: ADLIB:MSS_IF
  7.866                        MSSTOP_0/MSS_ADLIB_INST/U_73:PIN5INT (f)
               +     0.488          net: MSSTOP_0/MSS_ADLIB_INST/FABACETRIGINT_NET
  8.354                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABACETRIG (f)
                                    
  8.354                        data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       mss_aclk
               +     0.000          Clock source
  10.000                       MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK (r)
               +     3.384          Clock generation
  13.384
               -    -1.606          Library setup time: ADLIB:MSS_APB_IP
  14.990                       MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABACETRIG
                                    
  14.990                       data required time


END SET mss_ccc_gla1 to mss_aclk

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  Delay (ns):                  10.919
  Slack (ns):                  1.258
  Arrival (ns):                14.303
  Required (ns):               15.561
  Setup (ns):                  -2.177
  Minimum Period (ns):         8.742

Path 2
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  10.817
  Slack (ns):                  1.361
  Arrival (ns):                14.201
  Required (ns):               15.562
  Setup (ns):                  -2.178
  Minimum Period (ns):         8.639

Path 3
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]
  Delay (ns):                  10.766
  Slack (ns):                  1.410
  Arrival (ns):                14.150
  Required (ns):               15.560
  Setup (ns):                  -2.176
  Minimum Period (ns):         8.590

Path 4
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]
  Delay (ns):                  10.648
  Slack (ns):                  1.531
  Arrival (ns):                14.032
  Required (ns):               15.563
  Setup (ns):                  -2.179
  Minimum Period (ns):         8.469

Path 5
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[7]
  Delay (ns):                  10.606
  Slack (ns):                  1.570
  Arrival (ns):                13.990
  Required (ns):               15.560
  Setup (ns):                  -2.176
  Minimum Period (ns):         8.430


Expanded Path 1
  From: MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  data required time                             15.561
  data arrival time                          -   14.303
  slack                                          1.258
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.384          Clock generation
  3.384
               +     2.863          cell: ADLIB:MSS_APB_IP
  6.247                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[4] (r)
               +     0.122          net: MSSTOP_0/MSS_ADLIB_INST/MSSPADDR[4]INT_NET
  6.369                        MSSTOP_0/MSS_ADLIB_INST/U_31:PIN2INT (r)
               +     0.095          cell: ADLIB:MSS_IF
  6.464                        MSSTOP_0/MSS_ADLIB_INST/U_31:PIN2 (r)
               +     1.176          net: MSSTOP_0_MSS_MASTER_APB_PADDR_[4]
  7.640                        corepwm_0/genblk96.genblk97.reg_if/genblk12.prdata_rd_mux1.PRDATA_generated17_0:A (r)
               +     0.470          cell: ADLIB:NOR2A
  8.110                        corepwm_0/genblk96.genblk97.reg_if/genblk12.prdata_rd_mux1.PRDATA_generated17_0:Y (r)
               +     1.321          net: corepwm_0/genblk96_genblk97_reg_if/PRDATA_generated17_0
  9.431                        corepwm_0/genblk96.genblk97.reg_if/genblk12.prdata_rd_mux1.PRDATA_generated17:A (r)
               +     0.445          cell: ADLIB:OR3B
  9.876                        corepwm_0/genblk96.genblk97.reg_if/genblk12.prdata_rd_mux1.PRDATA_generated17:Y (f)
               +     1.142          net: corepwm_0/genblk96_genblk97_reg_if/PRDATA_generated17
  11.018                       corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg_RNITT7B[5]:B (f)
               +     0.592          cell: ADLIB:OR2A
  11.610                       corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg_RNITT7B[5]:Y (f)
               +     0.306          net: corepwm_0_genblk96_genblk97_reg_if_genblk0_gen_pos_neg_shregs[1]_psh_negedge_reg_m[5]
  11.916                       CoreAPB3_0/u_mux_p_to_b3/PRDATA_4:B (f)
               +     0.895          cell: ADLIB:AOI1
  12.811                       CoreAPB3_0/u_mux_p_to_b3/PRDATA_4:Y (r)
               +     0.987          net: PRDATA_4
  13.798                       MSSTOP_0/MSS_ADLIB_INST/U_38:PIN5 (r)
               +     0.079          cell: ADLIB:MSS_IF
  13.877                       MSSTOP_0/MSS_ADLIB_INST/U_38:PIN5INT (r)
               +     0.426          net: MSSTOP_0/MSS_ADLIB_INST/MSSPRDATA[4]INT_NET
  14.303                       MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4] (r)
                                    
  14.303                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       mss_fabric_interface_clock
               +     0.000          Clock source
  10.000                       MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.384          Clock generation
  13.384
               -    -2.177          Library setup time: ADLIB:MSS_APB_IP
  15.561                       MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
                                    
  15.561                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        corepwm_0/genblk96.genblk97.reg_if/period_reg[0]/U1:CLK
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  6.436
  Slack (ns):                  3.834
  Arrival (ns):                11.728
  Required (ns):               15.562
  Setup (ns):                  -2.178

Path 2
  From:                        corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[1]/U1:CLK
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  5.982
  Slack (ns):                  4.256
  Arrival (ns):                11.306
  Required (ns):               15.562
  Setup (ns):                  -2.178

Path 3
  From:                        corepwm_0/genblk96.genblk97.reg_if/period_reg[2]/U1:CLK
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]
  Delay (ns):                  5.697
  Slack (ns):                  4.563
  Arrival (ns):                11.000
  Required (ns):               15.563
  Setup (ns):                  -2.179

Path 4
  From:                        corepwm_0/genblk96.genblk97.reg_if/period_reg[4]/U1:CLK
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  Delay (ns):                  5.480
  Slack (ns):                  4.765
  Arrival (ns):                10.796
  Required (ns):               15.561
  Setup (ns):                  -2.177

Path 5
  From:                        corepwm_0/genblk96.genblk97.reg_if/period_reg[5]/U1:CLK
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[5]
  Delay (ns):                  5.456
  Slack (ns):                  4.790
  Arrival (ns):                10.772
  Required (ns):               15.562
  Setup (ns):                  -2.178


Expanded Path 1
  From: corepwm_0/genblk96.genblk97.reg_if/period_reg[0]/U1:CLK
  To: MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  data required time                             15.562
  data arrival time                          -   11.728
  slack                                          3.834
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.630          Clock generation
  4.630
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.630                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.630                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.662          net: FAB_CLK
  5.292                        corepwm_0/genblk96.genblk97.reg_if/period_reg[0]/U1:CLK (r)
               +     0.528          cell: ADLIB:DFN1C0
  5.820                        corepwm_0/genblk96.genblk97.reg_if/period_reg[0]/U1:Q (r)
               +     1.632          net: corepwm_0/period_reg[0]
  7.452                        corepwm_0/genblk96.genblk97.reg_if/period_reg_RNIBV6C[0]:A (r)
               +     0.470          cell: ADLIB:NOR2A
  7.922                        corepwm_0/genblk96.genblk97.reg_if/period_reg_RNIBV6C[0]:Y (r)
               +     0.296          net: corepwm_0/genblk96_genblk97_reg_if/period_reg_m[0]
  8.218                        corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg_RNI4TEN[1]:C (r)
               +     0.699          cell: ADLIB:AO1A
  8.917                        corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg_RNI4TEN[1]:Y (r)
               +     0.306          net: corepwm_0_genblk96_genblk97_reg_if_PRDATA_regif_0_iv_1[0]
  9.223                        CoreAPB3_0/u_mux_p_to_b3/PRDATA_0:B (r)
               +     0.895          cell: ADLIB:OA1B
  10.118                       CoreAPB3_0/u_mux_p_to_b3/PRDATA_0:Y (r)
               +     1.110          net: PRDATA_0
  11.228                       MSSTOP_0/MSS_ADLIB_INST/U_36:PIN6 (r)
               +     0.076          cell: ADLIB:MSS_IF
  11.304                       MSSTOP_0/MSS_ADLIB_INST/U_36:PIN6INT (r)
               +     0.424          net: MSSTOP_0/MSS_ADLIB_INST/MSSPRDATA[0]INT_NET
  11.728                       MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0] (r)
                                    
  11.728                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       mss_fabric_interface_clock
               +     0.000          Clock source
  10.000                       MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.384          Clock generation
  13.384
               -    -2.178          Library setup time: ADLIB:MSS_APB_IP
  15.562                       MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
                                    
  15.562                       data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        corepwm_0/genblk96.genblk97.reg_if/period_reg[0]/U1:CLK
  To:                          corepwm_0/genblk100.genblk102.genblk103.timebase/period_cnt[2]:D
  Delay (ns):                  8.665
  Slack (ns):                  0.824
  Arrival (ns):                13.957
  Required (ns):               14.781
  Setup (ns):                  0.522
  Minimum Period (ns):         9.176

Path 2
  From:                        corepwm_0/genblk96.genblk97.reg_if/period_reg[0]/U1:CLK
  To:                          corepwm_0/genblk100.genblk102.genblk103.timebase/period_cnt[7]:D
  Delay (ns):                  8.594
  Slack (ns):                  0.894
  Arrival (ns):                13.886
  Required (ns):               14.780
  Setup (ns):                  0.522
  Minimum Period (ns):         9.106

Path 3
  From:                        corepwm_0/genblk96.genblk97.reg_if/period_reg[5]/U1:CLK
  To:                          corepwm_0/genblk100.genblk102.genblk103.timebase/period_cnt[2]:D
  Delay (ns):                  8.488
  Slack (ns):                  0.977
  Arrival (ns):                13.804
  Required (ns):               14.781
  Setup (ns):                  0.522
  Minimum Period (ns):         9.023

Path 4
  From:                        corepwm_0/genblk100.genblk102.genblk103.timebase/period_cnt[0]:CLK
  To:                          corepwm_0/genblk100.genblk102.genblk103.timebase/period_cnt[2]:D
  Delay (ns):                  8.500
  Slack (ns):                  0.989
  Arrival (ns):                13.792
  Required (ns):               14.781
  Setup (ns):                  0.522
  Minimum Period (ns):         9.011

Path 5
  From:                        corepwm_0/genblk100.genblk102.genblk103.timebase/period_cnt[0]:CLK
  To:                          corepwm_0/genblk96.genblk97.reg_if/period_reg[3]/U1:D
  Delay (ns):                  8.465
  Slack (ns):                  1.023
  Arrival (ns):                13.757
  Required (ns):               14.780
  Setup (ns):                  0.522
  Minimum Period (ns):         8.977


Expanded Path 1
  From: corepwm_0/genblk96.genblk97.reg_if/period_reg[0]/U1:CLK
  To: corepwm_0/genblk100.genblk102.genblk103.timebase/period_cnt[2]:D
  data required time                             14.781
  data arrival time                          -   13.957
  slack                                          0.824
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.630          Clock generation
  4.630
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.630                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.630                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.662          net: FAB_CLK
  5.292                        corepwm_0/genblk96.genblk97.reg_if/period_reg[0]/U1:CLK (r)
               +     0.528          cell: ADLIB:DFN1C0
  5.820                        corepwm_0/genblk96.genblk97.reg_if/period_reg[0]/U1:Q (r)
               +     0.649          net: corepwm_0/period_reg[0]
  6.469                        corepwm_0/genblk100.genblk102.genblk103.timebase/un1_period_cnt_0_I_24:A (r)
               +     0.470          cell: ADLIB:NOR2A
  6.939                        corepwm_0/genblk100.genblk102.genblk103.timebase/un1_period_cnt_0_I_24:Y (r)
               +     0.296          net: corepwm_0/genblk100_genblk102_genblk103_timebase/N_10
  7.235                        corepwm_0/genblk100.genblk102.genblk103.timebase/un1_period_cnt_0_I_26:C (r)
               +     0.698          cell: ADLIB:AO1C
  7.933                        corepwm_0/genblk100.genblk102.genblk103.timebase/un1_period_cnt_0_I_26:Y (f)
               +     0.623          net: corepwm_0/genblk100_genblk102_genblk103_timebase/N_12
  8.556                        corepwm_0/genblk100.genblk102.genblk103.timebase/un1_period_cnt_0_I_31:A (f)
               +     0.895          cell: ADLIB:OA1A
  9.451                        corepwm_0/genblk100.genblk102.genblk103.timebase/un1_period_cnt_0_I_31:Y (r)
               +     0.306          net: corepwm_0/genblk100_genblk102_genblk103_timebase/N_17_0
  9.757                        corepwm_0/genblk100.genblk102.genblk103.timebase/un1_period_cnt_0_I_32:A (r)
               +     0.895          cell: ADLIB:OA1
  10.652                       corepwm_0/genblk100.genblk102.genblk103.timebase/un1_period_cnt_0_I_32:Y (r)
               +     0.306          net: corepwm_0/genblk100_genblk102_genblk103_timebase/DWACT_COMP0_E[2]
  10.958                       corepwm_0/genblk100.genblk102.genblk103.timebase/un1_period_cnt_0_I_39:B (r)
               +     0.516          cell: ADLIB:AO1
  11.474                       corepwm_0/genblk100.genblk102.genblk103.timebase/un1_period_cnt_0_I_39:Y (r)
               +     1.600          net: corepwm_0/genblk100_genblk102_genblk103_timebase/N_51_i
  13.074                       corepwm_0/genblk100.genblk102.genblk103.timebase/period_cnt_RNO[2]:C (r)
               +     0.587          cell: ADLIB:XA1
  13.661                       corepwm_0/genblk100.genblk102.genblk103.timebase/period_cnt_RNO[2]:Y (r)
               +     0.296          net: corepwm_0/genblk100_genblk102_genblk103_timebase/N_7
  13.957                       corepwm_0/genblk100.genblk102.genblk103.timebase/period_cnt[2]:D (r)
                                    
  13.957                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       mss_ccc_gla1
               +     0.000          Clock source
  10.000                       MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.630          Clock generation
  14.630
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  14.630                       MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  14.630                       MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.673          net: FAB_CLK
  15.303                       corepwm_0/genblk100.genblk102.genblk103.timebase/period_cnt[2]:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1C0
  14.781                       corepwm_0/genblk100.genblk102.genblk103.timebase/period_cnt[2]:D
                                    
  14.781                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        corepwm_0/genblk104.genblk105.pwm_gen/genblk33.PWM_output_generation[1].genblk34.PWM_int[1]/U1:CLK
  To:                          PWM[1]
  Delay (ns):                  5.700
  Slack (ns):
  Arrival (ns):                10.992
  Required (ns):
  Clock to Out (ns):           10.992


Expanded Path 1
  From: corepwm_0/genblk104.genblk105.pwm_gen/genblk33.PWM_output_generation[1].genblk34.PWM_int[1]/U1:CLK
  To: PWM[1]
  data required time                             N/C
  data arrival time                          -   10.992
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.630          Clock generation
  4.630
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.630                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.630                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.662          net: FAB_CLK
  5.292                        corepwm_0/genblk104.genblk105.pwm_gen/genblk33.PWM_output_generation[1].genblk34.PWM_int[1]/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  5.963                        corepwm_0/genblk104.genblk105.pwm_gen/genblk33.PWM_output_generation[1].genblk34.PWM_int[1]/U1:Q (f)
               +     1.060          net: PWM_c[1]
  7.023                        PWM_pad[1]/U0/U1:D (f)
               +     0.600          cell: ADLIB:IOTRI_OB_EB
  7.623                        PWM_pad[1]/U0/U1:DOUT (f)
               +     0.000          net: PWM_pad[1]/U0/NET1
  7.623                        PWM_pad[1]/U0/U0:D (f)
               +     3.369          cell: ADLIB:IOPAD_TRI
  10.992                       PWM_pad[1]/U0/U0:PAD (f)
               +     0.000          net: PWM[1]
  10.992                       PWM[1] (f)
                                    
  10.992                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.630          Clock generation
  N/C
                                    
  N/C                          PWM[1] (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_aclk to mss_ccc_gla1

Path 1
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK
  To:                          MyAPBFabricMaster_0/PWDATA_M_1[0]/U1:D
  Delay (ns):                  10.300
  Slack (ns):                  1.097
  Arrival (ns):                13.684
  Required (ns):               14.781
  Setup (ns):                  0.522

Path 2
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK
  To:                          MyAPBFabricMaster_0/PSEL_M/U1:D
  Delay (ns):                  10.124
  Slack (ns):                  1.319
  Arrival (ns):                13.508
  Required (ns):               14.827
  Setup (ns):                  0.522

Path 3
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK
  To:                          MyAPBFabricMaster_0/PADDR_M_1[3]/U1:D
  Delay (ns):                  10.027
  Slack (ns):                  1.367
  Arrival (ns):                13.411
  Required (ns):               14.778
  Setup (ns):                  0.522

Path 4
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK
  To:                          MyAPBFabricMaster_0/PADDR_M_1[6]/U1:D
  Delay (ns):                  10.032
  Slack (ns):                  1.411
  Arrival (ns):                13.416
  Required (ns):               14.827
  Setup (ns):                  0.522

Path 5
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK
  To:                          MyAPBFabricMaster_0/PADDR_M_1[17]:D
  Delay (ns):                  9.894
  Slack (ns):                  1.535
  Arrival (ns):                13.278
  Required (ns):               14.813
  Setup (ns):                  0.490


Expanded Path 1
  From: MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK
  To: MyAPBFabricMaster_0/PWDATA_M_1[0]/U1:D
  data required time                             14.781
  data arrival time                          -   13.684
  slack                                          1.097
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_aclk
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK (r)
               +     3.384          Clock generation
  3.384
               +     4.215          cell: ADLIB:MSS_APB_IP
  7.599                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACEFLAGS[15] (f)
               +     0.193          net: MSSTOP_0/MSS_ADLIB_INST/ACEFLAGS[15]INT_NET
  7.792                        MSSTOP_0/MSS_ADLIB_INST/U_80:PIN2INT (f)
               +     0.094          cell: ADLIB:MSS_IF
  7.886                        MSSTOP_0/MSS_ADLIB_INST/U_80:PIN2 (f)
               +     1.607          net: MSSTOP_0_ACEFLAGS15to15
  9.493                        MyAPBFabricMaster_0/state_RNIGES4[0]:B (f)
               +     0.571          cell: ADLIB:NOR2B
  10.064                       MyAPBFabricMaster_0/state_RNIGES4[0]:Y (f)
               +     1.253          net: MyAPBFabricMaster_0/state_ns[1]
  11.317                       MyAPBFabricMaster_0/state_RNI3RKD[3]:A (f)
               +     0.489          cell: ADLIB:OR2
  11.806                       MyAPBFabricMaster_0/state_RNI3RKD[3]:Y (f)
               +     1.094          net: MyAPBFabricMaster_0/N_164
  12.900                       MyAPBFabricMaster_0/PWDATA_M_1[0]/U0:S (f)
               +     0.473          cell: ADLIB:MX2
  13.373                       MyAPBFabricMaster_0/PWDATA_M_1[0]/U0:Y (f)
               +     0.311          net: MyAPBFabricMaster_0/PWDATA_M_1[0]/Y
  13.684                       MyAPBFabricMaster_0/PWDATA_M_1[0]/U1:D (f)
                                    
  13.684                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       mss_ccc_gla1
               +     0.000          Clock source
  10.000                       MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.630          Clock generation
  14.630
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  14.630                       MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  14.630                       MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.673          net: FAB_CLK
  15.303                       MyAPBFabricMaster_0/PWDATA_M_1[0]/U1:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1C0
  14.781                       MyAPBFabricMaster_0/PWDATA_M_1[0]/U1:D
                                    
  14.781                       data required time


END SET mss_aclk to mss_ccc_gla1

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[8]/U1:D
  Delay (ns):                  9.725
  Slack (ns):                  1.725
  Arrival (ns):                13.109
  Required (ns):               14.834
  Setup (ns):                  0.490

Path 2
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[2]/U1:D
  Delay (ns):                  9.649
  Slack (ns):                  1.767
  Arrival (ns):                13.033
  Required (ns):               14.800
  Setup (ns):                  0.490

Path 3
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[1]/U1:D
  Delay (ns):                  9.514
  Slack (ns):                  1.936
  Arrival (ns):                12.898
  Required (ns):               14.834
  Setup (ns):                  0.490

Path 4
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[5]/U1:D
  Delay (ns):                  9.512
  Slack (ns):                  1.938
  Arrival (ns):                12.896
  Required (ns):               14.834
  Setup (ns):                  0.490

Path 5
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[7]/U1:D
  Delay (ns):                  9.512
  Slack (ns):                  1.938
  Arrival (ns):                12.896
  Required (ns):               14.834
  Setup (ns):                  0.490


Expanded Path 1
  From: MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To: corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[8]/U1:D
  data required time                             14.834
  data arrival time                          -   13.109
  slack                                          1.725
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.384          Clock generation
  3.384
               +     2.863          cell: ADLIB:MSS_APB_IP
  6.247                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[4] (f)
               +     0.155          net: MSSTOP_0/MSS_ADLIB_INST/MSSPADDR[4]INT_NET
  6.402                        MSSTOP_0/MSS_ADLIB_INST/U_31:PIN2INT (f)
               +     0.094          cell: ADLIB:MSS_IF
  6.496                        MSSTOP_0/MSS_ADLIB_INST/U_31:PIN2 (f)
               +     1.107          net: MSSTOP_0_MSS_MASTER_APB_PADDR_[4]
  7.603                        corepwm_0/genblk96.genblk97.reg_if/genblk12.prdata_rd_mux1.PRDATA_generated17_0:A (f)
               +     0.571          cell: ADLIB:NOR2A
  8.174                        corepwm_0/genblk96.genblk97.reg_if/genblk12.prdata_rd_mux1.PRDATA_generated17_0:Y (f)
               +     1.464          net: corepwm_0/genblk96_genblk97_reg_if/PRDATA_generated17_0
  9.638                        corepwm_0/genblk96.genblk97.reg_if/genblk12.prdata_rd_mux1.PRDATA_generated17:A (f)
               +     0.327          cell: ADLIB:OR3B
  9.965                        corepwm_0/genblk96.genblk97.reg_if/genblk12.prdata_rd_mux1.PRDATA_generated17:Y (r)
               +     1.091          net: corepwm_0/genblk96_genblk97_reg_if/PRDATA_generated17
  11.056                       corepwm_0/genblk96.genblk97.reg_if/psh_negedge_reg_1_sqmuxa:C (r)
               +     0.552          cell: ADLIB:NOR3A
  11.608                       corepwm_0/genblk96.genblk97.reg_if/psh_negedge_reg_1_sqmuxa:Y (f)
               +     0.758          net: corepwm_0/genblk96_genblk97_reg_if/psh_negedge_reg_1_sqmuxa
  12.366                       corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[8]/U0:S (f)
               +     0.437          cell: ADLIB:MX2
  12.803                       corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[8]/U0:Y (r)
               +     0.306          net: corepwm_0/genblk96_genblk97_reg_if/genblk0_gen_pos_neg_shregs[1]_psh_negedge_reg[8]/Y
  13.109                       corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[8]/U1:D (r)
                                    
  13.109                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       mss_ccc_gla1
               +     0.000          Clock source
  10.000                       MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.630          Clock generation
  14.630
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  14.630                       MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  14.630                       MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.694          net: FAB_CLK
  15.324                       corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[8]/U1:CLK (r)
               -     0.490          Library setup time: ADLIB:DFN1C0
  14.834                       corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[8]/U1:D
                                    
  14.834                       data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[1]/U1:CLR
  Delay (ns):                  7.076
  Slack (ns):                  4.593
  Arrival (ns):                10.460
  Required (ns):               15.053
  Setup (ns):

Path 2
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[6]/U1:CLR
  Delay (ns):                  7.076
  Slack (ns):                  4.593
  Arrival (ns):                10.460
  Required (ns):               15.053
  Setup (ns):

Path 3
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          corepwm_0/genblk100.genblk102.genblk103.timebase/period_cnt[4]:CLR
  Delay (ns):                  6.869
  Slack (ns):                  4.792
  Arrival (ns):                10.253
  Required (ns):               15.045
  Setup (ns):

Path 4
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          corepwm_0/genblk96.genblk97.reg_if/period_reg[4]/U1:CLR
  Delay (ns):                  6.762
  Slack (ns):                  4.899
  Arrival (ns):                10.146
  Required (ns):               15.045
  Setup (ns):

Path 5
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          corepwm_0/genblk96.genblk97.reg_if/period_reg[5]/U1:CLR
  Delay (ns):                  6.688
  Slack (ns):                  4.973
  Arrival (ns):                10.072
  Required (ns):               15.045
  Setup (ns):


Expanded Path 1
  From: MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[1]/U1:CLR
  data required time                             15.053
  data arrival time                          -   10.460
  slack                                          4.593
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.925          Clock generation
  2.925
               +     0.459          net: MSSTOP_0/GLA0
  3.384                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     3.331          cell: ADLIB:MSS_APB_IP
  6.715                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.121          net: MSSTOP_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  6.836                        MSSTOP_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.095          cell: ADLIB:MSS_IF
  6.931                        MSSTOP_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     3.529          net: MSSTOP_0_M2F_RESET_N
  10.460                       corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[1]/U1:CLR (r)
                                    
  10.460                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       mss_ccc_gla1
               +     0.000          Clock source
  10.000                       MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.630          Clock generation
  14.630
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  14.630                       MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  14.630                       MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.694          net: FAB_CLK
  15.324                       corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[1]/U1:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1C0
  15.053                       corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[1]/U1:CLR
                                    
  15.053                       data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.139
  External Setup (ns):         -4.586


Expanded Path 1
  From: MSS_RESET_N
  To: MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSSTOP_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        MSSTOP_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSSTOP_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.925          Clock generation
  N/C
               +     0.459          net: MSSTOP_0/GLA0
  N/C                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.139          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSSTOP_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

