Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 20:25:26 2011


Design: SDTOP
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                8.742
Frequency (MHz):            114.390
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                9.176
Frequency (MHz):            108.980
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      6.095
Max Clock-To-Out (ns):      10.992

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        -4.586
External Hold (ns):         3.536
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSSTOP_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_aclk

Path 1
  From:                        MyAPBFabricMaster_0/FPGA_TRIGGER/U1:CLK
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABACETRIG
  Delay (ns):                  1.423
  Slack (ns):                  1.782
  Arrival (ns):                5.311
  Required (ns):               3.529
  Hold (ns):                   1.056


Expanded Path 1
  From: MyAPBFabricMaster_0/FPGA_TRIGGER/U1:CLK
  To: MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABACETRIG
  data arrival time                              5.311
  data required time                         -   3.529
  slack                                          1.782
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     3.558          Clock generation
  3.558
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.330          net: FAB_CLK
  3.888                        MyAPBFabricMaster_0/FPGA_TRIGGER/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.137                        MyAPBFabricMaster_0/FPGA_TRIGGER/U1:Q (r)
               +     0.931          net: MyAPBFabricMaster_0_FPGA_TRIGGER
  5.068                        MSSTOP_0/MSS_ADLIB_INST/U_73:PIN5 (r)
               +     0.037          cell: ADLIB:MSS_IF
  5.105                        MSSTOP_0/MSS_ADLIB_INST/U_73:PIN5INT (r)
               +     0.206          net: MSSTOP_0/MSS_ADLIB_INST/FABACETRIGINT_NET
  5.311                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABACETRIG (r)
                                    
  5.311                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_aclk
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK (r)
               +     2.473          Clock generation
  2.473
               +     1.056          Library hold time: ADLIB:MSS_APB_IP
  3.529                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABACETRIG
                                    
  3.529                        data required time


END SET mss_ccc_gla1 to mss_aclk

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
  Delay (ns):                  3.301
  Slack (ns):                  1.967
  Arrival (ns):                5.774
  Required (ns):               3.807
  Hold (ns):                   1.334

Path 2
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[5]
  Delay (ns):                  3.806
  Slack (ns):                  2.493
  Arrival (ns):                6.279
  Required (ns):               3.786
  Hold (ns):                   1.313

Path 3
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]
  Delay (ns):                  3.861
  Slack (ns):                  2.547
  Arrival (ns):                6.334
  Required (ns):               3.787
  Hold (ns):                   1.314

Path 4
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]
  Delay (ns):                  3.876
  Slack (ns):                  2.564
  Arrival (ns):                6.349
  Required (ns):               3.785
  Hold (ns):                   1.312

Path 5
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[7]
  Delay (ns):                  3.957
  Slack (ns):                  2.645
  Arrival (ns):                6.430
  Required (ns):               3.785
  Hold (ns):                   1.312


Expanded Path 1
  From: MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
  data arrival time                              5.774
  data required time                         -   3.807
  slack                                          1.967
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.473          Clock generation
  2.473
               +     1.327          cell: ADLIB:MSS_APB_IP
  3.800                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[14] (r)
               +     0.059          net: MSSTOP_0/MSS_ADLIB_INST/MSSPADDR[14]INT_NET
  3.859                        MSSTOP_0/MSS_ADLIB_INST/U_34:PIN3INT (r)
               +     0.040          cell: ADLIB:MSS_IF
  3.899                        MSSTOP_0/MSS_ADLIB_INST/U_34:PIN3 (r)
               +     0.588          net: MSSTOP_0_MSS_MASTER_APB_PADDR_[14]
  4.487                        CoreAPB3_0/iPSELS[7]:A (r)
               +     0.228          cell: ADLIB:OR3C
  4.715                        CoreAPB3_0/iPSELS[7]:Y (f)
               +     0.152          net: CoreAPB3_0_APBmslave7_PSELx
  4.867                        CoreAPB3_0/u_mux_p_to_b3/PRDATA_6:C (f)
               +     0.171          cell: ADLIB:AOI1
  5.038                        CoreAPB3_0/u_mux_p_to_b3/PRDATA_6:Y (r)
               +     0.491          net: PRDATA_6
  5.529                        MSSTOP_0/MSS_ADLIB_INST/U_38:PIN6 (r)
               +     0.036          cell: ADLIB:MSS_IF
  5.565                        MSSTOP_0/MSS_ADLIB_INST/U_38:PIN6INT (r)
               +     0.209          net: MSSTOP_0/MSS_ADLIB_INST/MSSPRDATA[6]INT_NET
  5.774                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6] (r)
                                    
  5.774                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.473          Clock generation
  2.473
               +     1.334          Library hold time: ADLIB:MSS_APB_IP
  3.807                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
                                    
  3.807                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        MyAPBFabricMaster_0/PWDATA_M_1[0]/U1:CLK
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABPWDATA[0]
  Delay (ns):                  0.855
  Slack (ns):                  0.932
  Arrival (ns):                4.743
  Required (ns):               3.811
  Hold (ns):                   1.338

Path 2
  From:                        MyAPBFabricMaster_0/PWDATA_M_1[1]/U1:CLK
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABPWDATA[1]
  Delay (ns):                  1.080
  Slack (ns):                  1.160
  Arrival (ns):                4.970
  Required (ns):               3.810
  Hold (ns):                   1.337

Path 3
  From:                        MyAPBFabricMaster_0/PADDR_M_1[17]:CLK
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABPADDR[30]
  Delay (ns):                  1.108
  Slack (ns):                  1.230
  Arrival (ns):                4.996
  Required (ns):               3.766
  Hold (ns):                   1.293

Path 4
  From:                        MyAPBFabricMaster_0/PSEL_M/U1:CLK
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABPWRITE
  Delay (ns):                  1.093
  Slack (ns):                  1.289
  Arrival (ns):                5.004
  Required (ns):               3.715
  Hold (ns):                   1.242

Path 5
  From:                        MyAPBFabricMaster_0/PSEL_M/U1:CLK
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABPSEL
  Delay (ns):                  1.073
  Slack (ns):                  1.348
  Arrival (ns):                4.984
  Required (ns):               3.636
  Hold (ns):                   1.163


Expanded Path 1
  From: MyAPBFabricMaster_0/PWDATA_M_1[0]/U1:CLK
  To: MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABPWDATA[0]
  data arrival time                              4.743
  data required time                         -   3.811
  slack                                          0.932
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     3.558          Clock generation
  3.558
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.330          net: FAB_CLK
  3.888                        MyAPBFabricMaster_0/PWDATA_M_1[0]/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.137                        MyAPBFabricMaster_0/PWDATA_M_1[0]/U1:Q (r)
               +     0.366          net: PWDATA_M_1[0]
  4.503                        MSSTOP_0/MSS_ADLIB_INST/U_47:PIN6 (r)
               +     0.036          cell: ADLIB:MSS_IF
  4.539                        MSSTOP_0/MSS_ADLIB_INST/U_47:PIN6INT (r)
               +     0.204          net: MSSTOP_0/MSS_ADLIB_INST/FABPWDATA[0]INT_NET
  4.743                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABPWDATA[0] (r)
                                    
  4.743                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.473          Clock generation
  2.473
               +     1.338          Library hold time: ADLIB:MSS_APB_IP
  3.811                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABPWDATA[0]
                                    
  3.811                        data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        MyAPBFabricMaster_0/state[3]:CLK
  To:                          MyAPBFabricMaster_0/state[5]:D
  Delay (ns):                  0.470
  Slack (ns):                  0.474
  Arrival (ns):                4.381
  Required (ns):               3.907
  Hold (ns):                   0.000

Path 2
  From:                        MyAPBFabricMaster_0/counter[2]:CLK
  To:                          MyAPBFabricMaster_0/counter[2]:D
  Delay (ns):                  0.688
  Slack (ns):                  0.672
  Arrival (ns):                4.575
  Required (ns):               3.903
  Hold (ns):                   0.000

Path 3
  From:                        MyAPBFabricMaster_0/PADDR_M_1[17]:CLK
  To:                          MyAPBFabricMaster_0/PADDR_M_1[17]:D
  Delay (ns):                  0.710
  Slack (ns):                  0.694
  Arrival (ns):                4.598
  Required (ns):               3.904
  Hold (ns):                   0.000

Path 4
  From:                        MyAPBFabricMaster_0/counter[12]:CLK
  To:                          MyAPBFabricMaster_0/counter[12]:D
  Delay (ns):                  0.720
  Slack (ns):                  0.704
  Arrival (ns):                4.608
  Required (ns):               3.904
  Hold (ns):                   0.000

Path 5
  From:                        MyAPBFabricMaster_0/counter[9]:CLK
  To:                          MyAPBFabricMaster_0/counter[9]:D
  Delay (ns):                  0.721
  Slack (ns):                  0.704
  Arrival (ns):                4.614
  Required (ns):               3.910
  Hold (ns):                   0.000


Expanded Path 1
  From: MyAPBFabricMaster_0/state[3]:CLK
  To: MyAPBFabricMaster_0/state[5]:D
  data arrival time                              4.381
  data required time                         -   3.907
  slack                                          0.474
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     3.558          Clock generation
  3.558
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.353          net: FAB_CLK
  3.911                        MyAPBFabricMaster_0/state[3]:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.160                        MyAPBFabricMaster_0/state[3]:Q (r)
               +     0.221          net: MyAPBFabricMaster_0/state[3]
  4.381                        MyAPBFabricMaster_0/state[5]:D (r)
                                    
  4.381                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     3.558          Clock generation
  3.558
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.349          net: FAB_CLK
  3.907                        MyAPBFabricMaster_0/state[5]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  3.907                        MyAPBFabricMaster_0/state[5]:D
                                    
  3.907                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        corepwm_0/genblk104.genblk105.pwm_gen/genblk33.PWM_output_generation[1].genblk34.PWM_int[1]/U1:CLK
  To:                          PWM[1]
  Delay (ns):                  2.212
  Slack (ns):
  Arrival (ns):                6.095
  Required (ns):
  Clock to Out (ns):           6.095


Expanded Path 1
  From: corepwm_0/genblk104.genblk105.pwm_gen/genblk33.PWM_output_generation[1].genblk34.PWM_int[1]/U1:CLK
  To: PWM[1]
  data arrival time                              6.095
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     3.558          Clock generation
  3.558
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.325          net: FAB_CLK
  3.883                        corepwm_0/genblk104.genblk105.pwm_gen/genblk33.PWM_output_generation[1].genblk34.PWM_int[1]/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.132                        corepwm_0/genblk104.genblk105.pwm_gen/genblk33.PWM_output_generation[1].genblk34.PWM_int[1]/U1:Q (r)
               +     0.565          net: PWM_c[1]
  4.697                        PWM_pad[1]/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  4.976                        PWM_pad[1]/U0/U1:DOUT (r)
               +     0.000          net: PWM_pad[1]/U0/NET1
  4.976                        PWM_pad[1]/U0/U0:D (r)
               +     1.119          cell: ADLIB:IOPAD_TRI
  6.095                        PWM_pad[1]/U0/U0:PAD (r)
               +     0.000          net: PWM[1]
  6.095                        PWM[1] (r)
                                    
  6.095                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     3.558          Clock generation
  N/C
                                    
  N/C                          PWM[1] (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_aclk to mss_ccc_gla1

Path 1
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK
  To:                          MyAPBFabricMaster_0/state[0]:D
  Delay (ns):                  3.774
  Slack (ns):                  2.343
  Arrival (ns):                6.247
  Required (ns):               3.904
  Hold (ns):                   0.000

Path 2
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK
  To:                          MyAPBFabricMaster_0/FPGA_TRIGGER/U1:D
  Delay (ns):                  3.792
  Slack (ns):                  2.361
  Arrival (ns):                6.265
  Required (ns):               3.904
  Hold (ns):                   0.000

Path 3
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK
  To:                          MyAPBFabricMaster_0/state[1]:D
  Delay (ns):                  3.812
  Slack (ns):                  2.378
  Arrival (ns):                6.285
  Required (ns):               3.907
  Hold (ns):                   0.000

Path 4
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK
  To:                          MyAPBFabricMaster_0/PADDR_M_1[12]/U1:D
  Delay (ns):                  4.171
  Slack (ns):                  2.744
  Arrival (ns):                6.644
  Required (ns):               3.900
  Hold (ns):                   0.000

Path 5
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK
  To:                          MyAPBFabricMaster_0/PSEL_M/U1:D
  Delay (ns):                  4.496
  Slack (ns):                  3.038
  Arrival (ns):                6.969
  Required (ns):               3.931
  Hold (ns):                   0.000


Expanded Path 1
  From: MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK
  To: MyAPBFabricMaster_0/state[0]:D
  data arrival time                              6.247
  data required time                         -   3.904
  slack                                          2.343
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_aclk
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACLK (r)
               +     2.473          Clock generation
  2.473
               +     2.009          cell: ADLIB:MSS_APB_IP
  4.482                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:ACEFLAGS[15] (r)
               +     0.080          net: MSSTOP_0/MSS_ADLIB_INST/ACEFLAGS[15]INT_NET
  4.562                        MSSTOP_0/MSS_ADLIB_INST/U_80:PIN2INT (r)
               +     0.045          cell: ADLIB:MSS_IF
  4.607                        MSSTOP_0/MSS_ADLIB_INST/U_80:PIN2 (r)
               +     0.866          net: MSSTOP_0_ACEFLAGS15to15
  5.473                        MyAPBFabricMaster_0/state_RNO_0[0]:B (r)
               +     0.168          cell: ADLIB:NOR2A
  5.641                        MyAPBFabricMaster_0/state_RNO_0[0]:Y (f)
               +     0.152          net: MyAPBFabricMaster_0/N_167
  5.793                        MyAPBFabricMaster_0/state_RNO[0]:C (f)
               +     0.306          cell: ADLIB:AO1A
  6.099                        MyAPBFabricMaster_0/state_RNO[0]:Y (f)
               +     0.148          net: MyAPBFabricMaster_0/state_ns[0]
  6.247                        MyAPBFabricMaster_0/state[0]:D (f)
                                    
  6.247                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     3.558          Clock generation
  3.558
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.346          net: FAB_CLK
  3.904                        MyAPBFabricMaster_0/state[0]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1P0
  3.904                        MyAPBFabricMaster_0/state[0]:D
                                    
  3.904                        data required time


END SET mss_aclk to mss_ccc_gla1

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MyAPBFabricMaster_0/state[3]:D
  Delay (ns):                  2.333
  Slack (ns):                  0.875
  Arrival (ns):                4.806
  Required (ns):               3.931
  Hold (ns):                   0.000

Path 2
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          corepwm_0/genblk96.genblk97.reg_if/psh_period_reg[5]/U1:D
  Delay (ns):                  2.464
  Slack (ns):                  1.006
  Arrival (ns):                4.937
  Required (ns):               3.931
  Hold (ns):                   0.000

Path 3
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MyAPBFabricMaster_0/state[6]:D
  Delay (ns):                  2.436
  Slack (ns):                  1.012
  Arrival (ns):                4.909
  Required (ns):               3.897
  Hold (ns):                   0.000

Path 4
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[3]/U1:D
  Delay (ns):                  2.482
  Slack (ns):                  1.024
  Arrival (ns):                4.955
  Required (ns):               3.931
  Hold (ns):                   0.000

Path 5
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          corepwm_0/genblk96.genblk97.reg_if/genblk0.gen_pos_neg_shregs[1].psh_negedge_reg[6]/U1:D
  Delay (ns):                  2.477
  Slack (ns):                  1.033
  Arrival (ns):                4.950
  Required (ns):               3.917
  Hold (ns):                   0.000


Expanded Path 1
  From: MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MyAPBFabricMaster_0/state[3]:D
  data arrival time                              4.806
  data required time                         -   3.931
  slack                                          0.875
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.473          Clock generation
  2.473
               +     1.389          cell: ADLIB:MSS_APB_IP
  3.862                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FABPREADY (r)
               +     0.061          net: MSSTOP_0/MSS_ADLIB_INST/FABPREADYINT_NET
  3.923                        MSSTOP_0/MSS_ADLIB_INST/U_43:PIN1INT (r)
               +     0.042          cell: ADLIB:MSS_IF
  3.965                        MSSTOP_0/MSS_ADLIB_INST/U_43:PIN1 (r)
               +     0.460          net: MyAPBFabricMaster_0_APB_bif_PREADY
  4.425                        MyAPBFabricMaster_0/state_RNIIMS4[2]:A (r)
               +     0.209          cell: ADLIB:NOR2B
  4.634                        MyAPBFabricMaster_0/state_RNIIMS4[2]:Y (r)
               +     0.172          net: MyAPBFabricMaster_0/state_ns[3]
  4.806                        MyAPBFabricMaster_0/state[3]:D (r)
                                    
  4.806                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     3.558          Clock generation
  3.558
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.373          net: FAB_CLK
  3.931                        MyAPBFabricMaster_0/state[3]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  3.931                        MyAPBFabricMaster_0/state[3]:D
                                    
  3.931                        data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MyAPBFabricMaster_0/state[0]:PRE
  Delay (ns):                  2.265
  Slack (ns):                  0.834
  Arrival (ns):                4.738
  Required (ns):               3.904
  Hold (ns):

Path 2
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MyAPBFabricMaster_0/PADDR_M_1[5]/U1:CLR
  Delay (ns):                  2.274
  Slack (ns):                  0.847
  Arrival (ns):                4.747
  Required (ns):               3.900
  Hold (ns):

Path 3
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MyAPBFabricMaster_0/PADDR_M_1[17]:CLR
  Delay (ns):                  2.311
  Slack (ns):                  0.880
  Arrival (ns):                4.784
  Required (ns):               3.904
  Hold (ns):

Path 4
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MyAPBFabricMaster_0/FPGA_TRIGGER/U1:CLR
  Delay (ns):                  2.311
  Slack (ns):                  0.880
  Arrival (ns):                4.784
  Required (ns):               3.904
  Hold (ns):

Path 5
  From:                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          MyAPBFabricMaster_0/PWDATA_M_1[0]/U1:CLR
  Delay (ns):                  2.311
  Slack (ns):                  0.880
  Arrival (ns):                4.784
  Required (ns):               3.904
  Hold (ns):


Expanded Path 1
  From: MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: MyAPBFabricMaster_0/state[0]:PRE
  data arrival time                              4.738
  data required time                         -   3.904
  slack                                          0.834
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.248          Clock generation
  2.248
               +     0.225          net: MSSTOP_0/GLA0
  2.473                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.569          cell: ADLIB:MSS_APB_IP
  4.042                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.059          net: MSSTOP_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  4.101                        MSSTOP_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.045          cell: ADLIB:MSS_IF
  4.146                        MSSTOP_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     0.592          net: MSSTOP_0_M2F_RESET_N
  4.738                        MyAPBFabricMaster_0/state[0]:PRE (r)
                                    
  4.738                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     3.558          Clock generation
  3.558
               +     0.000          net: MSSTOP_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  3.558                        MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.346          net: FAB_CLK
  3.904                        MyAPBFabricMaster_0/state[0]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1P0
  3.904                        MyAPBFabricMaster_0/state[0]:PRE
                                    
  3.904                        data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.277
  Slack (ns):
  Arrival (ns):                0.277
  Required (ns):
  Hold (ns):                   1.294
  External Hold (ns):          3.536


Expanded Path 1
  From: MSS_RESET_N
  To: MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.277
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        MSSTOP_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        MSSTOP_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: MSSTOP_0/MSS_RESET_0_MSS_RESET_N_Y
  0.277                        MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.277                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSSTOP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.248          Clock generation
  N/C
               +     0.271          net: MSSTOP_0/GLA0
  N/C                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.294          Library hold time: ADLIB:MSS_APB_IP
  N/C                          MSSTOP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSSTOP_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

