-- fab_logic.vhd
-------------------------------------------------------------------------------
-- Title      : ACE Control Logic to PCD
-------------------------------------------------------------------------------
-- File       : fab_logic.vhd
-- Author     : Pavan Marisetti
-- Device     : SmartFusion
-- Standard   : VHDL
-------------------------------------------------------------------------------

library ieee;  
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fab_logic is
  port (FAB_CLK           : in    std_logic;
		RESET_N           : in    std_logic;
        ENBL              : in    std_logic;
        PADDR             : in    std_logic_vector(19 downto 0);
        PSEL              : in    std_logic;
        PENABLE           : in    std_logic;
        PWRITE            : in    std_logic;
        PRDATA            : out   std_logic_vector(31 downto 0);
        PWDATA            : in    std_logic_vector(31 downto 0);
        PREADY            : out   std_logic;
        PSLVER            : out   std_logic;
        FABACETRIG        : out   std_logic;
        interrupt_out     : out   std_logic; -- Debug signals
        interrupt_sync_out: out   std_logic  -- Debug signals
       );
   end;

architecture fab_logic of fab_logic is


  signal counter2          : std_logic_vector(31 downto 0);
  signal counter3          : std_logic_vector(7 downto 0);

  signal usec_delay_en     : std_logic;
  signal Interrupt         : std_logic;
  signal Interrupt_sync    : std_logic;

begin
   PREADY            <= '1'; 
   PSLVER            <= '0';
   PRDATA            <= (others=>'0');

--generate 10Khz signal called interrupt based on Enable signal from MSS
INTRPT_PROC:process(FAB_CLK, RESET_N)
  begin
    if RESET_N = '0' then       
       counter2 <= (others=>'0');
       Interrupt <= '0';
	elsif (FAB_CLK'event and FAB_CLK = '1') then
       if(ENBL = '1') then
         if(counter2 = X"00000FA0")then
            Interrupt <= '1';
            counter2 <= counter2 + 1;
         elsif (counter2 = X"00001F40")then
            Interrupt <= '0';
            counter2 <= X"00000000";
         else
           counter2 <= counter2 + 1;
         end if;
       end if;
    end if; 
 end process;

-- Delay signal generation
INTRPT_SYNC_PROC:process(FAB_CLK, RESET_N)
  begin
    if RESET_N = '0' then       
       Interrupt_sync <= '0';
	elsif (FAB_CLK'event and FAB_CLK = '1') then
       Interrupt_sync <= Interrupt;
    end if;
 end process;

ACE_TRIG_PROC:process(FAB_CLK, RESET_N)
  begin
    if RESET_N = '0' then       
       FABACETRIG      <= '1';
       usec_delay_en   <= '0';
       counter3 <= (others=>'0');
	elsif (FAB_CLK'event and FAB_CLK = '1') then
       if((Interrupt_sync = '0' and Interrupt = '1'))then -- 10 Khz Rising edge detection
          usec_delay_en   <= '1';
       elsif(usec_delay_en = '1') then -- 1 Usec Delay logic and assertion of FABACETRIG to low 
          if(counter3 = X"50") then
            usec_delay_en   <= '0';
            counter3 <= (others=>'0');
            FABACETRIG <= '0';
          else
            counter3 <= counter3 + 1;
          end if;
       elsif(PENABLE = '1' and PSEL = '1' and PWRITE = '1') then  -- assertion of FABACETRIG to high/low 
          FABACETRIG <= PWDATA(31);
       end if;
    end if;
 end process;
     
interrupt_out      <= interrupt; -- Debug signals
interrupt_sync_out <= interrupt_sync; -- Debug signals 

end fab_logic;