`

    #Build: Synplify Pro E-2010.09A-1, Build 006R, Oct  6 2010
    #install: C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1
    #OS: Windows XP 5.1
    #Hostname: WXP-ALIM2

    #Implementation: synthesis

    #Thu Mar 24 11:35:16 2011

    $ Start of Compile
    #Thu Mar 24 11:35:16 2011

    Synopsys Verilog Compiler, version comp520rcp1, Build 028R, built Sep 23 2010
    @N: :  | Running in 32-bit mode
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

    @I::"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v"
    @I::"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v"
    @I::"D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\hdl\MyAPBPeripheral.v"
    @I::"D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\DirectCore\corepwm\4.1.106\rtl\vlog\core\reg_if.v"
    @I::"D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\DirectCore\corepwm\4.1.106\rtl\vlog\core\tach_if.v"
    @I::"D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\DirectCore\corepwm\4.1.106\rtl\vlog\core\timebase.v"
    @I::"D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\DirectCore\corepwm\4.1.106\rtl\vlog\core\pwm_gen.v"
    @I::"D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\DirectCore\corepwm\4.1.106\rtl\vlog\core\corepwm.v"
    @I::"D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\work\MSSTOP\mss_tshell.v"
    @I::"D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\SmartFusionMSS\MSS\2.4.105\mss_comps.v"
    @I::"D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\work\MSSTOP\MSS_CCC_0\MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v"
    @I::"D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\work\MSSTOP\MSSTOP.v"
    @I::"D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v"
    @I::"D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v"
    @I::"D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\work\SDTOP\SDTOP.v"
    Verilog syntax check successful!
    File D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\DirectCore\corepwm\4.1.106\rtl\vlog\core\reg_if.v changed - recompiling
    File D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\DirectCore\corepwm\4.1.106\rtl\vlog\core\tach_if.v changed - recompiling
    File D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\DirectCore\corepwm\4.1.106\rtl\vlog\core\timebase.v changed - recompiling
    File D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\DirectCore\corepwm\4.1.106\rtl\vlog\core\pwm_gen.v changed - recompiling
    File D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\DirectCore\corepwm\4.1.106\rtl\vlog\core\corepwm.v changed - recompiling
    File D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\work\MSSTOP\mss_tshell.v changed - recompiling
    File D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\SmartFusionMSS\MSS\2.4.105\mss_comps.v changed - recompiling
    File D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\work\MSSTOP\MSS_CCC_0\MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v changed - recompiling
    File D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\work\MSSTOP\MSSTOP.v changed - recompiling
    File D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v changed - recompiling
    File D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v changed - recompiling
    File D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\component\work\SDTOP\SDTOP.v changed - recompiling
    Selecting top level module SDTOP
    @W:CG775 : coreapb3.v(30) | Found Component CoreAPB3 in library COREAPB3_LIB
    @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3

    @N:CG364 : coreapb3.v(30) | Synthesizing module CoreAPB3

    	APB_DWIDTH=6'b100000
    	RANGESIZE=21'b000000001000000000000
    	IADDR_ENABLE=1'b0
    	APBSLOT0ENABLE=1'b0
    	APBSLOT1ENABLE=1'b0
    	APBSLOT2ENABLE=1'b0
    	APBSLOT3ENABLE=1'b0
    	APBSLOT4ENABLE=1'b0
    	APBSLOT5ENABLE=1'b0
    	APBSLOT6ENABLE=1'b0
    	APBSLOT7ENABLE=1'b1
    	APBSLOT8ENABLE=1'b0
    	APBSLOT9ENABLE=1'b0
    	APBSLOT10ENABLE=1'b0
    	APBSLOT11ENABLE=1'b0
    	APBSLOT12ENABLE=1'b0
    	APBSLOT13ENABLE=1'b0
    	APBSLOT14ENABLE=1'b0
    	APBSLOT15ENABLE=1'b0
    	RANGEBITS=32'b00000000000000000000000000001100
    	RANGEBITS_LT16=32'b00000000000000000000000000001100
    	IADDR_31_24_8B_A=12'b000000001100
    	IADDR_23_16_8B_A=12'b000000001000
    	IADDR_15_8_8B_A=12'b000000000100
    	IADDR_7_0_8B_A=12'b000000000000
    	IADDR_31_16_16B_A=12'b000000000100
    	IADDR_15_0_16B_A=12'b000000000000
    	IADDR_31_0_32B_A=12'b000000000000
    	SL0=16'b0000000000000000
    	SL1=16'b0000000000000000
    	SL2=16'b0000000000000000
    	SL3=16'b0000000000000000
    	SL4=16'b0000000000000000
    	SL5=16'b0000000000000000
    	SL6=16'b0000000000000000
    	SL7=16'b0000000010000000
    	SL8=16'b0000000000000000
    	SL9=16'b0000000000000000
    	SL10=16'b0000000000000000
    	SL11=16'b0000000000000000
    	SL12=16'b0000000000000000
    	SL13=16'b0000000000000000
    	SL14=16'b0000000000000000
    	SL15=16'b0000000000000000
       Generated name = CoreAPB3_Z1

    @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC

    @N:CG364 : MyAPBPeripheral.v(4) | Synthesizing module MyAPBFabricMaster

    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[0] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[1] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[4] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[7] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[8] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[10] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[11] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[13] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[14] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[15] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[16] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[18] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[19] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[20] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[21] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[22] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[23] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[24] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[25] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[26] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[27] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[28] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[29] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PADDR_M[31] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[2] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[3] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[4] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[5] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[6] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[7] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[8] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[9] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[10] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[11] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[12] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[13] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[14] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[16] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[17] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[18] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[19] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[20] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[21] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[22] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[23] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[24] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[25] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[26] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[27] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[28] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[29] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[30] to a constant 0
    @W:CL190 : MyAPBPeripheral.v(114) | Optimizing register bit PWDATA_M[31] to a constant 0
    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 31 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 29 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 28 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 27 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 26 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 25 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 24 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 23 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 22 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 21 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 20 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 19 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 18 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 16 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 15 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 14 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 13 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 11 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 10 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 8 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 7 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 4 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 1 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 0 of PADDR_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 31 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 30 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 29 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 28 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 27 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 26 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 25 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 24 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 23 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 22 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 21 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 20 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 19 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 18 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 17 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 16 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 14 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 13 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 12 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 11 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 10 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 9 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 8 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 7 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 6 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 5 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 4 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 3 of PWDATA_M[31:0]

    @W:CL260 : MyAPBPeripheral.v(114) | Pruning Register bit 2 of PWDATA_M[31:0]

    @N:CG364 : corepwm.v(26) | Synthesizing module corepwm

    	FAMILY=32'b00000000000000000000000000001111
    	CONFIG_MODE=32'b00000000000000000000000000000000
    	PWM_NUM=32'b00000000000000000000000000000001
    	APB_DWIDTH=32'b00000000000000000000000000001000
    	FIXED_PRESCALE_EN=32'b00000000000000000000000000000001
    	FIXED_PRESCALE=32'b00000000000000000000000000000000
    	FIXED_PERIOD_EN=32'b00000000000000000000000000000000
    	FIXED_PERIOD=32'b00000000000000000000000000000001
    	DAC_MODE1=32'b00000000000000000000000000000000
    	DAC_MODE2=32'b00000000000000000000000000000000
    	DAC_MODE3=32'b00000000000000000000000000000000
    	DAC_MODE4=32'b00000000000000000000000000000000
    	DAC_MODE5=32'b00000000000000000000000000000000
    	DAC_MODE6=32'b00000000000000000000000000000000
    	DAC_MODE7=32'b00000000000000000000000000000000
    	DAC_MODE8=32'b00000000000000000000000000000000
    	DAC_MODE9=32'b00000000000000000000000000000000
    	DAC_MODE10=32'b00000000000000000000000000000000
    	DAC_MODE11=32'b00000000000000000000000000000000
    	DAC_MODE12=32'b00000000000000000000000000000000
    	DAC_MODE13=32'b00000000000000000000000000000000
    	DAC_MODE14=32'b00000000000000000000000000000000
    	DAC_MODE15=32'b00000000000000000000000000000000
    	DAC_MODE16=32'b00000000000000000000000000000000
    	SHADOW_REG_EN1=32'b00000000000000000000000000000000
    	SHADOW_REG_EN2=32'b00000000000000000000000000000000
    	SHADOW_REG_EN3=32'b00000000000000000000000000000000
    	SHADOW_REG_EN4=32'b00000000000000000000000000000000
    	SHADOW_REG_EN5=32'b00000000000000000000000000000000
    	SHADOW_REG_EN6=32'b00000000000000000000000000000000
    	SHADOW_REG_EN7=32'b00000000000000000000000000000000
    	SHADOW_REG_EN8=32'b00000000000000000000000000000000
    	SHADOW_REG_EN9=32'b00000000000000000000000000000000
    	SHADOW_REG_EN10=32'b00000000000000000000000000000000
    	SHADOW_REG_EN11=32'b00000000000000000000000000000000
    	SHADOW_REG_EN12=32'b00000000000000000000000000000000
    	SHADOW_REG_EN13=32'b00000000000000000000000000000000
    	SHADOW_REG_EN14=32'b00000000000000000000000000000000
    	SHADOW_REG_EN15=32'b00000000000000000000000000000000
    	SHADOW_REG_EN16=32'b00000000000000000000000000000000
    	FIXED_PWM_POS_EN1=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN2=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN3=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN4=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN5=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN6=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN7=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN8=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN9=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN10=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN11=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN12=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN13=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN14=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN15=32'b00000000000000000000000000000001
    	FIXED_PWM_POS_EN16=32'b00000000000000000000000000000001
    	FIXED_PWM_POSEDGE1=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE2=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE3=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE4=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE5=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE6=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE7=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE8=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE9=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE10=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE11=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE12=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE13=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE14=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE15=32'b00000000000000000000000000000000
    	FIXED_PWM_POSEDGE16=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN1=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN2=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN3=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN4=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN5=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN6=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN7=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN8=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN9=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN10=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN11=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN12=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN13=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN14=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN15=32'b00000000000000000000000000000000
    	FIXED_PWM_NEG_EN16=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE1=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE2=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE3=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE4=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE5=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE6=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE7=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE8=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE9=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE10=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE11=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE12=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE13=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE14=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE15=32'b00000000000000000000000000000000
    	FIXED_PWM_NEGEDGE16=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE1=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE2=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE3=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE4=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE5=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE6=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE7=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE8=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE9=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE10=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE11=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE12=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE13=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE14=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE15=32'b00000000000000000000000000000000
    	PWM_STRETCH_VALUE16=32'b00000000000000000000000000000000
    	TACH_NUM=32'b00000000000000000000000000000001
    	TACH_EDGE1=32'b00000000000000000000000000000000
    	TACH_EDGE2=32'b00000000000000000000000000000000
    	TACH_EDGE3=32'b00000000000000000000000000000000
    	TACH_EDGE4=32'b00000000000000000000000000000000
    	TACH_EDGE5=32'b00000000000000000000000000000000
    	TACH_EDGE6=32'b00000000000000000000000000000000
    	TACH_EDGE7=32'b00000000000000000000000000000000
    	TACH_EDGE8=32'b00000000000000000000000000000000
    	TACH_EDGE9=32'b00000000000000000000000000000000
    	TACH_EDGE10=32'b00000000000000000000000000000000
    	TACH_EDGE11=32'b00000000000000000000000000000000
    	TACH_EDGE12=32'b00000000000000000000000000000000
    	TACH_EDGE13=32'b00000000000000000000000000000000
    	TACH_EDGE14=32'b00000000000000000000000000000000
    	TACH_EDGE15=32'b00000000000000000000000000000000
    	TACH_EDGE16=32'b00000000000000000000000000000000
    	TACHINT_ACT_LEVEL=32'b00000000000000000000000000000000
    	all_ones=16'b1111111111111111
    	DAC_MODE=16'b0000000000000000
    	SHADOW_REG_EN=16'b0000000000000000
    	FIXED_PWM_POS_EN=16'b1111111111111111
    	FIXED_PWM_NEG_EN=16'b0000000000000000
    	FIXED_PWM_POSEDGE=128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
    	FIXED_PWM_NEGEDGE=128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
       Generated name = corepwm_Z2

    @N:CG364 : reg_if.v(26) | Synthesizing module reg_if

    	PWM_NUM=32'b00000000000000000000000000000001
    	APB_DWIDTH=32'b00000000000000000000000000001000
    	FIXED_PRESCALE_EN=32'b00000000000000000000000000000001
    	FIXED_PRESCALE=32'b00000000000000000000000000000000
    	FIXED_PERIOD_EN=32'b00000000000000000000000000000000
    	FIXED_PERIOD=32'b00000000000000000000000000000001
    	DAC_MODE=16'b0000000000000000
    	SHADOW_REG_EN=16'b0000000000000000
    	FIXED_PWM_POS_EN=16'b1111111111111111
    	FIXED_PWM_POSEDGE=128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
    	FIXED_PWM_NEG_EN=16'b0000000000000000
    	FIXED_PWM_NEGEDGE=128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
       Generated name = reg_if_Z3

    @W:CL169 : reg_if.v(235) | Pruning Register prescale_reg[7:0]

    @W:CL169 : reg_if.v(235) | Pruning Register pwm_enable_reg[16:1]

    @W:CL169 : reg_if.v(163) | Pruning Register genblk1.gen_pos_neg_regs[1].pwm_posedge_reg[8:1]

    @W:CL169 : reg_if.v(163) | Pruning Register genblk1.gen_pos_neg_regs[1].pwm_negedge_reg[8:1]

    @W:CL169 : reg_if.v(115) | Pruning Register genblk0.gen_pos_neg_shregs[1].psh_posedge_reg[8:1]

    @W:CL169 : reg_if.v(88) | Pruning Register psh_prescale_reg[7:0]

    @W:CL265 : reg_if.v(88) | Pruning bit 8 of psh_enable_reg1[8:1] - not in use ...

    @W:CL265 : reg_if.v(88) | Pruning bit 7 of psh_enable_reg1[8:1] - not in use ...

    @W:CL265 : reg_if.v(88) | Pruning bit 6 of psh_enable_reg1[8:1] - not in use ...

    @W:CL265 : reg_if.v(88) | Pruning bit 5 of psh_enable_reg1[8:1] - not in use ...

    @W:CL265 : reg_if.v(88) | Pruning bit 4 of psh_enable_reg1[8:1] - not in use ...

    @W:CL265 : reg_if.v(88) | Pruning bit 3 of psh_enable_reg1[8:1] - not in use ...

    @W:CL265 : reg_if.v(88) | Pruning bit 2 of psh_enable_reg1[8:1] - not in use ...

    @W:CL169 : reg_if.v(88) | Pruning Register psh_enable_reg2[16:9]

    @N:CG364 : timebase.v(26) | Synthesizing module timebase

    	APB_DWIDTH=32'b00000000000000000000000000001000
       Generated name = timebase_8s

    @N:CG364 : pwm_gen.v(26) | Synthesizing module pwm_gen

    	PWM_NUM=32'b00000000000000000000000000000001
    	APB_DWIDTH=32'b00000000000000000000000000001000
    	DAC_MODE=16'b0000000000000000
       Generated name = pwm_gen_1s_8s_0

    @W:CG133 : pwm_gen.v(43) | No assignment to acc
    @W:CG360 : corepwm.v(181) | No assignment to wire TACHINT

    @W:CG133 : corepwm.v(193) | No assignment to PRDATA_TACH
    @W:CG360 : corepwm.v(194) | No assignment to wire PWM_STRETCH_VALUE_int

    @W:CG360 : corepwm.v(195) | No assignment to wire TACH_EDGE

    @W:CG360 : corepwm.v(196) | No assignment to wire tachint_mask

    @W:CG133 : corepwm.v(197) | No assignment to TACHPRESCALE
    @W:CG133 : corepwm.v(198) | No assignment to PWM_STRETCH
    @W:CG133 : corepwm.v(199) | No assignment to TACHIRQMASK
    @W:CG133 : corepwm.v(200) | No assignment to TACHMODE
    @W:CG133 : corepwm.v(202) | No assignment to tach_prescale_cnt
    @W:CG133 : corepwm.v(203) | No assignment to tach_prescale_value
    @W:CG133 : corepwm.v(204) | No assignment to prescale_decode_value
    @W:CG133 : corepwm.v(205) | No assignment to tach_cnt_clk
    @W:CG360 : corepwm.v(207) | No assignment to wire update_status

    @W:CG133 : corepwm.v(1173) | No assignment to t
    @W:CL169 : corepwm.v(419) | Pruning Register genblk37.gen_tachstatus[0].TACHSTATUS[0]

    @W:CL169 : corepwm.v(419) | Pruning Register genblk37.gen_tachstatus[0].status_clear[0]

    @N:CG364 : smartfusion.v(1133) | Synthesizing module GND

    @N:CG364 : smartfusion.v(2609) | Synthesizing module INBUF_A

    @N:CG364 : smartfusion.v(2614) | Synthesizing module OUTBUF_A

    @N:CG364 : mss_tshell.v(1) | Synthesizing module MSS_APB

    @N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC

    @N:CG364 : smartfusion.v(2566) | Synthesizing module RCOSC

    @N:CG364 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module MSSTOP_tmp_MSS_CCC_0_MSS_CCC

    @N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS

    @N:CG364 : MSSTOP.v(5) | Synthesizing module MSSTOP

    @N:CG364 : SDTOP.v(5) | Synthesizing module SDTOP

    @W:CL157 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible
    @W:CL157 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible
    @W:CL157 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(48) | Input MAINXIN is unused
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused
    @W:CL159 : MSSTOP_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused
    @W:CL246 : corepwm.v(174) | Input port bits 1 to 0 of PADDR[7:0] are unused

    @A:CL153 : corepwm.v(198) | *Unassigned bits of PWM_STRETCH[0] have been referenced and are being tied to 0 - simulation mismatch possible
    @W:CL157 : corepwm.v(181) | *Output TACHINT has undriven bits - a simulation mismatch is possible
    @W:CL159 : corepwm.v(180) | Input TACHIN is unused
    @N:CL201 : MyAPBPeripheral.v(114) | Trying to extract state machine for register state
    Extracted state machine for register state
    State machine has 9 reachable states with original encodings of:
       0000
       0001
       0010
       0011
       0100
       0101
       0110
       0111
       1000
    @W:CL159 : MyAPBPeripheral.v(47) | Input PRDATA_M is unused
    @W:CL159 : MyAPBPeripheral.v(49) | Input PSLVERR_M is unused
    @W:CL246 : coreapb3.v(54) | Input port bits 23 to 16 of PADDR[23:0] are unused

    @W:CL159 : coreapb3.v(52) | Input PRESETN is unused
    @W:CL159 : coreapb3.v(53) | Input PCLK is unused
    @W:CL159 : coreapb3.v(83) | Input PRDATAS0 is unused
    @W:CL159 : coreapb3.v(84) | Input PRDATAS1 is unused
    @W:CL159 : coreapb3.v(85) | Input PRDATAS2 is unused
    @W:CL159 : coreapb3.v(86) | Input PRDATAS3 is unused
    @W:CL159 : coreapb3.v(87) | Input PRDATAS4 is unused
    @W:CL159 : coreapb3.v(88) | Input PRDATAS5 is unused
    @W:CL159 : coreapb3.v(89) | Input PRDATAS6 is unused
    @W:CL159 : coreapb3.v(91) | Input PRDATAS8 is unused
    @W:CL159 : coreapb3.v(92) | Input PRDATAS9 is unused
    @W:CL159 : coreapb3.v(93) | Input PRDATAS10 is unused
    @W:CL159 : coreapb3.v(94) | Input PRDATAS11 is unused
    @W:CL159 : coreapb3.v(95) | Input PRDATAS12 is unused
    @W:CL159 : coreapb3.v(96) | Input PRDATAS13 is unused
    @W:CL159 : coreapb3.v(97) | Input PRDATAS14 is unused
    @W:CL159 : coreapb3.v(98) | Input PRDATAS15 is unused
    @W:CL159 : coreapb3.v(99) | Input PREADYS0 is unused
    @W:CL159 : coreapb3.v(100) | Input PREADYS1 is unused
    @W:CL159 : coreapb3.v(101) | Input PREADYS2 is unused
    @W:CL159 : coreapb3.v(102) | Input PREADYS3 is unused
    @W:CL159 : coreapb3.v(103) | Input PREADYS4 is unused
    @W:CL159 : coreapb3.v(104) | Input PREADYS5 is unused
    @W:CL159 : coreapb3.v(105) | Input PREADYS6 is unused
    @W:CL159 : coreapb3.v(107) | Input PREADYS8 is unused
    @W:CL159 : coreapb3.v(108) | Input PREADYS9 is unused
    @W:CL159 : coreapb3.v(109) | Input PREADYS10 is unused
    @W:CL159 : coreapb3.v(110) | Input PREADYS11 is unused
    @W:CL159 : coreapb3.v(111) | Input PREADYS12 is unused
    @W:CL159 : coreapb3.v(112) | Input PREADYS13 is unused
    @W:CL159 : coreapb3.v(113) | Input PREADYS14 is unused
    @W:CL159 : coreapb3.v(114) | Input PREADYS15 is unused
    @W:CL159 : coreapb3.v(115) | Input PSLVERRS0 is unused
    @W:CL159 : coreapb3.v(116) | Input PSLVERRS1 is unused
    @W:CL159 : coreapb3.v(117) | Input PSLVERRS2 is unused
    @W:CL159 : coreapb3.v(118) | Input PSLVERRS3 is unused
    @W:CL159 : coreapb3.v(119) | Input PSLVERRS4 is unused
    @W:CL159 : coreapb3.v(120) | Input PSLVERRS5 is unused
    @W:CL159 : coreapb3.v(121) | Input PSLVERRS6 is unused
    @W:CL159 : coreapb3.v(123) | Input PSLVERRS8 is unused
    @W:CL159 : coreapb3.v(124) | Input PSLVERRS9 is unused
    @W:CL159 : coreapb3.v(125) | Input PSLVERRS10 is unused
    @W:CL159 : coreapb3.v(126) | Input PSLVERRS11 is unused
    @W:CL159 : coreapb3.v(127) | Input PSLVERRS12 is unused
    @W:CL159 : coreapb3.v(128) | Input PSLVERRS13 is unused
    @W:CL159 : coreapb3.v(129) | Input PSLVERRS14 is unused
    @W:CL159 : coreapb3.v(130) | Input PSLVERRS15 is unused
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Thu Mar 24 11:35:18 2011

    ###########################################################]

`
Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO111 : corepwm.v(181) | tristate driver TACHINT on net TACHINT has its enable tied to GND (module corepwm_Z2) @W:MO111 : msstop_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module MSSTOP_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : msstop_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module MSSTOP_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : msstop_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module MSSTOP_tmp_MSS_CCC_0_MSS_CCC) @W:BN132 : myapbperipheral.v(114) | Removing sequential instance MyAPBFabricMaster_0.PADDR_M_1[30], because it is equivalent to instance MyAPBFabricMaster_0.PADDR_M_1[17] @W:BN132 : myapbperipheral.v(114) | Removing sequential instance MyAPBFabricMaster_0.PWRITE_M, because it is equivalent to instance MyAPBFabricMaster_0.PSEL_M @W:BN132 : myapbperipheral.v(114) | Removing sequential instance MyAPBFabricMaster_0.PWDATA_M_1[15], because it is equivalent to instance MyAPBFabricMaster_0.PADDR_M_1[12] @W:BN132 : myapbperipheral.v(114) | Removing sequential instance MyAPBFabricMaster_0.PADDR_M_1[9], because it is equivalent to instance MyAPBFabricMaster_0.PADDR_M_1[12] Available hyper_sources - for debug and ip models None Found @W: : msstop_tmp_mss_ccc_0_mss_ccc.v(81) | Net MSSTOP_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. @W: : msstop_tmp_mss_ccc_0_mss_ccc.v(81) | Net corepwm_0/PCLK appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB) Encoding state machine work.MyAPBFabricMaster(verilog)-state[8:0] original code -> new code 0000 -> 000000001 0001 -> 000000010 0010 -> 000000100 0011 -> 000001000 0100 -> 000010000 0101 -> 000100000 0110 -> 001000000 0111 -> 010000000 1000 -> 100000000 @N:MF238 : myapbperipheral.v(79) | Found 16 bit incrementor, 'un3_counter[15:0]' @N:MF179 : reg_if.v(245) | Found 8 bit by 8 bit '<' comparator, 'genblk1\.gen_pos_neg_regs\[1\]\.un1_period_cnt' @N: : timebase.v(69) | Found counter in view:work.timebase_8s(verilog) inst period_cnt[7:0] @N: : timebase.v(47) | Found counter in view:work.timebase_8s(verilog) inst prescale_cnt[7:0] @N:MF179 : timebase.v(77) | Found 8 bit by 8 bit '<' comparator, 'un1_period_cnt' Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 58MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 58MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 59MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 59MB) Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 59MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 59MB) Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 59MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ---------------------------------------------------------------------- MSSTOP_0.MSS_ADLIB_INST / M2FRESETn 72 : 72 asynchronous set/reset ====================================================================== Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 59MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 59MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 59MB) Writing Analyst data base D:\Appsnotes\2011\ACE_sequencing\Final_design\FAB_TRIGGER_DEMO\FAB_TRIGGER_DEMO\synthesis\SDTOP.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 59MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 59MB) @W:MT420 : | Found inferred clock MSSTOP|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:MSSTOP_0.MSS_ADLIB_INST_EMCCLK" @W:MT420 : | Found inferred clock MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:MSSTOP_0_FAB_CLK" @W:MT420 : | Found inferred clock MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:MSSTOP_0.MSS_ADLIB_INST_FCLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Thu Mar 24 11:35:20 2011 # Top view: SDTOP Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -0.587 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock 100.0 MHz 94.5 MHz 10.000 10.587 -0.587 inferred Inferred_clkgroup_2 MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock 100.0 MHz 100.5 MHz 10.000 9.947 0.053 inferred Inferred_clkgroup_1 ======================================================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | 10.000 0.053 | No paths - | No paths - | No paths - MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock | 10.000 -0.587 | No paths - | No paths - | No paths - ========================================================================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[1] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 Q period_cnt[1] 0.737 -0.587 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[0] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 Q period_cnt[0] 0.737 -0.372 corepwm_0.genblk96\.genblk97\.reg_if.period_reg[1] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1E0C0 Q period_reg[1] 0.580 0.068 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[6] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 Q period_cnt[6] 0.737 0.224 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[2] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 Q period_cnt[2] 0.737 0.292 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[3] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 Q period_cnt[3] 0.737 0.476 corepwm_0.genblk96\.genblk97\.reg_if.period_reg[0] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1E0C0 Q period_reg[0] 0.580 0.508 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[5] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 Q period_cnt[5] 0.737 0.563 corepwm_0.genblk96\.genblk97\.reg_if.period_reg[2] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1E0C0 Q period_reg[2] 0.737 0.666 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[4] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 Q period_cnt[4] 0.737 0.678 ================================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[4] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 D period_cnt_RNO[4] 9.461 -0.587 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[6] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 D period_cnt_RNO[6] 9.461 -0.587 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[1] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 D N_5 9.461 -0.567 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[2] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 D N_7 9.461 -0.567 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[3] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 D period_cnt_RNO[3] 9.461 -0.567 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[5] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 D period_cnt_RNO[5] 9.461 -0.567 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[7] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 D N_17 9.461 -0.567 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[0] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1C0 D period_cnt_n0 9.461 -0.438 corepwm_0.genblk96\.genblk97\.reg_if.period_reg[0] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1E0C0 E un1_period_cnt 9.566 0.504 corepwm_0.genblk96\.genblk97\.reg_if.period_reg[1] MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock DFN1E0C0 E un1_period_cnt 9.566 0.504 ===================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 10.049 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.587 Number of logic level(s): 6 Starting point: corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[1] / Q Ending point: corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[4] / D The start point is clocked by MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------ corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[1] DFN1C0 Q Out 0.737 0.737 - period_cnt[1] Net - - 1.669 - 9 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_22 OR2A B In - 2.405 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_22 OR2A Y Out 0.646 3.052 - N_8 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_28 AO1C C In - 3.373 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_28 AO1C Y Out 0.633 4.006 - N_14 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_31 OA1A B In - 4.327 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_31 OA1A Y Out 0.902 5.229 - N_17_0 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_32 OA1 A In - 5.551 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_32 OA1 Y Out 0.984 6.535 - DWACT_COMP0_E[2] Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_39 AO1 B In - 6.856 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_39 AO1 Y Out 0.567 7.423 - N_51_i Net - - 1.639 - 8 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt_RNO[4] NOR3C C In - 9.062 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt_RNO[4] NOR3C Y Out 0.666 9.727 - period_cnt_RNO[4] Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[4] DFN1C0 D In - 10.049 - ========================================================================================================================================== Total path delay (propagation time + setup) of 10.587 is 5.672(53.6%) logic and 4.915(46.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 10.049 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.587 Number of logic level(s): 6 Starting point: corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[1] / Q Ending point: corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[6] / D The start point is clocked by MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------ corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[1] DFN1C0 Q Out 0.737 0.737 - period_cnt[1] Net - - 1.669 - 9 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_22 OR2A B In - 2.405 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_22 OR2A Y Out 0.646 3.052 - N_8 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_28 AO1C C In - 3.373 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_28 AO1C Y Out 0.633 4.006 - N_14 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_31 OA1A B In - 4.327 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_31 OA1A Y Out 0.902 5.229 - N_17_0 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_32 OA1 A In - 5.551 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_32 OA1 Y Out 0.984 6.535 - DWACT_COMP0_E[2] Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_39 AO1 B In - 6.856 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_39 AO1 Y Out 0.567 7.423 - N_51_i Net - - 1.639 - 8 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt_RNO[6] NOR3C C In - 9.062 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt_RNO[6] NOR3C Y Out 0.666 9.727 - period_cnt_RNO[6] Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[6] DFN1C0 D In - 10.049 - ========================================================================================================================================== Total path delay (propagation time + setup) of 10.587 is 5.672(53.6%) logic and 4.915(46.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 10.028 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.566 Number of logic level(s): 6 Starting point: corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[1] / Q Ending point: corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[1] / D The start point is clocked by MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------ corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[1] DFN1C0 Q Out 0.737 0.737 - period_cnt[1] Net - - 1.669 - 9 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_22 OR2A B In - 2.405 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_22 OR2A Y Out 0.646 3.052 - N_8 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_28 AO1C C In - 3.373 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_28 AO1C Y Out 0.633 4.006 - N_14 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_31 OA1A B In - 4.327 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_31 OA1A Y Out 0.902 5.229 - N_17_0 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_32 OA1 A In - 5.551 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_32 OA1 Y Out 0.984 6.535 - DWACT_COMP0_E[2] Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_39 AO1 B In - 6.856 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_39 AO1 Y Out 0.567 7.423 - N_51_i Net - - 1.639 - 8 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt_RNO[1] XA1 C In - 9.062 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt_RNO[1] XA1 Y Out 0.645 9.706 - N_5 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[1] DFN1C0 D In - 10.028 - ========================================================================================================================================== Total path delay (propagation time + setup) of 10.567 is 5.652(53.5%) logic and 4.915(46.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 10.028 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.566 Number of logic level(s): 6 Starting point: corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[1] / Q Ending point: corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[2] / D The start point is clocked by MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------ corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[1] DFN1C0 Q Out 0.737 0.737 - period_cnt[1] Net - - 1.669 - 9 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_22 OR2A B In - 2.405 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_22 OR2A Y Out 0.646 3.052 - N_8 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_28 AO1C C In - 3.373 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_28 AO1C Y Out 0.633 4.006 - N_14 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_31 OA1A B In - 4.327 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_31 OA1A Y Out 0.902 5.229 - N_17_0 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_32 OA1 A In - 5.551 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_32 OA1 Y Out 0.984 6.535 - DWACT_COMP0_E[2] Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_39 AO1 B In - 6.856 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_39 AO1 Y Out 0.567 7.423 - N_51_i Net - - 1.639 - 8 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt_RNO[2] XA1 C In - 9.062 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt_RNO[2] XA1 Y Out 0.645 9.706 - N_7 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[2] DFN1C0 D In - 10.028 - ========================================================================================================================================== Total path delay (propagation time + setup) of 10.567 is 5.652(53.5%) logic and 4.915(46.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 10.028 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.566 Number of logic level(s): 6 Starting point: corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[1] / Q Ending point: corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[3] / D The start point is clocked by MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSSTOP_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------ corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[1] DFN1C0 Q Out 0.737 0.737 - period_cnt[1] Net - - 1.669 - 9 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_22 OR2A B In - 2.405 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_22 OR2A Y Out 0.646 3.052 - N_8 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_28 AO1C C In - 3.373 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_28 AO1C Y Out 0.633 4.006 - N_14 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_31 OA1A B In - 4.327 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_31 OA1A Y Out 0.902 5.229 - N_17_0 Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_32 OA1 A In - 5.551 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_32 OA1 Y Out 0.984 6.535 - DWACT_COMP0_E[2] Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_39 AO1 B In - 6.856 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.un1_period_cnt_0.I_39 AO1 Y Out 0.567 7.423 - N_51_i Net - - 1.639 - 8 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt_RNO[3] XA1A C In - 9.062 - corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt_RNO[3] XA1A Y Out 0.645 9.706 - period_cnt_RNO[3] Net - - 0.322 - 1 corepwm_0.genblk100\.genblk102\.genblk103\.timebase.period_cnt[3] DFN1C0 D In - 10.028 - ========================================================================================================================================== Total path delay (propagation time + setup) of 10.567 is 5.652(53.5%) logic and 4.915(46.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[5] MSSTOP_0_MSS_MASTER_APB_PADDR_\[5\] 2.679 0.053 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[6] MSSTOP_0_MSS_MASTER_APB_PADDR_\[6\] 2.679 0.090 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[4] MSSTOP_0_MSS_MASTER_APB_PADDR_\[4\] 2.679 0.192 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[7] MSSTOP_0_MSS_MASTER_APB_PADDR_\[7\] 2.679 0.229 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[2] MSSTOP_0_MSS_MASTER_APB_PADDR_\[2\] 2.679 0.409 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[3] MSSTOP_0_MSS_MASTER_APB_PADDR_\[3\] 2.679 0.519 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[14] MSSTOP_0_MSS_MASTER_APB_PADDR_\[14\] 2.679 2.947 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[12] MSSTOP_0_MSS_MASTER_APB_PADDR_\[12\] 2.679 3.009 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[13] MSSTOP_0_MSS_MASTER_APB_PADDR_\[13\] 2.679 3.060 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[15] MSSTOP_0_MSS_MASTER_APB_PADDR_\[15\] 2.679 3.187 ======================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------ MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[0] PRDATA_0 10.000 0.053 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[1] PRDATA_1 10.000 0.842 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[2] PRDATA_2 10.000 0.842 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[3] PRDATA_3 10.000 0.842 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[4] PRDATA_4 10.000 0.842 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[5] PRDATA_5 10.000 0.842 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[6] PRDATA_6 10.000 0.842 MSSTOP_0.MSS_ADLIB_INST MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[7] PRDATA_7 10.000 0.842 ============================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 9.947 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.053 Number of logic level(s): 5 Starting point: MSSTOP_0.MSS_ADLIB_INST / MSSPADDR[5] Ending point: MSSTOP_0.MSS_ADLIB_INST / MSSPRDATA[0] The start point is clocked by MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by MSSTOP_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSSTOP_0.MSS_ADLIB_INST MSS_APB MSSPADDR[5] Out 2.679 2.679 - MSSTOP_0_MSS_MASTER_APB_PADDR_\[5\] Net - - 0.806 - 3 corepwm_0.genblk96\.genblk97\.reg_if.psh_prescale_reg7_1_0 OR2 B In - 3.485 - corepwm_0.genblk96\.genblk97\.reg_if.psh_prescale_reg7_1_0 OR2 Y Out 0.646 4.132 - psh_prescale_reg7_1_0 Net - - 0.386 - 2 corepwm_0.genblk96\.genblk97\.reg_if.psh_prescale_reg7 OR3A C In - 4.518 - corepwm_0.genblk96\.genblk97\.reg_if.psh_prescale_reg7 OR3A Y Out 0.751 5.268 - psh_prescale_reg7 Net - - 1.669 - 9 corepwm_0.genblk96\.genblk97\.reg_if.period_reg_RNIBV6C[0] NOR2A B In - 6.937 - corepwm_0.genblk96\.genblk97\.reg_if.period_reg_RNIBV6C[0] NOR2A Y Out 0.407 7.343 - period_reg_m[0] Net - - 0.322 - 1 corepwm_0.genblk96\.genblk97\.reg_if.genblk0\.gen_pos_neg_shregs\[1\]\.psh_negedge_reg_RNI4TEN[1] AO1A C In - 7.665 - corepwm_0.genblk96\.genblk97\.reg_if.genblk0\.gen_pos_neg_shregs\[1\]\.psh_negedge_reg_RNI4TEN[1] AO1A Y Out 0.655 8.320 - PRDATA_regif_0_iv_1[0] Net - - 0.322 - 1 CoreAPB3_0.u_mux_p_to_b3.PRDATA_0 OA1B B In - 8.642 - CoreAPB3_0.u_mux_p_to_b3.PRDATA_0 OA1B Y Out 0.984 9.625 - PRDATA_0 Net - - 0.322 - 1 MSSTOP_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[0] In - 9.947 - =========================================================================================================================================================================== Total path delay (propagation time + setup) of 9.947 is 6.122(61.5%) logic and 3.825(38.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F200M3F_FBGA256_Std Report for cell SDTOP.verilog Core Cell usage: cell count area count*area AND2 3 1.0 3.0 AND2A 4 1.0 4.0 AND3 19 1.0 19.0 AO1 5 1.0 5.0 AO1A 7 1.0 7.0 AO1B 1 1.0 1.0 AO1C 6 1.0 6.0 AO1D 1 1.0 1.0 AOI1 8 1.0 8.0 AOI1A 4 1.0 4.0 AOI1B 1 1.0 1.0 GND 10 0.0 0.0 INV 1 1.0 1.0 MSS_CCC 1 0.0 0.0 NOR2 10 1.0 10.0 NOR2A 14 1.0 14.0 NOR2B 14 1.0 14.0 NOR3A 9 1.0 9.0 NOR3B 5 1.0 5.0 NOR3C 10 1.0 10.0 OA1 3 1.0 3.0 OA1A 4 1.0 4.0 OA1B 1 1.0 1.0 OA1C 1 1.0 1.0 OR2 8 1.0 8.0 OR2A 26 1.0 26.0 OR2B 2 1.0 2.0 OR3 2 1.0 2.0 OR3A 2 1.0 2.0 OR3B 2 1.0 2.0 OR3C 2 1.0 2.0 RCOSC 1 0.0 0.0 VCC 10 0.0 0.0 XA1 2 1.0 2.0 XA1A 5 1.0 5.0 XNOR2 12 1.0 12.0 XOR2 15 1.0 15.0 DFN1C0 33 1.0 33.0 DFN1E0C0 8 1.0 8.0 DFN1E0P0 1 1.0 1.0 DFN1E1C0 28 1.0 28.0 DFN1E1P0 1 1.0 1.0 DFN1P0 1 1.0 1.0 MSS_APB 1 0.0 0.0 ----- ---------- TOTAL 304 281.0 IO Cell usage: cell count INBUF_A 5 INBUF_MSS 1 OUTBUF 1 OUTBUF_A 2 ----- TOTAL 9 Core Cells : 281 of 4608 (6%) IO Cells : 9 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Mar 24 11:35:20 2011 ###########################################################]