library verilog;
use verilog.vl_types.all;
entity SDTOP is
    port(
        ADCDirectInput_0: in     vl_logic;
        ADCDirectInput_1: in     vl_logic;
        ADCDirectInput_2: in     vl_logic;
        VAREF1          : in     vl_logic;
        SDD_0           : out    vl_logic;
        SDD_1           : out    vl_logic;
        VAREF0          : in     vl_logic;
        MSS_RESET_N     : in     vl_logic;
        PWM             : out    vl_logic_vector(1 downto 1)
    );
end SDTOP;
