library verilog;
use verilog.vl_types.all;
entity corepwm is
    generic(
        FAMILY          : integer := 0;
        CONFIG_MODE     : integer := 0;
        PWM_NUM         : integer := 1;
        APB_DWIDTH      : integer := 8;
        FIXED_PRESCALE_EN: integer := 1;
        FIXED_PRESCALE  : integer := 8;
        FIXED_PERIOD_EN : integer := 0;
        FIXED_PERIOD    : integer := 8;
        DAC_MODE1       : integer := 0;
        DAC_MODE2       : integer := 0;
        DAC_MODE3       : integer := 0;
        DAC_MODE4       : integer := 0;
        DAC_MODE5       : integer := 0;
        DAC_MODE6       : integer := 0;
        DAC_MODE7       : integer := 0;
        DAC_MODE8       : integer := 0;
        DAC_MODE9       : integer := 0;
        DAC_MODE10      : integer := 0;
        DAC_MODE11      : integer := 0;
        DAC_MODE12      : integer := 0;
        DAC_MODE13      : integer := 0;
        DAC_MODE14      : integer := 0;
        DAC_MODE15      : integer := 0;
        DAC_MODE16      : integer := 0;
        SHADOW_REG_EN1  : integer := 0;
        SHADOW_REG_EN2  : integer := 0;
        SHADOW_REG_EN3  : integer := 0;
        SHADOW_REG_EN4  : integer := 0;
        SHADOW_REG_EN5  : integer := 0;
        SHADOW_REG_EN6  : integer := 0;
        SHADOW_REG_EN7  : integer := 0;
        SHADOW_REG_EN8  : integer := 0;
        SHADOW_REG_EN9  : integer := 0;
        SHADOW_REG_EN10 : integer := 0;
        SHADOW_REG_EN11 : integer := 0;
        SHADOW_REG_EN12 : integer := 0;
        SHADOW_REG_EN13 : integer := 0;
        SHADOW_REG_EN14 : integer := 0;
        SHADOW_REG_EN15 : integer := 0;
        SHADOW_REG_EN16 : integer := 0;
        FIXED_PWM_POS_EN1: integer := 1;
        FIXED_PWM_POS_EN2: integer := 1;
        FIXED_PWM_POS_EN3: integer := 1;
        FIXED_PWM_POS_EN4: integer := 1;
        FIXED_PWM_POS_EN5: integer := 1;
        FIXED_PWM_POS_EN6: integer := 1;
        FIXED_PWM_POS_EN7: integer := 1;
        FIXED_PWM_POS_EN8: integer := 1;
        FIXED_PWM_POS_EN9: integer := 1;
        FIXED_PWM_POS_EN10: integer := 1;
        FIXED_PWM_POS_EN11: integer := 1;
        FIXED_PWM_POS_EN12: integer := 1;
        FIXED_PWM_POS_EN13: integer := 1;
        FIXED_PWM_POS_EN14: integer := 1;
        FIXED_PWM_POS_EN15: integer := 1;
        FIXED_PWM_POS_EN16: integer := 1;
        FIXED_PWM_POSEDGE1: integer := 0;
        FIXED_PWM_POSEDGE2: integer := 0;
        FIXED_PWM_POSEDGE3: integer := 0;
        FIXED_PWM_POSEDGE4: integer := 0;
        FIXED_PWM_POSEDGE5: integer := 0;
        FIXED_PWM_POSEDGE6: integer := 0;
        FIXED_PWM_POSEDGE7: integer := 0;
        FIXED_PWM_POSEDGE8: integer := 0;
        FIXED_PWM_POSEDGE9: integer := 0;
        FIXED_PWM_POSEDGE10: integer := 0;
        FIXED_PWM_POSEDGE11: integer := 0;
        FIXED_PWM_POSEDGE12: integer := 0;
        FIXED_PWM_POSEDGE13: integer := 0;
        FIXED_PWM_POSEDGE14: integer := 0;
        FIXED_PWM_POSEDGE15: integer := 0;
        FIXED_PWM_POSEDGE16: integer := 0;
        FIXED_PWM_NEG_EN1: integer := 0;
        FIXED_PWM_NEG_EN2: integer := 0;
        FIXED_PWM_NEG_EN3: integer := 0;
        FIXED_PWM_NEG_EN4: integer := 0;
        FIXED_PWM_NEG_EN5: integer := 0;
        FIXED_PWM_NEG_EN6: integer := 0;
        FIXED_PWM_NEG_EN7: integer := 0;
        FIXED_PWM_NEG_EN8: integer := 0;
        FIXED_PWM_NEG_EN9: integer := 0;
        FIXED_PWM_NEG_EN10: integer := 0;
        FIXED_PWM_NEG_EN11: integer := 0;
        FIXED_PWM_NEG_EN12: integer := 0;
        FIXED_PWM_NEG_EN13: integer := 0;
        FIXED_PWM_NEG_EN14: integer := 0;
        FIXED_PWM_NEG_EN15: integer := 0;
        FIXED_PWM_NEG_EN16: integer := 0;
        FIXED_PWM_NEGEDGE1: integer := 0;
        FIXED_PWM_NEGEDGE2: integer := 0;
        FIXED_PWM_NEGEDGE3: integer := 0;
        FIXED_PWM_NEGEDGE4: integer := 0;
        FIXED_PWM_NEGEDGE5: integer := 0;
        FIXED_PWM_NEGEDGE6: integer := 0;
        FIXED_PWM_NEGEDGE7: integer := 0;
        FIXED_PWM_NEGEDGE8: integer := 0;
        FIXED_PWM_NEGEDGE9: integer := 0;
        FIXED_PWM_NEGEDGE10: integer := 0;
        FIXED_PWM_NEGEDGE11: integer := 0;
        FIXED_PWM_NEGEDGE12: integer := 0;
        FIXED_PWM_NEGEDGE13: integer := 0;
        FIXED_PWM_NEGEDGE14: integer := 0;
        FIXED_PWM_NEGEDGE15: integer := 0;
        FIXED_PWM_NEGEDGE16: integer := 0;
        PWM_STRETCH_VALUE1: integer := 0;
        PWM_STRETCH_VALUE2: integer := 0;
        PWM_STRETCH_VALUE3: integer := 0;
        PWM_STRETCH_VALUE4: integer := 0;
        PWM_STRETCH_VALUE5: integer := 0;
        PWM_STRETCH_VALUE6: integer := 0;
        PWM_STRETCH_VALUE7: integer := 0;
        PWM_STRETCH_VALUE8: integer := 0;
        PWM_STRETCH_VALUE9: integer := 0;
        PWM_STRETCH_VALUE10: integer := 0;
        PWM_STRETCH_VALUE11: integer := 0;
        PWM_STRETCH_VALUE12: integer := 0;
        PWM_STRETCH_VALUE13: integer := 0;
        PWM_STRETCH_VALUE14: integer := 0;
        PWM_STRETCH_VALUE15: integer := 0;
        PWM_STRETCH_VALUE16: integer := 0;
        TACH_NUM        : integer := 1;
        TACH_EDGE1      : integer := 0;
        TACH_EDGE2      : integer := 0;
        TACH_EDGE3      : integer := 0;
        TACH_EDGE4      : integer := 0;
        TACH_EDGE5      : integer := 0;
        TACH_EDGE6      : integer := 0;
        TACH_EDGE7      : integer := 0;
        TACH_EDGE8      : integer := 0;
        TACH_EDGE9      : integer := 0;
        TACH_EDGE10     : integer := 0;
        TACH_EDGE11     : integer := 0;
        TACH_EDGE12     : integer := 0;
        TACH_EDGE13     : integer := 0;
        TACH_EDGE14     : integer := 0;
        TACH_EDGE15     : integer := 0;
        TACH_EDGE16     : integer := 0;
        TACHINT_ACT_LEVEL: integer := 0
    );
    port(
        PRESETN         : in     vl_logic;
        PCLK            : in     vl_logic;
        PSEL            : in     vl_logic;
        PENABLE         : in     vl_logic;
        PWRITE          : in     vl_logic;
        PADDR           : in     vl_logic_vector(7 downto 0);
        PWDATA          : in     vl_logic_vector;
        PRDATA          : out    vl_logic_vector;
        PREADY          : out    vl_logic;
        PSLVERR         : out    vl_logic;
        TACHIN          : in     vl_logic_vector;
        TACHINT         : out    vl_logic;
        PWM             : out    vl_logic_vector
    );
end corepwm;
