#Build: Synplify Pro D-2010.03A-SP1 Igloo2 Alpha, Build 120R, Jul 13 2010 #install: \\idm\tools\releases\test\Synopsys\Synplify\pc\synplify_D201003ASP1_G4 #OS: Windows XP 5.1 #Hostname: WXP-CAE-01 #Implementation: synthesis #Wed Sep 22 11:16:44 2010 $ Start of Compile #Wed Sep 22 11:16:44 2010 Synopsys Verilog Compiler, version comp510rc, Build 117R, built Jul 13 2010 @N: : | Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @I::"\\idm\tools\releases\test\Synopsys\Synplify\pc\synplify_D201003ASP1_G4\lib\proasic\smartfusion.v" @I::"C:\Actelprj\Dynamic_webserver_Lab\HW\component\Actel\SmartFusionMSS\MSS\2.3.104\mss_comps.v" @I::"C:\Actelprj\Dynamic_webserver_Lab\HW\component\work\mss_Dynamic_webserver\MSS_CCC_0\mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v" @I::"C:\Actelprj\Dynamic_webserver_Lab\HW\component\work\mss_Dynamic_webserver\mss_Dynamic_webserver.v" Verilog syntax check successful! Selecting top level module mss_Dynamic_webserver @N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS @N:CG364 : mss_comps.v(37) | Synthesizing module OUTBUF_MSS @N:CG364 : mss_comps.v(85) | Synthesizing module BIBUF_OPEND_MSS @N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC @N:CG364 : mss_comps.v(1) | Synthesizing module MSS_XTLOSC @N:CG364 : smartfusion.v(1133) | Synthesizing module GND @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC @N:CG364 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC @N:CG364 : mss_comps.v(67) | Synthesizing module BIBUF_MSS @N:CG364 : mss_comps.v(51) | Synthesizing module TRIBUFF_MSS @N:CG364 : mss_comps.v(680) | Synthesizing module MSS_APB @N:CG364 : mss_Dynamic_webserver.v(5) | Synthesizing module mss_Dynamic_webserver @W:CL157 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL159 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused @W:CL159 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused @W:CL159 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused @W:CL159 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused @W:CL159 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused @W:CL159 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused @W:CL159 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused @W:CL159 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused @W:CL159 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused @W:CL159 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused @W:CL159 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused @W:CL159 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused @W:CL159 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused @W:CL159 : mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Sep 22 11:16:45 2010 ###########################################################] Synopsys Actel Technology Mapper, Version map520act, Build 096R, Built Jul 16 2010 10:19:54 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version D-2010.03A-SP1 Igloo2 Alpha @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO111 : mss_dynamic_webserver_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : mss_dynamic_webserver_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : mss_dynamic_webserver_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC) Automatic dissolve at startup in view:work.mss_Dynamic_webserver(verilog) of MSS_CCC_0(mss_Dynamic_webserver_tmp_MSS_CCC_0_MSS_CCC) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB) Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB) Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB) Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB) Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB) Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB) Writing Analyst data base C:\Actelprj\Dynamic_webserver_Lab\HW\synthesis\mss_Dynamic_webserver.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) Writing EDIF Netlist and constraint files D-2010.03A-SP1 Igloo2 Alpha Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) @W:MT246 : mss_dynamic_webserver.v(131) | Blackbox MSS_APB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_dynamic_webserver.v(102) | Blackbox TRIBUFF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_dynamic_webserver_tmp_mss_ccc_0_mss_ccc.v(97) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Sep 22 11:16:49 2010 # Top view: mss_Dynamic_webserver Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: 4.169 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------- System 100.0 MHz 171.5 MHz 10.000 5.831 4.169 system default_clkgroup ================================================================================================================ Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------- MSS_CCC_0.I_XTLOSC System MSS_XTLOSC CLKOUT N_CLKA_XTLOSC 0.000 4.169 MSS_ADLIB_INST System MSS_APB EMCCLK MSS_ADLIB_INST_EMCCLK 0.000 9.678 MSS_ADLIB_INST System MSS_APB SPI0DO MSS_SPI_0_DO_D 0.000 9.678 MSS_ADLIB_INST System MSS_APB SPI0DOE MSS_SPI_0_DO_E 0.000 9.678 MSS_ADLIB_INST System MSS_APB SPI1DO MSS_SPI_1_DO_D 0.000 9.678 MSS_ADLIB_INST System MSS_APB SPI1DOE MSS_SPI_1_DO_E 0.000 9.678 =========================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------- MSS_ADLIB_INST System MSS_APB PLLLOCK MSS_ADLIB_INST_PLLLOCK 10.000 4.169 MSS_ADLIB_INST System MSS_APB FCLK MSS_ADLIB_INST_FCLK 10.000 4.491 MSS_ADLIB_INST System MSS_APB MACCLKCCC MSS_ADLIB_INST_MACCLKCCC 10.000 4.491 MSS_ADLIB_INST System MSS_APB EMCCLKRTN MSS_ADLIB_INST_EMCCLK 10.000 9.678 MSS_SPI_0_DO System TRIBUFF_MSS D MSS_SPI_0_DO_D 10.000 9.678 MSS_SPI_0_DO System TRIBUFF_MSS E MSS_SPI_0_DO_E 10.000 9.678 MSS_SPI_1_DO System TRIBUFF_MSS D MSS_SPI_1_DO_D 10.000 9.678 MSS_SPI_1_DO System TRIBUFF_MSS E MSS_SPI_1_DO_E 10.000 9.678 ============================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 5.831 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : 4.169 Number of logic level(s): 1 Starting point: MSS_CCC_0.I_XTLOSC / CLKOUT Ending point: MSS_ADLIB_INST / PLLLOCK The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------- MSS_CCC_0.I_XTLOSC MSS_XTLOSC CLKOUT Out 0.000 0.000 - N_CLKA_XTLOSC Net - - 0.322 - 1 MSS_CCC_0.I_MSSCCC MSS_CCC CLKA In - 0.322 - MSS_CCC_0.I_MSSCCC MSS_CCC LOCKMSS Out 5.188 5.509 - MSS_ADLIB_INST_PLLLOCK Net - - 0.322 - 1 MSS_ADLIB_INST MSS_APB PLLLOCK In - 5.831 - ============================================================================================== Total path delay (propagation time + setup) of 5.831 is 5.188(89.0%) logic and 0.643(11.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F200M3F_FBGA256_Std Report for cell mss_Dynamic_webserver.verilog Core Cell usage: cell count area count*area GND 2 0.0 0.0 MSS_APB 1 0.0 0.0 MSS_CCC 1 0.0 0.0 VCC 2 0.0 0.0 ----- ---------- TOTAL 6 0.0 IO Cell usage: cell count BIBUF_MSS 5 BIBUF_OPEND_MSS 2 INBUF_MSS 8 MSS_XTLOSC 1 OUTBUF_MSS 5 TRIBUFF_MSS 2 ----- TOTAL 23 Core Cells : 0 of 4608 (0%) IO Cells : 23 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Sep 22 11:16:49 2010 ###########################################################]