#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 #install: \\idm\tools\releases\production\Libero\Libero_91\PC_Libero_9_1_0_18_winxp_32\Synopsys\synplify_E201009A-1 #OS: Windows XP 5.1 #Hostname: VXP-ARNIS #Implementation: synthesis #Wed Apr 27 13:45:49 2011 $ Start of Compile #Wed Apr 27 13:45:49 2011 Synopsys VHDL Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 @N: : | Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : top_level.vhd(8) | Top entity is set to top_level. VHDL syntax check successful! Options changed - recompiling @N:CD630 : top_level.vhd(8) | Synthesizing work.top_level.def_arch @N:CD630 : fic_master_trans.vhd(27) | Synthesizing work.fic_master_trans.fic_master_trans @N:CD233 : fic_master_trans.vhd(48) | Using sequential encoding for type ahb_master_states Post processing for work.fic_master_trans.fic_master_trans @N:CD630 : smartfusion.vhd(1784) | Synthesizing smartfusion.gnd.syn_black_box Post processing for smartfusion.gnd.syn_black_box @N:CD630 : mss_top.vhd(8) | Synthesizing work.mss_top.def_arch @N:CD630 : mss_comps.vhd(4) | Synthesizing work.inbuf_mss.def_arch Post processing for work.inbuf_mss.def_arch @N:CD630 : mss_comps.vhd(65) | Synthesizing work.bibuf_mss.def_arch Post processing for work.bibuf_mss.def_arch @N:CD630 : mss_comps.vhd(24) | Synthesizing work.outbuf_mss.def_arch Post processing for work.outbuf_mss.def_arch @N:CD630 : mss_comps.vhd(87) | Synthesizing work.bibuf_opend_mss.def_arch Post processing for work.bibuf_opend_mss.def_arch @N:CD630 : mss_comps.vhd(168) | Synthesizing work.mssint.def_arch Post processing for work.mssint.def_arch @N:CD630 : mss_comps.vhd(44) | Synthesizing work.tribuff_mss.def_arch Post processing for work.tribuff_mss.def_arch @N:CD630 : mss_tshell.vhd(4) | Synthesizing work.mss_ahb.def_arch Post processing for work.mss_ahb.def_arch @N:CD630 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(8) | Synthesizing work.mss_top_tmp_mss_ccc_0_mss_ccc.def_arch @N:CD630 : smartfusion.vhd(2742) | Synthesizing smartfusion.vcc.syn_black_box Post processing for smartfusion.vcc.syn_black_box @N:CD630 : mss_comps.vhd(432) | Synthesizing work.mss_xtlosc.def_arch Post processing for work.mss_xtlosc.def_arch @N:CD630 : mss_comps.vhd(472) | Synthesizing work.mss_ccc.def_arch Post processing for work.mss_ccc.def_arch Post processing for work.mss_top_tmp_mss_ccc_0_mss_ccc.def_arch @W:CL240 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(38) | LPXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(37) | MAINXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(36) | RCOSC_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible Post processing for work.mss_top.def_arch Post processing for work.top_level.def_arch @W:CL168 : top_level.vhd(358) | Pruning instance GND - not in use ... @W:CL168 : top_level.vhd(210) | Pruning instance VCC - not in use ... @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(10) | Input CLKA is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(11) | Input CLKA_PAD is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(12) | Input CLKA_PADP is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(13) | Input CLKA_PADN is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(14) | Input CLKB is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(15) | Input CLKB_PAD is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(16) | Input CLKB_PADP is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(17) | Input CLKB_PADN is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(18) | Input CLKC is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(19) | Input CLKC_PAD is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(20) | Input CLKC_PADP is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(21) | Input CLKC_PADN is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(23) | Input LPXIN is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.vhd(24) | Input MAC_CLK is unused @N:CL177 : fic_master_trans.vhd(63) | Sharing sequential element HWRITE. @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(8) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(9) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(10) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(11) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(12) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(13) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(14) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(15) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(16) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(17) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(18) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(19) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(20) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(21) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(22) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(23) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(24) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(25) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(26) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(27) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(28) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(29) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(30) to a constant 0 @W:CL190 : fic_master_trans.vhd(63) | Optimizing register bit HWRITE_DATA_TEMP(31) to a constant 0 @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 31 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 30 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 29 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 28 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 27 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 26 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 25 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 24 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 23 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 22 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 21 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 20 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 19 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 18 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 17 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 16 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 15 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 14 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 13 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 12 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 11 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 10 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 9 of HWRITE_DATA_TEMP(31 downto 0) @W:CL260 : fic_master_trans.vhd(63) | Pruning Register bit 8 of HWRITE_DATA_TEMP(31 downto 0) @W:CL159 : fic_master_trans.vhd(40) | Input HRESP is unused @W:CL159 : fic_master_trans.vhd(41) | Input HRDATA is unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Apr 27 13:45:50 2011 ###########################################################] Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:BN132 : fic_master_trans.vhd(63) | Removing sequential instance fic_master_trans_0.HTRANS[1:0], because it is equivalent to instance fic_master_trans_0.HSIZE[1:0] Available hyper_sources - for debug and ip models None Found @W: : mss_top_tmp_mss_ccc_0_mss_ccc.vhd(117) | Net mss_top_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. @W: : mss_top_tmp_mss_ccc_0_mss_ccc.vhd(117) | Net mss_top_0.MSS_ADLIB_INST_MACCLKCCC appears to be a clock source which was not identfied. Assuming default frequency. @W: : mss_top_tmp_mss_ccc_0_mss_ccc.vhd(117) | Net FAB_CLK appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) @N: : fic_master_trans.vhd(63) | Found counter in view:work.fic_master_trans(fic_master_trans) inst HWRITE_DATA_TEMP[7:0] @N:MF238 : fic_master_trans.vhd(76) | Found 30 bit incrementor, 'un2_haddr_temp[31:2]' @W:MO129 : fic_master_trans.vhd(63) | Sequential instance fic_master_trans_0.HSIZE[0] has been reduced to a combinational gate by constant propagation @W:BN132 : fic_master_trans.vhd(63) | Removing sequential instance fic_master_trans_0.HSIZE[1], because it is equivalent to instance fic_master_trans_0.HSEL_1 Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ----------------------------------------------------------------------------- fic_master_trans_0.HADDR_TEMP_0_sqmuxa / Y 31 mss_top_0.MSSINT_GPO_0 / Y 43 : 42 asynchronous set/reset ============================================================================= Replicating Combinational Instance fic_master_trans_0.HADDR_TEMP_0_sqmuxa, fanout 31 segments 2 Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Added 0 Buffers Added 1 Cells via replication Added 0 Sequential Cells via replication Added 1 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Writing Analyst data base C:\appnotes\AC363\A2F_AC363_DF\Pipelined_Mode\HW_FIC_MASTER\synthesis\top_level.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) @W:MT246 : mss_top.vhd(1077) | Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_top.vhd(1039) | Blackbox TRIBUFF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_top_tmp_mss_ccc_0_mss_ccc.vhd(155) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock mss_top|MSS_EMI_0_CLK_D_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:mss_top_0.MSS_EMI_0_CLK_D" @W:MT420 : | Found inferred clock mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:FAB_CLK" @W:MT420 : | Found inferred clock mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_MACCLKCCC_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:mss_top_0.MSS_ADLIB_INST_MACCLKCCC" @W:MT420 : | Found inferred clock mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:mss_top_0.MSS_ADLIB_INST_FCLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Apr 27 13:45:54 2011 # Top view: top_level Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: 0.867 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock 100.0 MHz 109.5 MHz 10.000 9.133 0.867 inferred Inferred_clkgroup_3 mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock 100.0 MHz 189.8 MHz 10.000 5.269 4.731 inferred Inferred_clkgroup_1 System 100.0 MHz NA 10.000 NA NA system system_clkgroup ======================================================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock System | 10.000 4.732 | No paths - | No paths - | No paths - mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock | 10.000 0.867 | No paths - | No paths - | No paths - ========================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- fic_master_trans_0.HWRITE_DATA_TEMP[1] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1C0 Q Z\\fic_master_trans_0_HWDATA_\[1\]\\ 0.737 0.867 fic_master_trans_0.HADDR_TEMP[5] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 Q Z\\fic_master_trans_0_HADDR_\[5\]\\ 0.737 0.888 fic_master_trans_0.HADDR_TEMP[6] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 Q Z\\fic_master_trans_0_HADDR_\[6\]\\ 0.737 0.890 fic_master_trans_0.HWRITE_DATA_TEMP[0] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1C0 Q Z\\fic_master_trans_0_HWDATA_\[0\]\\ 0.737 0.914 fic_master_trans_0.HADDR_TEMP[7] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 Q Z\\fic_master_trans_0_HADDR_\[7\]\\ 0.737 0.951 fic_master_trans_0.HWRITE_DATA_TEMP[2] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1C0 Q Z\\fic_master_trans_0_HWDATA_\[2\]\\ 0.737 1.210 fic_master_trans_0.HWRITE_DATA_TEMP[6] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1C0 Q Z\\fic_master_trans_0_HWDATA_\[6\]\\ 0.737 1.246 fic_master_trans_0.HADDR_TEMP[3] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 Q Z\\fic_master_trans_0_HADDR_\[3\]\\ 0.737 1.352 fic_master_trans_0.HWRITE_DATA_TEMP[5] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1C0 Q Z\\fic_master_trans_0_HWDATA_\[5\]\\ 0.737 1.359 fic_master_trans_0.HADDR_TEMP[2] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 Q Z\\fic_master_trans_0_HADDR_\[2\]\\ 0.737 1.392 =================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------- fic_master_trans_0.ahb_states[0] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1C0 D HADDR_TEMP_0_sqmuxa 9.461 0.867 fic_master_trans_0.HADDR_TEMP[30] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1C0 D I_203 9.461 0.888 fic_master_trans_0.HADDR_TEMP[31] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1C0 D I_210 9.461 0.888 fic_master_trans_0.HADDR_TEMP[10] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 E HADDR_TEMP_0_sqmuxa_0 9.566 0.926 fic_master_trans_0.HADDR_TEMP[11] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 E HADDR_TEMP_0_sqmuxa_0 9.566 0.926 fic_master_trans_0.HADDR_TEMP[12] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 E HADDR_TEMP_0_sqmuxa_0 9.566 0.926 fic_master_trans_0.HADDR_TEMP[13] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 E HADDR_TEMP_0_sqmuxa_0 9.566 0.926 fic_master_trans_0.HADDR_TEMP[14] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 E HADDR_TEMP_0_sqmuxa_0 9.566 0.926 fic_master_trans_0.HADDR_TEMP[15] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1C0 E HADDR_TEMP_0_sqmuxa_0 9.566 0.926 fic_master_trans_0.HADDR_TEMP[16] mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1C0 E HADDR_TEMP_0_sqmuxa_0 9.566 0.926 ================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 8.594 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.867 Number of logic level(s): 4 Starting point: fic_master_trans_0.HWRITE_DATA_TEMP[1] / Q Ending point: fic_master_trans_0.ahb_states[0] / D The start point is clocked by mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by mss_top_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------ fic_master_trans_0.HWRITE_DATA_TEMP[1] DFN1E1C0 Q Out 0.737 0.737 - Z\\fic_master_trans_0_HWDATA_\[1\]\\ Net - - 1.184 - 4 fic_master_trans_0.HWRITE_DATA_TEMP_RNI784C[2] NOR3C B In - 1.921 - fic_master_trans_0.HWRITE_DATA_TEMP_RNI784C[2] NOR3C Y Out 0.607 2.527 - HWRITE_DATA_TEMP_c2 Net - - 0.386 - 2 fic_master_trans_0.HWRITE_DATA_TEMP_RNIMT5G[3] NOR2B A In - 2.913 - fic_master_trans_0.HWRITE_DATA_TEMP_RNIMT5G[3] NOR2B Y Out 0.514 3.427 - HWRITE_DATA_TEMP_c3 Net - - 0.806 - 3 fic_master_trans_0.HWRITE_DATA_TEMP_RNIJUO61[7] AOI1B B In - 4.234 - fic_master_trans_0.HWRITE_DATA_TEMP_RNIJUO61[7] AOI1B Y Out 0.911 5.144 - un1_hreadyout Net - - 0.806 - 3 fic_master_trans_0.ahb_states_RNIA6791[0] NOR2A A In - 5.951 - fic_master_trans_0.ahb_states_RNIA6791[0] NOR2A Y Out 0.516 6.467 - HADDR_TEMP_0_sqmuxa Net - - 2.127 - 15 fic_master_trans_0.ahb_states[0] DFN1C0 D In - 8.594 - ================================================================================================================== Total path delay (propagation time + setup) of 9.133 is 3.823(41.9%) logic and 5.309(58.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------- mss_top_0.MSS_ADLIB_INST mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_AHB SPI0DOE MSS_SPI_0_DO_E 4.947 4.731 mss_top_0.MSS_ADLIB_INST mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_AHB SPI1DO MSS_SPI_1_DO_D 4.643 5.035 mss_top_0.MSS_ADLIB_INST mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_AHB SPI0DO MSS_SPI_0_DO_D 4.350 5.329 mss_top_0.MSS_ADLIB_INST mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_AHB SPI1DOE MSS_SPI_1_DO_E 4.318 5.361 mss_top_0.MSS_ADLIB_INST mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_AHB GPO[0] MSSINT_GPO_0_A 4.132 5.547 ============================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------- mss_top_0.MSS_SPI_0_DO mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock TRIBUFF_MSS E MSS_SPI_0_DO_E 10.000 4.731 mss_top_0.MSS_SPI_1_DO mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock TRIBUFF_MSS D MSS_SPI_1_DO_D 10.000 5.035 mss_top_0.MSS_SPI_0_DO mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock TRIBUFF_MSS D MSS_SPI_0_DO_D 10.000 5.329 mss_top_0.MSS_SPI_1_DO mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock TRIBUFF_MSS E MSS_SPI_1_DO_E 10.000 5.361 mss_top_0.MSSINT_GPO_0 mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSSINT A MSSINT_GPO_0_A 10.000 5.547 ============================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 5.269 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 4.731 Number of logic level(s): 0 Starting point: mss_top_0.MSS_ADLIB_INST / SPI0DOE Ending point: mss_top_0.MSS_SPI_0_DO / E The start point is clocked by mss_top_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------- mss_top_0.MSS_ADLIB_INST MSS_AHB SPI0DOE Out 4.947 4.947 - MSS_SPI_0_DO_E Net - - 0.322 - 1 mss_top_0.MSS_SPI_0_DO TRIBUFF_MSS E In - 5.269 - ================================================================================================= Total path delay (propagation time + setup) of 5.269 is 4.947(93.9%) logic and 0.322(6.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F200M3F_FBGA256_Std Report for cell top_level.def_arch Core Cell usage: cell count area count*area AND2 11 1.0 11.0 AND3 44 1.0 44.0 AOI1B 1 1.0 1.0 AX1C 2 1.0 2.0 GND 4 0.0 0.0 INV 1 1.0 1.0 MSSINT 1 0.0 0.0 MSS_CCC 1 0.0 0.0 NOR2A 2 1.0 2.0 NOR2B 8 1.0 8.0 NOR3C 2 1.0 2.0 VCC 4 0.0 0.0 XOR2 35 1.0 35.0 DFN1C0 4 1.0 4.0 DFN1E0C0 1 1.0 1.0 DFN1E1C0 23 1.0 23.0 DFN1E1P0 14 1.0 14.0 MSS_AHB 1 0.0 0.0 ----- ---------- TOTAL 159 148.0 IO Cell usage: cell count BIBUF_MSS 21 BIBUF_OPEND_MSS 4 INBUF_MSS 9 MSS_XTLOSC 1 OUTBUF 3 OUTBUF_MSS 40 TRIBUFF_MSS 2 ----- TOTAL 80 Core Cells : 148 of 4608 (3%) IO Cells : 80 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:03s realtime, 0h:00m:02s cputime # Wed Apr 27 13:45:54 2011 ###########################################################]