Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Dec 07 11:23:40 2011


Design: top_level
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      6.792
Max Clock-To-Out (ns):      11.457

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      7.506
Max Clock-To-Out (ns):      12.482

Clock Domain:               mss_ccc_gla1
Period (ns):                7.319
Frequency (MHz):            136.631
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.119
External Hold (ns):         4.172
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                20.000
Frequency (MHz):            50.000
Required Period (ns):       20.833
Required Frequency (MHz):   48.001
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               Input_clk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      5.720
Max Clock-To-Out (ns):      9.060

Clock Domain:               FAB_CLK
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          FABHREADYOUT
  Delay (ns):                  3.760
  Slack (ns):
  Arrival (ns):                6.792
  Required (ns):
  Clock to Out (ns):           6.792


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: FABHREADYOUT
  data arrival time                              6.792
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.032          Clock generation
  3.032
               +     1.746          cell: ADLIB:MSS_AHB_IP
  4.778                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (r)
               +     0.079          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  4.857                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (r)
               +     0.041          cell: ADLIB:MSS_IF
  4.898                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (r)
               +     0.530          net: FABHREADYOUT_c
  5.428                        FABHREADYOUT_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  5.707                        FABHREADYOUT_pad/U0/U1:DOUT (r)
               +     0.000          net: FABHREADYOUT_pad/U0/NET1
  5.707                        FABHREADYOUT_pad/U0/U0:D (r)
               +     1.085          cell: ADLIB:IOPAD_TRI
  6.792                        FABHREADYOUT_pad/U0/U0:PAD (r)
               +     0.000          net: FABHREADYOUT
  6.792                        FABHREADYOUT (r)
                                    
  6.792                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.032          Clock generation
  N/C
                                    
  N/C                          FABHREADYOUT (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        fic_master_trans_0/HSEL_1/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHSIZE[1]
  Delay (ns):                  0.979
  Slack (ns):                  0.912
  Arrival (ns):                5.302
  Required (ns):               4.390
  Hold (ns):                   1.358

Path 2
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[7]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[7]
  Delay (ns):                  0.998
  Slack (ns):                  0.947
  Arrival (ns):                5.330
  Required (ns):               4.383
  Hold (ns):                   1.351

Path 3
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[2]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[2]
  Delay (ns):                  1.010
  Slack (ns):                  0.959
  Arrival (ns):                5.342
  Required (ns):               4.383
  Hold (ns):                   1.351

Path 4
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[4]
  Delay (ns):                  1.036
  Slack (ns):                  0.985
  Arrival (ns):                5.368
  Required (ns):               4.383
  Hold (ns):                   1.351

Path 5
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[6]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[6]
  Delay (ns):                  1.136
  Slack (ns):                  1.074
  Arrival (ns):                5.459
  Required (ns):               4.385
  Hold (ns):                   1.353


Expanded Path 1
  From: fic_master_trans_0/HSEL_1/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHSIZE[1]
  data arrival time                              5.302
  data required time                         -   4.390
  slack                                          0.912
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.288          net: FAB_CLK
  4.323                        fic_master_trans_0/HSEL_1/U1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.571                        fic_master_trans_0/HSEL_1/U1:Q (r)
               +     0.695          net: fic_master_trans_0_HSEL
  5.266                        mss_top_0/MSS_ADLIB_INST/U_59:PIN6 (r)
               +     0.036          cell: ADLIB:MSS_IF
  5.302                        mss_top_0/MSS_ADLIB_INST/U_59:PIN6INT (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/FABHSIZE[1]INT_NET
  5.302                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHSIZE[1] (r)
                                    
  5.302                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.032          Clock generation
  3.032
               +     1.358          Library hold time: ADLIB:MSS_AHB_IP
  4.390                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHSIZE[1]
                                    
  4.390                        data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_0
  Delay (ns):                  4.474
  Slack (ns):
  Arrival (ns):                7.506
  Required (ns):
  Clock to Out (ns):           7.506


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: M2F_GPO_0
  data arrival time                              7.506
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.032          Clock generation
  3.032
               +     2.073          cell: ADLIB:MSS_AHB_IP
  5.105                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  5.105                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (r)
               +     0.041          cell: ADLIB:MSS_IF
  5.146                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (r)
               +     0.965          net: mss_top_0/MSSINT_GPO_0_A
  6.111                        M2F_GPO_0_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  6.390                        M2F_GPO_0_pad/U0/U1:DOUT (r)
               +     0.000          net: M2F_GPO_0_pad/U0/NET1
  6.390                        M2F_GPO_0_pad/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  7.506                        M2F_GPO_0_pad/U0/U0:PAD (r)
               +     0.000          net: M2F_GPO_0
  7.506                        M2F_GPO_0 (r)
                                    
  7.506                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.032          Clock generation
  N/C
                                    
  N/C                          M2F_GPO_0 (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        fic_master_trans_0/HADDR_TEMP[1]:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[1]:D
  Delay (ns):                  0.568
  Slack (ns):                  0.550
  Arrival (ns):                4.908
  Required (ns):               4.358
  Hold (ns):                   0.000

Path 2
  From:                        fic_master_trans_0/HADDR_TEMP[0]:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[0]:D
  Delay (ns):                  0.580
  Slack (ns):                  0.562
  Arrival (ns):                4.920
  Required (ns):               4.358
  Hold (ns):                   0.000

Path 3
  From:                        fic_master_trans_0/HSEL_1/U1:CLK
  To:                          fic_master_trans_0/HSEL_1/U1:D
  Delay (ns):                  0.796
  Slack (ns):                  0.781
  Arrival (ns):                5.119
  Required (ns):               4.338
  Hold (ns):                   0.000

Path 4
  From:                        fic_master_trans_0/HADDR_TEMP[18]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[18]/U1:D
  Delay (ns):                  0.803
  Slack (ns):                  0.785
  Arrival (ns):                5.142
  Required (ns):               4.357
  Hold (ns):                   0.000

Path 5
  From:                        fic_master_trans_0/HADDR_TEMP[20]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[20]/U1:D
  Delay (ns):                  0.821
  Slack (ns):                  0.803
  Arrival (ns):                5.160
  Required (ns):               4.357
  Hold (ns):                   0.000


Expanded Path 1
  From: fic_master_trans_0/HADDR_TEMP[1]:CLK
  To: fic_master_trans_0/HADDR_TEMP[1]:D
  data arrival time                              4.908
  data required time                         -   4.358
  slack                                          0.550
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.305          net: FAB_CLK
  4.340                        fic_master_trans_0/HADDR_TEMP[1]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.588                        fic_master_trans_0/HADDR_TEMP[1]:Q (r)
               +     0.320          net: _fic_master_trans_0_HADDR_[1]_
  4.908                        fic_master_trans_0/HADDR_TEMP[1]:D (r)
                                    
  4.908                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.323          net: FAB_CLK
  4.358                        fic_master_trans_0/HADDR_TEMP[1]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.358                        fic_master_trans_0/HADDR_TEMP[1]:D
                                    
  4.358                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HSEL_1/U1:D
  Delay (ns):                  3.851
  Slack (ns):                  2.545
  Arrival (ns):                6.883
  Required (ns):               4.338
  Hold (ns):                   0.000

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/ahb_states[0]:D
  Delay (ns):                  4.049
  Slack (ns):                  2.718
  Arrival (ns):                7.081
  Required (ns):               4.363
  Hold (ns):                   0.000

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[29]/U1:D
  Delay (ns):                  4.389
  Slack (ns):                  3.058
  Arrival (ns):                7.421
  Required (ns):               4.363
  Hold (ns):                   0.000

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[2]/U1:D
  Delay (ns):                  4.398
  Slack (ns):                  3.071
  Arrival (ns):                7.430
  Required (ns):               4.359
  Hold (ns):                   0.000

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[8]/U1:D
  Delay (ns):                  4.395
  Slack (ns):                  3.073
  Arrival (ns):                7.427
  Required (ns):               4.354
  Hold (ns):                   0.000


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: fic_master_trans_0/HSEL_1/U1:D
  data arrival time                              6.883
  data required time                         -   4.338
  slack                                          2.545
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.032          Clock generation
  3.032
               +     1.715          cell: ADLIB:MSS_AHB_IP
  4.747                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (f)
               +     0.095          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  4.842                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (f)
               +     0.042          cell: ADLIB:MSS_IF
  4.884                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (f)
               +     0.959          net: FABHREADYOUT_c
  5.843                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[7]:C (f)
               +     0.175          cell: ADLIB:AOI1B
  6.018                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[7]:Y (f)
               +     0.467          net: fic_master_trans_0/un1_hreadyout
  6.485                        fic_master_trans_0/HSEL_1/U0:A (f)
               +     0.251          cell: ADLIB:MX2
  6.736                        fic_master_trans_0/HSEL_1/U0:Y (f)
               +     0.147          net: fic_master_trans_0/HSEL_1/Y
  6.883                        fic_master_trans_0/HSEL_1/U1:D (f)
                                    
  6.883                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.303          net: FAB_CLK
  4.338                        fic_master_trans_0/HSEL_1/U1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.338                        fic_master_trans_0/HSEL_1/U1:D
                                    
  4.338                        data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_pclk1 to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[1]:CLR
  Delay (ns):                  2.294
  Slack (ns):                  0.968
  Arrival (ns):                5.326
  Required (ns):               4.358
  Hold (ns):

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[7]/U1:PRE
  Delay (ns):                  2.736
  Slack (ns):                  1.405
  Arrival (ns):                5.768
  Required (ns):               4.363
  Hold (ns):

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[0]:CLR
  Delay (ns):                  2.733
  Slack (ns):                  1.407
  Arrival (ns):                5.765
  Required (ns):               4.358
  Hold (ns):

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[17]/U1:CLR
  Delay (ns):                  2.765
  Slack (ns):                  1.440
  Arrival (ns):                5.797
  Required (ns):               4.357
  Hold (ns):

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[2]/U1:PRE
  Delay (ns):                  2.818
  Slack (ns):                  1.491
  Arrival (ns):                5.850
  Required (ns):               4.359
  Hold (ns):


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: fic_master_trans_0/HADDR_TEMP[1]:CLR
  data arrival time                              5.326
  data required time                         -   4.358
  slack                                          0.968
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.032          Clock generation
  3.032
               +     2.073          cell: ADLIB:MSS_AHB_IP
  5.105                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  5.105                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (r)
               +     0.041          cell: ADLIB:MSS_IF
  5.146                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (r)
               +     0.180          net: mss_top_0/MSSINT_GPO_0_A
  5.326                        fic_master_trans_0/HADDR_TEMP[1]:CLR (r)
                                    
  5.326                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.323          net: FAB_CLK
  4.358                        fic_master_trans_0/HADDR_TEMP[1]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  4.358                        fic_master_trans_0/HADDR_TEMP[1]:CLR
                                    
  4.358                        data required time


END SET mss_pclk1 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   1.354
  External Hold (ns):          4.172


Expanded Path 1
  From: MSS_RESET_N
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        mss_top_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        mss_top_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: mss_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.276                        mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.370          net: mss_top_0/GLA0
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.354          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_ccc_gla0

Path 1
  From:                        fic_master_trans_0/HADDR_TEMP[0]:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[0]
  Delay (ns):                  0.924
  Slack (ns):                  0.888
  Arrival (ns):                5.264
  Required (ns):               4.376
  Hold (ns):                   1.282

Path 2
  From:                        fic_master_trans_0/HADDR_TEMP[28]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[28]
  Delay (ns):                  1.010
  Slack (ns):                  0.922
  Arrival (ns):                5.341
  Required (ns):               4.419
  Hold (ns):                   1.325

Path 3
  From:                        fic_master_trans_0/HADDR_TEMP[17]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[17]
  Delay (ns):                  0.878
  Slack (ns):                  0.946
  Arrival (ns):                5.217
  Required (ns):               4.271
  Hold (ns):                   1.177

Path 4
  From:                        fic_master_trans_0/HADDR_TEMP[20]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[20]
  Delay (ns):                  0.888
  Slack (ns):                  0.970
  Arrival (ns):                5.227
  Required (ns):               4.257
  Hold (ns):                   1.163

Path 5
  From:                        fic_master_trans_0/HADDR_TEMP[22]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[22]
  Delay (ns):                  0.914
  Slack (ns):                  0.974
  Arrival (ns):                5.253
  Required (ns):               4.279
  Hold (ns):                   1.185


Expanded Path 1
  From: fic_master_trans_0/HADDR_TEMP[0]:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[0]
  data arrival time                              5.264
  data required time                         -   4.376
  slack                                          0.888
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.305          net: FAB_CLK
  4.340                        fic_master_trans_0/HADDR_TEMP[0]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.588                        fic_master_trans_0/HADDR_TEMP[0]:Q (r)
               +     0.413          net: _fic_master_trans_0_HADDR_[0]_
  5.001                        mss_top_0/MSS_ADLIB_INST/U_30:PIN5 (r)
               +     0.037          cell: ADLIB:MSS_IF
  5.038                        mss_top_0/MSS_ADLIB_INST/U_30:PIN5INT (r)
               +     0.226          net: mss_top_0/MSS_ADLIB_INST/FABHADDR[0]INT_NET
  5.264                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[0] (r)
                                    
  5.264                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.370          net: mss_top_0/GLA0
  3.094                        mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.282          Library hold time: ADLIB:MSS_AHB_IP
  4.376                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[0]
                                    
  4.376                        data required time


END SET mss_ccc_gla1 to mss_ccc_gla0

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain Input_clk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          FAB_CLK
  Delay (ns):                  5.720
  Slack (ns):
  Arrival (ns):                5.720
  Required (ns):
  Clock to Out (ns):           5.720


Expanded Path 1
  From: mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: FAB_CLK
  data arrival time                              5.720
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Input_clk
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     4.035          cell: ADLIB:MSS_CCC_IP
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.290          net: FAB_CLK
  4.325                        FAB_CLK_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  4.604                        FAB_CLK_pad/U0/U1:DOUT (r)
               +     0.000          net: FAB_CLK_pad/U0/NET1
  4.604                        FAB_CLK_pad/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  5.720                        FAB_CLK_pad/U0/U0:PAD (r)
               +     0.000          net: FAB_CLK_c
  5.720                        FAB_CLK (r)
                                    
  5.720                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          Input_clk
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          FAB_CLK (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain FAB_CLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

