Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Dec 07 16:07:42 2011


Design: top_level
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      7.853
Max Clock-To-Out (ns):      13.358

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      8.272
Max Clock-To-Out (ns):      13.699

Clock Domain:               mss_ccc_gla1
Period (ns):                8.222
Frequency (MHz):            121.625
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.119
External Hold (ns):         4.172
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                20.000
Frequency (MHz):            50.000
Required Period (ns):       20.833
Required Frequency (MHz):   48.001
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               Input_clk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      5.741
Max Clock-To-Out (ns):      9.093

Clock Domain:               FAB_CLK
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          FABHREADYOUT
  Delay (ns):                  4.821
  Slack (ns):
  Arrival (ns):                7.853
  Required (ns):
  Clock to Out (ns):           7.853


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: FABHREADYOUT
  data arrival time                              7.853
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.032          Clock generation
  3.032
               +     2.801          cell: ADLIB:MSS_AHB_IP
  5.833                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (r)
               +     0.079          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  5.912                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (r)
               +     0.041          cell: ADLIB:MSS_IF
  5.953                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (r)
               +     0.536          net: FABHREADYOUT_c
  6.489                        FABHREADYOUT_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  6.768                        FABHREADYOUT_pad/U0/U1:DOUT (r)
               +     0.000          net: FABHREADYOUT_pad/U0/NET1
  6.768                        FABHREADYOUT_pad/U0/U0:D (r)
               +     1.085          cell: ADLIB:IOPAD_TRI
  7.853                        FABHREADYOUT_pad/U0/U0:PAD (r)
               +     0.000          net: FABHREADYOUT
  7.853                        FABHREADYOUT (r)
                                    
  7.853                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.032          Clock generation
  N/C
                                    
  N/C                          FABHREADYOUT (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        fic_master_trans_0/HSEL/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHSIZE[1]
  Delay (ns):                  0.482
  Slack (ns):                  0.442
  Arrival (ns):                4.832
  Required (ns):               4.390
  Hold (ns):                   1.358

Path 2
  From:                        fic_master_trans_0/HSEL/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  Delay (ns):                  0.545
  Slack (ns):                  0.675
  Arrival (ns):                4.895
  Required (ns):               4.220
  Hold (ns):                   1.188

Path 3
  From:                        fic_master_trans_0/HSEL/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHSEL
  Delay (ns):                  0.689
  Slack (ns):                  0.883
  Arrival (ns):                5.039
  Required (ns):               4.156
  Hold (ns):                   1.124

Path 4
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[6]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[6]
  Delay (ns):                  0.994
  Slack (ns):                  0.942
  Arrival (ns):                5.327
  Required (ns):               4.385
  Hold (ns):                   1.353

Path 5
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[1]
  Delay (ns):                  1.015
  Slack (ns):                  0.957
  Arrival (ns):                5.338
  Required (ns):               4.381
  Hold (ns):                   1.349


Expanded Path 1
  From: fic_master_trans_0/HSEL/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHSIZE[1]
  data arrival time                              4.832
  data required time                         -   4.390
  slack                                          0.442
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.315          net: FAB_CLK
  4.350                        fic_master_trans_0/HSEL/U1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.598                        fic_master_trans_0/HSEL/U1:Q (r)
               +     0.198          net: fic_master_trans_0_HSEL
  4.796                        mss_top_0/MSS_ADLIB_INST/U_59:PIN6 (r)
               +     0.036          cell: ADLIB:MSS_IF
  4.832                        mss_top_0/MSS_ADLIB_INST/U_59:PIN6INT (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/FABHSIZE[1]INT_NET
  4.832                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHSIZE[1] (r)
                                    
  4.832                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.032          Clock generation
  3.032
               +     1.358          Library hold time: ADLIB:MSS_AHB_IP
  4.390                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHSIZE[1]
                                    
  4.390                        data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_0
  Delay (ns):                  5.240
  Slack (ns):
  Arrival (ns):                8.272
  Required (ns):
  Clock to Out (ns):           8.272


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: M2F_GPO_0
  data arrival time                              8.272
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.032          Clock generation
  3.032
               +     2.073          cell: ADLIB:MSS_AHB_IP
  5.105                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  5.105                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (r)
               +     0.041          cell: ADLIB:MSS_IF
  5.146                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (r)
               +     1.762          net: mss_top_0/MSSINT_GPO_0_A
  6.908                        M2F_GPO_0_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  7.187                        M2F_GPO_0_pad/U0/U1:DOUT (r)
               +     0.000          net: M2F_GPO_0_pad/U0/NET1
  7.187                        M2F_GPO_0_pad/U0/U0:D (r)
               +     1.085          cell: ADLIB:IOPAD_TRI
  8.272                        M2F_GPO_0_pad/U0/U0:PAD (r)
               +     0.000          net: M2F_GPO_0
  8.272                        M2F_GPO_0 (r)
                                    
  8.272                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.032          Clock generation
  N/C
                                    
  N/C                          M2F_GPO_0 (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        fic_master_trans_0/HADDR_TEMP[1]:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[1]:D
  Delay (ns):                  0.557
  Slack (ns):                  0.529
  Arrival (ns):                4.946
  Required (ns):               4.417
  Hold (ns):                   0.000

Path 2
  From:                        fic_master_trans_0/HADDR_TEMP[0]:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[0]:D
  Delay (ns):                  0.557
  Slack (ns):                  0.540
  Arrival (ns):                4.893
  Required (ns):               4.353
  Hold (ns):                   0.000

Path 3
  From:                        fic_master_trans_0/ahb_states[0]:CLK
  To:                          fic_master_trans_0/ahb_states[0]:D
  Delay (ns):                  0.739
  Slack (ns):                  0.723
  Arrival (ns):                5.070
  Required (ns):               4.347
  Hold (ns):                   0.000

Path 4
  From:                        fic_master_trans_0/HADDR_TEMP[20]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[20]/U1:D
  Delay (ns):                  0.789
  Slack (ns):                  0.765
  Arrival (ns):                5.159
  Required (ns):               4.394
  Hold (ns):                   0.000

Path 5
  From:                        fic_master_trans_0/HADDR_TEMP[22]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[22]/U1:D
  Delay (ns):                  0.789
  Slack (ns):                  0.765
  Arrival (ns):                5.159
  Required (ns):               4.394
  Hold (ns):                   0.000


Expanded Path 1
  From: fic_master_trans_0/HADDR_TEMP[1]:CLK
  To: fic_master_trans_0/HADDR_TEMP[1]:D
  data arrival time                              4.946
  data required time                         -   4.417
  slack                                          0.529
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.354          net: FAB_CLK
  4.389                        fic_master_trans_0/HADDR_TEMP[1]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.637                        fic_master_trans_0/HADDR_TEMP[1]:Q (r)
               +     0.309          net: _fic_master_trans_0_HADDR_[1]_
  4.946                        fic_master_trans_0/HADDR_TEMP[1]:D (r)
                                    
  4.946                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.382          net: FAB_CLK
  4.417                        fic_master_trans_0/HADDR_TEMP[1]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.417                        fic_master_trans_0/HADDR_TEMP[1]:D
                                    
  4.417                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/ahb_states[0]:D
  Delay (ns):                  5.085
  Slack (ns):                  3.770
  Arrival (ns):                8.117
  Required (ns):               4.347
  Hold (ns):                   0.000

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[2]/U1:D
  Delay (ns):                  5.317
  Slack (ns):                  4.005
  Arrival (ns):                8.349
  Required (ns):               4.344
  Hold (ns):                   0.000

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[3]/U1:D
  Delay (ns):                  5.319
  Slack (ns):                  4.007
  Arrival (ns):                8.351
  Required (ns):               4.344
  Hold (ns):                   0.000

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[20]/U1:D
  Delay (ns):                  5.504
  Slack (ns):                  4.142
  Arrival (ns):                8.536
  Required (ns):               4.394
  Hold (ns):                   0.000

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[24]/U1:D
  Delay (ns):                  5.504
  Slack (ns):                  4.142
  Arrival (ns):                8.536
  Required (ns):               4.394
  Hold (ns):                   0.000


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: fic_master_trans_0/ahb_states[0]:D
  data arrival time                              8.117
  data required time                         -   4.347
  slack                                          3.770
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.032          Clock generation
  3.032
               +     2.801          cell: ADLIB:MSS_AHB_IP
  5.833                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (r)
               +     0.079          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  5.912                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (r)
               +     0.041          cell: ADLIB:MSS_IF
  5.953                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (r)
               +     0.965          net: FABHREADYOUT_c
  6.918                        fic_master_trans_0/HWRITE_DATA_TEMP_RNI7LN21[1]:B (r)
               +     0.221          cell: ADLIB:NOR2B
  7.139                        fic_master_trans_0/HWRITE_DATA_TEMP_RNI7LN21[1]:Y (r)
               +     0.502          net: fic_master_trans_0/un9_hreadyout
  7.641                        fic_master_trans_0/ahb_states_RNIHRUB2[0]:B (r)
               +     0.290          cell: ADLIB:MX2
  7.931                        fic_master_trans_0/ahb_states_RNIHRUB2[0]:Y (r)
               +     0.186          net: fic_master_trans_0/ahb_states_RNIHRUB2[0]
  8.117                        fic_master_trans_0/ahb_states[0]:D (r)
                                    
  8.117                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.312          net: FAB_CLK
  4.347                        fic_master_trans_0/ahb_states[0]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.347                        fic_master_trans_0/ahb_states[0]:D
                                    
  4.347                        data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_pclk1 to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[0]:CLR
  Delay (ns):                  2.722
  Slack (ns):                  1.401
  Arrival (ns):                5.754
  Required (ns):               4.353
  Hold (ns):

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[2]/U1:PRE
  Delay (ns):                  2.719
  Slack (ns):                  1.408
  Arrival (ns):                5.751
  Required (ns):               4.343
  Hold (ns):

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[17]/U1:CLR
  Delay (ns):                  2.735
  Slack (ns):                  1.420
  Arrival (ns):                5.767
  Required (ns):               4.347
  Hold (ns):

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[12]/U1:PRE
  Delay (ns):                  2.735
  Slack (ns):                  1.420
  Arrival (ns):                5.767
  Required (ns):               4.347
  Hold (ns):

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[5]/U1:PRE
  Delay (ns):                  2.824
  Slack (ns):                  1.509
  Arrival (ns):                5.856
  Required (ns):               4.347
  Hold (ns):


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: fic_master_trans_0/HADDR_TEMP[0]:CLR
  data arrival time                              5.754
  data required time                         -   4.353
  slack                                          1.401
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.032          Clock generation
  3.032
               +     2.073          cell: ADLIB:MSS_AHB_IP
  5.105                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  5.105                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (r)
               +     0.041          cell: ADLIB:MSS_IF
  5.146                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (r)
               +     0.608          net: mss_top_0/MSSINT_GPO_0_A
  5.754                        fic_master_trans_0/HADDR_TEMP[0]:CLR (r)
                                    
  5.754                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.318          net: FAB_CLK
  4.353                        fic_master_trans_0/HADDR_TEMP[0]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  4.353                        fic_master_trans_0/HADDR_TEMP[0]:CLR
                                    
  4.353                        data required time


END SET mss_pclk1 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   1.354
  External Hold (ns):          4.172


Expanded Path 1
  From: MSS_RESET_N
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        mss_top_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        mss_top_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: mss_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.276                        mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.370          net: mss_top_0/GLA0
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.354          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_ccc_gla0

Path 1
  From:                        fic_master_trans_0/HADDR_TEMP[28]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[28]
  Delay (ns):                  0.629
  Slack (ns):                  0.560
  Arrival (ns):                4.979
  Required (ns):               4.419
  Hold (ns):                   1.325

Path 2
  From:                        fic_master_trans_0/HADDR_TEMP[0]:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[0]
  Delay (ns):                  0.646
  Slack (ns):                  0.606
  Arrival (ns):                4.982
  Required (ns):               4.376
  Hold (ns):                   1.282

Path 3
  From:                        fic_master_trans_0/HADDR_TEMP[29]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[29]
  Delay (ns):                  0.694
  Slack (ns):                  0.628
  Arrival (ns):                5.044
  Required (ns):               4.416
  Hold (ns):                   1.322

Path 4
  From:                        fic_master_trans_0/HADDR_TEMP[31]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[31]
  Delay (ns):                  0.698
  Slack (ns):                  0.633
  Arrival (ns):                5.048
  Required (ns):               4.415
  Hold (ns):                   1.321

Path 5
  From:                        fic_master_trans_0/HADDR_TEMP[1]:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[1]
  Delay (ns):                  0.642
  Slack (ns):                  0.661
  Arrival (ns):                5.031
  Required (ns):               4.370
  Hold (ns):                   1.276


Expanded Path 1
  From: fic_master_trans_0/HADDR_TEMP[28]/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[28]
  data arrival time                              4.979
  data required time                         -   4.419
  slack                                          0.560
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.315          net: FAB_CLK
  4.350                        fic_master_trans_0/HADDR_TEMP[28]/U1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.598                        fic_master_trans_0/HADDR_TEMP[28]/U1:Q (r)
               +     0.136          net: _fic_master_trans_0_HADDR_[28]_
  4.734                        mss_top_0/MSS_ADLIB_INST/U_46:PIN4 (r)
               +     0.037          cell: ADLIB:MSS_IF
  4.771                        mss_top_0/MSS_ADLIB_INST/U_46:PIN4INT (r)
               +     0.208          net: mss_top_0/MSS_ADLIB_INST/FABHADDR[28]INT_NET
  4.979                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[28] (r)
                                    
  4.979                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.370          net: mss_top_0/GLA0
  3.094                        mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.325          Library hold time: ADLIB:MSS_AHB_IP
  4.419                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[28]
                                    
  4.419                        data required time


END SET mss_ccc_gla1 to mss_ccc_gla0

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain Input_clk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          FAB_CLK
  Delay (ns):                  5.741
  Slack (ns):
  Arrival (ns):                5.741
  Required (ns):
  Clock to Out (ns):           5.741


Expanded Path 1
  From: mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: FAB_CLK
  data arrival time                              5.741
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Input_clk
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     4.035          cell: ADLIB:MSS_CCC_IP
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.311          net: FAB_CLK
  4.346                        FAB_CLK_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  4.625                        FAB_CLK_pad/U0/U1:DOUT (r)
               +     0.000          net: FAB_CLK_pad/U0/NET1
  4.625                        FAB_CLK_pad/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  5.741                        FAB_CLK_pad/U0/U0:PAD (r)
               +     0.000          net: FAB_CLK_c
  5.741                        FAB_CLK (r)
                                    
  5.741                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          Input_clk
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          FAB_CLK (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain FAB_CLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

