Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Dec 07 16:57:05 2011


Design: top_level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      7.434
Max Clock-To-Out (ns):      14.192

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      7.621
Max Clock-To-Out (ns):      14.450

Clock Domain:               mss_ccc_gla1
Period (ns):                9.008
Frequency (MHz):            111.012
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.206
External Hold (ns):         4.012
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                25.000
Frequency (MHz):            40.000
Required Period (ns):       20.833
Required Frequency (MHz):   48.001
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               Input_clk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      5.789
Max Clock-To-Out (ns):      9.891

Clock Domain:               FAB_CLK
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          FABHREADYOUT
  Delay (ns):                  4.485
  Slack (ns):
  Arrival (ns):                7.434
  Required (ns):
  Clock to Out (ns):           7.434


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: FABHREADYOUT
  data arrival time                              7.434
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.567          cell: ADLIB:MSS_AHB_IP
  4.516                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (r)
               +     0.080          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  4.596                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (r)
               +     0.042          cell: ADLIB:MSS_IF
  4.638                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (r)
               +     1.398          net: FABHREADYOUT_c
  6.036                        FABHREADYOUT_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  6.315                        FABHREADYOUT_pad/U0/U1:DOUT (r)
               +     0.000          net: FABHREADYOUT_pad/U0/NET1
  6.315                        FABHREADYOUT_pad/U0/U0:D (r)
               +     1.119          cell: ADLIB:IOPAD_TRI
  7.434                        FABHREADYOUT_pad/U0/U0:PAD (r)
               +     0.000          net: FABHREADYOUT
  7.434                        FABHREADYOUT (r)
                                    
  7.434                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  N/C
                                    
  N/C                          FABHREADYOUT (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[5]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[5]
  Delay (ns):                  0.952
  Slack (ns):                  1.028
  Arrival (ns):                5.317
  Required (ns):               4.289
  Hold (ns):                   1.340

Path 2
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[7]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[7]
  Delay (ns):                  1.056
  Slack (ns):                  1.136
  Arrival (ns):                5.421
  Required (ns):               4.285
  Hold (ns):                   1.336

Path 3
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[2]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[2]
  Delay (ns):                  1.070
  Slack (ns):                  1.149
  Arrival (ns):                5.437
  Required (ns):               4.288
  Hold (ns):                   1.339

Path 4
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[4]
  Delay (ns):                  1.090
  Slack (ns):                  1.170
  Arrival (ns):                5.457
  Required (ns):               4.287
  Hold (ns):                   1.338

Path 5
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[3]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[3]
  Delay (ns):                  1.094
  Slack (ns):                  1.175
  Arrival (ns):                5.461
  Required (ns):               4.286
  Hold (ns):                   1.337


Expanded Path 1
  From: fic_master_trans_0/HWRITE_DATA_TEMP[5]/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[5]
  data arrival time                              5.317
  data required time                         -   4.289
  slack                                          1.028
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.330          net: FAB_CLK
  4.365                        fic_master_trans_0/HWRITE_DATA_TEMP[5]/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.614                        fic_master_trans_0/HWRITE_DATA_TEMP[5]/U1:Q (r)
               +     0.463          net: _fic_master_trans_0_HWDATA_[5]_
  5.077                        mss_top_0/MSS_ADLIB_INST/U_49:PIN4 (r)
               +     0.037          cell: ADLIB:MSS_IF
  5.114                        mss_top_0/MSS_ADLIB_INST/U_49:PIN4INT (r)
               +     0.203          net: mss_top_0/MSS_ADLIB_INST/FABHWDATA[5]INT_NET
  5.317                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[5] (r)
                                    
  5.317                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.340          Library hold time: ADLIB:MSS_AHB_IP
  4.289                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[5]
                                    
  4.289                        data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_0
  Delay (ns):                  4.672
  Slack (ns):
  Arrival (ns):                7.621
  Required (ns):
  Clock to Out (ns):           7.621


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: M2F_GPO_0
  data arrival time                              7.621
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     2.949          Clock generation
  2.949
               +     2.091          cell: ADLIB:MSS_AHB_IP
  5.040                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  5.040                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (r)
               +     0.042          cell: ADLIB:MSS_IF
  5.082                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (r)
               +     1.141          net: mss_top_0/MSSINT_GPO_0_A
  6.223                        M2F_GPO_0_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  6.502                        M2F_GPO_0_pad/U0/U1:DOUT (r)
               +     0.000          net: M2F_GPO_0_pad/U0/NET1
  6.502                        M2F_GPO_0_pad/U0/U0:D (r)
               +     1.119          cell: ADLIB:IOPAD_TRI
  7.621                        M2F_GPO_0_pad/U0/U0:PAD (r)
               +     0.000          net: M2F_GPO_0
  7.621                        M2F_GPO_0 (r)
                                    
  7.621                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     2.949          Clock generation
  N/C
                                    
  N/C                          M2F_GPO_0 (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        fic_master_trans_0/HADDR_TEMP[0]:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[0]:D
  Delay (ns):                  0.585
  Slack (ns):                  0.570
  Arrival (ns):                4.948
  Required (ns):               4.378
  Hold (ns):                   0.000

Path 2
  From:                        fic_master_trans_0/HADDR_TEMP[1]:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[1]:D
  Delay (ns):                  0.596
  Slack (ns):                  0.581
  Arrival (ns):                4.959
  Required (ns):               4.378
  Hold (ns):                   0.000

Path 3
  From:                        fic_master_trans_0/HSEL_1/U1:CLK
  To:                          fic_master_trans_0/HSEL_1/U1:D
  Delay (ns):                  0.800
  Slack (ns):                  0.784
  Arrival (ns):                5.165
  Required (ns):               4.381
  Hold (ns):                   0.000

Path 4
  From:                        fic_master_trans_0/HADDR_TEMP[21]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[21]/U1:D
  Delay (ns):                  0.823
  Slack (ns):                  0.804
  Arrival (ns):                5.198
  Required (ns):               4.394
  Hold (ns):                   0.000

Path 5
  From:                        fic_master_trans_0/HADDR_TEMP[28]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[28]/U1:D
  Delay (ns):                  0.822
  Slack (ns):                  0.805
  Arrival (ns):                5.192
  Required (ns):               4.387
  Hold (ns):                   0.000


Expanded Path 1
  From: fic_master_trans_0/HADDR_TEMP[0]:CLK
  To: fic_master_trans_0/HADDR_TEMP[0]:D
  data arrival time                              4.948
  data required time                         -   4.378
  slack                                          0.570
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.328          net: FAB_CLK
  4.363                        fic_master_trans_0/HADDR_TEMP[0]:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.612                        fic_master_trans_0/HADDR_TEMP[0]:Q (r)
               +     0.336          net: _fic_master_trans_0_HADDR_[0]_
  4.948                        fic_master_trans_0/HADDR_TEMP[0]:D (r)
                                    
  4.948                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.343          net: FAB_CLK
  4.378                        fic_master_trans_0/HADDR_TEMP[0]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.378                        fic_master_trans_0/HADDR_TEMP[0]:D
                                    
  4.378                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HSEL_1/U1:D
  Delay (ns):                  3.423
  Slack (ns):                  1.991
  Arrival (ns):                6.372
  Required (ns):               4.381
  Hold (ns):                   0.000

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[21]/U1:D
  Delay (ns):                  4.118
  Slack (ns):                  2.673
  Arrival (ns):                7.067
  Required (ns):               4.394
  Hold (ns):                   0.000

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[15]/U1:D
  Delay (ns):                  4.118
  Slack (ns):                  2.673
  Arrival (ns):                7.067
  Required (ns):               4.394
  Hold (ns):                   0.000

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[18]/U1:D
  Delay (ns):                  4.117
  Slack (ns):                  2.679
  Arrival (ns):                7.066
  Required (ns):               4.387
  Hold (ns):                   0.000

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[29]/U1:D
  Delay (ns):                  4.159
  Slack (ns):                  2.710
  Arrival (ns):                7.108
  Required (ns):               4.398
  Hold (ns):                   0.000


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: fic_master_trans_0/HSEL_1/U1:D
  data arrival time                              6.372
  data required time                         -   4.381
  slack                                          1.991
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.523          cell: ADLIB:MSS_AHB_IP
  4.472                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (f)
               +     0.095          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  4.567                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (f)
               +     0.042          cell: ADLIB:MSS_IF
  4.609                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (f)
               +     0.915          net: FABHREADYOUT_c
  5.524                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[7]:C (f)
               +     0.176          cell: ADLIB:AOI1B
  5.700                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[7]:Y (f)
               +     0.272          net: fic_master_trans_0/un1_hreadyout
  5.972                        fic_master_trans_0/HSEL_1/U0:A (f)
               +     0.252          cell: ADLIB:MX2
  6.224                        fic_master_trans_0/HSEL_1/U0:Y (f)
               +     0.148          net: fic_master_trans_0/HSEL_1/Y
  6.372                        fic_master_trans_0/HSEL_1/U1:D (f)
                                    
  6.372                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.346          net: FAB_CLK
  4.381                        fic_master_trans_0/HSEL_1/U1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.381                        fic_master_trans_0/HSEL_1/U1:D
                                    
  4.381                        data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_pclk1 to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[19]/U1:CLR
  Delay (ns):                  2.769
  Slack (ns):                  1.331
  Arrival (ns):                5.718
  Required (ns):               4.387
  Hold (ns):

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[1]:CLR
  Delay (ns):                  2.768
  Slack (ns):                  1.339
  Arrival (ns):                5.717
  Required (ns):               4.378
  Hold (ns):

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[14]/U1:PRE
  Delay (ns):                  2.789
  Slack (ns):                  1.344
  Arrival (ns):                5.738
  Required (ns):               4.394
  Hold (ns):

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[8]/U1:PRE
  Delay (ns):                  2.888
  Slack (ns):                  1.439
  Arrival (ns):                5.837
  Required (ns):               4.398
  Hold (ns):

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[13]/U1:PRE
  Delay (ns):                  2.882
  Slack (ns):                  1.444
  Arrival (ns):                5.831
  Required (ns):               4.387
  Hold (ns):


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: fic_master_trans_0/HADDR_TEMP[19]/U1:CLR
  data arrival time                              5.718
  data required time                         -   4.387
  slack                                          1.331
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     2.949          Clock generation
  2.949
               +     2.091          cell: ADLIB:MSS_AHB_IP
  5.040                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  5.040                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (r)
               +     0.042          cell: ADLIB:MSS_IF
  5.082                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (r)
               +     0.636          net: mss_top_0/MSSINT_GPO_0_A
  5.718                        fic_master_trans_0/HADDR_TEMP[19]/U1:CLR (r)
                                    
  5.718                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.352          net: FAB_CLK
  4.387                        fic_master_trans_0/HADDR_TEMP[19]/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  4.387                        fic_master_trans_0/HADDR_TEMP[19]/U1:CLR
                                    
  4.387                        data required time


END SET mss_pclk1 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.277
  Slack (ns):
  Arrival (ns):                0.277
  Required (ns):
  Hold (ns):                   1.294
  External Hold (ns):          4.012


Expanded Path 1
  From: MSS_RESET_N
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.277
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        mss_top_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        mss_top_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: mss_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.277                        mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.277                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.271          net: mss_top_0/GLA0
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.294          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_ccc_gla0

Path 1
  From:                        fic_master_trans_0/HADDR_TEMP[25]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[25]
  Delay (ns):                  0.925
  Slack (ns):                  1.011
  Arrival (ns):                5.300
  Required (ns):               4.289
  Hold (ns):                   1.294

Path 2
  From:                        fic_master_trans_0/HADDR_TEMP[15]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[15]
  Delay (ns):                  0.941
  Slack (ns):                  1.034
  Arrival (ns):                5.316
  Required (ns):               4.282
  Hold (ns):                   1.287

Path 3
  From:                        fic_master_trans_0/HADDR_TEMP[20]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[20]
  Delay (ns):                  0.960
  Slack (ns):                  1.044
  Arrival (ns):                5.330
  Required (ns):               4.286
  Hold (ns):                   1.291

Path 4
  From:                        fic_master_trans_0/HADDR_TEMP[22]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[22]
  Delay (ns):                  1.004
  Slack (ns):                  1.090
  Arrival (ns):                5.374
  Required (ns):               4.284
  Hold (ns):                   1.289

Path 5
  From:                        fic_master_trans_0/HADDR_TEMP[0]:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[0]
  Delay (ns):                  1.074
  Slack (ns):                  1.127
  Arrival (ns):                5.437
  Required (ns):               4.310
  Hold (ns):                   1.315


Expanded Path 1
  From: fic_master_trans_0/HADDR_TEMP[25]/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[25]
  data arrival time                              5.300
  data required time                         -   4.289
  slack                                          1.011
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.340          net: FAB_CLK
  4.375                        fic_master_trans_0/HADDR_TEMP[25]/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.624                        fic_master_trans_0/HADDR_TEMP[25]/U1:Q (r)
               +     0.433          net: _fic_master_trans_0_HADDR_[25]_
  5.057                        mss_top_0/MSS_ADLIB_INST/U_45:PIN4 (r)
               +     0.037          cell: ADLIB:MSS_IF
  5.094                        mss_top_0/MSS_ADLIB_INST/U_45:PIN4INT (r)
               +     0.206          net: mss_top_0/MSS_ADLIB_INST/FABHADDR[25]INT_NET
  5.300                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[25] (r)
                                    
  5.300                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.271          net: mss_top_0/GLA0
  2.995                        mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.294          Library hold time: ADLIB:MSS_AHB_IP
  4.289                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[25]
                                    
  4.289                        data required time


END SET mss_ccc_gla1 to mss_ccc_gla0

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain Input_clk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          FAB_CLK
  Delay (ns):                  5.789
  Slack (ns):
  Arrival (ns):                5.789
  Required (ns):
  Clock to Out (ns):           5.789


Expanded Path 1
  From: mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: FAB_CLK
  data arrival time                              5.789
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Input_clk
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     4.035          cell: ADLIB:MSS_CCC_IP
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.387          net: FAB_CLK
  4.422                        FAB_CLK_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  4.701                        FAB_CLK_pad/U0/U1:DOUT (r)
               +     0.000          net: FAB_CLK_pad/U0/NET1
  4.701                        FAB_CLK_pad/U0/U0:D (r)
               +     1.088          cell: ADLIB:IOPAD_TRI
  5.789                        FAB_CLK_pad/U0/U0:PAD (r)
               +     0.000          net: FAB_CLK_c
  5.789                        FAB_CLK (r)
                                    
  5.789                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          Input_clk
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          FAB_CLK (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain FAB_CLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

