Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Dec 07 11:23:40 2011


Design: top_level
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      6.792
Max Clock-To-Out (ns):      11.457

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      7.506
Max Clock-To-Out (ns):      12.482

Clock Domain:               mss_ccc_gla1
Period (ns):                7.319
Frequency (MHz):            136.631
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.119
External Hold (ns):         4.172
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                20.000
Frequency (MHz):            50.000
Required Period (ns):       20.833
Required Frequency (MHz):   48.001
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               Input_clk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      5.720
Max Clock-To-Out (ns):      9.060

Clock Domain:               FAB_CLK
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          FABHREADYOUT
  Delay (ns):                  7.387
  Slack (ns):
  Arrival (ns):                11.457
  Required (ns):
  Clock to Out (ns):           11.457


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: FABHREADYOUT
  data required time                             N/C
  data arrival time                          -   11.457
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.070          Clock generation
  4.070
               +     3.002          cell: ADLIB:MSS_AHB_IP
  7.072                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (f)
               +     0.159          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  7.231                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (f)
               +     0.073          cell: ADLIB:MSS_IF
  7.304                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (f)
               +     0.944          net: FABHREADYOUT_c
  8.248                        FABHREADYOUT_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  8.748                        FABHREADYOUT_pad/U0/U1:DOUT (f)
               +     0.000          net: FABHREADYOUT_pad/U0/NET1
  8.748                        FABHREADYOUT_pad/U0/U0:D (f)
               +     2.709          cell: ADLIB:IOPAD_TRI
  11.457                       FABHREADYOUT_pad/U0/U0:PAD (f)
               +     0.000          net: FABHREADYOUT
  11.457                       FABHREADYOUT (f)
                                    
  11.457                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.070          Clock generation
  N/C
                                    
  N/C                          FABHREADYOUT (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        fic_master_trans_0/HSEL_1/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWRITE
  Delay (ns):                  2.659
  Slack (ns):                  9.756
  Arrival (ns):                8.402
  Required (ns):               18.158
  Setup (ns):                  -1.588

Path 2
  From:                        fic_master_trans_0/HSEL_1/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHSEL
  Delay (ns):                  2.183
  Slack (ns):                  9.893
  Arrival (ns):                7.926
  Required (ns):               17.819
  Setup (ns):                  -1.249

Path 3
  From:                        fic_master_trans_0/HSEL_1/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  Delay (ns):                  1.827
  Slack (ns):                  10.226
  Arrival (ns):                7.570
  Required (ns):               17.796
  Setup (ns):                  -1.226

Path 4
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[3]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[3]
  Delay (ns):                  2.141
  Slack (ns):                  10.263
  Arrival (ns):                7.897
  Required (ns):               18.160
  Setup (ns):                  -1.590

Path 5
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[0]:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[0]
  Delay (ns):                  2.137
  Slack (ns):                  10.289
  Arrival (ns):                7.893
  Required (ns):               18.182
  Setup (ns):                  -1.612


Expanded Path 1
  From: fic_master_trans_0/HSEL_1/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWRITE
  data required time                             18.158
  data arrival time                          -   8.402
  slack                                          9.756
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.494          net: FAB_CLK
  5.743                        fic_master_trans_0/HSEL_1/U1:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  6.302                        fic_master_trans_0/HSEL_1/U1:Q (f)
               +     1.309          net: fic_master_trans_0_HSEL
  7.611                        mss_top_0/MSS_ADLIB_INST/U_92:PIN4 (f)
               +     0.079          cell: ADLIB:MSS_IF
  7.690                        mss_top_0/MSS_ADLIB_INST/U_92:PIN4INT (f)
               +     0.712          net: mss_top_0/MSS_ADLIB_INST/FABHWRITEINT_NET
  8.402                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWRITE (f)
                                    
  8.402                        data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_fabric_interface_clock
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.070          Clock generation
  16.570
               -    -1.588          Library setup time: ADLIB:MSS_AHB_IP
  18.158                       mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWRITE
                                    
  18.158                       data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_0
  Delay (ns):                  8.412
  Slack (ns):
  Arrival (ns):                12.482
  Required (ns):
  Clock to Out (ns):           12.482


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: M2F_GPO_0
  data required time                             N/C
  data arrival time                          -   12.482
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.070          Clock generation
  4.070
               +     3.458          cell: ADLIB:MSS_AHB_IP
  7.528                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (f)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  7.528                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (f)
               +     0.073          cell: ADLIB:MSS_IF
  7.601                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (f)
               +     1.573          net: mss_top_0/MSSINT_GPO_0_A
  9.174                        M2F_GPO_0_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  9.674                        M2F_GPO_0_pad/U0/U1:DOUT (f)
               +     0.000          net: M2F_GPO_0_pad/U0/NET1
  9.674                        M2F_GPO_0_pad/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  12.482                       M2F_GPO_0_pad/U0/U0:PAD (f)
               +     0.000          net: M2F_GPO_0
  12.482                       M2F_GPO_0 (f)
                                    
  12.482                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.070          Clock generation
  N/C
                                    
  N/C                          M2F_GPO_0 (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[12]/U1:D
  Delay (ns):                  6.924
  Slack (ns):                  5.181
  Arrival (ns):                12.680
  Required (ns):               17.861
  Setup (ns):                  0.409
  Minimum Period (ns):         7.319

Path 2
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[0]:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[12]/U1:D
  Delay (ns):                  6.907
  Slack (ns):                  5.198
  Arrival (ns):                12.663
  Required (ns):               17.861
  Setup (ns):                  0.409
  Minimum Period (ns):         7.302

Path 3
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[2]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[12]/U1:D
  Delay (ns):                  6.902
  Slack (ns):                  5.202
  Arrival (ns):                12.659
  Required (ns):               17.861
  Setup (ns):                  0.409
  Minimum Period (ns):         7.298

Path 4
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[23]/U1:D
  Delay (ns):                  6.880
  Slack (ns):                  5.225
  Arrival (ns):                12.636
  Required (ns):               17.861
  Setup (ns):                  0.409
  Minimum Period (ns):         7.275

Path 5
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[0]:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[23]/U1:D
  Delay (ns):                  6.863
  Slack (ns):                  5.242
  Arrival (ns):                12.619
  Required (ns):               17.861
  Setup (ns):                  0.409
  Minimum Period (ns):         7.258


Expanded Path 1
  From: fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLK
  To: fic_master_trans_0/HADDR_TEMP[12]/U1:D
  data required time                             17.861
  data arrival time                          -   12.680
  slack                                          5.181
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.507          net: FAB_CLK
  5.756                        fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  6.315                        fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:Q (f)
               +     0.390          net: _fic_master_trans_0_HWDATA_[1]_
  6.705                        fic_master_trans_0/HWRITE_DATA_TEMP_RNI784C[2]:B (f)
               +     0.460          cell: ADLIB:NOR3C
  7.165                        fic_master_trans_0/HWRITE_DATA_TEMP_RNI784C[2]:Y (f)
               +     0.775          net: fic_master_trans_0/HWRITE_DATA_TEMP_c2
  7.940                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIMT5G[3]:A (f)
               +     0.390          cell: ADLIB:NOR2B
  8.330                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIMT5G[3]:Y (f)
               +     0.262          net: fic_master_trans_0/HWRITE_DATA_TEMP_c3
  8.592                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[7]:B (f)
               +     0.684          cell: ADLIB:AOI1B
  9.276                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[7]:Y (r)
               +     0.992          net: fic_master_trans_0/un1_hreadyout
  10.268                       fic_master_trans_0/ahb_states_RNIA6791_0[0]:A (r)
               +     0.392          cell: ADLIB:NOR2A
  10.660                       fic_master_trans_0/ahb_states_RNIA6791_0[0]:Y (r)
               +     1.380          net: fic_master_trans_0/HADDR_TEMP_0_sqmuxa_0
  12.040                       fic_master_trans_0/HADDR_TEMP[12]/U0:S (r)
               +     0.385          cell: ADLIB:MX2
  12.425                       fic_master_trans_0/HADDR_TEMP[12]/U0:Y (r)
               +     0.255          net: fic_master_trans_0/HADDR_TEMP[12]/Y
  12.680                       fic_master_trans_0/HADDR_TEMP[12]/U1:D (r)
                                    
  12.680                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.521          net: FAB_CLK
  18.270                       fic_master_trans_0/HADDR_TEMP[12]/U1:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1P0
  17.861                       fic_master_trans_0/HADDR_TEMP[12]/U1:D
                                    
  17.861                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[12]/U1:D
  Delay (ns):                  8.688
  Slack (ns):                  5.077
  Arrival (ns):                12.758
  Required (ns):               17.835
  Setup (ns):                  0.435

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[7]/U1:D
  Delay (ns):                  8.643
  Slack (ns):                  5.129
  Arrival (ns):                12.713
  Required (ns):               17.842
  Setup (ns):                  0.435

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[23]/U1:D
  Delay (ns):                  8.653
  Slack (ns):                  5.138
  Arrival (ns):                12.723
  Required (ns):               17.861
  Setup (ns):                  0.409

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[5]/U1:D
  Delay (ns):                  8.600
  Slack (ns):                  5.172
  Arrival (ns):                12.670
  Required (ns):               17.842
  Setup (ns):                  0.435

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[4]/U1:D
  Delay (ns):                  8.548
  Slack (ns):                  5.224
  Arrival (ns):                12.618
  Required (ns):               17.842
  Setup (ns):                  0.435


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: fic_master_trans_0/HADDR_TEMP[12]/U1:D
  data required time                             17.835
  data arrival time                          -   12.758
  slack                                          5.077
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.070          Clock generation
  4.070
               +     3.002          cell: ADLIB:MSS_AHB_IP
  7.072                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (f)
               +     0.159          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  7.231                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (f)
               +     0.073          cell: ADLIB:MSS_IF
  7.304                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (f)
               +     1.611          net: FABHREADYOUT_c
  8.915                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[7]:C (f)
               +     0.307          cell: ADLIB:AOI1B
  9.222                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[7]:Y (f)
               +     0.918          net: fic_master_trans_0/un1_hreadyout
  10.140                       fic_master_trans_0/ahb_states_RNIA6791_0[0]:A (f)
               +     0.476          cell: ADLIB:NOR2A
  10.616                       fic_master_trans_0/ahb_states_RNIA6791_0[0]:Y (f)
               +     1.501          net: fic_master_trans_0/HADDR_TEMP_0_sqmuxa_0
  12.117                       fic_master_trans_0/HADDR_TEMP[12]/U0:S (f)
               +     0.394          cell: ADLIB:MX2
  12.511                       fic_master_trans_0/HADDR_TEMP[12]/U0:Y (f)
               +     0.247          net: fic_master_trans_0/HADDR_TEMP[12]/Y
  12.758                       fic_master_trans_0/HADDR_TEMP[12]/U1:D (f)
                                    
  12.758                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.521          net: FAB_CLK
  18.270                       fic_master_trans_0/HADDR_TEMP[12]/U1:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1P0
  17.835                       fic_master_trans_0/HADDR_TEMP[12]/U1:D
                                    
  17.835                       data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_pclk1 to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[31]/U1:CLR
  Delay (ns):                  5.977
  Slack (ns):                  7.993
  Arrival (ns):                10.047
  Required (ns):               18.040
  Setup (ns):

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[6]/U1:CLR
  Delay (ns):                  5.921
  Slack (ns):                  8.027
  Arrival (ns):                9.991
  Required (ns):               18.018
  Setup (ns):

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[7]/U1:CLR
  Delay (ns):                  5.797
  Slack (ns):                  8.165
  Arrival (ns):                9.867
  Required (ns):               18.032
  Setup (ns):

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLR
  Delay (ns):                  5.797
  Slack (ns):                  8.165
  Arrival (ns):                9.867
  Required (ns):               18.032
  Setup (ns):

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[2]/U1:CLR
  Delay (ns):                  5.797
  Slack (ns):                  8.165
  Arrival (ns):                9.867
  Required (ns):               18.032
  Setup (ns):


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: fic_master_trans_0/HADDR_TEMP[31]/U1:CLR
  data required time                             18.040
  data arrival time                          -   10.047
  slack                                          7.993
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.070          Clock generation
  4.070
               +     3.680          cell: ADLIB:MSS_AHB_IP
  7.750                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  7.750                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (r)
               +     0.074          cell: ADLIB:MSS_IF
  7.824                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (r)
               +     2.223          net: mss_top_0/MSSINT_GPO_0_A
  10.047                       fic_master_trans_0/HADDR_TEMP[31]/U1:CLR (r)
                                    
  10.047                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.516          net: FAB_CLK
  18.265                       fic_master_trans_0/HADDR_TEMP[31]/U1:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  18.040                       fic_master_trans_0/HADDR_TEMP[31]/U1:CLR
                                    
  18.040                       data required time


END SET mss_pclk1 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.830
  External Setup (ns):         -5.119


Expanded Path 1
  From: MSS_RESET_N
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        mss_top_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        mss_top_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: mss_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.525          net: mss_top_0/GLA0
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.830          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_ccc_gla0

Path 1
  From:                        fic_master_trans_0/HADDR_TEMP[9]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[9]
  Delay (ns):                  2.493
  Slack (ns):                  9.231
  Arrival (ns):                8.258
  Required (ns):               17.489
  Setup (ns):                  -0.919

Path 2
  From:                        fic_master_trans_0/HADDR_TEMP[7]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[7]
  Delay (ns):                  2.440
  Slack (ns):                  9.288
  Arrival (ns):                8.217
  Required (ns):               17.505
  Setup (ns):                  -0.935

Path 3
  From:                        fic_master_trans_0/HADDR_TEMP[2]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[2]
  Delay (ns):                  2.299
  Slack (ns):                  9.290
  Arrival (ns):                8.071
  Required (ns):               17.361
  Setup (ns):                  -0.791

Path 4
  From:                        fic_master_trans_0/HADDR_TEMP[4]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[4]
  Delay (ns):                  2.262
  Slack (ns):                  9.326
  Arrival (ns):                8.039
  Required (ns):               17.365
  Setup (ns):                  -0.795

Path 5
  From:                        fic_master_trans_0/HADDR_TEMP[3]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[3]
  Delay (ns):                  2.302
  Slack (ns):                  9.343
  Arrival (ns):                8.079
  Required (ns):               17.422
  Setup (ns):                  -0.852


Expanded Path 1
  From: fic_master_trans_0/HADDR_TEMP[9]/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[9]
  data required time                             17.489
  data arrival time                          -   8.258
  slack                                          9.231
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.516          net: FAB_CLK
  5.765                        fic_master_trans_0/HADDR_TEMP[9]/U1:CLK (r)
               +     0.559          cell: ADLIB:DFN1P0
  6.324                        fic_master_trans_0/HADDR_TEMP[9]/U1:Q (f)
               +     1.435          net: _fic_master_trans_0_HADDR_[9]_
  7.759                        mss_top_0/MSS_ADLIB_INST/U_33:PIN5 (f)
               +     0.158          cell: ADLIB:MSS_IF
  7.917                        mss_top_0/MSS_ADLIB_INST/U_33:PIN5INT (f)
               +     0.341          net: mss_top_0/MSS_ADLIB_INST/FABHADDR[9]INT_NET
  8.258                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[9] (f)
                                    
  8.258                        data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla0
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  16.045
               +     0.525          net: mss_top_0/GLA0
  16.570                       mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -0.919          Library setup time: ADLIB:MSS_AHB_IP
  17.489                       mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[9]
                                    
  17.489                       data required time


END SET mss_ccc_gla1 to mss_ccc_gla0

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain Input_clk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          FAB_CLK
  Delay (ns):                  9.060
  Slack (ns):
  Arrival (ns):                9.060
  Required (ns):
  Clock to Out (ns):           9.060


Expanded Path 1
  From: mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: FAB_CLK
  data required time                             N/C
  data arrival time                          -   9.060
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Input_clk
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     5.249          cell: ADLIB:MSS_CCC_IP
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (f)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (f)
               +     0.503          net: FAB_CLK
  5.752                        FAB_CLK_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  6.252                        FAB_CLK_pad/U0/U1:DOUT (f)
               +     0.000          net: FAB_CLK_pad/U0/NET1
  6.252                        FAB_CLK_pad/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  9.060                        FAB_CLK_pad/U0/U0:PAD (f)
               +     0.000          net: FAB_CLK_c
  9.060                        FAB_CLK (f)
                                    
  9.060                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          Input_clk
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          FAB_CLK (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain FAB_CLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

