Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Dec 07 16:57:05 2011


Design: top_level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      7.434
Max Clock-To-Out (ns):      14.192

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      7.621
Max Clock-To-Out (ns):      14.450

Clock Domain:               mss_ccc_gla1
Period (ns):                9.008
Frequency (MHz):            111.012
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.206
External Hold (ns):         4.012
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                25.000
Frequency (MHz):            40.000
Required Period (ns):       20.833
Required Frequency (MHz):   48.001
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               Input_clk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      5.789
Max Clock-To-Out (ns):      9.891

Clock Domain:               FAB_CLK
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          FABHREADYOUT
  Delay (ns):                  10.188
  Slack (ns):
  Arrival (ns):                14.192
  Required (ns):
  Clock to Out (ns):           14.192


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: FABHREADYOUT
  data required time                             N/C
  data arrival time                          -   14.192
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  4.004
               +     3.190          cell: ADLIB:MSS_AHB_IP
  7.194                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (f)
               +     0.191          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  7.385                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (f)
               +     0.088          cell: ADLIB:MSS_IF
  7.473                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (f)
               +     2.750          net: FABHREADYOUT_c
  10.223                       FABHREADYOUT_pad/U0/U1:D (f)
               +     0.600          cell: ADLIB:IOTRI_OB_EB
  10.823                       FABHREADYOUT_pad/U0/U1:DOUT (f)
               +     0.000          net: FABHREADYOUT_pad/U0/NET1
  10.823                       FABHREADYOUT_pad/U0/U0:D (f)
               +     3.369          cell: ADLIB:IOPAD_TRI
  14.192                       FABHREADYOUT_pad/U0/U0:PAD (f)
               +     0.000          net: FABHREADYOUT
  14.192                       FABHREADYOUT (f)
                                    
  14.192                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  N/C
                                    
  N/C                          FABHREADYOUT (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        fic_master_trans_0/HSEL_1/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWRITE
  Delay (ns):                  4.412
  Slack (ns):                  8.311
  Arrival (ns):                10.334
  Required (ns):               18.645
  Setup (ns):                  -2.141

Path 2
  From:                        fic_master_trans_0/HSEL_1/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHSEL
  Delay (ns):                  2.877
  Slack (ns):                  9.149
  Arrival (ns):                8.799
  Required (ns):               17.948
  Setup (ns):                  -1.444

Path 3
  From:                        fic_master_trans_0/HSEL_1/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  Delay (ns):                  2.414
  Slack (ns):                  9.629
  Arrival (ns):                8.336
  Required (ns):               17.965
  Setup (ns):                  -1.461

Path 4
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[1]
  Delay (ns):                  2.539
  Slack (ns):                  10.006
  Arrival (ns):                8.466
  Required (ns):               18.472
  Setup (ns):                  -1.968

Path 5
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[6]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[6]
  Delay (ns):                  2.491
  Slack (ns):                  10.056
  Arrival (ns):                8.413
  Required (ns):               18.469
  Setup (ns):                  -1.965


Expanded Path 1
  From: fic_master_trans_0/HSEL_1/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWRITE
  data required time                             18.645
  data arrival time                          -   10.334
  slack                                          8.311
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.673          net: FAB_CLK
  5.922                        fic_master_trans_0/HSEL_1/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  6.593                        fic_master_trans_0/HSEL_1/U1:Q (f)
               +     2.685          net: fic_master_trans_0_HSEL
  9.278                        mss_top_0/MSS_ADLIB_INST/U_92:PIN4 (f)
               +     0.095          cell: ADLIB:MSS_IF
  9.373                        mss_top_0/MSS_ADLIB_INST/U_92:PIN4INT (f)
               +     0.961          net: mss_top_0/MSS_ADLIB_INST/FABHWRITEINT_NET
  10.334                       mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWRITE (f)
                                    
  10.334                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_fabric_interface_clock
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  16.504
               -    -2.141          Library setup time: ADLIB:MSS_AHB_IP
  18.645                       mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWRITE
                                    
  18.645                       data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_0
  Delay (ns):                  10.446
  Slack (ns):
  Arrival (ns):                14.450
  Required (ns):
  Clock to Out (ns):           14.450


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: M2F_GPO_0
  data required time                             N/C
  data arrival time                          -   14.450
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.004          Clock generation
  4.004
               +     4.163          cell: ADLIB:MSS_AHB_IP
  8.167                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (f)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  8.167                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (f)
               +     0.088          cell: ADLIB:MSS_IF
  8.255                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (f)
               +     2.226          net: mss_top_0/MSSINT_GPO_0_A
  10.481                       M2F_GPO_0_pad/U0/U1:D (f)
               +     0.600          cell: ADLIB:IOTRI_OB_EB
  11.081                       M2F_GPO_0_pad/U0/U1:DOUT (f)
               +     0.000          net: M2F_GPO_0_pad/U0/NET1
  11.081                       M2F_GPO_0_pad/U0/U0:D (f)
               +     3.369          cell: ADLIB:IOPAD_TRI
  14.450                       M2F_GPO_0_pad/U0/U0:PAD (f)
               +     0.000          net: M2F_GPO_0
  14.450                       M2F_GPO_0 (f)
                                    
  14.450                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.004          Clock generation
  N/C
                                    
  N/C                          M2F_GPO_0 (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[19]/U1:D
  Delay (ns):                  8.522
  Slack (ns):                  3.492
  Arrival (ns):                14.449
  Required (ns):               17.941
  Setup (ns):                  0.490
  Minimum Period (ns):         9.008

Path 2
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[2]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[19]/U1:D
  Delay (ns):                  8.494
  Slack (ns):                  3.520
  Arrival (ns):                14.421
  Required (ns):               17.941
  Setup (ns):                  0.490
  Minimum Period (ns):         8.980

Path 3
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[0]:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[19]/U1:D
  Delay (ns):                  8.262
  Slack (ns):                  3.752
  Arrival (ns):                14.189
  Required (ns):               17.941
  Setup (ns):                  0.490
  Minimum Period (ns):         8.748

Path 4
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[30]/U1:D
  Delay (ns):                  8.238
  Slack (ns):                  3.756
  Arrival (ns):                14.165
  Required (ns):               17.921
  Setup (ns):                  0.490
  Minimum Period (ns):         8.744

Path 5
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[2]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[30]/U1:D
  Delay (ns):                  8.210
  Slack (ns):                  3.784
  Arrival (ns):                14.137
  Required (ns):               17.921
  Setup (ns):                  0.490
  Minimum Period (ns):         8.716


Expanded Path 1
  From: fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLK
  To: fic_master_trans_0/HADDR_TEMP[19]/U1:D
  data required time                             17.941
  data arrival time                          -   14.449
  slack                                          3.492
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.678          net: FAB_CLK
  5.927                        fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  6.598                        fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:Q (f)
               +     0.464          net: _fic_master_trans_0_HWDATA_[1]_
  7.062                        fic_master_trans_0/HWRITE_DATA_TEMP_RNI784C[2]:B (f)
               +     0.552          cell: ADLIB:NOR3C
  7.614                        fic_master_trans_0/HWRITE_DATA_TEMP_RNI784C[2]:Y (f)
               +     0.338          net: fic_master_trans_0/HWRITE_DATA_TEMP_c2
  7.952                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIMT5G[3]:A (f)
               +     0.468          cell: ADLIB:NOR2B
  8.420                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIMT5G[3]:Y (f)
               +     0.889          net: fic_master_trans_0/HWRITE_DATA_TEMP_c3
  9.309                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[7]:B (f)
               +     0.821          cell: ADLIB:AOI1B
  10.130                       fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[7]:Y (r)
               +     1.102          net: fic_master_trans_0/un1_hreadyout
  11.232                       fic_master_trans_0/ahb_states_RNIA6791_0[0]:A (r)
               +     0.470          cell: ADLIB:NOR2A
  11.702                       fic_master_trans_0/ahb_states_RNIA6791_0[0]:Y (r)
               +     1.979          net: fic_master_trans_0/HADDR_TEMP_0_sqmuxa_0
  13.681                       fic_master_trans_0/HADDR_TEMP[19]/U0:S (r)
               +     0.462          cell: ADLIB:MX2
  14.143                       fic_master_trans_0/HADDR_TEMP[19]/U0:Y (r)
               +     0.306          net: fic_master_trans_0/HADDR_TEMP[19]/Y
  14.449                       fic_master_trans_0/HADDR_TEMP[19]/U1:D (r)
                                    
  14.449                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.682          net: FAB_CLK
  18.431                       fic_master_trans_0/HADDR_TEMP[19]/U1:CLK (r)
               -     0.490          Library setup time: ADLIB:DFN1C0
  17.941                       fic_master_trans_0/HADDR_TEMP[19]/U1:D
                                    
  17.941                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[19]/U1:D
  Delay (ns):                  10.228
  Slack (ns):                  3.677
  Arrival (ns):                14.232
  Required (ns):               17.909
  Setup (ns):                  0.522

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[30]/U1:D
  Delay (ns):                  9.884
  Slack (ns):                  4.033
  Arrival (ns):                13.888
  Required (ns):               17.921
  Setup (ns):                  0.490

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[31]/U1:D
  Delay (ns):                  9.839
  Slack (ns):                  4.046
  Arrival (ns):                13.843
  Required (ns):               17.889
  Setup (ns):                  0.522

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[27]/U1:D
  Delay (ns):                  9.835
  Slack (ns):                  4.084
  Arrival (ns):                13.839
  Required (ns):               17.923
  Setup (ns):                  0.522

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[4]/U1:D
  Delay (ns):                  9.803
  Slack (ns):                  4.134
  Arrival (ns):                13.807
  Required (ns):               17.941
  Setup (ns):                  0.490


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: fic_master_trans_0/HADDR_TEMP[19]/U1:D
  data required time                             17.909
  data arrival time                          -   14.232
  slack                                          3.677
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  4.004
               +     3.190          cell: ADLIB:MSS_AHB_IP
  7.194                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (f)
               +     0.191          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  7.385                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (f)
               +     0.088          cell: ADLIB:MSS_IF
  7.473                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (f)
               +     1.839          net: FABHREADYOUT_c
  9.312                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[7]:C (f)
               +     0.369          cell: ADLIB:AOI1B
  9.681                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[7]:Y (f)
               +     1.050          net: fic_master_trans_0/un1_hreadyout
  10.731                       fic_master_trans_0/ahb_states_RNIA6791_0[0]:A (f)
               +     0.571          cell: ADLIB:NOR2A
  11.302                       fic_master_trans_0/ahb_states_RNIA6791_0[0]:Y (f)
               +     2.161          net: fic_master_trans_0/HADDR_TEMP_0_sqmuxa_0
  13.463                       fic_master_trans_0/HADDR_TEMP[19]/U0:S (f)
               +     0.473          cell: ADLIB:MX2
  13.936                       fic_master_trans_0/HADDR_TEMP[19]/U0:Y (f)
               +     0.296          net: fic_master_trans_0/HADDR_TEMP[19]/Y
  14.232                       fic_master_trans_0/HADDR_TEMP[19]/U1:D (f)
                                    
  14.232                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.682          net: FAB_CLK
  18.431                       fic_master_trans_0/HADDR_TEMP[19]/U1:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1C0
  17.909                       fic_master_trans_0/HADDR_TEMP[19]/U1:D
                                    
  17.909                       data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_pclk1 to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[27]/U1:CLR
  Delay (ns):                  7.344
  Slack (ns):                  6.826
  Arrival (ns):                11.348
  Required (ns):               18.174
  Setup (ns):

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[10]/U1:PRE
  Delay (ns):                  7.000
  Slack (ns):                  7.156
  Arrival (ns):                11.004
  Required (ns):               18.160
  Setup (ns):

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[15]/U1:CLR
  Delay (ns):                  7.000
  Slack (ns):                  7.168
  Arrival (ns):                11.004
  Required (ns):               18.172
  Setup (ns):

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[0]:CLR
  Delay (ns):                  6.969
  Slack (ns):                  7.173
  Arrival (ns):                10.973
  Required (ns):               18.146
  Setup (ns):

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[22]/U1:CLR
  Delay (ns):                  6.956
  Slack (ns):                  7.200
  Arrival (ns):                10.960
  Required (ns):               18.160
  Setup (ns):


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: fic_master_trans_0/HADDR_TEMP[27]/U1:CLR
  data required time                             18.174
  data arrival time                          -   11.348
  slack                                          6.826
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.004          Clock generation
  4.004
               +     4.440          cell: ADLIB:MSS_AHB_IP
  8.444                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  8.444                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (r)
               +     0.089          cell: ADLIB:MSS_IF
  8.533                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (r)
               +     2.815          net: mss_top_0/MSSINT_GPO_0_A
  11.348                       fic_master_trans_0/HADDR_TEMP[27]/U1:CLR (r)
                                    
  11.348                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.696          net: FAB_CLK
  18.445                       fic_master_trans_0/HADDR_TEMP[27]/U1:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1C0
  18.174                       fic_master_trans_0/HADDR_TEMP[27]/U1:CLR
                                    
  18.174                       data required time


END SET mss_pclk1 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.139
  External Setup (ns):         -5.206


Expanded Path 1
  From: MSS_RESET_N
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        mss_top_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        mss_top_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: mss_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.459          net: mss_top_0/GLA0
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.139          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_ccc_gla0

Path 1
  From:                        fic_master_trans_0/HADDR_TEMP[29]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[29]
  Delay (ns):                  3.800
  Slack (ns):                  8.104
  Arrival (ns):                9.749
  Required (ns):               17.853
  Setup (ns):                  -1.349

Path 2
  From:                        fic_master_trans_0/HADDR_TEMP[31]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[31]
  Delay (ns):                  3.244
  Slack (ns):                  8.421
  Arrival (ns):                9.155
  Required (ns):               17.576
  Setup (ns):                  -1.072

Path 3
  From:                        fic_master_trans_0/HADDR_TEMP[10]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[10]
  Delay (ns):                  3.304
  Slack (ns):                  8.428
  Arrival (ns):                9.235
  Required (ns):               17.663
  Setup (ns):                  -1.159

Path 4
  From:                        fic_master_trans_0/HADDR_TEMP[3]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[3]
  Delay (ns):                  3.242
  Slack (ns):                  8.457
  Arrival (ns):                9.173
  Required (ns):               17.630
  Setup (ns):                  -1.126

Path 5
  From:                        fic_master_trans_0/HADDR_TEMP[5]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[5]
  Delay (ns):                  3.007
  Slack (ns):                  8.542
  Arrival (ns):                8.956
  Required (ns):               17.498
  Setup (ns):                  -0.994


Expanded Path 1
  From: fic_master_trans_0/HADDR_TEMP[29]/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[29]
  data required time                             17.853
  data arrival time                          -   9.749
  slack                                          8.104
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.700          net: FAB_CLK
  5.949                        fic_master_trans_0/HADDR_TEMP[29]/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1P0
  6.620                        fic_master_trans_0/HADDR_TEMP[29]/U1:Q (f)
               +     2.474          net: _fic_master_trans_0_HADDR_[29]_
  9.094                        mss_top_0/MSS_ADLIB_INST/U_46:PIN6 (f)
               +     0.174          cell: ADLIB:MSS_IF
  9.268                        mss_top_0/MSS_ADLIB_INST/U_46:PIN6INT (f)
               +     0.481          net: mss_top_0/MSS_ADLIB_INST/FABHADDR[29]INT_NET
  9.749                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[29] (f)
                                    
  9.749                        data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla0
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  16.045
               +     0.459          net: mss_top_0/GLA0
  16.504                       mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.349          Library setup time: ADLIB:MSS_AHB_IP
  17.853                       mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[29]
                                    
  17.853                       data required time


END SET mss_ccc_gla1 to mss_ccc_gla0

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain Input_clk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          FAB_CLK
  Delay (ns):                  9.891
  Slack (ns):
  Arrival (ns):                9.891
  Required (ns):
  Clock to Out (ns):           9.891


Expanded Path 1
  From: mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: FAB_CLK
  data required time                             N/C
  data arrival time                          -   9.891
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Input_clk
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     5.249          cell: ADLIB:MSS_CCC_IP
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (f)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (f)
               +     0.791          net: FAB_CLK
  6.040                        FAB_CLK_pad/U0/U1:D (f)
               +     0.600          cell: ADLIB:IOTRI_OB_EB
  6.640                        FAB_CLK_pad/U0/U1:DOUT (f)
               +     0.000          net: FAB_CLK_pad/U0/NET1
  6.640                        FAB_CLK_pad/U0/U0:D (f)
               +     3.251          cell: ADLIB:IOPAD_TRI
  9.891                        FAB_CLK_pad/U0/U0:PAD (f)
               +     0.000          net: FAB_CLK_c
  9.891                        FAB_CLK (f)
                                    
  9.891                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          Input_clk
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          FAB_CLK (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain FAB_CLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

