-------------------------------------------------------------------------------
-- Title      : Custom AHB Master
-------------------------------------------------------------------------------
-- File       : fic_master_trans.vhd
-- Author     : Pavan Marisetti
-- Company    : Microsemi Corporation
-- Device     : SmartFusion
-- Standard   : VHDL
-------------------------------------------------------------------------------
-- Description: This design consists of AHB master in FPGA fabric 
--              that writes 32-bit data to 256 locations of eSRAM starting 
--              from the address 0x20007FFC. 
-------------------------------------------------------------------------------
-- Copyright (c) 2011   Microsemi Corporation
--                      All rights reserved.
-------------------------------------------------------------------------------
-- Revisions  : V1.0
-------------------------------------------------------------------------------

library ieee;  
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library smartfusion;
use smartfusion.all;

entity fic_master_trans is
  port (
		RESET_N           : in    std_logic;    
        HCLK              : in    std_logic;
        HTRANS            : out   std_logic_vector(1 downto 0);
        HSIZE             : out   std_logic_vector(1 downto 0);
        HWRITE            : out   std_logic;
        HWDATA            : out   std_logic_vector(31 downto 0);
        HADDR             : out   std_logic_vector(31 downto 0);
        HMASTLOCK         : out   std_logic;
        HREADY            : out   std_logic;
        HSEL              : out   std_logic;
        HREADYOUT         : in    std_logic;
        HRESP             : in    std_logic;
        HRDATA            : in    std_logic_vector(31 downto 0)
       );
end;

architecture fic_master_trans of fic_master_trans is


type ahb_master_states is (address_phase,data_phase); 


  signal ahb_states        : ahb_master_states;
  signal HADDR_TEMP        : std_logic_vector(31 downto 0);
  signal HWRITE_DATA_TEMP  : std_logic_vector(31 downto 0); 
begin
     
       HMASTLOCK         <= '0';
       HREADY            <= '1';
       HADDR             <= HADDR_TEMP;
       HWDATA            <= HWRITE_DATA_TEMP;

AHB_MASTER: process(hclk, RESET_N)
  begin
    if RESET_N = '0' then
       HTRANS            <= "00";
       HWRITE            <= '0';
       HADDR_TEMP        <= X"20007FFC";--"00100000000000 0011 1111 1111 1111"; --eSRAM
       HSEL              <= '0';
       HSIZE             <= "00";
       ahb_states        <=  address_phase; 
       HWRITE_DATA_TEMP  <= (others =>'0');
	elsif (hclk'event and hclk = '1') then
       case ahb_states is
		 when address_phase =>
           if( HREADYOUT = '1' and HWRITE_DATA_TEMP(7 downto 0) /=X"FF") then
             ahb_states <= data_phase;
             HADDR_TEMP <= HADDR_TEMP + 4;
             HWRITE <= '1';
             HTRANS <= "10";
             HSIZE <= "10";
             HSEL <= '1';
           else
             HTRANS            <= "00";
             HWRITE            <= '0';
             HSEL              <= '0';
             HSIZE             <= "00";
             ahb_states <= address_phase;
           end if;
		 when data_phase =>
             HWRITE_DATA_TEMP <= HWRITE_DATA_TEMP + 1;
             ahb_states <= address_phase;
         when others =>
       end case;
     end if;
   end process;


         
end fic_master_trans;