-- Version: 10.0 10.0.9.37

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity mss_top is

    port( FABHWRITE    : in    std_logic;
          FABHSEL      : in    std_logic;
          FABHMASTLOCK : in    std_logic;
          FABHREADY    : in    std_logic;
          FABHREADYOUT : out   std_logic;
          FABHRESP     : out   std_logic;
          FAB_CLK      : out   std_logic;
          MAINXIN      : in    std_logic;
          FAB_LOCK     : out   std_logic;
          M2F_GPO_0    : out   std_logic;
          FABHADDR     : in    std_logic_vector(31 downto 0);
          FABHTRANS    : in    std_logic_vector(1 downto 0);
          FABHSIZE     : in    std_logic_vector(1 downto 0);
          FABHWDATA    : in    std_logic_vector(31 downto 0);
          FABHRDATA    : out   std_logic_vector(31 downto 0);
          UART_0_TXD   : out   std_logic;
          UART_0_RXD   : in    std_logic;
          UART_1_TXD   : out   std_logic;
          UART_1_RXD   : in    std_logic;
          SPI_0_DI     : in    std_logic;
          SPI_0_DO     : out   std_logic;
          SPI_0_CLK    : inout std_logic := 'Z';
          SPI_0_SS     : inout std_logic := 'Z';
          SPI_1_DI     : in    std_logic;
          SPI_1_DO     : out   std_logic;
          SPI_1_CLK    : inout std_logic := 'Z';
          SPI_1_SS     : inout std_logic := 'Z';
          I2C_0_SDA    : inout std_logic := 'Z';
          I2C_0_SCL    : inout std_logic := 'Z';
          I2C_1_SDA    : inout std_logic := 'Z';
          I2C_1_SCL    : inout std_logic := 'Z';
          EMC_DB       : inout std_logic_vector(15 downto 0) := (others => 'Z');
          EMC_AB       : out   std_logic_vector(25 downto 0);
          EMC_BYTEN    : out   std_logic_vector(1 downto 0);
          EMC_CS0_N    : out   std_logic;
          EMC_CS1_N    : out   std_logic;
          EMC_OEN0_N   : out   std_logic;
          EMC_OEN1_N   : out   std_logic;
          EMC_CLK      : out   std_logic;
          EMC_RW_N     : out   std_logic;
          MAC_RXD      : in    std_logic_vector(1 downto 0);
          MAC_TXD      : out   std_logic_vector(1 downto 0);
          MAC_MDIO     : inout std_logic := 'Z';
          MAC_CRSDV    : in    std_logic;
          MAC_RXER     : in    std_logic;
          MAC_TXEN     : out   std_logic;
          MAC_MDC      : out   std_logic;
          MSS_RESET_N  : in    std_logic
        );

end mss_top;

architecture DEF_ARCH of mss_top is 

  component BIBUF_MSS
    generic (ACT_CONFIG:integer := 0; ACT_PIN:string := "");

    port( PAD : inout   std_logic;
          D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component INBUF_MSS
    generic (ACT_CONFIG:integer := 0; ACT_PIN:string := "");

    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component OUTBUF_MSS
    generic (ACT_CONFIG:integer := 0; ACT_PIN:string := "");

    port( D   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component BIBUF_OPEND_MSS
    generic (ACT_CONFIG:integer := 0; ACT_PIN:string := "");

    port( PAD : inout   std_logic;
          E   : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component TRIBUFF_MSS
    generic (ACT_CONFIG:integer := 0; ACT_PIN:string := "");

    port( D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component mss_top_tmp_MSS_CCC_0_MSS_CCC
    port( CLKA           : in    std_logic := 'U';
          CLKA_PAD       : in    std_logic := 'U';
          CLKA_PADP      : in    std_logic := 'U';
          CLKA_PADN      : in    std_logic := 'U';
          CLKB           : in    std_logic := 'U';
          CLKB_PAD       : in    std_logic := 'U';
          CLKB_PADP      : in    std_logic := 'U';
          CLKB_PADN      : in    std_logic := 'U';
          CLKC           : in    std_logic := 'U';
          CLKC_PAD       : in    std_logic := 'U';
          CLKC_PADP      : in    std_logic := 'U';
          CLKC_PADN      : in    std_logic := 'U';
          GLA            : out   std_logic;
          GLB            : out   std_logic;
          GLC            : out   std_logic;
          FAB_CLK        : out   std_logic;
          YB             : out   std_logic;
          YC             : out   std_logic;
          MAINXIN        : in    std_logic := 'U';
          LPXIN          : in    std_logic := 'U';
          FAB_LOCK       : out   std_logic;
          MAC_CLK        : in    std_logic := 'U';
          RCOSC_CLKOUT   : out   std_logic;
          MAINXIN_CLKOUT : out   std_logic;
          LPXIN_CLKOUT   : out   std_logic;
          GLA0           : out   std_logic;
          MSS_LOCK       : out   std_logic;
          MAC_CLK_CCC    : out   std_logic;
          MAC_CLK_IO     : out   std_logic
        );
  end component;

  component MSS_AHB
    generic (ACT_CONFIG:integer := 0; ACT_DIE:string := ""; 
        ACT_FCLK:integer := 0; ACT_PKG:string := "");

    port( MSSHADDR       : out   std_logic_vector(19 downto 0);
          MSSHWDATA      : out   std_logic_vector(31 downto 0);
          MSSHTRANS      : out   std_logic_vector(1 downto 0);
          MSSHSIZE       : out   std_logic_vector(1 downto 0);
          MSSHLOCK       : out   std_logic;
          MSSHWRITE      : out   std_logic;
          MSSHRDATA      : in    std_logic_vector(31 downto 0) := (others => 'U');
          MSSHREADY      : in    std_logic := 'U';
          MSSHRESP       : in    std_logic := 'U';
          FABHADDR       : in    std_logic_vector(31 downto 0) := (others => 'U');
          FABHWDATA      : in    std_logic_vector(31 downto 0) := (others => 'U');
          FABHTRANS      : in    std_logic_vector(1 downto 0) := (others => 'U');
          FABHSIZE       : in    std_logic_vector(1 downto 0) := (others => 'U');
          FABHMASTLOCK   : in    std_logic := 'U';
          FABHWRITE      : in    std_logic := 'U';
          FABHSEL        : in    std_logic := 'U';
          FABHREADY      : in    std_logic := 'U';
          FABHRDATA      : out   std_logic_vector(31 downto 0);
          FABHREADYOUT   : out   std_logic;
          FABHRESP       : out   std_logic;
          SYNCCLKFDBK    : in    std_logic := 'U';
          CALIBOUT       : out   std_logic;
          CALIBIN        : in    std_logic := 'U';
          FABINT         : in    std_logic := 'U';
          MSSINT         : out   std_logic_vector(7 downto 0);
          WDINT          : out   std_logic;
          F2MRESETn      : in    std_logic := 'U';
          DMAREADY       : in    std_logic_vector(1 downto 0) := (others => 'U');
          RXEV           : in    std_logic := 'U';
          VRON           : in    std_logic := 'U';
          M2FRESETn      : out   std_logic;
          DEEPSLEEP      : out   std_logic;
          SLEEP          : out   std_logic;
          TXEV           : out   std_logic;
          GPI            : in    std_logic_vector(31 downto 0) := (others => 'U');
          GPO            : out   std_logic_vector(31 downto 0);
          UART0CTSn      : in    std_logic := 'U';
          UART0DSRn      : in    std_logic := 'U';
          UART0RIn       : in    std_logic := 'U';
          UART0DCDn      : in    std_logic := 'U';
          UART0RTSn      : out   std_logic;
          UART0DTRn      : out   std_logic;
          UART1CTSn      : in    std_logic := 'U';
          UART1DSRn      : in    std_logic := 'U';
          UART1RIn       : in    std_logic := 'U';
          UART1DCDn      : in    std_logic := 'U';
          UART1RTSn      : out   std_logic;
          UART1DTRn      : out   std_logic;
          I2C0SMBUSNI    : in    std_logic := 'U';
          I2C0SMBALERTNI : in    std_logic := 'U';
          I2C0BCLK       : in    std_logic := 'U';
          I2C0SMBUSNO    : out   std_logic;
          I2C0SMBALERTNO : out   std_logic;
          I2C1SMBUSNI    : in    std_logic := 'U';
          I2C1SMBALERTNI : in    std_logic := 'U';
          I2C1BCLK       : in    std_logic := 'U';
          I2C1SMBUSNO    : out   std_logic;
          I2C1SMBALERTNO : out   std_logic;
          MACM2FTXD      : out   std_logic_vector(1 downto 0);
          MACF2MRXD      : in    std_logic_vector(1 downto 0) := (others => 'U');
          MACM2FTXEN     : out   std_logic;
          MACF2MCRSDV    : in    std_logic := 'U';
          MACF2MRXER     : in    std_logic := 'U';
          MACF2MMDI      : in    std_logic := 'U';
          MACM2FMDO      : out   std_logic;
          MACM2FMDEN     : out   std_logic;
          MACM2FMDC      : out   std_logic;
          FABSDD0D       : in    std_logic := 'U';
          FABSDD1D       : in    std_logic := 'U';
          FABSDD2D       : in    std_logic := 'U';
          FABSDD0CLK     : in    std_logic := 'U';
          FABSDD1CLK     : in    std_logic := 'U';
          FABSDD2CLK     : in    std_logic := 'U';
          FABACETRIG     : in    std_logic := 'U';
          ACEFLAGS       : out   std_logic_vector(31 downto 0);
          CMP0           : out   std_logic;
          CMP1           : out   std_logic;
          CMP2           : out   std_logic;
          CMP3           : out   std_logic;
          CMP4           : out   std_logic;
          CMP5           : out   std_logic;
          CMP6           : out   std_logic;
          CMP7           : out   std_logic;
          CMP8           : out   std_logic;
          CMP9           : out   std_logic;
          CMP10          : out   std_logic;
          CMP11          : out   std_logic;
          LVTTL0EN       : in    std_logic := 'U';
          LVTTL1EN       : in    std_logic := 'U';
          LVTTL2EN       : in    std_logic := 'U';
          LVTTL3EN       : in    std_logic := 'U';
          LVTTL4EN       : in    std_logic := 'U';
          LVTTL5EN       : in    std_logic := 'U';
          LVTTL6EN       : in    std_logic := 'U';
          LVTTL7EN       : in    std_logic := 'U';
          LVTTL8EN       : in    std_logic := 'U';
          LVTTL9EN       : in    std_logic := 'U';
          LVTTL10EN      : in    std_logic := 'U';
          LVTTL11EN      : in    std_logic := 'U';
          LVTTL0         : out   std_logic;
          LVTTL1         : out   std_logic;
          LVTTL2         : out   std_logic;
          LVTTL3         : out   std_logic;
          LVTTL4         : out   std_logic;
          LVTTL5         : out   std_logic;
          LVTTL6         : out   std_logic;
          LVTTL7         : out   std_logic;
          LVTTL8         : out   std_logic;
          LVTTL9         : out   std_logic;
          LVTTL10        : out   std_logic;
          LVTTL11        : out   std_logic;
          PUFABn         : out   std_logic;
          VCC15GOOD      : out   std_logic;
          VCC33GOOD      : out   std_logic;
          FCLK           : in    std_logic := 'U';
          MACCLKCCC      : in    std_logic := 'U';
          RCOSC          : in    std_logic := 'U';
          MACCLK         : in    std_logic := 'U';
          PLLLOCK        : in    std_logic := 'U';
          MSSRESETn      : in    std_logic := 'U';
          GPOE           : out   std_logic_vector(31 downto 0);
          SPI0DO         : out   std_logic;
          SPI0DOE        : out   std_logic;
          SPI0DI         : in    std_logic := 'U';
          SPI0CLKI       : in    std_logic := 'U';
          SPI0CLKO       : out   std_logic;
          SPI0MODE       : out   std_logic;
          SPI0SSI        : in    std_logic := 'U';
          SPI0SSO        : out   std_logic_vector(7 downto 0);
          UART0TXD       : out   std_logic;
          UART0RXD       : in    std_logic := 'U';
          I2C0SDAI       : in    std_logic := 'U';
          I2C0SDAO       : out   std_logic;
          I2C0SCLI       : in    std_logic := 'U';
          I2C0SCLO       : out   std_logic;
          SPI1DO         : out   std_logic;
          SPI1DOE        : out   std_logic;
          SPI1DI         : in    std_logic := 'U';
          SPI1CLKI       : in    std_logic := 'U';
          SPI1CLKO       : out   std_logic;
          SPI1MODE       : out   std_logic;
          SPI1SSI        : in    std_logic := 'U';
          SPI1SSO        : out   std_logic_vector(7 downto 0);
          UART1TXD       : out   std_logic;
          UART1RXD       : in    std_logic := 'U';
          I2C1SDAI       : in    std_logic := 'U';
          I2C1SDAO       : out   std_logic;
          I2C1SCLI       : in    std_logic := 'U';
          I2C1SCLO       : out   std_logic;
          MACTXD         : out   std_logic_vector(1 downto 0);
          MACRXD         : in    std_logic_vector(1 downto 0) := (others => 'U');
          MACTXEN        : out   std_logic;
          MACCRSDV       : in    std_logic := 'U';
          MACRXER        : in    std_logic := 'U';
          MACMDI         : in    std_logic := 'U';
          MACMDO         : out   std_logic;
          MACMDEN        : out   std_logic;
          MACMDC         : out   std_logic;
          EMCCLK         : out   std_logic;
          EMCCLKRTN      : in    std_logic := 'U';
          EMCRDB         : in    std_logic_vector(15 downto 0) := (others => 'U');
          EMCAB          : out   std_logic_vector(25 downto 0);
          EMCWDB         : out   std_logic_vector(15 downto 0);
          EMCRWn         : out   std_logic;
          EMCCS0n        : out   std_logic;
          EMCCS1n        : out   std_logic;
          EMCOEN0n       : out   std_logic;
          EMCOEN1n       : out   std_logic;
          EMCBYTEN       : out   std_logic_vector(1 downto 0);
          EMCDBOE        : out   std_logic;
          ADC0           : in    std_logic := 'U';
          ADC1           : in    std_logic := 'U';
          ADC2           : in    std_logic := 'U';
          ADC3           : in    std_logic := 'U';
          ADC4           : in    std_logic := 'U';
          ADC5           : in    std_logic := 'U';
          ADC6           : in    std_logic := 'U';
          ADC7           : in    std_logic := 'U';
          ADC8           : in    std_logic := 'U';
          ADC9           : in    std_logic := 'U';
          ADC10          : in    std_logic := 'U';
          ADC11          : in    std_logic := 'U';
          SDD0           : out   std_logic;
          SDD1           : out   std_logic;
          SDD2           : out   std_logic;
          ABPS0          : in    std_logic := 'U';
          ABPS1          : in    std_logic := 'U';
          ABPS2          : in    std_logic := 'U';
          ABPS3          : in    std_logic := 'U';
          ABPS4          : in    std_logic := 'U';
          ABPS5          : in    std_logic := 'U';
          ABPS6          : in    std_logic := 'U';
          ABPS7          : in    std_logic := 'U';
          ABPS8          : in    std_logic := 'U';
          ABPS9          : in    std_logic := 'U';
          ABPS10         : in    std_logic := 'U';
          ABPS11         : in    std_logic := 'U';
          TM0            : in    std_logic := 'U';
          TM1            : in    std_logic := 'U';
          TM2            : in    std_logic := 'U';
          TM3            : in    std_logic := 'U';
          TM4            : in    std_logic := 'U';
          TM5            : in    std_logic := 'U';
          CM0            : in    std_logic := 'U';
          CM1            : in    std_logic := 'U';
          CM2            : in    std_logic := 'U';
          CM3            : in    std_logic := 'U';
          CM4            : in    std_logic := 'U';
          CM5            : in    std_logic := 'U';
          GNDTM0         : in    std_logic := 'U';
          GNDTM1         : in    std_logic := 'U';
          GNDTM2         : in    std_logic := 'U';
          VAREF0         : in    std_logic := 'U';
          VAREF1         : in    std_logic := 'U';
          VAREF2         : in    std_logic := 'U';
          VAREFOUT       : out   std_logic;
          GNDVAREF       : in    std_logic := 'U';
          PUn            : in    std_logic := 'U'
        );
  end component;

  component MSSINT
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal MSS_ADLIB_INST_FCLK, MSS_ADLIB_INST_MACCLK, 
        MSS_ADLIB_INST_MACCLKCCC, MSS_ADLIB_INST_PLLLOCK, 
        MSS_ADLIB_INST_SYNCCLKFDBK, MSS_EMI_0_AB_0_D, 
        MSS_EMI_0_AB_1_D, MSS_EMI_0_AB_2_D, MSS_EMI_0_AB_3_D, 
        MSS_EMI_0_AB_4_D, MSS_EMI_0_AB_5_D, MSS_EMI_0_AB_6_D, 
        MSS_EMI_0_AB_7_D, MSS_EMI_0_AB_8_D, MSS_EMI_0_AB_9_D, 
        MSS_EMI_0_AB_10_D, MSS_EMI_0_AB_11_D, MSS_EMI_0_AB_12_D, 
        MSS_EMI_0_AB_13_D, MSS_EMI_0_AB_14_D, MSS_EMI_0_AB_15_D, 
        MSS_EMI_0_AB_16_D, MSS_EMI_0_AB_17_D, MSS_EMI_0_AB_18_D, 
        MSS_EMI_0_AB_19_D, MSS_EMI_0_AB_20_D, MSS_EMI_0_AB_21_D, 
        MSS_EMI_0_AB_22_D, MSS_EMI_0_AB_23_D, MSS_EMI_0_AB_24_D, 
        MSS_EMI_0_AB_25_D, MSS_EMI_0_BYTEN_0_D, 
        MSS_EMI_0_BYTEN_1_D, MSS_EMI_0_CLK_D, MSS_EMI_0_CS0_N_D, 
        MSS_EMI_0_CS1_N_D, MSS_EMI_0_DB_0_D, MSS_EMI_0_DB_0_Y, 
        MSS_EMI_0_DB_1_D, MSS_EMI_0_DB_1_Y, MSS_EMI_0_DB_2_D, 
        MSS_EMI_0_DB_2_Y, MSS_EMI_0_DB_3_D, MSS_EMI_0_DB_3_Y, 
        MSS_EMI_0_DB_4_D, MSS_EMI_0_DB_4_Y, MSS_EMI_0_DB_5_D, 
        MSS_EMI_0_DB_5_Y, MSS_EMI_0_DB_6_D, MSS_EMI_0_DB_6_Y, 
        MSS_EMI_0_DB_7_D, MSS_EMI_0_DB_7_Y, MSS_EMI_0_DB_8_D, 
        MSS_EMI_0_DB_8_Y, MSS_EMI_0_DB_9_D, MSS_EMI_0_DB_9_Y, 
        MSS_EMI_0_DB_10_D, MSS_EMI_0_DB_10_Y, MSS_EMI_0_DB_11_D, 
        MSS_EMI_0_DB_11_Y, MSS_EMI_0_DB_12_D, MSS_EMI_0_DB_12_Y, 
        MSS_EMI_0_DB_13_D, MSS_EMI_0_DB_13_Y, MSS_EMI_0_DB_14_D, 
        MSS_EMI_0_DB_14_Y, MSS_EMI_0_DB_15_D, MSS_EMI_0_DB_15_E, 
        MSS_EMI_0_DB_15_Y, MSS_EMI_0_OEN0_N_D, MSS_EMI_0_OEN1_N_D, 
        MSS_EMI_0_RW_N_D, MSS_I2C_0_SCL_E, MSS_I2C_0_SCL_Y, 
        MSS_I2C_0_SDA_E, MSS_I2C_0_SDA_Y, MSS_I2C_1_SCL_E, 
        MSS_I2C_1_SCL_Y, MSS_I2C_1_SDA_E, MSS_I2C_1_SDA_Y, 
        MSS_MAC_0_CRSDV_Y, MSS_MAC_0_MDC_D, MSS_MAC_0_MDIO_D, 
        MSS_MAC_0_MDIO_E, MSS_MAC_0_MDIO_Y, MSS_MAC_0_RXD_0_Y, 
        MSS_MAC_0_RXD_1_Y, MSS_MAC_0_RXER_Y, MSS_MAC_0_TXD_0_D, 
        MSS_MAC_0_TXD_1_D, MSS_MAC_0_TXEN_D, 
        MSS_RESET_0_MSS_RESET_N_Y, MSS_SPI_0_CLK_D, 
        MSS_SPI_0_CLK_Y, MSS_SPI_0_DI_Y, MSS_SPI_0_DO_D, 
        MSS_SPI_0_DO_E, MSS_SPI_0_SS_D, MSS_SPI_0_SS_E, 
        MSS_SPI_0_SS_Y, MSS_SPI_1_CLK_D, MSS_SPI_1_CLK_Y, 
        MSS_SPI_1_DI_Y, MSS_SPI_1_DO_D, MSS_SPI_1_DO_E, 
        MSS_SPI_1_SS_D, MSS_SPI_1_SS_E, MSS_SPI_1_SS_Y, 
        MSS_UART_0_RXD_Y, MSS_UART_0_TXD_D, MSS_UART_1_RXD_Y, 
        MSS_UART_1_TXD_D, MSSINT_GPO_0_A, GND_net, VCC_net
         : std_logic;
    signal nc151, nc23, nc175, nc58, nc116, nc74, nc133, nc167, 
        nc84, nc39, nc72, nc82, nc145, nc160, nc57, nc156, nc125, 
        nc73, nc107, nc66, nc83, nc9, nc171, nc54, nc135, nc41, 
        nc100, nc52, nc29, nc118, nc60, nc141, nc45, nc53, nc121, 
        nc158, nc162, nc11, nc131, nc96, nc79, nc146, nc89, nc119, 
        nc48, nc126, nc15, nc102, nc3, nc47, nc90, nc159, nc136, 
        nc59, nc18, nc44, nc117, nc164, nc148, nc42, nc17, nc2, 
        nc110, nc128, nc43, nc157, nc36, nc61, nc104, nc138, nc14, 
        nc150, nc149, nc12, nc30, nc65, nc7, nc129, nc8, nc13, 
        nc26, nc139, nc163, nc112, nc68, nc49, nc170, nc91, nc5, 
        nc20, nc147, nc67, nc152, nc127, nc103, nc76, nc140, nc86, 
        nc95, nc120, nc165, nc137, nc64, nc19, nc70, nc62, nc80, 
        nc130, nc98, nc114, nc56, nc105, nc63, nc172, nc97, nc161, 
        nc31, nc154, nc50, nc142, nc94, nc122, nc35, nc4, nc92, 
        nc101, nc166, nc132, nc21, nc93, nc69, nc174, nc38, nc113, 
        nc106, nc25, nc1, nc37, nc144, nc153, nc46, nc71, nc124, 
        nc81, nc168, nc34, nc28, nc115, nc134, nc32, nc40, nc99, 
        nc75, nc85, nc27, nc108, nc16, nc155, nc51, nc33, nc173, 
        nc169, nc78, nc24, nc88, nc111, nc55, nc10, nc22, nc143, 
        nc77, nc6, nc109, nc87, nc123 : std_logic;

begin 

    FAB_CLK <= MSS_ADLIB_INST_SYNCCLKFDBK;

    MSS_EMI_0_DB_12 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D2")

      port map(PAD => EMC_DB(12), D => MSS_EMI_0_DB_12_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_12_Y);
    
    MSS_MAC_0_RXER : INBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "AA4")

      port map(PAD => MAC_RXER, Y => MSS_MAC_0_RXER_Y);
    
    MSS_EMI_0_AB_24 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C16")

      port map(D => MSS_EMI_0_AB_24_D, PAD => EMC_AB(24));
    
    MSS_EMI_0_AB_4 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "E11")

      port map(D => MSS_EMI_0_AB_4_D, PAD => EMC_AB(4));
    
    MSS_EMI_0_AB_22 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C17")

      port map(D => MSS_EMI_0_AB_22_D, PAD => EMC_AB(22));
    
    MSS_EMI_0_OEN0_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D10")

      port map(D => MSS_EMI_0_OEN0_N_D, PAD => EMC_OEN0_N);
    
    MSS_I2C_0_SDA : BIBUF_OPEND_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "V21")

      port map(PAD => I2C_0_SDA, E => MSS_I2C_0_SDA_E, Y => 
        MSS_I2C_0_SDA_Y);
    
    MSS_MAC_0_MDC : OUTBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "AA3")

      port map(D => MSS_MAC_0_MDC_D, PAD => MAC_MDC);
    
    MSS_EMI_0_CS1_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A6")

      port map(D => MSS_EMI_0_CS1_N_D, PAD => EMC_CS1_N);
    
    MSS_EMI_0_AB_7 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A12")

      port map(D => MSS_EMI_0_AB_7_D, PAD => EMC_AB(7));
    
    MSS_EMI_0_AB_23 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C18")

      port map(D => MSS_EMI_0_AB_23_D, PAD => EMC_AB(23));
    
    MSS_EMI_0_DB_10 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "F4")

      port map(PAD => EMC_DB(10), D => MSS_EMI_0_DB_10_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_10_Y);
    
    MSS_EMI_0_DB_2 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "K5")

      port map(PAD => EMC_DB(2), D => MSS_EMI_0_DB_2_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_2_Y);
    
    MSS_EMI_0_BYTEN_0 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B9")

      port map(D => MSS_EMI_0_BYTEN_0_D, PAD => EMC_BYTEN(0));
    
    MSS_SPI_0_DO : TRIBUFF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "U17")

      port map(D => MSS_SPI_0_DO_D, E => MSS_SPI_0_DO_E, PAD => 
        SPI_0_DO);
    
    MSS_EMI_0_AB_25 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D16")

      port map(D => MSS_EMI_0_AB_25_D, PAD => EMC_AB(25));
    
    MSS_EMI_0_AB_19 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B17")

      port map(D => MSS_EMI_0_AB_19_D, PAD => EMC_AB(19));
    
    \VCC\ : VCC
      port map(Y => VCC_net);
    
    MSS_EMI_0_OEN1_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C10")

      port map(D => MSS_EMI_0_OEN1_N_D, PAD => EMC_OEN1_N);
    
    MSS_EMI_0_AB_14 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B13")

      port map(D => MSS_EMI_0_AB_14_D, PAD => EMC_AB(14));
    
    MSS_EMI_0_AB_2 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B10")

      port map(D => MSS_EMI_0_AB_2_D, PAD => EMC_AB(2));
    
    MSS_EMI_0_AB_12 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A14")

      port map(D => MSS_EMI_0_AB_12_D, PAD => EMC_AB(12));
    
    MSS_SPI_1_CLK : BIBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "AA22")

      port map(PAD => SPI_1_CLK, D => MSS_SPI_1_CLK_D, E => 
        MSS_SPI_1_SS_E, Y => MSS_SPI_1_CLK_Y);
    
    MSS_MAC_0_RXD_1 : INBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "U5")

      port map(PAD => MAC_RXD(1), Y => MSS_MAC_0_RXD_1_Y);
    
    MSS_EMI_0_AB_20 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "F13")

      port map(D => MSS_EMI_0_AB_20_D, PAD => EMC_AB(20));
    
    MSS_UART_1_RXD : INBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "W22")

      port map(PAD => UART_1_RXD, Y => MSS_UART_1_RXD_Y);
    
    MSS_EMI_0_DB_3 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "J4")

      port map(PAD => EMC_DB(3), D => MSS_EMI_0_DB_3_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_3_Y);
    
    MSS_EMI_0_AB_17 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C15")

      port map(D => MSS_EMI_0_AB_17_D, PAD => EMC_AB(17));
    
    MSS_EMI_0_DB_8 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "H3")

      port map(PAD => EMC_DB(8), D => MSS_EMI_0_DB_8_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_8_Y);
    
    MSS_I2C_1_SDA : BIBUF_OPEND_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "V22")

      port map(PAD => I2C_1_SDA, E => MSS_I2C_1_SDA_E, Y => 
        MSS_I2C_1_SDA_Y);
    
    MSS_EMI_0_DB_6 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "J1")

      port map(PAD => EMC_DB(6), D => MSS_EMI_0_DB_6_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_6_Y);
    
    MSS_EMI_0_AB_13 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A15")

      port map(D => MSS_EMI_0_AB_13_D, PAD => EMC_AB(13));
    
    MSS_SPI_0_CLK : BIBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "W19")

      port map(PAD => SPI_0_CLK, D => MSS_SPI_0_CLK_D, E => 
        MSS_SPI_0_SS_E, Y => MSS_SPI_0_CLK_Y);
    
    MSS_EMI_0_AB_21 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "F14")

      port map(D => MSS_EMI_0_AB_21_D, PAD => EMC_AB(21));
    
    MSS_EMI_0_DB_1 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "K3")

      port map(PAD => EMC_DB(1), D => MSS_EMI_0_DB_1_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_1_Y);
    
    MSS_EMI_0_AB_16 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C14")

      port map(D => MSS_EMI_0_AB_16_D, PAD => EMC_AB(16));
    
    MSS_EMI_0_DB_11 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "G5")

      port map(PAD => EMC_DB(11), D => MSS_EMI_0_DB_11_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_11_Y);
    
    \GND\ : GND
      port map(Y => GND_net);
    
    MSS_SPI_0_SS : BIBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "Y20")

      port map(PAD => SPI_0_SS, D => MSS_SPI_0_SS_D, E => 
        MSS_SPI_0_SS_E, Y => MSS_SPI_0_SS_Y);
    
    MSS_RESET_0_MSS_RESET_N : INBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "R1")

      port map(PAD => MSS_RESET_N, Y => MSS_RESET_0_MSS_RESET_N_Y);
    
    MSS_EMI_0_DB_0 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "K2")

      port map(PAD => EMC_DB(0), D => MSS_EMI_0_DB_0_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_0_Y);
    
    MSS_MAC_0_TXEN : OUTBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "Y4")

      port map(D => MSS_MAC_0_TXEN_D, PAD => MAC_TXEN);
    
    MSS_EMI_0_AB_15 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B14")

      port map(D => MSS_EMI_0_AB_15_D, PAD => EMC_AB(15));
    
    MSS_CCC_0 : mss_top_tmp_MSS_CCC_0_MSS_CCC
      port map(CLKA => GND_net, CLKA_PAD => GND_net, CLKA_PADP
         => GND_net, CLKA_PADN => GND_net, CLKB => GND_net, 
        CLKB_PAD => GND_net, CLKB_PADP => GND_net, CLKB_PADN => 
        GND_net, CLKC => GND_net, CLKC_PAD => GND_net, CLKC_PADP
         => GND_net, CLKC_PADN => GND_net, GLA => OPEN, GLB => 
        OPEN, GLC => OPEN, FAB_CLK => MSS_ADLIB_INST_SYNCCLKFDBK, 
        YB => OPEN, YC => OPEN, MAINXIN => MAINXIN, LPXIN => 
        GND_net, FAB_LOCK => FAB_LOCK, MAC_CLK => GND_net, 
        RCOSC_CLKOUT => OPEN, MAINXIN_CLKOUT => OPEN, 
        LPXIN_CLKOUT => OPEN, GLA0 => MSS_ADLIB_INST_FCLK, 
        MSS_LOCK => MSS_ADLIB_INST_PLLLOCK, MAC_CLK_CCC => 
        MSS_ADLIB_INST_MACCLKCCC, MAC_CLK_IO => 
        MSS_ADLIB_INST_MACCLK);
    
    MSS_EMI_0_AB_3 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B11")

      port map(D => MSS_EMI_0_AB_3_D, PAD => EMC_AB(3));
    
    MSS_SPI_0_DI : INBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "V18")

      port map(PAD => SPI_0_DI, Y => MSS_SPI_0_DI_Y);
    
    MSS_I2C_1_SCL : BIBUF_OPEND_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "U20")

      port map(PAD => I2C_1_SCL, E => MSS_I2C_1_SCL_E, Y => 
        MSS_I2C_1_SCL_Y);
    
    MSS_EMI_0_AB_8 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C13")

      port map(D => MSS_EMI_0_AB_8_D, PAD => EMC_AB(8));
    
    MSS_MAC_0_TXD_1 : OUTBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "W5")

      port map(D => MSS_MAC_0_TXD_1_D, PAD => MAC_TXD(1));
    
    MSS_EMI_0_AB_6 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B12")

      port map(D => MSS_EMI_0_AB_6_D, PAD => EMC_AB(6));
    
    MSS_ADLIB_INST : MSS_AHB
      generic map(ACT_CONFIG => 0, ACT_DIE => "IP6X5M2",
         ACT_FCLK => 80000000, ACT_PKG => "fg484")

      port map(MSSHADDR(19) => nc151, MSSHADDR(18) => nc23, 
        MSSHADDR(17) => nc175, MSSHADDR(16) => nc58, MSSHADDR(15)
         => nc116, MSSHADDR(14) => nc74, MSSHADDR(13) => nc133, 
        MSSHADDR(12) => nc167, MSSHADDR(11) => nc84, MSSHADDR(10)
         => nc39, MSSHADDR(9) => nc72, MSSHADDR(8) => nc82, 
        MSSHADDR(7) => nc145, MSSHADDR(6) => nc160, MSSHADDR(5)
         => nc57, MSSHADDR(4) => nc156, MSSHADDR(3) => nc125, 
        MSSHADDR(2) => nc73, MSSHADDR(1) => nc107, MSSHADDR(0)
         => nc66, MSSHWDATA(31) => nc83, MSSHWDATA(30) => nc9, 
        MSSHWDATA(29) => nc171, MSSHWDATA(28) => nc54, 
        MSSHWDATA(27) => nc135, MSSHWDATA(26) => nc41, 
        MSSHWDATA(25) => nc100, MSSHWDATA(24) => nc52, 
        MSSHWDATA(23) => nc29, MSSHWDATA(22) => nc118, 
        MSSHWDATA(21) => nc60, MSSHWDATA(20) => nc141, 
        MSSHWDATA(19) => nc45, MSSHWDATA(18) => nc53, 
        MSSHWDATA(17) => nc121, MSSHWDATA(16) => nc158, 
        MSSHWDATA(15) => nc162, MSSHWDATA(14) => nc11, 
        MSSHWDATA(13) => nc131, MSSHWDATA(12) => nc96, 
        MSSHWDATA(11) => nc79, MSSHWDATA(10) => nc146, 
        MSSHWDATA(9) => nc89, MSSHWDATA(8) => nc119, MSSHWDATA(7)
         => nc48, MSSHWDATA(6) => nc126, MSSHWDATA(5) => nc15, 
        MSSHWDATA(4) => nc102, MSSHWDATA(3) => nc3, MSSHWDATA(2)
         => nc47, MSSHWDATA(1) => nc90, MSSHWDATA(0) => nc159, 
        MSSHTRANS(1) => nc136, MSSHTRANS(0) => nc59, MSSHSIZE(1)
         => nc18, MSSHSIZE(0) => nc44, MSSHLOCK => OPEN, 
        MSSHWRITE => OPEN, MSSHRDATA(31) => GND_net, 
        MSSHRDATA(30) => GND_net, MSSHRDATA(29) => GND_net, 
        MSSHRDATA(28) => GND_net, MSSHRDATA(27) => GND_net, 
        MSSHRDATA(26) => GND_net, MSSHRDATA(25) => GND_net, 
        MSSHRDATA(24) => GND_net, MSSHRDATA(23) => GND_net, 
        MSSHRDATA(22) => GND_net, MSSHRDATA(21) => GND_net, 
        MSSHRDATA(20) => GND_net, MSSHRDATA(19) => GND_net, 
        MSSHRDATA(18) => GND_net, MSSHRDATA(17) => GND_net, 
        MSSHRDATA(16) => GND_net, MSSHRDATA(15) => GND_net, 
        MSSHRDATA(14) => GND_net, MSSHRDATA(13) => GND_net, 
        MSSHRDATA(12) => GND_net, MSSHRDATA(11) => GND_net, 
        MSSHRDATA(10) => GND_net, MSSHRDATA(9) => GND_net, 
        MSSHRDATA(8) => GND_net, MSSHRDATA(7) => GND_net, 
        MSSHRDATA(6) => GND_net, MSSHRDATA(5) => GND_net, 
        MSSHRDATA(4) => GND_net, MSSHRDATA(3) => GND_net, 
        MSSHRDATA(2) => GND_net, MSSHRDATA(1) => GND_net, 
        MSSHRDATA(0) => GND_net, MSSHREADY => VCC_net, MSSHRESP
         => GND_net, FABHADDR(31) => FABHADDR(31), FABHADDR(30)
         => FABHADDR(30), FABHADDR(29) => FABHADDR(29), 
        FABHADDR(28) => FABHADDR(28), FABHADDR(27) => 
        FABHADDR(27), FABHADDR(26) => FABHADDR(26), FABHADDR(25)
         => FABHADDR(25), FABHADDR(24) => FABHADDR(24), 
        FABHADDR(23) => FABHADDR(23), FABHADDR(22) => 
        FABHADDR(22), FABHADDR(21) => FABHADDR(21), FABHADDR(20)
         => FABHADDR(20), FABHADDR(19) => FABHADDR(19), 
        FABHADDR(18) => FABHADDR(18), FABHADDR(17) => 
        FABHADDR(17), FABHADDR(16) => FABHADDR(16), FABHADDR(15)
         => FABHADDR(15), FABHADDR(14) => FABHADDR(14), 
        FABHADDR(13) => FABHADDR(13), FABHADDR(12) => 
        FABHADDR(12), FABHADDR(11) => FABHADDR(11), FABHADDR(10)
         => FABHADDR(10), FABHADDR(9) => FABHADDR(9), FABHADDR(8)
         => FABHADDR(8), FABHADDR(7) => FABHADDR(7), FABHADDR(6)
         => FABHADDR(6), FABHADDR(5) => FABHADDR(5), FABHADDR(4)
         => FABHADDR(4), FABHADDR(3) => FABHADDR(3), FABHADDR(2)
         => FABHADDR(2), FABHADDR(1) => FABHADDR(1), FABHADDR(0)
         => FABHADDR(0), FABHWDATA(31) => FABHWDATA(31), 
        FABHWDATA(30) => FABHWDATA(30), FABHWDATA(29) => 
        FABHWDATA(29), FABHWDATA(28) => FABHWDATA(28), 
        FABHWDATA(27) => FABHWDATA(27), FABHWDATA(26) => 
        FABHWDATA(26), FABHWDATA(25) => FABHWDATA(25), 
        FABHWDATA(24) => FABHWDATA(24), FABHWDATA(23) => 
        FABHWDATA(23), FABHWDATA(22) => FABHWDATA(22), 
        FABHWDATA(21) => FABHWDATA(21), FABHWDATA(20) => 
        FABHWDATA(20), FABHWDATA(19) => FABHWDATA(19), 
        FABHWDATA(18) => FABHWDATA(18), FABHWDATA(17) => 
        FABHWDATA(17), FABHWDATA(16) => FABHWDATA(16), 
        FABHWDATA(15) => FABHWDATA(15), FABHWDATA(14) => 
        FABHWDATA(14), FABHWDATA(13) => FABHWDATA(13), 
        FABHWDATA(12) => FABHWDATA(12), FABHWDATA(11) => 
        FABHWDATA(11), FABHWDATA(10) => FABHWDATA(10), 
        FABHWDATA(9) => FABHWDATA(9), FABHWDATA(8) => 
        FABHWDATA(8), FABHWDATA(7) => FABHWDATA(7), FABHWDATA(6)
         => FABHWDATA(6), FABHWDATA(5) => FABHWDATA(5), 
        FABHWDATA(4) => FABHWDATA(4), FABHWDATA(3) => 
        FABHWDATA(3), FABHWDATA(2) => FABHWDATA(2), FABHWDATA(1)
         => FABHWDATA(1), FABHWDATA(0) => FABHWDATA(0), 
        FABHTRANS(1) => FABHTRANS(1), FABHTRANS(0) => 
        FABHTRANS(0), FABHSIZE(1) => FABHSIZE(1), FABHSIZE(0) => 
        FABHSIZE(0), FABHMASTLOCK => FABHMASTLOCK, FABHWRITE => 
        FABHWRITE, FABHSEL => FABHSEL, FABHREADY => FABHREADY, 
        FABHRDATA(31) => FABHRDATA(31), FABHRDATA(30) => 
        FABHRDATA(30), FABHRDATA(29) => FABHRDATA(29), 
        FABHRDATA(28) => FABHRDATA(28), FABHRDATA(27) => 
        FABHRDATA(27), FABHRDATA(26) => FABHRDATA(26), 
        FABHRDATA(25) => FABHRDATA(25), FABHRDATA(24) => 
        FABHRDATA(24), FABHRDATA(23) => FABHRDATA(23), 
        FABHRDATA(22) => FABHRDATA(22), FABHRDATA(21) => 
        FABHRDATA(21), FABHRDATA(20) => FABHRDATA(20), 
        FABHRDATA(19) => FABHRDATA(19), FABHRDATA(18) => 
        FABHRDATA(18), FABHRDATA(17) => FABHRDATA(17), 
        FABHRDATA(16) => FABHRDATA(16), FABHRDATA(15) => 
        FABHRDATA(15), FABHRDATA(14) => FABHRDATA(14), 
        FABHRDATA(13) => FABHRDATA(13), FABHRDATA(12) => 
        FABHRDATA(12), FABHRDATA(11) => FABHRDATA(11), 
        FABHRDATA(10) => FABHRDATA(10), FABHRDATA(9) => 
        FABHRDATA(9), FABHRDATA(8) => FABHRDATA(8), FABHRDATA(7)
         => FABHRDATA(7), FABHRDATA(6) => FABHRDATA(6), 
        FABHRDATA(5) => FABHRDATA(5), FABHRDATA(4) => 
        FABHRDATA(4), FABHRDATA(3) => FABHRDATA(3), FABHRDATA(2)
         => FABHRDATA(2), FABHRDATA(1) => FABHRDATA(1), 
        FABHRDATA(0) => FABHRDATA(0), FABHREADYOUT => 
        FABHREADYOUT, FABHRESP => FABHRESP, SYNCCLKFDBK => 
        MSS_ADLIB_INST_SYNCCLKFDBK, CALIBOUT => OPEN, CALIBIN => 
        GND_net, FABINT => GND_net, MSSINT(7) => nc117, MSSINT(6)
         => nc164, MSSINT(5) => nc148, MSSINT(4) => nc42, 
        MSSINT(3) => nc17, MSSINT(2) => nc2, MSSINT(1) => nc110, 
        MSSINT(0) => nc128, WDINT => OPEN, F2MRESETn => VCC_net, 
        DMAREADY(1) => GND_net, DMAREADY(0) => GND_net, RXEV => 
        GND_net, VRON => GND_net, M2FRESETn => OPEN, DEEPSLEEP
         => OPEN, SLEEP => OPEN, TXEV => OPEN, GPI(31) => GND_net, 
        GPI(30) => GND_net, GPI(29) => GND_net, GPI(28) => 
        GND_net, GPI(27) => GND_net, GPI(26) => GND_net, GPI(25)
         => GND_net, GPI(24) => GND_net, GPI(23) => GND_net, 
        GPI(22) => GND_net, GPI(21) => GND_net, GPI(20) => 
        GND_net, GPI(19) => GND_net, GPI(18) => GND_net, GPI(17)
         => GND_net, GPI(16) => GND_net, GPI(15) => GND_net, 
        GPI(14) => GND_net, GPI(13) => GND_net, GPI(12) => 
        GND_net, GPI(11) => GND_net, GPI(10) => GND_net, GPI(9)
         => GND_net, GPI(8) => GND_net, GPI(7) => GND_net, GPI(6)
         => GND_net, GPI(5) => GND_net, GPI(4) => GND_net, GPI(3)
         => GND_net, GPI(2) => GND_net, GPI(1) => GND_net, GPI(0)
         => GND_net, GPO(31) => nc43, GPO(30) => nc157, GPO(29)
         => nc36, GPO(28) => nc61, GPO(27) => nc104, GPO(26) => 
        nc138, GPO(25) => nc14, GPO(24) => nc150, GPO(23) => 
        nc149, GPO(22) => nc12, GPO(21) => nc30, GPO(20) => nc65, 
        GPO(19) => nc7, GPO(18) => nc129, GPO(17) => nc8, GPO(16)
         => nc13, GPO(15) => nc26, GPO(14) => nc139, GPO(13) => 
        nc163, GPO(12) => nc112, GPO(11) => nc68, GPO(10) => nc49, 
        GPO(9) => nc170, GPO(8) => nc91, GPO(7) => nc5, GPO(6)
         => nc20, GPO(5) => nc147, GPO(4) => nc67, GPO(3) => 
        nc152, GPO(2) => nc127, GPO(1) => nc103, GPO(0) => 
        MSSINT_GPO_0_A, UART0CTSn => GND_net, UART0DSRn => 
        GND_net, UART0RIn => GND_net, UART0DCDn => GND_net, 
        UART0RTSn => OPEN, UART0DTRn => OPEN, UART1CTSn => 
        GND_net, UART1DSRn => GND_net, UART1RIn => GND_net, 
        UART1DCDn => GND_net, UART1RTSn => OPEN, UART1DTRn => 
        OPEN, I2C0SMBUSNI => GND_net, I2C0SMBALERTNI => GND_net, 
        I2C0BCLK => GND_net, I2C0SMBUSNO => OPEN, I2C0SMBALERTNO
         => OPEN, I2C1SMBUSNI => GND_net, I2C1SMBALERTNI => 
        GND_net, I2C1BCLK => GND_net, I2C1SMBUSNO => OPEN, 
        I2C1SMBALERTNO => OPEN, MACM2FTXD(1) => nc76, 
        MACM2FTXD(0) => nc140, MACF2MRXD(1) => GND_net, 
        MACF2MRXD(0) => GND_net, MACM2FTXEN => OPEN, MACF2MCRSDV
         => GND_net, MACF2MRXER => GND_net, MACF2MMDI => GND_net, 
        MACM2FMDO => OPEN, MACM2FMDEN => OPEN, MACM2FMDC => OPEN, 
        FABSDD0D => GND_net, FABSDD1D => GND_net, FABSDD2D => 
        GND_net, FABSDD0CLK => GND_net, FABSDD1CLK => GND_net, 
        FABSDD2CLK => GND_net, FABACETRIG => GND_net, 
        ACEFLAGS(31) => nc86, ACEFLAGS(30) => nc95, ACEFLAGS(29)
         => nc120, ACEFLAGS(28) => nc165, ACEFLAGS(27) => nc137, 
        ACEFLAGS(26) => nc64, ACEFLAGS(25) => nc19, ACEFLAGS(24)
         => nc70, ACEFLAGS(23) => nc62, ACEFLAGS(22) => nc80, 
        ACEFLAGS(21) => nc130, ACEFLAGS(20) => nc98, ACEFLAGS(19)
         => nc114, ACEFLAGS(18) => nc56, ACEFLAGS(17) => nc105, 
        ACEFLAGS(16) => nc63, ACEFLAGS(15) => nc172, ACEFLAGS(14)
         => nc97, ACEFLAGS(13) => nc161, ACEFLAGS(12) => nc31, 
        ACEFLAGS(11) => nc154, ACEFLAGS(10) => nc50, ACEFLAGS(9)
         => nc142, ACEFLAGS(8) => nc94, ACEFLAGS(7) => nc122, 
        ACEFLAGS(6) => nc35, ACEFLAGS(5) => nc4, ACEFLAGS(4) => 
        nc92, ACEFLAGS(3) => nc101, ACEFLAGS(2) => nc166, 
        ACEFLAGS(1) => nc132, ACEFLAGS(0) => nc21, CMP0 => OPEN, 
        CMP1 => OPEN, CMP2 => OPEN, CMP3 => OPEN, CMP4 => OPEN, 
        CMP5 => OPEN, CMP6 => OPEN, CMP7 => OPEN, CMP8 => OPEN, 
        CMP9 => OPEN, CMP10 => OPEN, CMP11 => OPEN, LVTTL0EN => 
        GND_net, LVTTL1EN => GND_net, LVTTL2EN => GND_net, 
        LVTTL3EN => GND_net, LVTTL4EN => GND_net, LVTTL5EN => 
        GND_net, LVTTL6EN => GND_net, LVTTL7EN => GND_net, 
        LVTTL8EN => GND_net, LVTTL9EN => GND_net, LVTTL10EN => 
        GND_net, LVTTL11EN => GND_net, LVTTL0 => OPEN, LVTTL1 => 
        OPEN, LVTTL2 => OPEN, LVTTL3 => OPEN, LVTTL4 => OPEN, 
        LVTTL5 => OPEN, LVTTL6 => OPEN, LVTTL7 => OPEN, LVTTL8
         => OPEN, LVTTL9 => OPEN, LVTTL10 => OPEN, LVTTL11 => 
        OPEN, PUFABn => OPEN, VCC15GOOD => OPEN, VCC33GOOD => 
        OPEN, FCLK => MSS_ADLIB_INST_FCLK, MACCLKCCC => 
        MSS_ADLIB_INST_MACCLKCCC, RCOSC => GND_net, MACCLK => 
        MSS_ADLIB_INST_MACCLK, PLLLOCK => MSS_ADLIB_INST_PLLLOCK, 
        MSSRESETn => MSS_RESET_0_MSS_RESET_N_Y, GPOE(31) => nc93, 
        GPOE(30) => nc69, GPOE(29) => nc174, GPOE(28) => nc38, 
        GPOE(27) => nc113, GPOE(26) => nc106, GPOE(25) => nc25, 
        GPOE(24) => nc1, GPOE(23) => nc37, GPOE(22) => nc144, 
        GPOE(21) => nc153, GPOE(20) => nc46, GPOE(19) => nc71, 
        GPOE(18) => nc124, GPOE(17) => nc81, GPOE(16) => nc168, 
        GPOE(15) => nc34, GPOE(14) => nc28, GPOE(13) => nc115, 
        GPOE(12) => nc134, GPOE(11) => nc32, GPOE(10) => nc40, 
        GPOE(9) => nc99, GPOE(8) => nc75, GPOE(7) => nc85, 
        GPOE(6) => nc27, GPOE(5) => nc108, GPOE(4) => nc16, 
        GPOE(3) => nc155, GPOE(2) => nc51, GPOE(1) => nc33, 
        GPOE(0) => nc173, SPI0DO => MSS_SPI_0_DO_D, SPI0DOE => 
        MSS_SPI_0_DO_E, SPI0DI => MSS_SPI_0_DI_Y, SPI0CLKI => 
        MSS_SPI_0_CLK_Y, SPI0CLKO => MSS_SPI_0_CLK_D, SPI0MODE
         => MSS_SPI_0_SS_E, SPI0SSI => MSS_SPI_0_SS_Y, SPI0SSO(7)
         => nc169, SPI0SSO(6) => nc78, SPI0SSO(5) => nc24, 
        SPI0SSO(4) => nc88, SPI0SSO(3) => nc111, SPI0SSO(2) => 
        nc55, SPI0SSO(1) => nc10, SPI0SSO(0) => MSS_SPI_0_SS_D, 
        UART0TXD => MSS_UART_0_TXD_D, UART0RXD => 
        MSS_UART_0_RXD_Y, I2C0SDAI => MSS_I2C_0_SDA_Y, I2C0SDAO
         => MSS_I2C_0_SDA_E, I2C0SCLI => MSS_I2C_0_SCL_Y, 
        I2C0SCLO => MSS_I2C_0_SCL_E, SPI1DO => MSS_SPI_1_DO_D, 
        SPI1DOE => MSS_SPI_1_DO_E, SPI1DI => MSS_SPI_1_DI_Y, 
        SPI1CLKI => MSS_SPI_1_CLK_Y, SPI1CLKO => MSS_SPI_1_CLK_D, 
        SPI1MODE => MSS_SPI_1_SS_E, SPI1SSI => MSS_SPI_1_SS_Y, 
        SPI1SSO(7) => nc22, SPI1SSO(6) => nc143, SPI1SSO(5) => 
        nc77, SPI1SSO(4) => nc6, SPI1SSO(3) => nc109, SPI1SSO(2)
         => nc87, SPI1SSO(1) => nc123, SPI1SSO(0) => 
        MSS_SPI_1_SS_D, UART1TXD => MSS_UART_1_TXD_D, UART1RXD
         => MSS_UART_1_RXD_Y, I2C1SDAI => MSS_I2C_1_SDA_Y, 
        I2C1SDAO => MSS_I2C_1_SDA_E, I2C1SCLI => MSS_I2C_1_SCL_Y, 
        I2C1SCLO => MSS_I2C_1_SCL_E, MACTXD(1) => 
        MSS_MAC_0_TXD_1_D, MACTXD(0) => MSS_MAC_0_TXD_0_D, 
        MACRXD(1) => MSS_MAC_0_RXD_1_Y, MACRXD(0) => 
        MSS_MAC_0_RXD_0_Y, MACTXEN => MSS_MAC_0_TXEN_D, MACCRSDV
         => MSS_MAC_0_CRSDV_Y, MACRXER => MSS_MAC_0_RXER_Y, 
        MACMDI => MSS_MAC_0_MDIO_Y, MACMDO => MSS_MAC_0_MDIO_D, 
        MACMDEN => MSS_MAC_0_MDIO_E, MACMDC => MSS_MAC_0_MDC_D, 
        EMCCLK => MSS_EMI_0_CLK_D, EMCCLKRTN => MSS_EMI_0_CLK_D, 
        EMCRDB(15) => MSS_EMI_0_DB_15_Y, EMCRDB(14) => 
        MSS_EMI_0_DB_14_Y, EMCRDB(13) => MSS_EMI_0_DB_13_Y, 
        EMCRDB(12) => MSS_EMI_0_DB_12_Y, EMCRDB(11) => 
        MSS_EMI_0_DB_11_Y, EMCRDB(10) => MSS_EMI_0_DB_10_Y, 
        EMCRDB(9) => MSS_EMI_0_DB_9_Y, EMCRDB(8) => 
        MSS_EMI_0_DB_8_Y, EMCRDB(7) => MSS_EMI_0_DB_7_Y, 
        EMCRDB(6) => MSS_EMI_0_DB_6_Y, EMCRDB(5) => 
        MSS_EMI_0_DB_5_Y, EMCRDB(4) => MSS_EMI_0_DB_4_Y, 
        EMCRDB(3) => MSS_EMI_0_DB_3_Y, EMCRDB(2) => 
        MSS_EMI_0_DB_2_Y, EMCRDB(1) => MSS_EMI_0_DB_1_Y, 
        EMCRDB(0) => MSS_EMI_0_DB_0_Y, EMCAB(25) => 
        MSS_EMI_0_AB_25_D, EMCAB(24) => MSS_EMI_0_AB_24_D, 
        EMCAB(23) => MSS_EMI_0_AB_23_D, EMCAB(22) => 
        MSS_EMI_0_AB_22_D, EMCAB(21) => MSS_EMI_0_AB_21_D, 
        EMCAB(20) => MSS_EMI_0_AB_20_D, EMCAB(19) => 
        MSS_EMI_0_AB_19_D, EMCAB(18) => MSS_EMI_0_AB_18_D, 
        EMCAB(17) => MSS_EMI_0_AB_17_D, EMCAB(16) => 
        MSS_EMI_0_AB_16_D, EMCAB(15) => MSS_EMI_0_AB_15_D, 
        EMCAB(14) => MSS_EMI_0_AB_14_D, EMCAB(13) => 
        MSS_EMI_0_AB_13_D, EMCAB(12) => MSS_EMI_0_AB_12_D, 
        EMCAB(11) => MSS_EMI_0_AB_11_D, EMCAB(10) => 
        MSS_EMI_0_AB_10_D, EMCAB(9) => MSS_EMI_0_AB_9_D, EMCAB(8)
         => MSS_EMI_0_AB_8_D, EMCAB(7) => MSS_EMI_0_AB_7_D, 
        EMCAB(6) => MSS_EMI_0_AB_6_D, EMCAB(5) => 
        MSS_EMI_0_AB_5_D, EMCAB(4) => MSS_EMI_0_AB_4_D, EMCAB(3)
         => MSS_EMI_0_AB_3_D, EMCAB(2) => MSS_EMI_0_AB_2_D, 
        EMCAB(1) => MSS_EMI_0_AB_1_D, EMCAB(0) => 
        MSS_EMI_0_AB_0_D, EMCWDB(15) => MSS_EMI_0_DB_15_D, 
        EMCWDB(14) => MSS_EMI_0_DB_14_D, EMCWDB(13) => 
        MSS_EMI_0_DB_13_D, EMCWDB(12) => MSS_EMI_0_DB_12_D, 
        EMCWDB(11) => MSS_EMI_0_DB_11_D, EMCWDB(10) => 
        MSS_EMI_0_DB_10_D, EMCWDB(9) => MSS_EMI_0_DB_9_D, 
        EMCWDB(8) => MSS_EMI_0_DB_8_D, EMCWDB(7) => 
        MSS_EMI_0_DB_7_D, EMCWDB(6) => MSS_EMI_0_DB_6_D, 
        EMCWDB(5) => MSS_EMI_0_DB_5_D, EMCWDB(4) => 
        MSS_EMI_0_DB_4_D, EMCWDB(3) => MSS_EMI_0_DB_3_D, 
        EMCWDB(2) => MSS_EMI_0_DB_2_D, EMCWDB(1) => 
        MSS_EMI_0_DB_1_D, EMCWDB(0) => MSS_EMI_0_DB_0_D, EMCRWn
         => MSS_EMI_0_RW_N_D, EMCCS0n => MSS_EMI_0_CS0_N_D, 
        EMCCS1n => MSS_EMI_0_CS1_N_D, EMCOEN0n => 
        MSS_EMI_0_OEN0_N_D, EMCOEN1n => MSS_EMI_0_OEN1_N_D, 
        EMCBYTEN(1) => MSS_EMI_0_BYTEN_1_D, EMCBYTEN(0) => 
        MSS_EMI_0_BYTEN_0_D, EMCDBOE => MSS_EMI_0_DB_15_E, ADC0
         => GND_net, ADC1 => GND_net, ADC2 => GND_net, ADC3 => 
        GND_net, ADC4 => GND_net, ADC5 => GND_net, ADC6 => 
        GND_net, ADC7 => GND_net, ADC8 => GND_net, ADC9 => 
        GND_net, ADC10 => GND_net, ADC11 => GND_net, SDD0 => OPEN, 
        SDD1 => OPEN, SDD2 => OPEN, ABPS0 => GND_net, ABPS1 => 
        GND_net, ABPS2 => GND_net, ABPS3 => GND_net, ABPS4 => 
        GND_net, ABPS5 => GND_net, ABPS6 => GND_net, ABPS7 => 
        GND_net, ABPS8 => GND_net, ABPS9 => GND_net, ABPS10 => 
        GND_net, ABPS11 => GND_net, TM0 => GND_net, TM1 => 
        GND_net, TM2 => GND_net, TM3 => GND_net, TM4 => GND_net, 
        TM5 => GND_net, CM0 => GND_net, CM1 => GND_net, CM2 => 
        GND_net, CM3 => GND_net, CM4 => GND_net, CM5 => GND_net, 
        GNDTM0 => GND_net, GNDTM1 => GND_net, GNDTM2 => GND_net, 
        VAREF0 => GND_net, VAREF1 => GND_net, VAREF2 => GND_net, 
        VAREFOUT => OPEN, GNDVAREF => GND_net, PUn => GND_net);
    
    MSS_UART_1_TXD : OUTBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "V20")

      port map(D => MSS_UART_1_TXD_D, PAD => UART_1_TXD);
    
    MSS_EMI_0_AB_1 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A9")

      port map(D => MSS_EMI_0_AB_1_D, PAD => EMC_AB(1));
    
    MSS_EMI_0_AB_0 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A8")

      port map(D => MSS_EMI_0_AB_0_D, PAD => EMC_AB(0));
    
    MSS_EMI_0_DB_15 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B1")

      port map(PAD => EMC_DB(15), D => MSS_EMI_0_DB_15_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_15_Y);
    
    MSS_EMI_0_DB_14 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C1")

      port map(PAD => EMC_DB(14), D => MSS_EMI_0_DB_14_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_14_Y);
    
    MSS_MAC_0_TXD_0 : OUTBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "AA5")

      port map(D => MSS_MAC_0_TXD_0_D, PAD => MAC_TXD(0));
    
    MSS_EMI_0_AB_10 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D11")

      port map(D => MSS_EMI_0_AB_10_D, PAD => EMC_AB(10));
    
    MSS_SPI_1_DO : TRIBUFF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "T17")

      port map(D => MSS_SPI_1_DO_D, E => MSS_SPI_1_DO_E, PAD => 
        SPI_1_DO);
    
    MSS_EMI_0_AB_11 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D12")

      port map(D => MSS_EMI_0_AB_11_D, PAD => EMC_AB(11));
    
    MSS_EMI_0_DB_9 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "G3")

      port map(PAD => EMC_DB(9), D => MSS_EMI_0_DB_9_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_9_Y);
    
    MSS_EMI_0_BYTEN_1 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C9")

      port map(D => MSS_EMI_0_BYTEN_1_D, PAD => EMC_BYTEN(1));
    
    MSS_EMI_0_AB_18 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B16")

      port map(D => MSS_EMI_0_AB_18_D, PAD => EMC_AB(18));
    
    MSS_MAC_0_CRSDV : INBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "W4")

      port map(PAD => MAC_CRSDV, Y => MSS_MAC_0_CRSDV_Y);
    
    MSS_EMI_0_DB_5 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "J2")

      port map(PAD => EMC_DB(5), D => MSS_EMI_0_DB_5_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_5_Y);
    
    MSSINT_GPO_0 : MSSINT
      port map(A => MSSINT_GPO_0_A, Y => M2F_GPO_0);
    
    MSS_SPI_1_SS : BIBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "W21")

      port map(PAD => SPI_1_SS, D => MSS_SPI_1_SS_D, E => 
        MSS_SPI_1_SS_E, Y => MSS_SPI_1_SS_Y);
    
    MSS_MAC_0_MDIO : BIBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "V4")

      port map(PAD => MAC_MDIO, D => MSS_MAC_0_MDIO_D, E => 
        MSS_MAC_0_MDIO_E, Y => MSS_MAC_0_MDIO_Y);
    
    MSS_I2C_0_SCL : BIBUF_OPEND_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "U21")

      port map(PAD => I2C_0_SCL, E => MSS_I2C_0_SCL_E, Y => 
        MSS_I2C_0_SCL_Y);
    
    MSS_EMI_0_DB_4 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "J3")

      port map(PAD => EMC_DB(4), D => MSS_EMI_0_DB_4_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_4_Y);
    
    MSS_UART_0_RXD : INBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "U18")

      port map(PAD => UART_0_RXD, Y => MSS_UART_0_RXD_Y);
    
    MSS_EMI_0_AB_9 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D13")

      port map(D => MSS_EMI_0_AB_9_D, PAD => EMC_AB(9));
    
    MSS_EMI_0_CLK : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "C6")

      port map(D => MSS_EMI_0_CLK_D, PAD => EMC_CLK);
    
    MSS_EMI_0_DB_13 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "D3")

      port map(PAD => EMC_DB(13), D => MSS_EMI_0_DB_13_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_13_Y);
    
    MSS_MAC_0_RXD_0 : INBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "V5")

      port map(PAD => MAC_RXD(0), Y => MSS_MAC_0_RXD_0_Y);
    
    MSS_UART_0_TXD : OUTBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "Y22")

      port map(D => MSS_UART_0_TXD_D, PAD => UART_0_TXD);
    
    MSS_EMI_0_CS0_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "A5")

      port map(D => MSS_EMI_0_CS0_N_D, PAD => EMC_CS0_N);
    
    MSS_EMI_0_RW_N : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "B6")

      port map(D => MSS_EMI_0_RW_N_D, PAD => EMC_RW_N);
    
    MSS_EMI_0_AB_5 : OUTBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "E12")

      port map(D => MSS_EMI_0_AB_5_D, PAD => EMC_AB(5));
    
    MSS_EMI_0_DB_7 : BIBUF_MSS
      generic map(ACT_CONFIG => 536870912, ACT_PIN => "H1")

      port map(PAD => EMC_DB(7), D => MSS_EMI_0_DB_7_D, E => 
        MSS_EMI_0_DB_15_E, Y => MSS_EMI_0_DB_7_Y);
    
    MSS_SPI_1_DI : INBUF_MSS
      generic map(ACT_CONFIG => 0, ACT_PIN => "V19")

      port map(PAD => SPI_1_DI, Y => MSS_SPI_1_DI_Y);
    

end DEF_ARCH; 
