********************************************************************
                            Global Usage Report
********************************************************************
  
Product: Designer
Release: v10.0
Version: 10.0.9.37
Date: Wed Dec 07 16:53:56 2011
Design Name: top_level  Family: SmartFusion  Die: A2F500M3G  Package: 484 FBGA
Design State: Post-Layout

The following nets have been routed to a chip global resource:

    Fanout            Name
    ----------------------
    44                Net   : FAB_CLK
                      Driver: mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1




