Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Dec 07 16:07:42 2011


Design: top_level
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      7.853
Max Clock-To-Out (ns):      13.358

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      8.272
Max Clock-To-Out (ns):      13.699

Clock Domain:               mss_ccc_gla1
Period (ns):                8.222
Frequency (MHz):            121.625
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.119
External Hold (ns):         4.172
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                20.000
Frequency (MHz):            50.000
Required Period (ns):       20.833
Required Frequency (MHz):   48.001
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               Input_clk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      5.741
Max Clock-To-Out (ns):      9.093

Clock Domain:               FAB_CLK
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          FABHREADYOUT
  Delay (ns):                  9.288
  Slack (ns):
  Arrival (ns):                13.358
  Required (ns):
  Clock to Out (ns):           13.358


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: FABHREADYOUT
  data required time                             N/C
  data arrival time                          -   13.358
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.070          Clock generation
  4.070
               +     4.894          cell: ADLIB:MSS_AHB_IP
  8.964                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (f)
               +     0.159          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  9.123                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (f)
               +     0.073          cell: ADLIB:MSS_IF
  9.196                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (f)
               +     0.953          net: FABHREADYOUT_c
  10.149                       FABHREADYOUT_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  10.649                       FABHREADYOUT_pad/U0/U1:DOUT (f)
               +     0.000          net: FABHREADYOUT_pad/U0/NET1
  10.649                       FABHREADYOUT_pad/U0/U0:D (f)
               +     2.709          cell: ADLIB:IOPAD_TRI
  13.358                       FABHREADYOUT_pad/U0/U0:PAD (f)
               +     0.000          net: FABHREADYOUT
  13.358                       FABHREADYOUT (f)
                                    
  13.358                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.070          Clock generation
  N/C
                                    
  N/C                          FABHREADYOUT (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        fic_master_trans_0/HSEL/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  Delay (ns):                  0.943
  Slack (ns):                  4.857
  Arrival (ns):                6.730
  Required (ns):               11.587
  Setup (ns):                  4.983

Path 2
  From:                        fic_master_trans_0/HSEL/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWRITE
  Delay (ns):                  2.219
  Slack (ns):                  5.997
  Arrival (ns):                8.006
  Required (ns):               14.003
  Setup (ns):                  2.567

Path 3
  From:                        fic_master_trans_0/HSEL/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHSIZE[1]
  Delay (ns):                  0.952
  Slack (ns):                  6.183
  Arrival (ns):                6.739
  Required (ns):               12.922
  Setup (ns):                  3.648

Path 4
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[0]:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[0]
  Delay (ns):                  2.141
  Slack (ns):                  8.638
  Arrival (ns):                7.893
  Required (ns):               16.531
  Setup (ns):                  0.039

Path 5
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[4]
  Delay (ns):                  2.110
  Slack (ns):                  8.767
  Arrival (ns):                7.853
  Required (ns):               16.620
  Setup (ns):                  -0.050


Expanded Path 1
  From: fic_master_trans_0/HSEL/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  data required time                             11.587
  data arrival time                          -   6.730
  slack                                          4.857
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.538          net: FAB_CLK
  5.787                        fic_master_trans_0/HSEL/U1:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  6.346                        fic_master_trans_0/HSEL/U1:Q (f)
               +     0.305          net: fic_master_trans_0_HSEL
  6.651                        mss_top_0/MSS_ADLIB_INST/U_60:PIN4 (f)
               +     0.079          cell: ADLIB:MSS_IF
  6.730                        mss_top_0/MSS_ADLIB_INST/U_60:PIN4INT (f)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/FABHTRANS1INT_NET
  6.730                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1 (f)
                                    
  6.730                        data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_fabric_interface_clock
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.070          Clock generation
  16.570
               -     4.983          Library setup time: ADLIB:MSS_AHB_IP
  11.587                       mss_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
                                    
  11.587                       data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_0
  Delay (ns):                  9.629
  Slack (ns):
  Arrival (ns):                13.699
  Required (ns):
  Clock to Out (ns):           13.699


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: M2F_GPO_0
  data required time                             N/C
  data arrival time                          -   13.699
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.070          Clock generation
  4.070
               +     3.458          cell: ADLIB:MSS_AHB_IP
  7.528                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (f)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  7.528                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (f)
               +     0.073          cell: ADLIB:MSS_IF
  7.601                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (f)
               +     2.889          net: mss_top_0/MSSINT_GPO_0_A
  10.490                       M2F_GPO_0_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  10.990                       M2F_GPO_0_pad/U0/U1:DOUT (f)
               +     0.000          net: M2F_GPO_0_pad/U0/NET1
  10.990                       M2F_GPO_0_pad/U0/U0:D (f)
               +     2.709          cell: ADLIB:IOPAD_TRI
  13.699                       M2F_GPO_0_pad/U0/U0:PAD (f)
               +     0.000          net: M2F_GPO_0
  13.699                       M2F_GPO_0 (f)
                                    
  13.699                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.070          Clock generation
  N/C
                                    
  N/C                          M2F_GPO_0 (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[11]/U1:D
  Delay (ns):                  7.924
  Slack (ns):                  4.278
  Arrival (ns):                13.667
  Required (ns):               17.945
  Setup (ns):                  0.409
  Minimum Period (ns):         8.222

Path 2
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[3]/U1:D
  Delay (ns):                  7.731
  Slack (ns):                  4.341
  Arrival (ns):                13.474
  Required (ns):               17.815
  Setup (ns):                  0.435
  Minimum Period (ns):         8.159

Path 3
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[16]/U1:D
  Delay (ns):                  7.807
  Slack (ns):                  4.369
  Arrival (ns):                13.550
  Required (ns):               17.919
  Setup (ns):                  0.435
  Minimum Period (ns):         8.131

Path 4
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[15]/U1:D
  Delay (ns):                  7.742
  Slack (ns):                  4.403
  Arrival (ns):                13.485
  Required (ns):               17.888
  Setup (ns):                  0.435
  Minimum Period (ns):         8.097

Path 5
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLK
  To:                          fic_master_trans_0/HSEL/U1:D
  Delay (ns):                  7.565
  Slack (ns):                  4.570
  Arrival (ns):                13.308
  Required (ns):               17.878
  Setup (ns):                  0.409
  Minimum Period (ns):         7.930


Expanded Path 1
  From: fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLK
  To: fic_master_trans_0/HADDR_TEMP[11]/U1:D
  data required time                             17.945
  data arrival time                          -   13.667
  slack                                          4.278
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.494          net: FAB_CLK
  5.743                        fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  6.302                        fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:Q (f)
               +     0.856          net: _fic_master_trans_0_HWDATA_[4]_
  7.158                        fic_master_trans_0/HWRITE_DATA_TEMP_RNI3V38[7]:B (f)
               +     0.476          cell: ADLIB:NOR2B
  7.634                        fic_master_trans_0/HWRITE_DATA_TEMP_RNI3V38[7]:Y (f)
               +     0.255          net: fic_master_trans_0/un6_hreadyout_0_0
  7.889                        fic_master_trans_0/HWRITE_DATA_TEMP_RNI6U7G[5]:C (f)
               +     0.517          cell: ADLIB:OR3C
  8.406                        fic_master_trans_0/HWRITE_DATA_TEMP_RNI6U7G[5]:Y (r)
               +     0.292          net: fic_master_trans_0/un6_hreadyout_0
  8.698                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIGICS[1]:C (r)
               +     0.486          cell: ADLIB:OR3B
  9.184                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIGICS[1]:Y (r)
               +     0.237          net: fic_master_trans_0/un12_hreadyout
  9.421                        fic_master_trans_0/HWRITE_DATA_TEMP_RNI7LN21[1]:A (r)
               +     0.308          cell: ADLIB:NOR2B
  9.729                        fic_master_trans_0/HWRITE_DATA_TEMP_RNI7LN21[1]:Y (r)
               +     1.226          net: fic_master_trans_0/un9_hreadyout
  10.955                       fic_master_trans_0/ahb_states_RNIHRUB2_0[0]:B (r)
               +     0.514          cell: ADLIB:MX2
  11.469                       fic_master_trans_0/ahb_states_RNIHRUB2_0[0]:Y (r)
               +     1.319          net: fic_master_trans_0/un2_hreadyout_0[0]
  12.788                       fic_master_trans_0/HADDR_TEMP[11]/U0:S (r)
               +     0.277          cell: ADLIB:MX2
  13.065                       fic_master_trans_0/HADDR_TEMP[11]/U0:Y (r)
               +     0.602          net: fic_master_trans_0/HADDR_TEMP[11]/Y
  13.667                       fic_master_trans_0/HADDR_TEMP[11]/U1:D (r)
                                    
  13.667                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.605          net: FAB_CLK
  18.354                       fic_master_trans_0/HADDR_TEMP[11]/U1:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1P0
  17.945                       fic_master_trans_0/HADDR_TEMP[11]/U1:D
                                    
  17.945                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[3]/U1:D
  Delay (ns):                  11.054
  Slack (ns):                  2.691
  Arrival (ns):                15.124
  Required (ns):               17.815
  Setup (ns):                  0.435

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[11]/U1:D
  Delay (ns):                  11.153
  Slack (ns):                  2.722
  Arrival (ns):                15.223
  Required (ns):               17.945
  Setup (ns):                  0.409

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[16]/U1:D
  Delay (ns):                  11.036
  Slack (ns):                  2.813
  Arrival (ns):                15.106
  Required (ns):               17.919
  Setup (ns):                  0.435

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[15]/U1:D
  Delay (ns):                  10.971
  Slack (ns):                  2.847
  Arrival (ns):                15.041
  Required (ns):               17.888
  Setup (ns):                  0.435

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[0]:D
  Delay (ns):                  10.863
  Slack (ns):                  2.884
  Arrival (ns):                14.933
  Required (ns):               17.817
  Setup (ns):                  0.435


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: fic_master_trans_0/HADDR_TEMP[3]/U1:D
  data required time                             17.815
  data arrival time                          -   15.124
  slack                                          2.691
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.070          Clock generation
  4.070
               +     4.972          cell: ADLIB:MSS_AHB_IP
  9.042                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (r)
               +     0.134          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  9.176                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (r)
               +     0.074          cell: ADLIB:MSS_IF
  9.250                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (r)
               +     1.601          net: FABHREADYOUT_c
  10.851                       fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[5]:C (r)
               +     0.302          cell: ADLIB:OA1
  11.153                       fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[5]:Y (r)
               +     1.164          net: fic_master_trans_0/un1_hreadyout
  12.317                       fic_master_trans_0/ahb_states_RNIHRUB2[0]:A (r)
               +     0.431          cell: ADLIB:MX2
  12.748                       fic_master_trans_0/ahb_states_RNIHRUB2[0]:Y (r)
               +     1.847          net: fic_master_trans_0/ahb_states_RNIHRUB2[0]
  14.595                       fic_master_trans_0/HADDR_TEMP[3]/U0:S (r)
               +     0.282          cell: ADLIB:MX2
  14.877                       fic_master_trans_0/HADDR_TEMP[3]/U0:Y (f)
               +     0.247          net: fic_master_trans_0/HADDR_TEMP[3]/Y
  15.124                       fic_master_trans_0/HADDR_TEMP[3]/U1:D (f)
                                    
  15.124                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.501          net: FAB_CLK
  18.250                       fic_master_trans_0/HADDR_TEMP[3]/U1:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1P0
  17.815                       fic_master_trans_0/HADDR_TEMP[3]/U1:D
                                    
  17.815                       data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_pclk1 to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[1]:CLR
  Delay (ns):                  7.042
  Slack (ns):                  7.017
  Arrival (ns):                11.112
  Required (ns):               18.129
  Setup (ns):

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[19]/U1:CLR
  Delay (ns):                  7.042
  Slack (ns):                  7.017
  Arrival (ns):                11.112
  Required (ns):               18.129
  Setup (ns):

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[18]/U1:CLR
  Delay (ns):                  7.042
  Slack (ns):                  7.017
  Arrival (ns):                11.112
  Required (ns):               18.129
  Setup (ns):

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[8]/U1:PRE
  Delay (ns):                  7.042
  Slack (ns):                  7.017
  Arrival (ns):                11.112
  Required (ns):               18.129
  Setup (ns):

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[9]/U1:PRE
  Delay (ns):                  7.042
  Slack (ns):                  7.017
  Arrival (ns):                11.112
  Required (ns):               18.129
  Setup (ns):


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: fic_master_trans_0/HADDR_TEMP[1]:CLR
  data required time                             18.129
  data arrival time                          -   11.112
  slack                                          7.017
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.070          Clock generation
  4.070
               +     3.680          cell: ADLIB:MSS_AHB_IP
  7.750                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  7.750                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (r)
               +     0.074          cell: ADLIB:MSS_IF
  7.824                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (r)
               +     3.288          net: mss_top_0/MSSINT_GPO_0_A
  11.112                       fic_master_trans_0/HADDR_TEMP[1]:CLR (r)
                                    
  11.112                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.605          net: FAB_CLK
  18.354                       fic_master_trans_0/HADDR_TEMP[1]:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  18.129                       fic_master_trans_0/HADDR_TEMP[1]:CLR
                                    
  18.129                       data required time


END SET mss_pclk1 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.830
  External Setup (ns):         -5.119


Expanded Path 1
  From: MSS_RESET_N
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        mss_top_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        mss_top_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: mss_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.525          net: mss_top_0/GLA0
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.830          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_ccc_gla0

Path 1
  From:                        fic_master_trans_0/HADDR_TEMP[15]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[15]
  Delay (ns):                  1.541
  Slack (ns):                  0.642
  Arrival (ns):                7.364
  Required (ns):               8.006
  Setup (ns):                  8.564

Path 2
  From:                        fic_master_trans_0/HADDR_TEMP[13]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[13]
  Delay (ns):                  1.497
  Slack (ns):                  0.658
  Arrival (ns):                7.320
  Required (ns):               7.978
  Setup (ns):                  8.592

Path 3
  From:                        fic_master_trans_0/HADDR_TEMP[12]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[12]
  Delay (ns):                  1.576
  Slack (ns):                  0.682
  Arrival (ns):                7.332
  Required (ns):               8.014
  Setup (ns):                  8.556

Path 4
  From:                        fic_master_trans_0/HADDR_TEMP[10]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[10]
  Delay (ns):                  1.534
  Slack (ns):                  0.735
  Arrival (ns):                7.357
  Required (ns):               8.092
  Setup (ns):                  8.478

Path 5
  From:                        fic_master_trans_0/HADDR_TEMP[20]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[20]
  Delay (ns):                  1.422
  Slack (ns):                  0.767
  Arrival (ns):                7.245
  Required (ns):               8.012
  Setup (ns):                  8.558


Expanded Path 1
  From: fic_master_trans_0/HADDR_TEMP[15]/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[15]
  data required time                             8.006
  data arrival time                          -   7.364
  slack                                          0.642
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.574          net: FAB_CLK
  5.823                        fic_master_trans_0/HADDR_TEMP[15]/U1:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  6.382                        fic_master_trans_0/HADDR_TEMP[15]/U1:Q (f)
               +     0.564          net: _fic_master_trans_0_HADDR_[15]_
  6.946                        mss_top_0/MSS_ADLIB_INST/U_35:PIN5 (f)
               +     0.079          cell: ADLIB:MSS_IF
  7.025                        mss_top_0/MSS_ADLIB_INST/U_35:PIN5INT (f)
               +     0.339          net: mss_top_0/MSS_ADLIB_INST/FABHADDR[15]INT_NET
  7.364                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[15] (f)
                                    
  7.364                        data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla0
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  16.045
               +     0.525          net: mss_top_0/GLA0
  16.570                       mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -     8.564          Library setup time: ADLIB:MSS_AHB_IP
  8.006                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[15]
                                    
  8.006                        data required time


END SET mss_ccc_gla1 to mss_ccc_gla0

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain Input_clk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          FAB_CLK
  Delay (ns):                  9.093
  Slack (ns):
  Arrival (ns):                9.093
  Required (ns):
  Clock to Out (ns):           9.093


Expanded Path 1
  From: mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: FAB_CLK
  data required time                             N/C
  data arrival time                          -   9.093
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Input_clk
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     5.249          cell: ADLIB:MSS_CCC_IP
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (f)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (f)
               +     0.536          net: FAB_CLK
  5.785                        FAB_CLK_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  6.285                        FAB_CLK_pad/U0/U1:DOUT (f)
               +     0.000          net: FAB_CLK_pad/U0/NET1
  6.285                        FAB_CLK_pad/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  9.093                        FAB_CLK_pad/U0/U0:PAD (f)
               +     0.000          net: FAB_CLK_c
  9.093                        FAB_CLK (f)
                                    
  9.093                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          Input_clk
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          FAB_CLK (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain FAB_CLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

