-- Version: 9.1 SP1 9.1.1.7
-- File used only for Simulation

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity top_level is

    port( EMC_CLK      : out   std_logic;
          EMC_CS0_N    : out   std_logic;
          EMC_CS1_N    : out   std_logic;
          EMC_OEN0_N   : out   std_logic;
          EMC_OEN1_N   : out   std_logic;
          EMC_RW_N     : out   std_logic;
          UART_1_TXD   : out   std_logic;
          UART_1_RXD   : in    std_logic;
          UART_0_TXD   : out   std_logic;
          UART_0_RXD   : in    std_logic;
          I2C_0_SCL    : inout std_logic := 'Z';
          I2C_0_SDA    : inout std_logic := 'Z';
          SPI_1_DO     : out   std_logic;
          SPI_1_SS     : inout std_logic := 'Z';
          SPI_1_CLK    : inout std_logic := 'Z';
          SPI_1_DI     : in    std_logic;
          SPI_0_DO     : out   std_logic;
          SPI_0_CLK    : inout std_logic := 'Z';
          SPI_0_SS     : inout std_logic := 'Z';
          SPI_0_DI     : in    std_logic;
          I2C_1_SDA    : inout std_logic := 'Z';
          I2C_1_SCL    : inout std_logic := 'Z';
          MAC_MDIO     : inout std_logic := 'Z';
          MAC_MDC      : out   std_logic;
          MAC_CRSDV    : in    std_logic;
          MAC_RXER     : in    std_logic;
          MAC_TXEN     : out   std_logic;
          MSS_RESET_N  : in    std_logic;
          MAINXIN      : in    std_logic;
          FAB_CLK      : out   std_logic;
          FABHREADYOUT : out   std_logic;
          M2F_GPO_0    : out   std_logic;
          EMC_DB       : inout std_logic_vector(15 downto 0) := (others => 'Z');
          EMC_AB       : out   std_logic_vector(25 downto 0);
          EMC_BYTEN    : out   std_logic_vector(1 downto 0);
          MAC_RXD      : in    std_logic_vector(1 downto 0);
          MAC_TXD      : out   std_logic_vector(1 downto 0)
        );

end top_level;

architecture DEF_ARCH of top_level is 

  component XOR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component IOPAD_TRI
    port( D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component OR3C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR2B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component MSS_IF
    port( PIN4    : in    std_logic := 'U';
          PIN5    : in    std_logic := 'U';
          PIN6    : in    std_logic := 'U';
          PIN1    : out   std_logic;
          PIN2    : out   std_logic;
          PIN3    : out   std_logic;
          PIN4INT : out   std_logic;
          PIN5INT : out   std_logic;
          PIN6INT : out   std_logic;
          PIN1INT : in    std_logic := 'U';
          PIN2INT : in    std_logic := 'U';
          PIN3INT : in    std_logic := 'U'
        );
  end component;

  component AND3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component DFN1P0
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          PRE : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component DFN1C0
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          CLR : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MX2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          S : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AND2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AX1C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component MSS_CCC_GL_IF
    port( PIN2    : in    std_logic := 'U';
          PIN3    : in    std_logic := 'U';
          PIN4    : in    std_logic := 'U';
          PIN1    : out   std_logic;
          PIN5    : out   std_logic;
          PIN2INT : out   std_logic;
          PIN3INT : out   std_logic;
          PIN4INT : out   std_logic;
          PIN1INT : in    std_logic := 'U';
          PIN5INT : in    std_logic := 'U'
        );
  end component;

  component IOPAD_BI
    port( D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Y   : out   std_logic;
          PAD : inout   std_logic
        );
  end component;

  component OR3B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component MSS_CCC_IP
    generic (VCOFREQUENCY:real := 0.0);

    port( CLKA      : in    std_logic := 'U';
          EXTFB     : in    std_logic := 'U';
          GLA       : out   std_logic;
          GLAMSS    : out   std_logic;
          LOCK      : out   std_logic;
          LOCKMSS   : out   std_logic;
          CLKB      : in    std_logic := 'U';
          GLB       : out   std_logic;
          YB        : out   std_logic;
          CLKC      : in    std_logic := 'U';
          GLC       : out   std_logic;
          YC        : out   std_logic;
          MACCLK    : out   std_logic;
          SDIN      : in    std_logic := 'U';
          SCLK      : in    std_logic := 'U';
          SSHIFT    : in    std_logic := 'U';
          SUPDATE   : in    std_logic := 'U';
          MODE      : in    std_logic := 'U';
          SDOUT     : out   std_logic;
          PLLEN     : in    std_logic := 'U';
          OADIV     : in    std_logic_vector(4 downto 0) := (others => 'U');
          OADIVHALF : in    std_logic := 'U';
          OADIVRST  : in    std_logic := 'U';
          OAMUX     : in    std_logic_vector(2 downto 0) := (others => 'U');
          BYPASSA   : in    std_logic := 'U';
          DLYGLA    : in    std_logic_vector(4 downto 0) := (others => 'U');
          DLYGLAMSS : in    std_logic_vector(4 downto 0) := (others => 'U');
          DLYGLAFAB : in    std_logic_vector(4 downto 0) := (others => 'U');
          OBDIV     : in    std_logic_vector(4 downto 0) := (others => 'U');
          OBDIVHALF : in    std_logic := 'U';
          OBDIVRST  : in    std_logic := 'U';
          OBMUX     : in    std_logic_vector(2 downto 0) := (others => 'U');
          BYPASSB   : in    std_logic := 'U';
          DLYGLB    : in    std_logic_vector(4 downto 0) := (others => 'U');
          OCDIV     : in    std_logic_vector(4 downto 0) := (others => 'U');
          OCDIVHALF : in    std_logic := 'U';
          OCDIVRST  : in    std_logic := 'U';
          OCMUX     : in    std_logic_vector(2 downto 0) := (others => 'U');
          BYPASSC   : in    std_logic := 'U';
          DLYGLC    : in    std_logic_vector(4 downto 0) := (others => 'U');
          FINDIV    : in    std_logic_vector(6 downto 0) := (others => 'U');
          FBDIV     : in    std_logic_vector(6 downto 0) := (others => 'U');
          FBDLY     : in    std_logic_vector(4 downto 0) := (others => 'U');
          FBSEL     : in    std_logic_vector(1 downto 0) := (others => 'U');
          XDLYSEL   : in    std_logic := 'U';
          VCOSEL    : in    std_logic_vector(2 downto 0) := (others => 'U');
          GLMUXINT  : in    std_logic := 'U';
          GLMUXSEL  : in    std_logic_vector(1 downto 0) := (others => 'U');
          GLMUXCFG  : in    std_logic_vector(1 downto 0) := (others => 'U')
        );
  end component;

  component IOTRI_OB_EB
    port( D    : in    std_logic := 'U';
          E    : in    std_logic := 'U';
          DOUT : out   std_logic;
          EOUT : out   std_logic
        );
  end component;

  component XNOR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OA1
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component IOPAD_IN
    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component NOR2A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component INV
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR2B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component MSS_AHB_IP
    generic (ACT_CONFIG:integer := 0; ACT_FCLK:integer := 0; 
        ACT_DIE:string := ""; ACT_PKG:string := "");

    port( FCLK           : in    std_logic := 'U';
          MACCLKCCC      : in    std_logic := 'U';
          RCOSC          : in    std_logic := 'U';
          MACCLK         : in    std_logic := 'U';
          PLLLOCK        : in    std_logic := 'U';
          MSSRESETn      : in    std_logic := 'U';
          GPOE           : out   std_logic_vector(31 downto 0);
          SPI0DO         : out   std_logic;
          SPI0DOE        : out   std_logic;
          SPI0DI         : in    std_logic := 'U';
          SPI0CLKI       : in    std_logic := 'U';
          SPI0CLKO       : out   std_logic;
          SPI0MODE       : out   std_logic;
          SPI0SSI        : in    std_logic := 'U';
          SPI0SSO        : out   std_logic_vector(7 downto 0);
          UART0TXD       : out   std_logic;
          UART0RXD       : in    std_logic := 'U';
          I2C0SDAI       : in    std_logic := 'U';
          I2C0SDAO       : out   std_logic;
          I2C0SCLI       : in    std_logic := 'U';
          I2C0SCLO       : out   std_logic;
          SPI1DO         : out   std_logic;
          SPI1DOE        : out   std_logic;
          SPI1DI         : in    std_logic := 'U';
          SPI1CLKI       : in    std_logic := 'U';
          SPI1CLKO       : out   std_logic;
          SPI1MODE       : out   std_logic;
          SPI1SSI        : in    std_logic := 'U';
          SPI1SSO        : out   std_logic_vector(7 downto 0);
          UART1TXD       : out   std_logic;
          UART1RXD       : in    std_logic := 'U';
          I2C1SDAI       : in    std_logic := 'U';
          I2C1SDAO       : out   std_logic;
          I2C1SCLI       : in    std_logic := 'U';
          I2C1SCLO       : out   std_logic;
          MACTXD         : out   std_logic_vector(1 downto 0);
          MACRXD         : in    std_logic_vector(1 downto 0) := (others => 'U');
          MACTXEN        : out   std_logic;
          MACCRSDV       : in    std_logic := 'U';
          MACRXER        : in    std_logic := 'U';
          MACMDI         : in    std_logic := 'U';
          MACMDO         : out   std_logic;
          MACMDEN        : out   std_logic;
          MACMDC         : out   std_logic;
          EMCCLK         : out   std_logic;
          EMCCLKRTN      : in    std_logic := 'U';
          EMCRDB         : in    std_logic_vector(15 downto 0) := (others => 'U');
          EMCAB          : out   std_logic_vector(25 downto 0);
          EMCWDB         : out   std_logic_vector(15 downto 0);
          EMCRWn         : out   std_logic;
          EMCCS0n        : out   std_logic;
          EMCCS1n        : out   std_logic;
          EMCOEN0n       : out   std_logic;
          EMCOEN1n       : out   std_logic;
          EMCBYTEN       : out   std_logic_vector(1 downto 0);
          EMCDBOE        : out   std_logic;
          ADC0           : in    std_logic := 'U';
          ADC1           : in    std_logic := 'U';
          ADC2           : in    std_logic := 'U';
          ADC3           : in    std_logic := 'U';
          ADC4           : in    std_logic := 'U';
          ADC5           : in    std_logic := 'U';
          ADC6           : in    std_logic := 'U';
          ADC7           : in    std_logic := 'U';
          ADC8           : in    std_logic := 'U';
          ADC9           : in    std_logic := 'U';
          ADC10          : in    std_logic := 'U';
          ADC11          : in    std_logic := 'U';
          SDD0           : out   std_logic;
          SDD1           : out   std_logic;
          SDD2           : out   std_logic;
          ABPS0          : in    std_logic := 'U';
          ABPS1          : in    std_logic := 'U';
          ABPS2          : in    std_logic := 'U';
          ABPS3          : in    std_logic := 'U';
          ABPS4          : in    std_logic := 'U';
          ABPS5          : in    std_logic := 'U';
          ABPS6          : in    std_logic := 'U';
          ABPS7          : in    std_logic := 'U';
          ABPS8          : in    std_logic := 'U';
          ABPS9          : in    std_logic := 'U';
          ABPS10         : in    std_logic := 'U';
          ABPS11         : in    std_logic := 'U';
          TM0            : in    std_logic := 'U';
          TM1            : in    std_logic := 'U';
          TM2            : in    std_logic := 'U';
          TM3            : in    std_logic := 'U';
          TM4            : in    std_logic := 'U';
          TM5            : in    std_logic := 'U';
          CM0            : in    std_logic := 'U';
          CM1            : in    std_logic := 'U';
          CM2            : in    std_logic := 'U';
          CM3            : in    std_logic := 'U';
          CM4            : in    std_logic := 'U';
          CM5            : in    std_logic := 'U';
          GNDTM0         : in    std_logic := 'U';
          GNDTM1         : in    std_logic := 'U';
          GNDTM2         : in    std_logic := 'U';
          VAREF0         : in    std_logic := 'U';
          VAREF1         : in    std_logic := 'U';
          VAREF2         : in    std_logic := 'U';
          VAREFOUT       : out   std_logic;
          GNDVAREF       : in    std_logic := 'U';
          PUn            : in    std_logic := 'U';
          MSSHADDR       : out   std_logic_vector(19 downto 0);
          MSSHWDATA      : out   std_logic_vector(31 downto 0);
          MSSHSIZE       : out   std_logic_vector(1 downto 0);
          MSSHRDATA      : in    std_logic_vector(31 downto 0) := (others => 'U');
          FABHADDR       : in    std_logic_vector(31 downto 0) := (others => 'U');
          FABHWDATA      : in    std_logic_vector(31 downto 0) := (others => 'U');
          FABHSIZE       : in    std_logic_vector(1 downto 0) := (others => 'U');
          FABHRDATA      : out   std_logic_vector(31 downto 0);
          DMAREADY       : in    std_logic_vector(1 downto 0) := (others => 'U');
          MSSINT         : out   std_logic_vector(7 downto 0);
          GPI            : in    std_logic_vector(31 downto 0) := (others => 'U');
          GPO            : out   std_logic_vector(31 downto 0);
          MACM2FTXD      : out   std_logic_vector(1 downto 0);
          MACF2MRXD      : in    std_logic_vector(1 downto 0) := (others => 'U');
          ACEFLAGS       : out   std_logic_vector(31 downto 0);
          UART0CTSn      : in    std_logic := 'U';
          UART0DSRn      : in    std_logic := 'U';
          UART0RTSn      : out   std_logic;
          UART0DTRn      : out   std_logic;
          UART0RIn       : in    std_logic := 'U';
          UART0DCDn      : in    std_logic := 'U';
          UART1CTSn      : in    std_logic := 'U';
          UART1DSRn      : in    std_logic := 'U';
          UART1RIn       : in    std_logic := 'U';
          UART1DCDn      : in    std_logic := 'U';
          I2C0SMBALERTNO : out   std_logic;
          I2C0BCLK       : in    std_logic := 'U';
          I2C0SMBALERTNI : in    std_logic := 'U';
          I2C0SMBUSNI    : in    std_logic := 'U';
          I2C1SMBALERTNO : out   std_logic;
          I2C1BCLK       : in    std_logic := 'U';
          I2C1SMBALERTNI : in    std_logic := 'U';
          I2C1SMBUSNI    : in    std_logic := 'U';
          UART1RTSn      : out   std_logic;
          UART1DTRn      : out   std_logic;
          TXEV           : out   std_logic;
          RXEV           : in    std_logic := 'U';
          VRON           : in    std_logic := 'U';
          MACM2FTXEN     : out   std_logic;
          MACF2MCRSDV    : in    std_logic := 'U';
          MACM2FMDEN     : out   std_logic;
          MACF2MRXER     : in    std_logic := 'U';
          MACM2FMDO      : out   std_logic;
          MACF2MMDI      : in    std_logic := 'U';
          MACM2FMDC      : out   std_logic;
          I2C0SMBUSNO    : out   std_logic;
          I2C1SMBUSNO    : out   std_logic;
          CALIBOUT       : out   std_logic;
          CALIBIN        : in    std_logic := 'U';
          LVTTL0         : out   std_logic;
          LVTTL1         : out   std_logic;
          LVTTL2         : out   std_logic;
          LVTTL0EN       : in    std_logic := 'U';
          LVTTL1EN       : in    std_logic := 'U';
          LVTTL2EN       : in    std_logic := 'U';
          LVTTL3         : out   std_logic;
          LVTTL4         : out   std_logic;
          LVTTL5         : out   std_logic;
          LVTTL3EN       : in    std_logic := 'U';
          LVTTL4EN       : in    std_logic := 'U';
          LVTTL5EN       : in    std_logic := 'U';
          LVTTL6         : out   std_logic;
          LVTTL7         : out   std_logic;
          LVTTL8         : out   std_logic;
          LVTTL6EN       : in    std_logic := 'U';
          LVTTL7EN       : in    std_logic := 'U';
          LVTTL8EN       : in    std_logic := 'U';
          LVTTL9         : out   std_logic;
          LVTTL10        : out   std_logic;
          LVTTL11        : out   std_logic;
          LVTTL9EN       : in    std_logic := 'U';
          LVTTL10EN      : in    std_logic := 'U';
          LVTTL11EN      : in    std_logic := 'U';
          CMP0           : out   std_logic;
          CMP1           : out   std_logic;
          CMP2           : out   std_logic;
          CMP3           : out   std_logic;
          CMP4           : out   std_logic;
          CMP5           : out   std_logic;
          FABSDD0D       : in    std_logic := 'U';
          FABSDD1D       : in    std_logic := 'U';
          FABSDD2D       : in    std_logic := 'U';
          CMP6           : out   std_logic;
          CMP7           : out   std_logic;
          CMP8           : out   std_logic;
          FABACETRIG     : in    std_logic := 'U';
          CMP9           : out   std_logic;
          FABSDD0CLK     : in    std_logic := 'U';
          FABSDD1CLK     : in    std_logic := 'U';
          FABSDD2CLK     : in    std_logic := 'U';
          VCC15GOOD      : out   std_logic;
          VCC33GOOD      : out   std_logic;
          PUFABn         : out   std_logic;
          DEEPSLEEP      : out   std_logic;
          SLEEP          : out   std_logic;
          M2FRESETn      : out   std_logic;
          WDINT          : out   std_logic;
          MSSHREADY      : in    std_logic := 'U';
          MSSHRESP       : in    std_logic := 'U';
          MSSHLOCK       : out   std_logic;
          FABHMASTLOCK   : in    std_logic := 'U';
          MSSHTRANS1     : out   std_logic;
          MSSHWRITE      : out   std_logic;
          FABINT         : in    std_logic := 'U';
          FABHTRANS1     : in    std_logic := 'U';
          FABHSEL        : in    std_logic := 'U';
          F2MRESETn      : in    std_logic := 'U';
          SYNCCLKFDBK    : in    std_logic := 'U';
          FABHREADYOUT   : out   std_logic;
          FABHRESP       : out   std_logic;
          FABHWRITE      : in    std_logic := 'U';
          FABHREADY      : in    std_logic := 'U';
          CMP10          : out   std_logic;
          CMP11          : out   std_logic
        );
  end component;

  component MSS_XTLOSC
    port( XTL    : in    std_logic := 'U';
          CLKOUT : out   std_logic
        );
  end component;

  component MSS_CCC_IF
    port( PIN2    : in    std_logic := 'U';
          PIN3    : in    std_logic := 'U';
          PIN4    : in    std_logic := 'U';
          PIN1    : out   std_logic;
          PIN2INT : out   std_logic;
          PIN3INT : out   std_logic;
          PIN4INT : out   std_logic;
          PIN1INT : in    std_logic := 'U'
        );
  end component;

  component GND
    port(Y : out std_logic); 
  end component;

  component VCC
    port(Y : out std_logic); 
  end component;

    signal fic_master_trans_0_HSEL, 
        \\\fic_master_trans_0_HWDATA_[0]\\\, 
        \\\fic_master_trans_0_HWDATA_[1]\\\, 
        \\\fic_master_trans_0_HWDATA_[2]\\\, 
        \\\fic_master_trans_0_HWDATA_[3]\\\, 
        \\\fic_master_trans_0_HWDATA_[4]\\\, 
        \\\fic_master_trans_0_HWDATA_[5]\\\, 
        \\\fic_master_trans_0_HWDATA_[6]\\\, 
        \\\fic_master_trans_0_HWDATA_[7]\\\, 
        \\\fic_master_trans_0_HADDR_[0]\\\, 
        \\\fic_master_trans_0_HADDR_[1]\\\, 
        \\\fic_master_trans_0_HADDR_[2]\\\, 
        \\\fic_master_trans_0_HADDR_[3]\\\, 
        \\\fic_master_trans_0_HADDR_[4]\\\, 
        \\\fic_master_trans_0_HADDR_[5]\\\, 
        \\\fic_master_trans_0_HADDR_[6]\\\, 
        \\\fic_master_trans_0_HADDR_[7]\\\, 
        \\\fic_master_trans_0_HADDR_[8]\\\, 
        \\\fic_master_trans_0_HADDR_[9]\\\, 
        \\\fic_master_trans_0_HADDR_[10]\\\, 
        \\\fic_master_trans_0_HADDR_[11]\\\, 
        \\\fic_master_trans_0_HADDR_[12]\\\, 
        \\\fic_master_trans_0_HADDR_[13]\\\, 
        \\\fic_master_trans_0_HADDR_[14]\\\, 
        \\\fic_master_trans_0_HADDR_[15]\\\, 
        \\\fic_master_trans_0_HADDR_[16]\\\, 
        \\\fic_master_trans_0_HADDR_[17]\\\, 
        \\\fic_master_trans_0_HADDR_[18]\\\, 
        \\\fic_master_trans_0_HADDR_[19]\\\, 
        \\\fic_master_trans_0_HADDR_[20]\\\, 
        \\\fic_master_trans_0_HADDR_[21]\\\, 
        \\\fic_master_trans_0_HADDR_[22]\\\, 
        \\\fic_master_trans_0_HADDR_[23]\\\, 
        \\\fic_master_trans_0_HADDR_[24]\\\, 
        \\\fic_master_trans_0_HADDR_[25]\\\, 
        \\\fic_master_trans_0_HADDR_[26]\\\, 
        \\\fic_master_trans_0_HADDR_[27]\\\, 
        \\\fic_master_trans_0_HADDR_[28]\\\, 
        \\\fic_master_trans_0_HADDR_[29]\\\, 
        \\\fic_master_trans_0_HADDR_[30]\\\, 
        \\\fic_master_trans_0_HADDR_[31]\\\, \FAB_CLK\, 
        FABHREADYOUT_c, \mss_top_0/MSS_EMI_0_CLK_D\, 
        \mss_top_0/MSS_SPI_1_DI_Y\, \mss_top_0/MSS_EMI_0_DB_7_Y\, 
        \mss_top_0/MSS_EMI_0_DB_7_D\, 
        \mss_top_0/MSS_EMI_0_DB_15_E\, 
        \mss_top_0/MSS_EMI_0_AB_5_D\, 
        \mss_top_0/MSS_EMI_0_RW_N_D\, 
        \mss_top_0/MSS_EMI_0_CS0_N_D\, 
        \mss_top_0/MSS_UART_0_TXD_D\, 
        \mss_top_0/MSS_MAC_0_RXD_0_Y\, 
        \mss_top_0/MSS_EMI_0_DB_13_Y\, 
        \mss_top_0/MSS_EMI_0_DB_13_D\, 
        \mss_top_0/MSS_EMI_0_AB_9_D\, 
        \mss_top_0/MSS_UART_0_RXD_Y\, 
        \mss_top_0/MSS_EMI_0_DB_4_Y\, 
        \mss_top_0/MSS_EMI_0_DB_4_D\, \mss_top_0/MSS_I2C_0_SCL_Y\, 
        \mss_top_0/MSS_I2C_0_SCL_E\, \mss_top_0/MSS_MAC_0_MDIO_Y\, 
        \mss_top_0/MSS_MAC_0_MDIO_D\, 
        \mss_top_0/MSS_MAC_0_MDIO_E\, \mss_top_0/MSS_SPI_1_SS_Y\, 
        \mss_top_0/MSS_SPI_1_SS_D\, \mss_top_0/MSS_SPI_1_SS_E\, 
        \mss_top_0/MSSINT_GPO_0_A\, \mss_top_0/MSS_EMI_0_DB_5_Y\, 
        \mss_top_0/MSS_EMI_0_DB_5_D\, 
        \mss_top_0/MSS_MAC_0_CRSDV_Y\, 
        \mss_top_0/MSS_EMI_0_AB_18_D\, 
        \mss_top_0/MSS_EMI_0_BYTEN_1_D\, 
        \mss_top_0/MSS_EMI_0_DB_9_Y\, 
        \mss_top_0/MSS_EMI_0_DB_9_D\, 
        \mss_top_0/MSS_EMI_0_AB_11_D\, \mss_top_0/MSS_SPI_1_DO_D\, 
        \mss_top_0/MSS_SPI_1_DO_E\, \mss_top_0/MSS_EMI_0_AB_10_D\, 
        \mss_top_0/MSS_MAC_0_TXD_0_D\, 
        \mss_top_0/MSS_EMI_0_DB_14_Y\, 
        \mss_top_0/MSS_EMI_0_DB_14_D\, 
        \mss_top_0/MSS_EMI_0_DB_15_Y\, 
        \mss_top_0/MSS_EMI_0_DB_15_D\, 
        \mss_top_0/MSS_EMI_0_AB_0_D\, 
        \mss_top_0/MSS_EMI_0_AB_1_D\, 
        \mss_top_0/MSS_UART_1_TXD_D\, 
        \mss_top_0/MSS_EMI_0_AB_2_D\, 
        \mss_top_0/MSS_EMI_0_AB_3_D\, 
        \mss_top_0/MSS_EMI_0_AB_4_D\, 
        \mss_top_0/MSS_EMI_0_AB_6_D\, 
        \mss_top_0/MSS_EMI_0_AB_7_D\, 
        \mss_top_0/MSS_EMI_0_AB_8_D\, 
        \mss_top_0/MSS_EMI_0_AB_12_D\, 
        \mss_top_0/MSS_EMI_0_AB_13_D\, 
        \mss_top_0/MSS_EMI_0_AB_14_D\, 
        \mss_top_0/MSS_EMI_0_AB_15_D\, 
        \mss_top_0/MSS_EMI_0_AB_16_D\, 
        \mss_top_0/MSS_EMI_0_AB_17_D\, 
        \mss_top_0/MSS_EMI_0_AB_19_D\, 
        \mss_top_0/MSS_EMI_0_AB_20_D\, 
        \mss_top_0/MSS_EMI_0_AB_21_D\, 
        \mss_top_0/MSS_EMI_0_AB_22_D\, 
        \mss_top_0/MSS_EMI_0_AB_23_D\, 
        \mss_top_0/MSS_EMI_0_AB_24_D\, 
        \mss_top_0/MSS_EMI_0_AB_25_D\, 
        \mss_top_0/MSS_EMI_0_BYTEN_0_D\, 
        \mss_top_0/MSS_EMI_0_CS1_N_D\, 
        \mss_top_0/MSS_EMI_0_OEN0_N_D\, 
        \mss_top_0/MSS_EMI_0_OEN1_N_D\, 
        \mss_top_0/MSS_EMI_0_DB_0_Y\, 
        \mss_top_0/MSS_EMI_0_DB_1_Y\, 
        \mss_top_0/MSS_EMI_0_DB_2_Y\, 
        \mss_top_0/MSS_EMI_0_DB_3_Y\, 
        \mss_top_0/MSS_EMI_0_DB_6_Y\, 
        \mss_top_0/MSS_EMI_0_DB_8_Y\, 
        \mss_top_0/MSS_EMI_0_DB_10_Y\, 
        \mss_top_0/MSS_EMI_0_DB_11_Y\, 
        \mss_top_0/MSS_EMI_0_DB_12_Y\, 
        \mss_top_0/MSS_EMI_0_DB_0_D\, 
        \mss_top_0/MSS_EMI_0_DB_1_D\, 
        \mss_top_0/MSS_EMI_0_DB_2_D\, 
        \mss_top_0/MSS_EMI_0_DB_3_D\, 
        \mss_top_0/MSS_EMI_0_DB_6_D\, 
        \mss_top_0/MSS_EMI_0_DB_8_D\, 
        \mss_top_0/MSS_EMI_0_DB_10_D\, 
        \mss_top_0/MSS_EMI_0_DB_11_D\, 
        \mss_top_0/MSS_EMI_0_DB_12_D\, 
        \mss_top_0/MSS_ADLIB_INST_FCLK\, 
        \mss_top_0/MSS_I2C_0_SDA_Y\, \mss_top_0/MSS_I2C_0_SDA_E\, 
        \mss_top_0/MSS_I2C_1_SCL_Y\, \mss_top_0/MSS_I2C_1_SCL_E\, 
        \mss_top_0/MSS_I2C_1_SDA_Y\, \mss_top_0/MSS_I2C_1_SDA_E\, 
        \mss_top_0/MSS_ADLIB_INST_MACCLKCCC\, 
        \mss_top_0/MSS_MAC_0_MDC_D\, 
        \mss_top_0/MSS_MAC_0_RXD_1_Y\, 
        \mss_top_0/MSS_MAC_0_RXER_Y\, 
        \mss_top_0/MSS_MAC_0_TXD_1_D\, 
        \mss_top_0/MSS_MAC_0_TXEN_D\, GLMUXINT_GND, 
        \mss_top_0/MSS_RESET_0_MSS_RESET_N_Y\, 
        \mss_top_0/MSS_ADLIB_INST_PLLLOCK\, 
        \mss_top_0/MSS_SPI_0_CLK_Y\, \mss_top_0/MSS_SPI_0_CLK_D\, 
        \mss_top_0/MSS_SPI_0_DI_Y\, \mss_top_0/MSS_SPI_0_DO_D\, 
        \mss_top_0/MSS_SPI_0_DO_E\, \mss_top_0/MSS_SPI_0_SS_E\, 
        \mss_top_0/MSS_SPI_0_SS_Y\, \mss_top_0/MSS_SPI_0_SS_D\, 
        \mss_top_0/MSS_SPI_1_CLK_Y\, \mss_top_0/MSS_SPI_1_CLK_D\, 
        \mss_top_0/MSS_UART_1_RXD_Y\, 
        \mss_top_0/MSS_CCC_0/N_CLKA_XTLOSC\, 
        \fic_master_trans_0/un2_hreadyout_0[0]\, 
        \fic_master_trans_0/un1_hreadyout\, 
        \fic_master_trans_0/un9_hreadyout\, 
        \fic_master_trans_0/ahb_states[0]_net_1\, 
        \fic_master_trans_0/DWACT_FINC_E[0]\, 
        \fic_master_trans_0/DWACT_FINC_E[4]\, 
        \fic_master_trans_0/DWACT_FINC_E[7]\, 
        \fic_master_trans_0/DWACT_FINC_E[6]\, 
        \fic_master_trans_0/un6_hreadyout_2\, 
        \fic_master_trans_0/un6_hreadyout_0_0\, 
        \fic_master_trans_0/un12_hreadyout\, 
        \fic_master_trans_0/un6_hreadyout_0\, 
        \fic_master_trans_0/un6_hreadyout_5\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP_c1\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP_n7\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP_c5\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP_n6\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP_n5\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP_c4\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP_n4\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP_n3\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP_n2\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP_RNO[0]_net_1\, 
        \fic_master_trans_0/HWRITE_DATA_TEMPe\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP_n1\, 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, 
        \fic_master_trans_0/HADDR_TEMP_0_sqmuxa\, 
        \fic_master_trans_0/I_4\, \fic_master_trans_0/I_5\, 
        \fic_master_trans_0/I_9\, \fic_master_trans_0/I_13\, 
        \fic_master_trans_0/I_20\, \fic_master_trans_0/I_24\, 
        \fic_master_trans_0/I_31\, \fic_master_trans_0/I_38\, 
        \fic_master_trans_0/I_45\, \fic_master_trans_0/I_52\, 
        \fic_master_trans_0/I_56\, \fic_master_trans_0/I_66\, 
        \fic_master_trans_0/I_73\, \fic_master_trans_0/I_77\, 
        \fic_master_trans_0/I_84\, \fic_master_trans_0/I_91\, 
        \fic_master_trans_0/I_98\, \fic_master_trans_0/I_105\, 
        \fic_master_trans_0/I_115\, \fic_master_trans_0/I_122\, 
        \fic_master_trans_0/I_129\, \fic_master_trans_0/I_136\, 
        \fic_master_trans_0/I_143\, \fic_master_trans_0/I_156\, 
        \fic_master_trans_0/I_166\, \fic_master_trans_0/I_173\, 
        \fic_master_trans_0/I_186\, \fic_master_trans_0/I_196\, 
        \fic_master_trans_0/I_203\, \fic_master_trans_0/I_210\, 
        \fic_master_trans_0/N_4\, 
        \fic_master_trans_0/DWACT_FINC_E[24]\, 
        \fic_master_trans_0/DWACT_FINC_E[23]\, 
        \fic_master_trans_0/DWACT_FINC_E[25]\, 
        \fic_master_trans_0/N_9\, 
        \fic_master_trans_0/DWACT_FINC_E[29]\, 
        \fic_master_trans_0/DWACT_FINC_E[30]\, 
        \fic_master_trans_0/N_14\, 
        \fic_master_trans_0/DWACT_FINC_E[15]\, 
        \fic_master_trans_0/DWACT_FINC_E[17]\, 
        \fic_master_trans_0/DWACT_FINC_E[22]\, 
        \fic_master_trans_0/N_21\, 
        \fic_master_trans_0/DWACT_FINC_E[21]\, 
        \fic_master_trans_0/DWACT_FINC_E[9]\, 
        \fic_master_trans_0/DWACT_FINC_E[12]\, 
        \fic_master_trans_0/DWACT_FINC_E[20]\, 
        \fic_master_trans_0/N_30\, 
        \fic_master_trans_0/DWACT_FINC_E[13]\, 
        \fic_master_trans_0/DWACT_FINC_E[19]\, 
        \fic_master_trans_0/N_35\, 
        \fic_master_trans_0/DWACT_FINC_E[18]\, 
        \fic_master_trans_0/N_42\, 
        \fic_master_trans_0/DWACT_FINC_E[33]\, 
        \fic_master_trans_0/DWACT_FINC_E[34]\, 
        \fic_master_trans_0/DWACT_FINC_E[2]\, 
        \fic_master_trans_0/DWACT_FINC_E[5]\, 
        \fic_master_trans_0/N_51\, 
        \fic_master_trans_0/DWACT_FINC_E[28]\, 
        \fic_master_trans_0/DWACT_FINC_E[16]\, 
        \fic_master_trans_0/N_56\, \fic_master_trans_0/N_61\, 
        \fic_master_trans_0/DWACT_FINC_E[14]\, 
        \fic_master_trans_0/N_66\, \fic_master_trans_0/N_71\, 
        \fic_master_trans_0/DWACT_FINC_E[10]\, 
        \fic_master_trans_0/N_78\, 
        \fic_master_trans_0/DWACT_FINC_E[11]\, 
        \fic_master_trans_0/N_83\, \fic_master_trans_0/N_88\, 
        \fic_master_trans_0/N_93\, 
        \fic_master_trans_0/DWACT_FINC_E[8]\, 
        \fic_master_trans_0/N_98\, \fic_master_trans_0/N_106\, 
        \fic_master_trans_0/N_113\, 
        \fic_master_trans_0/DWACT_FINC_E[3]\, 
        \fic_master_trans_0/N_121\, \fic_master_trans_0/N_126\, 
        \fic_master_trans_0/N_131\, 
        \fic_master_trans_0/DWACT_FINC_E[1]\, 
        \fic_master_trans_0/N_136\, \fic_master_trans_0/N_144\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[16]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[17]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[18]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[16]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[17]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[18]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[19]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[20]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[21]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[19]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[20]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[21]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[22]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[23]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[24]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[22]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[23]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[24]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[25]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[26]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[27]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[25]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[26]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[27]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[28]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[29]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[30]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[28]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[29]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[30]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[31]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/SPI0SSO[1]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/SPI0SSO[2]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[31]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/UART0CTSnINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/UART0DSRnINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/SPI0SSO[3]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/UART0RTSnINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/UART0DTRnINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/UART0RInINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/UART0DCDnINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/UART1CTSnINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/SPI1SSO[1]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/SPI1SSO[2]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/SPI1SSO[3]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/UART1DSRnINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/UART1RInINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/UART1DCDnINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/GPI[0]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/SPI1SSO[4]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/SPI1SSO[5]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/I2C0SMBALERTNOINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/I2C0BCLKINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/I2C0SMBALERTNIINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/I2C0SMBUSNIINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/SPI1SSO[6]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/SPI1SSO[7]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/I2C1SMBALERTNOINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/I2C1BCLKINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/I2C1SMBALERTNIINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/I2C1SMBUSNIINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/UART1RTSnINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/UART1DTRnINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/TXEVINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/RXEVINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/VRONINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/CALIBININT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/I2C0SMBUSNOINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/I2C1SMBUSNOINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/CALIBOUTINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[0]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[1]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[2]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[0]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[1]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[2]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[3]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[4]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[5]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[3]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[4]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[5]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[6]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[7]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[8]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[6]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[7]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[8]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[9]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[10]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[11]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[9]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[10]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[11]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[12]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[13]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[14]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[12]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[13]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[14]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[15]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[16]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[17]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[15]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[16]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[17]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[18]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[19]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[0]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[0]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[1]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[2]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[3]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[1]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[2]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[3]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[4]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[5]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[6]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[4]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[5]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[6]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[7]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[8]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[9]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[7]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[8]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[9]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[10]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[11]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[12]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[10]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[11]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[12]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[13]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[14]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[15]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[13]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[14]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[15]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/DEEPSLEEPINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[18]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[19]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[20]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/SLEEPINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSINT[0]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSINT[1]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[21]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[22]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[23]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSINT[2]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSINT[3]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSINT[4]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[24]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[25]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[26]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSINT[5]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/M2FRESETnINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSINT[6]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[27]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[28]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[29]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[0]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSINT[7]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/WDINTINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[30]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[31]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[0]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[1]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[2]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[3]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[1]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[2]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[3]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[4]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[5]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[6]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[4]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[5]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[6]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[7]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[8]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[9]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[7]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[8]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[9]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[10]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[11]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[12]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[10]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[11]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[12]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[13]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[14]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[15]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[13]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[14]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[15]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[16]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[17]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[18]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[16]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[17]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[18]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[19]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[20]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[21]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[19]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[20]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[21]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[22]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[23]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[24]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[22]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[23]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[24]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[25]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[26]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[27]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[25]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[26]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[27]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[28]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[29]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[30]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[28]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[29]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[30]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[31]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[31]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHREADYINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHRESPINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHLOCKINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHSIZE[0]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHSIZE[1]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHMASTLOCKINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHSIZE[0]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHSIZE[1]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHTRANS1INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/MSSHWRITEINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABINTINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHTRANS1INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHSELINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/F2MRESETnINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/DMAREADY[0]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/DMAREADY[1]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[16]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[17]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[18]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[16]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[17]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[18]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[19]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[20]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[21]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[19]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[20]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[21]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[22]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[23]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[24]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[22]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[23]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[24]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[25]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[26]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[27]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[25]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[26]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[27]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[28]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[29]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[30]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[28]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[29]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[30]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[31]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/SYNCCLKFDBKINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[31]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHRESPINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHWRITEINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABHREADYINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL0INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL1INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL2INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL0ENINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL1ENINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL2ENINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL3INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL4INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL5INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL3ENINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL4ENINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL5ENINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL6INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL7INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL6ENINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/LVTTL7ENINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/CMP0INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/CMP1INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/CMP2INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/CMP3INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/CMP4INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/CMP5INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABSDD0DINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABSDD1DINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/CMP6INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/CMP7INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABACETRIGINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABSDD0CLKINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/FABSDD1CLKINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[0]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[1]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[2]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[3]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[4]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[5]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[6]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[7]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[8]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[9]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[10]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[11]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[12]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[13]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[14]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[15]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[16]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[17]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[18]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[19]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[20]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[21]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[22]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[23]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[24]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[25]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[26]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[27]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[28]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[29]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[30]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[31]INT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/VCC15GOODINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/VCC33GOODINT_NET\, 
        \mss_top_0/MSS_ADLIB_INST/PUFABnINT_NET\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/SDIN_INT\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/SCLK_INT\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/SSHIFT_INT\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/SDOUT_INT\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/EXTFB_INT\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/LOCK_INT\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/CLKB_INT\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/YB_INT\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/MODE_INT\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/CLKC_INT\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/SUPDATE_INT\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT\, 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/YC_INT\, PLLEN_VCC, 
        \M2F_GPO_0_pad/U0/NET1\, \M2F_GPO_0_pad/U0/NET2\, 
        \FAB_CLK_pad/U0/NET1\, \FAB_CLK_pad/U0/NET2\, 
        \FABHREADYOUT_pad/U0/NET1\, \FABHREADYOUT_pad/U0/NET2\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP[4]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[24]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[28]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[10]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[13]/Y\, 
        \fic_master_trans_0/HSEL/Y\, 
        \fic_master_trans_0/HADDR_TEMP[25]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[2]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[4]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[17]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[26]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[12]/Y\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP[1]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[19]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[3]/Y\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP[7]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[14]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[18]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[15]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[5]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[21]/Y\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP[3]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[16]/Y\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP[6]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[20]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[23]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[8]/Y\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP[2]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[7]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[31]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[9]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[6]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[27]/Y\, 
        \fic_master_trans_0/HWRITE_DATA_TEMP[5]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[22]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[29]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[11]/Y\, 
        \fic_master_trans_0/HADDR_TEMP[30]/Y\, AFLSDF_VCC, 
        AFLSDF_GND : std_logic;
    signal GND_power_net1 : std_logic;
    signal VCC_power_net1 : std_logic;
    signal nc47, nc34, nc9, nc13, nc23, nc33, nc16, nc26, nc45, 
        nc27, nc17, nc36, nc48, nc37, nc5, nc52, nc51, nc4, nc42, 
        nc41, nc25, nc15, nc35, nc49, nc28, nc18, nc38, nc1, nc2, 
        nc50, nc22, nc12, nc21, nc11, nc3, nc32, nc40, nc31, nc44, 
        nc7, nc6, nc19, nc29, nc53, nc39, nc8, nc43, nc20, nc10, 
        nc24, nc14, nc46, nc30 : std_logic;

begin 

    GLMUXINT_GND <= GND_power_net1;
    AFLSDF_GND <= GND_power_net1;
    PLLEN_VCC <= VCC_power_net1;
    AFLSDF_VCC <= VCC_power_net1;

    \fic_master_trans_0/un2_haddr_temp_I_156\ : XOR2
      port map(A => \fic_master_trans_0/N_42\, B => 
        \\\fic_master_trans_0_HADDR_[25]\\\, Y => 
        \fic_master_trans_0/I_156\);
    
    \mss_top_0/MSS_EMI_0_CLK\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_CLK_D\, E => PLLEN_VCC, 
        PAD => EMC_CLK);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNI6U7G[5]\ : OR3C
      port map(A => \\\fic_master_trans_0_HWDATA_[5]\\\, B => 
        \\\fic_master_trans_0_HWDATA_[6]\\\, C => 
        \fic_master_trans_0/un6_hreadyout_0_0\, Y => 
        \fic_master_trans_0/un6_hreadyout_0\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNI3V38[7]\ : NOR2B
      port map(A => \\\fic_master_trans_0_HWDATA_[7]\\\, B => 
        \\\fic_master_trans_0_HWDATA_[4]\\\, Y => 
        \fic_master_trans_0/un6_hreadyout_0_0\);
    
    \mss_top_0/MSS_ADLIB_INST/U_95\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/I2C1SMBALERTNIINT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/I2C1BCLKINT_NET\, PIN6INT
         => \mss_top_0/MSS_ADLIB_INST/I2C1SMBUSNIINT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/SPI1SSO[6]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/SPI1SSO[7]INT_NET\, 
        PIN3INT => 
        \mss_top_0/MSS_ADLIB_INST/I2C1SMBALERTNOINT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_132\ : AND3
      port map(A => \\\fic_master_trans_0_HADDR_[20]\\\, B => 
        \\\fic_master_trans_0_HADDR_[21]\\\, C => 
        \\\fic_master_trans_0_HADDR_[22]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[15]\);
    
    \mss_top_0/MSS_ADLIB_INST/U_47\ : MSS_IF
      port map(PIN4 => \\\fic_master_trans_0_HADDR_[31]\\\, PIN5
         => \\\fic_master_trans_0_HADDR_[30]\\\, PIN6 => 
        \\\fic_master_trans_0_HWDATA_[0]\\\, PIN1 => OPEN, PIN2
         => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[31]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHADDR[30]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHWDATA[0]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[0]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/MSSINT[7]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/WDINTINT_NET\);
    
    \fic_master_trans_0/HADDR_TEMP[29]/U1\ : DFN1P0
      port map(D => \fic_master_trans_0/HADDR_TEMP[29]/Y\, CLK
         => \FAB_CLK\, PRE => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[29]\\\);
    
    \mss_top_0/MSS_ADLIB_INST/U_48\ : MSS_IF
      port map(PIN4 => \\\fic_master_trans_0_HWDATA_[2]\\\, PIN5
         => \\\fic_master_trans_0_HWDATA_[1]\\\, PIN6 => 
        \\\fic_master_trans_0_HWDATA_[3]\\\, PIN1 => OPEN, PIN2
         => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[2]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHWDATA[1]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHWDATA[3]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[1]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[2]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[3]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_196\ : XOR2
      port map(A => \fic_master_trans_0/N_14\, B => 
        \\\fic_master_trans_0_HADDR_[29]\\\, Y => 
        \fic_master_trans_0/I_196\);
    
    \fic_master_trans_0/un2_haddr_temp_I_114\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[28]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[10]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[12]\, Y => 
        \fic_master_trans_0/N_71\);
    
    \fic_master_trans_0/HADDR_TEMP[1]\ : DFN1C0
      port map(D => \\\fic_master_trans_0_HADDR_[1]\\\, CLK => 
        \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[1]\\\);
    
    \fic_master_trans_0/HADDR_TEMP[19]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[19]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[19]\\\);
    
    \fic_master_trans_0/HADDR_TEMP[24]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[24]\\\, B => 
        \fic_master_trans_0/I_143\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[24]/Y\);
    
    \mss_top_0/MSS_ADLIB_INST/U_84\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[26]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[27]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[28]INT_NET\);
    
    \mss_top_0/MSS_ADLIB_INST/U_46\ : MSS_IF
      port map(PIN4 => \\\fic_master_trans_0_HADDR_[28]\\\, PIN5
         => \\\fic_master_trans_0_HADDR_[27]\\\, PIN6 => 
        \\\fic_master_trans_0_HADDR_[29]\\\, PIN1 => OPEN, PIN2
         => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[28]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHADDR[27]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHADDR[29]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/MSSINT[5]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/M2FRESETnINT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/MSSINT[6]INT_NET\);
    
    \mss_top_0/MSS_ADLIB_INST/U_77\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[5]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[6]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[7]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_176\ : AND2
      port map(A => \\\fic_master_trans_0_HADDR_[26]\\\, B => 
        \\\fic_master_trans_0_HADDR_[27]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[20]\);
    
    \mss_top_0/MSS_ADLIB_INST/U_43\ : MSS_IF
      port map(PIN4 => \\\fic_master_trans_0_HADDR_[19]\\\, PIN5
         => \\\fic_master_trans_0_HADDR_[18]\\\, PIN6 => 
        \\\fic_master_trans_0_HADDR_[20]\\\, PIN1 => OPEN, PIN2
         => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[19]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHADDR[18]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHADDR[20]INT_NET\, 
        PIN1INT => GLMUXINT_GND, PIN2INT => GLMUXINT_GND, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/DEEPSLEEPINT_NET\);
    
    \fic_master_trans_0/HADDR_TEMP[27]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[27]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[27]\\\);
    
    \fic_master_trans_0/HADDR_TEMP[14]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[14]\\\, B => 
        \fic_master_trans_0/I_73\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[14]/Y\);
    
    \mss_top_0/MSS_ADLIB_INST/U_78\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[8]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[9]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[10]INT_NET\);
    
    \mss_top_0/MSS_ADLIB_INST/U_2\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[17]INT_NET\, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[16]INT_NET\, PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[18]INT_NET\, PIN1INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[16]INT_NET\, PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[17]INT_NET\, PIN3INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[18]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_185\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[29]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[30]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[21]\, Y => 
        \fic_master_trans_0/N_21\);
    
    \fic_master_trans_0/HADDR_TEMP[17]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[17]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[17]\\\);
    
    \mss_top_0/MSS_ADLIB_INST/U_67\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => GLMUXINT_GND, PIN2INT => GLMUXINT_GND, PIN3INT
         => GLMUXINT_GND);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNO[3]\ : AX1C
      port map(A => \\\fic_master_trans_0_HWDATA_[2]\\\, B => 
        \fic_master_trans_0/HWRITE_DATA_TEMP_c1\, C => 
        \\\fic_master_trans_0_HWDATA_[3]\\\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP_n3\);
    
    \fic_master_trans_0/HADDR_TEMP[27]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[27]\\\, B => 
        \fic_master_trans_0/I_173\, S => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, Y => 
        \fic_master_trans_0/HADDR_TEMP[27]/Y\);
    
    \mss_top_0/MSS_MAC_0_TXD_1\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_MAC_0_TXD_1_D\, E => PLLEN_VCC, 
        PAD => MAC_TXD(1));
    
    \mss_top_0/MSS_EMI_0_AB_6\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_6_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(6));
    
    \mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE3\ : MSS_CCC_GL_IF
      port map(PIN2 => GLMUXINT_GND, PIN3 => GLMUXINT_GND, PIN4
         => GLMUXINT_GND, PIN1 => OPEN, PIN5 => OPEN, PIN2INT => 
        OPEN, PIN3INT => \mss_top_0/MSS_CCC_0/I_MSSCCC/CLKC_INT\, 
        PIN4INT => \mss_top_0/MSS_CCC_0/I_MSSCCC/SUPDATE_INT\, 
        PIN1INT => \mss_top_0/MSS_CCC_0/I_MSSCCC/YC_INT\, PIN5INT
         => \mss_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT\);
    
    \mss_top_0/MSS_EMI_0_DB_8\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_8_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_8_Y\, PAD => EMC_DB(8));
    
    \mss_top_0/MSS_EMI_0_AB_2\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_2_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(2));
    
    \mss_top_0/MSS_ADLIB_INST/U_76\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[2]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[3]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[4]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_84\ : XOR2
      port map(A => \fic_master_trans_0/N_93\, B => 
        \\\fic_master_trans_0_HADDR_[16]\\\, Y => 
        \fic_master_trans_0/I_84\);
    
    \mss_top_0/MSS_EMI_0_AB_21\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_21_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(21));
    
    \fic_master_trans_0/un2_haddr_temp_I_66\ : XOR2
      port map(A => \fic_master_trans_0/N_106\, B => 
        \\\fic_master_trans_0_HADDR_[13]\\\, Y => 
        \fic_master_trans_0/I_66\);
    
    \fic_master_trans_0/HADDR_TEMP[17]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[17]\\\, B => 
        \fic_master_trans_0/I_91\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[17]/Y\);
    
    \mss_top_0/MSS_ADLIB_INST/U_73\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/FABACETRIGINT_NET\, PIN6INT => 
        OPEN, PIN1INT => \mss_top_0/MSS_ADLIB_INST/CMP6INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/CMP7INT_NET\, 
        PIN3INT => GLMUXINT_GND);
    
    \mss_top_0/MSS_ADLIB_INST/U_45\ : MSS_IF
      port map(PIN4 => \\\fic_master_trans_0_HADDR_[25]\\\, PIN5
         => \\\fic_master_trans_0_HADDR_[24]\\\, PIN6 => 
        \\\fic_master_trans_0_HADDR_[26]\\\, PIN1 => OPEN, PIN2
         => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[25]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHADDR[24]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHADDR[26]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/MSSINT[2]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/MSSINT[3]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/MSSINT[4]INT_NET\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[3]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HWRITE_DATA_TEMP[3]/Y\, 
        CLK => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q
         => \\\fic_master_trans_0_HWDATA_[3]\\\);
    
    \mss_top_0/MSS_ADLIB_INST/U_66\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL7ENINT_NET\, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL6ENINT_NET\, PIN6INT => 
        OPEN, PIN1INT => \mss_top_0/MSS_ADLIB_INST/LVTTL6INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/LVTTL7INT_NET\, 
        PIN3INT => GLMUXINT_GND);
    
    \mss_top_0/MSS_ADLIB_INST/U_63\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/VCC15GOODINT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/VCC33GOODINT_NET\, 
        PIN3INT => GLMUXINT_GND);
    
    \fic_master_trans_0/un2_haddr_temp_I_20\ : AX1C
      port map(A => \\\fic_master_trans_0_HADDR_[5]\\\, B => 
        \fic_master_trans_0/DWACT_FINC_E[0]\, C => 
        \\\fic_master_trans_0_HADDR_[6]\\\, Y => 
        \fic_master_trans_0/I_20\);
    
    \fic_master_trans_0/HADDR_TEMP[23]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[23]\\\, B => 
        \fic_master_trans_0/I_136\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[23]/Y\);
    
    \fic_master_trans_0/un2_haddr_temp_I_27\ : AND2
      port map(A => \\\fic_master_trans_0_HADDR_[5]\\\, B => 
        \\\fic_master_trans_0_HADDR_[6]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[1]\);
    
    \fic_master_trans_0/un2_haddr_temp_I_149\ : AND3
      port map(A => \\\fic_master_trans_0_HADDR_[2]\\\, B => 
        \\\fic_master_trans_0_HADDR_[3]\\\, C => 
        \\\fic_master_trans_0_HADDR_[4]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[34]\);
    
    \mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1\ : MSS_CCC_GL_IF
      port map(PIN2 => GLMUXINT_GND, PIN3 => GLMUXINT_GND, PIN4
         => GLMUXINT_GND, PIN1 => OPEN, PIN5 => \FAB_CLK\, 
        PIN2INT => \mss_top_0/MSS_CCC_0/I_MSSCCC/EXTFB_INT\, 
        PIN3INT => OPEN, PIN4INT => OPEN, PIN1INT => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/LOCK_INT\, PIN5INT => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT\);
    
    \mss_top_0/MSS_SPI_1_DO\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_SPI_1_DO_D\, E => 
        \mss_top_0/MSS_SPI_1_DO_E\, PAD => SPI_1_DO);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNIGICS[1]\ : OR3B
      port map(A => \\\fic_master_trans_0_HWDATA_[1]\\\, B => 
        \fic_master_trans_0/un6_hreadyout_2\, C => 
        \fic_master_trans_0/un6_hreadyout_0\, Y => 
        \fic_master_trans_0/un12_hreadyout\);
    
    \fic_master_trans_0/HADDR_TEMP[4]/U1\ : DFN1P0
      port map(D => \fic_master_trans_0/HADDR_TEMP[4]/Y\, CLK => 
        \FAB_CLK\, PRE => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[4]\\\);
    
    \fic_master_trans_0/un2_haddr_temp_I_76\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[6]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[7]\, C => 
        \\\fic_master_trans_0_HADDR_[14]\\\, Y => 
        \fic_master_trans_0/N_98\);
    
    \fic_master_trans_0/un2_haddr_temp_I_169\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[15]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[17]\, C => 
        \\\fic_master_trans_0_HADDR_[26]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[19]\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNO[6]\ : XOR2
      port map(A => \fic_master_trans_0/HWRITE_DATA_TEMP_c5\, B
         => \\\fic_master_trans_0_HWDATA_[6]\\\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP_n6\);
    
    \fic_master_trans_0/HADDR_TEMP[13]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[13]\\\, B => 
        \fic_master_trans_0/I_66\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[13]/Y\);
    
    \fic_master_trans_0/un2_haddr_temp_I_48\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[0]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[2]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[3]\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[4]\);
    
    \fic_master_trans_0/un2_haddr_temp_I_118\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[7]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[9]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[12]\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[13]\);
    
    \mss_top_0/MSS_ADLIB_INST/U_75\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => GLMUXINT_GND, PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[0]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[1]INT_NET\);
    
    \M2F_GPO_0_pad/U0/U0\ : IOPAD_TRI
      port map(D => \M2F_GPO_0_pad/U0/NET1\, E => 
        \M2F_GPO_0_pad/U0/NET2\, PAD => M2F_GPO_0);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[5]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HWRITE_DATA_TEMP[5]/Y\, 
        CLK => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q
         => \\\fic_master_trans_0_HWDATA_[5]\\\);
    
    \fic_master_trans_0/HADDR_TEMP[7]/U1\ : DFN1P0
      port map(D => \fic_master_trans_0/HADDR_TEMP[7]/Y\, CLK => 
        \FAB_CLK\, PRE => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[7]\\\);
    
    \fic_master_trans_0/un2_haddr_temp_I_12\ : AND3
      port map(A => \\\fic_master_trans_0_HADDR_[2]\\\, B => 
        \\\fic_master_trans_0_HADDR_[3]\\\, C => 
        \\\fic_master_trans_0_HADDR_[4]\\\, Y => 
        \fic_master_trans_0/N_144\);
    
    \mss_top_0/MSS_ADLIB_INST/U_3\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[20]INT_NET\, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[19]INT_NET\, PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[21]INT_NET\, PIN1INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[19]INT_NET\, PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[20]INT_NET\, PIN3INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[21]INT_NET\);
    
    \fic_master_trans_0/HADDR_TEMP[28]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[28]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[28]\\\);
    
    \mss_top_0/MSS_EMI_0_AB_16\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_16_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(16));
    
    \mss_top_0/MSS_ADLIB_INST/U_20\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => \mss_top_0/MSSINT_GPO_0_A\, 
        PIN2 => OPEN, PIN3 => OPEN, PIN4INT => OPEN, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[0]INT_NET\, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET\, 
        PIN2INT => GLMUXINT_GND, PIN3INT => GLMUXINT_GND);
    
    \mss_top_0/MSS_ADLIB_INST/U_82\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[20]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[21]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[22]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_65\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[6]\, B => 
        \\\fic_master_trans_0_HADDR_[11]\\\, C => 
        \\\fic_master_trans_0_HADDR_[12]\\\, Y => 
        \fic_master_trans_0/N_106\);
    
    \mss_top_0/MSS_EMI_0_AB_7\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_7_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(7));
    
    \fic_master_trans_0/HADDR_TEMP[18]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[18]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[18]\\\);
    
    \mss_top_0/MSS_ADLIB_INST/U_65\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/PUFABnINT_NET\, 
        PIN2INT => GLMUXINT_GND, PIN3INT => GLMUXINT_GND);
    
    \mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC\ : MSS_CCC_IP
      generic map(VCOFREQUENCY => 240.0)

      port map(CLKA => \mss_top_0/MSS_CCC_0/N_CLKA_XTLOSC\, EXTFB
         => \mss_top_0/MSS_CCC_0/I_MSSCCC/EXTFB_INT\, GLA => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT\, GLAMSS => 
        \mss_top_0/MSS_ADLIB_INST_FCLK\, LOCK => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/LOCK_INT\, LOCKMSS => 
        \mss_top_0/MSS_ADLIB_INST_PLLLOCK\, CLKB => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/CLKB_INT\, GLB => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT\, YB => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/YB_INT\, CLKC => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/CLKC_INT\, GLC => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/GLC_INT\, YC => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/YC_INT\, MACCLK => 
        \mss_top_0/MSS_ADLIB_INST_MACCLKCCC\, SDIN => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/SDIN_INT\, SCLK => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/SCLK_INT\, SSHIFT => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/SSHIFT_INT\, SUPDATE => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/SUPDATE_INT\, MODE => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/MODE_INT\, SDOUT => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/SDOUT_INT\, PLLEN => 
        PLLEN_VCC, OADIV(4) => GLMUXINT_GND, OADIV(3) => 
        GLMUXINT_GND, OADIV(2) => GLMUXINT_GND, OADIV(1) => 
        PLLEN_VCC, OADIV(0) => GLMUXINT_GND, OADIVHALF => 
        GLMUXINT_GND, OADIVRST => GLMUXINT_GND, OAMUX(2) => 
        PLLEN_VCC, OAMUX(1) => GLMUXINT_GND, OAMUX(0) => 
        GLMUXINT_GND, BYPASSA => GLMUXINT_GND, DLYGLA(4) => 
        GLMUXINT_GND, DLYGLA(3) => GLMUXINT_GND, DLYGLA(2) => 
        GLMUXINT_GND, DLYGLA(1) => GLMUXINT_GND, DLYGLA(0) => 
        GLMUXINT_GND, DLYGLAMSS(4) => GLMUXINT_GND, DLYGLAMSS(3)
         => PLLEN_VCC, DLYGLAMSS(2) => GLMUXINT_GND, DLYGLAMSS(1)
         => GLMUXINT_GND, DLYGLAMSS(0) => GLMUXINT_GND, 
        DLYGLAFAB(4) => GLMUXINT_GND, DLYGLAFAB(3) => PLLEN_VCC, 
        DLYGLAFAB(2) => PLLEN_VCC, DLYGLAFAB(1) => PLLEN_VCC, 
        DLYGLAFAB(0) => PLLEN_VCC, OBDIV(4) => GLMUXINT_GND, 
        OBDIV(3) => GLMUXINT_GND, OBDIV(2) => GLMUXINT_GND, 
        OBDIV(1) => GLMUXINT_GND, OBDIV(0) => GLMUXINT_GND, 
        OBDIVHALF => GLMUXINT_GND, OBDIVRST => GLMUXINT_GND, 
        OBMUX(2) => GLMUXINT_GND, OBMUX(1) => GLMUXINT_GND, 
        OBMUX(0) => GLMUXINT_GND, BYPASSB => PLLEN_VCC, DLYGLB(4)
         => GLMUXINT_GND, DLYGLB(3) => GLMUXINT_GND, DLYGLB(2)
         => GLMUXINT_GND, DLYGLB(1) => GLMUXINT_GND, DLYGLB(0)
         => GLMUXINT_GND, OCDIV(4) => GLMUXINT_GND, OCDIV(3) => 
        GLMUXINT_GND, OCDIV(2) => PLLEN_VCC, OCDIV(1) => 
        GLMUXINT_GND, OCDIV(0) => GLMUXINT_GND, OCDIVHALF => 
        GLMUXINT_GND, OCDIVRST => GLMUXINT_GND, OCMUX(2) => 
        PLLEN_VCC, OCMUX(1) => GLMUXINT_GND, OCMUX(0) => 
        GLMUXINT_GND, BYPASSC => GLMUXINT_GND, DLYGLC(4) => 
        GLMUXINT_GND, DLYGLC(3) => GLMUXINT_GND, DLYGLC(2) => 
        GLMUXINT_GND, DLYGLC(1) => GLMUXINT_GND, DLYGLC(0) => 
        GLMUXINT_GND, FINDIV(6) => GLMUXINT_GND, FINDIV(5) => 
        GLMUXINT_GND, FINDIV(4) => GLMUXINT_GND, FINDIV(3) => 
        GLMUXINT_GND, FINDIV(2) => GLMUXINT_GND, FINDIV(1) => 
        PLLEN_VCC, FINDIV(0) => PLLEN_VCC, FBDIV(6) => 
        GLMUXINT_GND, FBDIV(5) => PLLEN_VCC, FBDIV(4) => 
        GLMUXINT_GND, FBDIV(3) => PLLEN_VCC, FBDIV(2) => 
        PLLEN_VCC, FBDIV(1) => PLLEN_VCC, FBDIV(0) => PLLEN_VCC, 
        FBDLY(4) => GLMUXINT_GND, FBDLY(3) => GLMUXINT_GND, 
        FBDLY(2) => GLMUXINT_GND, FBDLY(1) => GLMUXINT_GND, 
        FBDLY(0) => PLLEN_VCC, FBSEL(1) => GLMUXINT_GND, FBSEL(0)
         => PLLEN_VCC, XDLYSEL => GLMUXINT_GND, VCOSEL(2) => 
        GLMUXINT_GND, VCOSEL(1) => GLMUXINT_GND, VCOSEL(0) => 
        GLMUXINT_GND, GLMUXINT => GLMUXINT_GND, GLMUXSEL(1) => 
        GLMUXINT_GND, GLMUXSEL(0) => GLMUXINT_GND, GLMUXCFG(1)
         => GLMUXINT_GND, GLMUXCFG(0) => GLMUXINT_GND);
    
    \fic_master_trans_0/HADDR_TEMP[5]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[5]\\\, B => 
        \fic_master_trans_0/I_13\, S => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, Y => 
        \fic_master_trans_0/HADDR_TEMP[5]/Y\);
    
    \mss_top_0/MSS_EMI_0_AB_11\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_11_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(11));
    
    \fic_master_trans_0/un2_haddr_temp_I_98\ : XOR2
      port map(A => \fic_master_trans_0/N_83\, B => 
        \\\fic_master_trans_0_HADDR_[18]\\\, Y => 
        \fic_master_trans_0/I_98\);
    
    \fic_master_trans_0/un2_haddr_temp_I_135\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[28]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[13]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[15]\, Y => 
        \fic_master_trans_0/N_56\);
    
    \fic_master_trans_0/un2_haddr_temp_I_111\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[0]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[2]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[5]\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[28]\);
    
    \FABHREADYOUT_pad/U0/U1\ : IOTRI_OB_EB
      port map(D => FABHREADYOUT_c, E => PLLEN_VCC, DOUT => 
        \FABHREADYOUT_pad/U0/NET1\, EOUT => 
        \FABHREADYOUT_pad/U0/NET2\);
    
    \mss_top_0/MSS_EMI_0_RW_N\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_RW_N_D\, E => PLLEN_VCC, 
        PAD => EMC_RW_N);
    
    \fic_master_trans_0/ahb_states_RNIHRUB2[0]\ : MX2
      port map(A => \fic_master_trans_0/un1_hreadyout\, B => 
        \fic_master_trans_0/un9_hreadyout\, S => 
        \fic_master_trans_0/ahb_states[0]_net_1\, Y => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[5]/U0\ : MX2
      port map(A => \fic_master_trans_0/HWRITE_DATA_TEMP_n5\, B
         => \\\fic_master_trans_0_HWDATA_[5]\\\, S => 
        \fic_master_trans_0/HWRITE_DATA_TEMPe\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP[5]/Y\);
    
    \fic_master_trans_0/un2_haddr_temp_I_69\ : AND3
      port map(A => \\\fic_master_trans_0_HADDR_[11]\\\, B => 
        \\\fic_master_trans_0_HADDR_[12]\\\, C => 
        \\\fic_master_trans_0_HADDR_[13]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[7]\);
    
    \fic_master_trans_0/un2_haddr_temp_I_159\ : AND3
      port map(A => \\\fic_master_trans_0_HADDR_[23]\\\, B => 
        \\\fic_master_trans_0_HADDR_[24]\\\, C => 
        \\\fic_master_trans_0_HADDR_[25]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[17]\);
    
    \mss_top_0/MSS_SPI_0_SS\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_SPI_0_SS_D\, E => 
        \mss_top_0/MSS_SPI_0_SS_E\, Y => 
        \mss_top_0/MSS_SPI_0_SS_Y\, PAD => SPI_0_SS);
    
    \fic_master_trans_0/un2_haddr_temp_I_34\ : AND3
      port map(A => \\\fic_master_trans_0_HADDR_[5]\\\, B => 
        \\\fic_master_trans_0_HADDR_[6]\\\, C => 
        \\\fic_master_trans_0_HADDR_[7]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[2]\);
    
    \mss_top_0/MSS_SPI_0_CLK\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_SPI_0_CLK_D\, E => 
        \mss_top_0/MSS_SPI_0_SS_E\, Y => 
        \mss_top_0/MSS_SPI_0_CLK_Y\, PAD => SPI_0_CLK);
    
    \mss_top_0/MSS_ADLIB_INST/U_31\ : MSS_IF
      port map(PIN4 => \\\fic_master_trans_0_HADDR_[4]\\\, PIN5
         => \\\fic_master_trans_0_HADDR_[3]\\\, PIN6 => 
        \\\fic_master_trans_0_HADDR_[5]\\\, PIN1 => OPEN, PIN2
         => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[4]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHADDR[3]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHADDR[5]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[3]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[4]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[5]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_80\ : AND2
      port map(A => \\\fic_master_trans_0_HADDR_[14]\\\, B => 
        \\\fic_master_trans_0_HADDR_[15]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[8]\);
    
    \fic_master_trans_0/un2_haddr_temp_I_87\ : AND3
      port map(A => \\\fic_master_trans_0_HADDR_[14]\\\, B => 
        \\\fic_master_trans_0_HADDR_[15]\\\, C => 
        \\\fic_master_trans_0_HADDR_[16]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[9]\);
    
    \fic_master_trans_0/un2_haddr_temp_I_199\ : AND2
      port map(A => \fic_master_trans_0/DWACT_FINC_E[29]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[30]\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[24]\);
    
    \fic_master_trans_0/HSEL/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HSEL/Y\, CLK => \FAB_CLK\, 
        CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        fic_master_trans_0_HSEL);
    
    \fic_master_trans_0/HADDR_TEMP[25]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[25]\\\, B => 
        \fic_master_trans_0/I_156\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[25]/Y\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[7]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HWRITE_DATA_TEMP[7]/Y\, 
        CLK => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q
         => \\\fic_master_trans_0_HWDATA_[7]\\\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNO[4]\ : XNOR2
      port map(A => \fic_master_trans_0/un6_hreadyout_5\, B => 
        \\\fic_master_trans_0_HWDATA_[4]\\\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP_n4\);
    
    \mss_top_0/MSS_EMI_0_DB_11\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_11_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_11_Y\, PAD => EMC_DB(11));
    
    \fic_master_trans_0/HADDR_TEMP[3]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[3]\\\, B => 
        \fic_master_trans_0/I_5\, S => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, Y => 
        \fic_master_trans_0/HADDR_TEMP[3]/Y\);
    
    \mss_top_0/MSS_ADLIB_INST/U_30\ : MSS_IF
      port map(PIN4 => \\\fic_master_trans_0_HADDR_[1]\\\, PIN5
         => \\\fic_master_trans_0_HADDR_[0]\\\, PIN6 => 
        \\\fic_master_trans_0_HADDR_[2]\\\, PIN1 => OPEN, PIN2
         => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[1]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHADDR[0]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHADDR[2]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[0]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[1]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[2]INT_NET\);
    
    \fic_master_trans_0/HADDR_TEMP[15]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[15]\\\, B => 
        \fic_master_trans_0/I_77\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[15]/Y\);
    
    \fic_master_trans_0/un2_haddr_temp_I_77\ : XOR2
      port map(A => \fic_master_trans_0/N_98\, B => 
        \\\fic_master_trans_0_HADDR_[15]\\\, Y => 
        \fic_master_trans_0/I_77\);
    
    \fic_master_trans_0/un2_haddr_temp_I_179\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[15]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[17]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[20]\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[21]\);
    
    \mss_top_0/MSS_EMI_0_AB_8\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_8_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(8));
    
    \mss_top_0/MSS_ADLIB_INST/U_39\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[8]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[7]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[9]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[7]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[8]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[9]INT_NET\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNO[0]\ : XNOR2
      port map(A => \fic_master_trans_0/HWRITE_DATA_TEMPe\, B => 
        \\\fic_master_trans_0_HWDATA_[0]\\\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP_RNO[0]_net_1\);
    
    \fic_master_trans_0/HADDR_TEMP[3]/U1\ : DFN1P0
      port map(D => \fic_master_trans_0/HADDR_TEMP[3]/Y\, CLK => 
        \FAB_CLK\, PRE => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[3]\\\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[5]\ : OA1
      port map(A => \fic_master_trans_0/un6_hreadyout_0\, B => 
        \fic_master_trans_0/un6_hreadyout_5\, C => FABHREADYOUT_c, 
        Y => \fic_master_trans_0/un1_hreadyout\);
    
    \fic_master_trans_0/un2_haddr_temp_I_62\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[0]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[2]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[5]\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[6]\);
    
    \mss_top_0/MSS_SPI_1_CLK\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_SPI_1_CLK_D\, E => 
        \mss_top_0/MSS_SPI_1_SS_E\, Y => 
        \mss_top_0/MSS_SPI_1_CLK_Y\, PAD => SPI_1_CLK);
    
    \fic_master_trans_0/un2_haddr_temp_I_115\ : XOR2
      port map(A => \fic_master_trans_0/N_71\, B => 
        \\\fic_master_trans_0_HADDR_[20]\\\, Y => 
        \fic_master_trans_0/I_115\);
    
    \mss_top_0/MSS_EMI_0_DB_14\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_14_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_14_Y\, PAD => EMC_DB(14));
    
    \mss_top_0/MSS_ADLIB_INST/U_5\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[26]INT_NET\, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[25]INT_NET\, PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[27]INT_NET\, PIN1INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[25]INT_NET\, PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[26]INT_NET\, PIN3INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[27]INT_NET\);
    
    \mss_top_0/MSS_MAC_0_RXD_1\ : IOPAD_IN
      port map(PAD => MAC_RXD(1), Y => 
        \mss_top_0/MSS_MAC_0_RXD_1_Y\);
    
    \fic_master_trans_0/HADDR_TEMP[0]\ : DFN1C0
      port map(D => \\\fic_master_trans_0_HADDR_[0]\\\, CLK => 
        \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[0]\\\);
    
    \fic_master_trans_0/un2_haddr_temp_I_186\ : XOR2
      port map(A => \fic_master_trans_0/N_21\, B => 
        \\\fic_master_trans_0_HADDR_[28]\\\, Y => 
        \fic_master_trans_0/I_186\);
    
    \fic_master_trans_0/un2_haddr_temp_I_5\ : XOR2
      port map(A => \\\fic_master_trans_0_HADDR_[2]\\\, B => 
        \\\fic_master_trans_0_HADDR_[3]\\\, Y => 
        \fic_master_trans_0/I_5\);
    
    \fic_master_trans_0/un2_haddr_temp_I_129\ : XOR2
      port map(A => \fic_master_trans_0/N_61\, B => 
        \\\fic_master_trans_0_HADDR_[22]\\\, Y => 
        \fic_master_trans_0/I_129\);
    
    \mss_top_0/MSS_EMI_0_DB_12\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_12_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_12_Y\, PAD => EMC_DB(12));
    
    \mss_top_0/MSS_SPI_0_DO\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_SPI_0_DO_D\, E => 
        \mss_top_0/MSS_SPI_0_DO_E\, PAD => SPI_0_DO);
    
    \mss_top_0/MSS_ADLIB_INST/U_9\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/UART1RInINT_NET\, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/UART1DSRnINT_NET\, PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/UART1DCDnINT_NET\, PIN1INT => 
        \mss_top_0/MSS_ADLIB_INST/SPI1SSO[1]INT_NET\, PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/SPI1SSO[2]INT_NET\, PIN3INT => 
        \mss_top_0/MSS_ADLIB_INST/SPI1SSO[3]INT_NET\);
    
    \mss_top_0/MSS_EMI_0_BYTEN_1\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_BYTEN_1_D\, E => 
        PLLEN_VCC, PAD => EMC_BYTEN(1));
    
    \fic_master_trans_0/HADDR_TEMP[8]/U1\ : DFN1P0
      port map(D => \fic_master_trans_0/HADDR_TEMP[8]/Y\, CLK => 
        \FAB_CLK\, PRE => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[8]\\\);
    
    \mss_top_0/MSS_EMI_0_AB_18\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_18_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(18));
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNO[2]\ : XOR2
      port map(A => \fic_master_trans_0/HWRITE_DATA_TEMP_c1\, B
         => \\\fic_master_trans_0_HWDATA_[2]\\\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP_n2\);
    
    \mss_top_0/MSS_ADLIB_INST/U_87\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[20]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHWDATA[19]INT_NET\, 
        PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[21]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[19]INT_NET\, 
        PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[20]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[21]INT_NET\);
    
    \mss_top_0/MSS_ADLIB_INST/U_34\ : MSS_IF
      port map(PIN4 => \\\fic_master_trans_0_HADDR_[13]\\\, PIN5
         => \\\fic_master_trans_0_HADDR_[12]\\\, PIN6 => 
        \\\fic_master_trans_0_HADDR_[14]\\\, PIN1 => OPEN, PIN2
         => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[13]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHADDR[12]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHADDR[14]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[12]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[13]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[14]INT_NET\);
    
    \mss_top_0/MSS_UART_0_RXD\ : IOPAD_IN
      port map(PAD => UART_0_RXD, Y => 
        \mss_top_0/MSS_UART_0_RXD_Y\);
    
    \mss_top_0/MSS_ADLIB_INST/U_88\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[23]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHWDATA[22]INT_NET\, 
        PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[24]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[22]INT_NET\, 
        PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[23]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[24]INT_NET\);
    
    \fic_master_trans_0/HADDR_TEMP[20]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[20]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[20]\\\);
    
    \mss_top_0/MSS_EMI_0_DB_3\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_3_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_3_Y\, PAD => EMC_DB(3));
    
    \mss_top_0/MSS_SPI_1_SS\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_SPI_1_SS_D\, E => 
        \mss_top_0/MSS_SPI_1_SS_E\, Y => 
        \mss_top_0/MSS_SPI_1_SS_Y\, PAD => SPI_1_SS);
    
    \fic_master_trans_0/un2_haddr_temp_I_41\ : AND2
      port map(A => \\\fic_master_trans_0_HADDR_[8]\\\, B => 
        \\\fic_master_trans_0_HADDR_[9]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[3]\);
    
    \mss_top_0/MSS_MAC_0_TXD_0\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_MAC_0_TXD_0_D\, E => PLLEN_VCC, 
        PAD => MAC_TXD(0));
    
    \fic_master_trans_0/un2_haddr_temp_I_30\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[0]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[1]\, C => 
        \\\fic_master_trans_0_HADDR_[7]\\\, Y => 
        \fic_master_trans_0/N_131\);
    
    \fic_master_trans_0/HADDR_TEMP[10]/U1\ : DFN1P0
      port map(D => \fic_master_trans_0/HADDR_TEMP[10]/Y\, CLK
         => \FAB_CLK\, PRE => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[10]\\\);
    
    \fic_master_trans_0/un2_haddr_temp_I_37\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[0]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[2]\, C => 
        \\\fic_master_trans_0_HADDR_[8]\\\, Y => 
        \fic_master_trans_0/N_126\);
    
    \mss_top_0/MSS_ADLIB_INST/U_51\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[11]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHWDATA[10]INT_NET\, 
        PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[12]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[10]INT_NET\, 
        PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[11]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[12]INT_NET\);
    
    \mss_top_0/MSS_ADLIB_INST/U_86\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[17]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHWDATA[16]INT_NET\, 
        PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[18]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[16]INT_NET\, 
        PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[17]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[18]INT_NET\);
    
    \mss_top_0/MSS_EMI_0_CS1_N\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_CS1_N_D\, E => PLLEN_VCC, 
        PAD => EMC_CS1_N);
    
    \mss_top_0/MSS_MAC_0_CRSDV\ : IOPAD_IN
      port map(PAD => MAC_CRSDV, Y => 
        \mss_top_0/MSS_MAC_0_CRSDV_Y\);
    
    \mss_top_0/MSS_I2C_1_SDA\ : IOPAD_BI
      port map(D => GLMUXINT_GND, E => 
        \mss_top_0/MSS_I2C_1_SDA_E\, Y => 
        \mss_top_0/MSS_I2C_1_SDA_Y\, PAD => I2C_1_SDA);
    
    \mss_top_0/MSS_ADLIB_INST/U_83\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[23]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[24]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[25]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_203\ : XOR2
      port map(A => \fic_master_trans_0/N_9\, B => 
        \\\fic_master_trans_0_HADDR_[30]\\\, Y => 
        \fic_master_trans_0/I_203\);
    
    \fic_master_trans_0/un2_haddr_temp_I_91\ : XOR2
      port map(A => \fic_master_trans_0/N_88\, B => 
        \\\fic_master_trans_0_HADDR_[17]\\\, Y => 
        \fic_master_trans_0/I_91\);
    
    \mss_top_0/MSS_ADLIB_INST/U_91\ : MSS_IF
      port map(PIN4 => \FAB_CLK\, PIN5 => GLMUXINT_GND, PIN6 => 
        GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => OPEN, 
        PIN4INT => \mss_top_0/MSS_ADLIB_INST/SYNCCLKFDBKINT_NET\, 
        PIN5INT => OPEN, PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[31]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[31]INT_NET\, 
        PIN2INT => GLMUXINT_GND, PIN3INT => GLMUXINT_GND);
    
    \fic_master_trans_0/un2_haddr_temp_I_142\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[28]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[13]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[16]\, Y => 
        \fic_master_trans_0/N_51\);
    
    \mss_top_0/MSS_ADLIB_INST/U_50\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => 
        \\\fic_master_trans_0_HWDATA_[7]\\\, PIN6 => GLMUXINT_GND, 
        PIN1 => OPEN, PIN2 => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[8]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHWDATA[7]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHWDATA[9]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[7]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[8]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[9]INT_NET\);
    
    \mss_top_0/MSS_UART_1_TXD\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_UART_1_TXD_D\, E => PLLEN_VCC, 
        PAD => UART_1_TXD);
    
    \fic_master_trans_0/HADDR_TEMP[29]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[29]\\\, B => 
        \fic_master_trans_0/I_196\, S => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, Y => 
        \fic_master_trans_0/HADDR_TEMP[29]/Y\);
    
    \fic_master_trans_0/un2_haddr_temp_I_162\ : AND2
      port map(A => \fic_master_trans_0/DWACT_FINC_E[15]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[17]\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[18]\);
    
    \fic_master_trans_0/un2_haddr_temp_I_136\ : XOR2
      port map(A => \fic_master_trans_0/N_56\, B => 
        \\\fic_master_trans_0_HADDR_[23]\\\, Y => 
        \fic_master_trans_0/I_136\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HWRITE_DATA_TEMP[4]/Y\, 
        CLK => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q
         => \\\fic_master_trans_0_HWDATA_[4]\\\);
    
    \mss_top_0/MSS_ADLIB_INST/U_59\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => fic_master_trans_0_HSEL, PIN1 => OPEN, PIN2 => OPEN, 
        PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHSIZE[0]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHMASTLOCKINT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHSIZE[1]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/MSSHLOCKINT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/MSSHSIZE[0]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/MSSHSIZE[1]INT_NET\);
    
    \fic_master_trans_0/HADDR_TEMP[19]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[19]\\\, B => 
        \fic_master_trans_0/I_105\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[19]/Y\);
    
    \mss_top_0/MSS_ADLIB_INST/U_90\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[29]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHWDATA[28]INT_NET\, 
        PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[30]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[28]INT_NET\, 
        PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[29]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[30]INT_NET\);
    
    \mss_top_0/MSS_ADLIB_INST/U_4\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[23]INT_NET\, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[22]INT_NET\, PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[24]INT_NET\, PIN1INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[22]INT_NET\, PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[23]INT_NET\, PIN3INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[24]INT_NET\);
    
    \mss_top_0/MSS_ADLIB_INST/U_85\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[29]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[30]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[31]INT_NET\);
    
    \fic_master_trans_0/HADDR_TEMP[9]/U1\ : DFN1P0
      port map(D => \fic_master_trans_0/HADDR_TEMP[9]/Y\, CLK => 
        \FAB_CLK\, PRE => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[9]\\\);
    
    \FAB_CLK_pad/U0/U1\ : IOTRI_OB_EB
      port map(D => \FAB_CLK\, E => PLLEN_VCC, DOUT => 
        \FAB_CLK_pad/U0/NET1\, EOUT => \FAB_CLK_pad/U0/NET2\);
    
    \mss_top_0/MSS_I2C_0_SDA\ : IOPAD_BI
      port map(D => GLMUXINT_GND, E => 
        \mss_top_0/MSS_I2C_0_SDA_E\, Y => 
        \mss_top_0/MSS_I2C_0_SDA_Y\, PAD => I2C_0_SDA);
    
    \mss_top_0/MSS_EMI_0_BYTEN_0\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_BYTEN_0_D\, E => 
        PLLEN_VCC, PAD => EMC_BYTEN(0));
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNI6N7K[4]\ : NOR2A
      port map(A => \\\fic_master_trans_0_HWDATA_[4]\\\, B => 
        \fic_master_trans_0/un6_hreadyout_5\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP_c4\);
    
    \fic_master_trans_0/un2_haddr_temp_I_210\ : XOR2
      port map(A => \fic_master_trans_0/N_4\, B => 
        \\\fic_master_trans_0_HADDR_[31]\\\, Y => 
        \fic_master_trans_0/I_210\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[3]/U0\ : MX2
      port map(A => \fic_master_trans_0/HWRITE_DATA_TEMP_n3\, B
         => \\\fic_master_trans_0_HWDATA_[3]\\\, S => 
        \fic_master_trans_0/HWRITE_DATA_TEMPe\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP[3]/Y\);
    
    \mss_top_0/MSS_MAC_0_TXEN\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_MAC_0_TXEN_D\, E => PLLEN_VCC, 
        PAD => MAC_TXEN);
    
    \fic_master_trans_0/un2_haddr_temp_I_4\ : INV
      port map(A => \\\fic_master_trans_0_HADDR_[2]\\\, Y => 
        \fic_master_trans_0/I_4\);
    
    \fic_master_trans_0/HADDR_TEMP[20]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[20]\\\, B => 
        \fic_master_trans_0/I_115\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[20]/Y\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[0]\ : DFN1C0
      port map(D => 
        \fic_master_trans_0/HWRITE_DATA_TEMP_RNO[0]_net_1\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HWDATA_[0]\\\);
    
    \mss_top_0/MSS_MAC_0_MDC\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_MAC_0_MDC_D\, E => PLLEN_VCC, 
        PAD => MAC_MDC);
    
    \fic_master_trans_0/un2_haddr_temp_I_104\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[6]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[10]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[11]\, Y => 
        \fic_master_trans_0/N_78\);
    
    \fic_master_trans_0/un2_haddr_temp_I_13\ : XOR2
      port map(A => \fic_master_trans_0/N_144\, B => 
        \\\fic_master_trans_0_HADDR_[5]\\\, Y => 
        \fic_master_trans_0/I_13\);
    
    \fic_master_trans_0/HADDR_TEMP[30]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[30]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[30]\\\);
    
    \mss_top_0/MSS_ADLIB_INST/U_32\ : MSS_IF
      port map(PIN4 => \\\fic_master_trans_0_HADDR_[7]\\\, PIN5
         => \\\fic_master_trans_0_HADDR_[6]\\\, PIN6 => 
        \\\fic_master_trans_0_HADDR_[8]\\\, PIN1 => OPEN, PIN2
         => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[7]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHADDR[6]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHADDR[8]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[6]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[7]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[8]INT_NET\);
    
    \fic_master_trans_0/HADDR_TEMP[10]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[10]\\\, B => 
        \fic_master_trans_0/I_45\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[10]/Y\);
    
    \mss_top_0/MSS_RESET_0_MSS_RESET_N\ : IOPAD_IN
      port map(PAD => MSS_RESET_N, Y => 
        \mss_top_0/MSS_RESET_0_MSS_RESET_N_Y\);
    
    \mss_top_0/MSS_ADLIB_INST/U_7\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/UART0CTSnINT_NET\, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[31]INT_NET\, PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/UART0DSRnINT_NET\, PIN1INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[31]INT_NET\, PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/SPI0SSO[1]INT_NET\, PIN3INT => 
        \mss_top_0/MSS_ADLIB_INST/SPI0SSO[2]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_152\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[34]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[2]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[5]\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[29]\);
    
    \fic_master_trans_0/un2_haddr_temp_I_9\ : AX1C
      port map(A => \\\fic_master_trans_0_HADDR_[3]\\\, B => 
        \\\fic_master_trans_0_HADDR_[2]\\\, C => 
        \\\fic_master_trans_0_HADDR_[4]\\\, Y => 
        \fic_master_trans_0/I_9\);
    
    \fic_master_trans_0/un2_haddr_temp_I_23\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[0]\, B => 
        \\\fic_master_trans_0_HADDR_[5]\\\, C => 
        \\\fic_master_trans_0_HADDR_[6]\\\, Y => 
        \fic_master_trans_0/N_136\);
    
    \mss_top_0/MSS_ADLIB_INST/U_54\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[20]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[19]INT_NET\, 
        PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[21]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[19]INT_NET\, 
        PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[20]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[21]INT_NET\);
    
    \mss_top_0/MSS_ADLIB_INST/U_6\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[29]INT_NET\, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[28]INT_NET\, PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/GPI[30]INT_NET\, PIN1INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[28]INT_NET\, PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[29]INT_NET\, PIN3INT => 
        \mss_top_0/MSS_ADLIB_INST/GPO[30]INT_NET\);
    
    \mss_top_0/MSS_ADLIB_INST/U_41\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[14]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[13]INT_NET\, 
        PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[15]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[13]INT_NET\, 
        PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[14]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[15]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_206\ : AND2
      port map(A => \\\fic_master_trans_0_HADDR_[29]\\\, B => 
        \\\fic_master_trans_0_HADDR_[30]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[25]\);
    
    \fic_master_trans_0/un2_haddr_temp_I_192\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[15]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[17]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[22]\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[23]\);
    
    \mss_top_0/MSS_EMI_0_AB_24\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_24_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(24));
    
    \mss_top_0/MSS_EMI_0_AB_20\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_20_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(20));
    
    \mss_top_0/MSS_ADLIB_INST/U_94\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/I2C0SMBALERTNIINT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/I2C0BCLKINT_NET\, PIN6INT
         => \mss_top_0/MSS_ADLIB_INST/I2C0SMBUSNIINT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/SPI1SSO[4]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/SPI1SSO[5]INT_NET\, 
        PIN3INT => 
        \mss_top_0/MSS_ADLIB_INST/I2C0SMBALERTNOINT_NET\);
    
    \mss_top_0/MSS_ADLIB_INST/U_10\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => \mss_top_0/MSS_ADLIB_INST/VRONINT_NET\, 
        PIN5INT => \mss_top_0/MSS_ADLIB_INST/RXEVINT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/CALIBININT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/UART1RTSnINT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/UART1DTRnINT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/TXEVINT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_189\ : AND3
      port map(A => \\\fic_master_trans_0_HADDR_[26]\\\, B => 
        \\\fic_master_trans_0_HADDR_[27]\\\, C => 
        \\\fic_master_trans_0_HADDR_[28]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[22]\);
    
    \fic_master_trans_0/HADDR_TEMP[21]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[21]\\\, B => 
        \fic_master_trans_0/I_122\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[21]/Y\);
    
    \mss_top_0/MSS_EMI_0_AB_3\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_3_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(3));
    
    \mss_top_0/MSS_ADLIB_INST/U_40\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[11]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[10]INT_NET\, 
        PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[12]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[10]INT_NET\, 
        PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[11]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[12]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_56\ : XOR2
      port map(A => \fic_master_trans_0/N_113\, B => 
        \\\fic_master_trans_0_HADDR_[12]\\\, Y => 
        \fic_master_trans_0/I_56\);
    
    \mss_top_0/MSS_EMI_0_DB_5\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_5_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_5_Y\, PAD => EMC_DB(5));
    
    \fic_master_trans_0/HADDR_TEMP[11]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[11]\\\, B => 
        \fic_master_trans_0/I_52\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[11]/Y\);
    
    \mss_top_0/MSS_ADLIB_INST/U_71\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/CMP0INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/CMP1INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/CMP2INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_172\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[29]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[13]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[19]\, Y => 
        \fic_master_trans_0/N_30\);
    
    \mss_top_0/MSS_ADLIB_INST/U_49\ : MSS_IF
      port map(PIN4 => \\\fic_master_trans_0_HWDATA_[5]\\\, PIN5
         => \\\fic_master_trans_0_HWDATA_[4]\\\, PIN6 => 
        \\\fic_master_trans_0_HWDATA_[6]\\\, PIN1 => OPEN, PIN2
         => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[5]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHWDATA[4]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHWDATA[6]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[4]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[5]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[6]INT_NET\);
    
    \fic_master_trans_0/HADDR_TEMP[30]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[30]\\\, B => 
        \fic_master_trans_0/I_203\, S => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, Y => 
        \fic_master_trans_0/HADDR_TEMP[30]/Y\);
    
    \fic_master_trans_0/HADDR_TEMP[2]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[2]\\\, B => 
        \fic_master_trans_0/I_4\, S => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, Y => 
        \fic_master_trans_0/HADDR_TEMP[2]/Y\);
    
    \fic_master_trans_0/HADDR_TEMP[4]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[4]\\\, B => 
        \fic_master_trans_0/I_9\, S => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, Y => 
        \fic_master_trans_0/HADDR_TEMP[4]/Y\);
    
    \fic_master_trans_0/HADDR_TEMP[26]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[26]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[26]\\\);
    
    \mss_top_0/MSS_ADLIB_INST/U_61\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => PLLEN_VCC, PIN6 => 
        GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => OPEN, 
        PIN4INT => \mss_top_0/MSS_ADLIB_INST/DMAREADY[0]INT_NET\, 
        PIN5INT => \mss_top_0/MSS_ADLIB_INST/F2MRESETnINT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/DMAREADY[1]INT_NET\, 
        PIN1INT => GLMUXINT_GND, PIN2INT => GLMUXINT_GND, PIN3INT
         => GLMUXINT_GND);
    
    \fic_master_trans_0/un2_haddr_temp_I_108\ : AND3
      port map(A => \\\fic_master_trans_0_HADDR_[17]\\\, B => 
        \\\fic_master_trans_0_HADDR_[18]\\\, C => 
        \\\fic_master_trans_0_HADDR_[19]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[12]\);
    
    \mss_top_0/MSS_EMI_0_DB_13\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_13_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_13_Y\, PAD => EMC_DB(13));
    
    \mss_top_0/MSS_I2C_0_SCL\ : IOPAD_BI
      port map(D => GLMUXINT_GND, E => 
        \mss_top_0/MSS_I2C_0_SCL_E\, Y => 
        \mss_top_0/MSS_I2C_0_SCL_Y\, PAD => I2C_0_SCL);
    
    \fic_master_trans_0/HADDR_TEMP[5]/U1\ : DFN1P0
      port map(D => \fic_master_trans_0/HADDR_TEMP[5]/Y\, CLK => 
        \FAB_CLK\, PRE => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[5]\\\);
    
    \fic_master_trans_0/HADDR_TEMP[16]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[16]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[16]\\\);
    
    \mss_top_0/MSS_EMI_0_AB_17\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_17_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(17));
    
    \fic_master_trans_0/un2_haddr_temp_I_165\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[29]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[13]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[18]\, Y => 
        \fic_master_trans_0/N_35\);
    
    \mss_top_0/MSS_ADLIB_INST/U_79\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[11]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[12]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[13]INT_NET\);
    
    \mss_top_0/MSS_ADLIB_INST/U_60\ : MSS_IF
      port map(PIN4 => fic_master_trans_0_HSEL, PIN5 => 
        GLMUXINT_GND, PIN6 => fic_master_trans_0_HSEL, PIN1 => 
        OPEN, PIN2 => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHTRANS1INT_NET\, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/FABINTINT_NET\, PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHSELINT_NET\, PIN1INT => 
        GLMUXINT_GND, PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHTRANS1INT_NET\, PIN3INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWRITEINT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_83\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[6]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[7]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[8]\, Y => 
        \fic_master_trans_0/N_93\);
    
    \fic_master_trans_0/un2_haddr_temp_I_55\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[4]\, B => 
        \\\fic_master_trans_0_HADDR_[10]\\\, C => 
        \\\fic_master_trans_0_HADDR_[11]\\\, Y => 
        \fic_master_trans_0/N_113\);
    
    \fic_master_trans_0/un2_haddr_temp_I_122\ : XOR2
      port map(A => \fic_master_trans_0/N_66\, B => 
        \\\fic_master_trans_0_HADDR_[21]\\\, Y => 
        \fic_master_trans_0/I_122\);
    
    \mss_top_0/MSS_EMI_0_AB_14\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_14_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(14));
    
    \fic_master_trans_0/HADDR_TEMP[24]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[24]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[24]\\\);
    
    \mss_top_0/MSS_EMI_0_AB_10\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_10_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(10));
    
    \fic_master_trans_0/un2_haddr_temp_I_143\ : XOR2
      port map(A => \fic_master_trans_0/N_51\, B => 
        \\\fic_master_trans_0_HADDR_[24]\\\, Y => 
        \fic_master_trans_0/I_143\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNO[7]\ : AX1C
      port map(A => \\\fic_master_trans_0_HWDATA_[6]\\\, B => 
        \fic_master_trans_0/HWRITE_DATA_TEMP_c5\, C => 
        \\\fic_master_trans_0_HWDATA_[7]\\\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP_n7\);
    
    \mss_top_0/MSS_EMI_0_DB_1\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_1_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_1_Y\, PAD => EMC_DB(1));
    
    \mss_top_0/MSS_EMI_0_DB_0\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_0_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_0_Y\, PAD => EMC_DB(0));
    
    \fic_master_trans_0/un2_haddr_temp_I_101\ : AND2
      port map(A => \\\fic_master_trans_0_HADDR_[17]\\\, B => 
        \\\fic_master_trans_0_HADDR_[18]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[11]\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNO[1]\ : XOR2
      port map(A => \\\fic_master_trans_0_HWDATA_[1]\\\, B => 
        \\\fic_master_trans_0_HWDATA_[0]\\\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP_n1\);
    
    \mss_top_0/MSS_ADLIB_INST/U_52\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[14]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHWDATA[13]INT_NET\, 
        PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[15]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[13]INT_NET\, 
        PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[14]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[15]INT_NET\);
    
    \fic_master_trans_0/HADDR_TEMP[23]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[23]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[23]\\\);
    
    \fic_master_trans_0/HADDR_TEMP[14]/U1\ : DFN1P0
      port map(D => \fic_master_trans_0/HADDR_TEMP[14]/Y\, CLK
         => \FAB_CLK\, PRE => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[14]\\\);
    
    \mss_top_0/MSS_ADLIB_INST/U_44\ : MSS_IF
      port map(PIN4 => \\\fic_master_trans_0_HADDR_[22]\\\, PIN5
         => \\\fic_master_trans_0_HADDR_[21]\\\, PIN6 => 
        \\\fic_master_trans_0_HADDR_[23]\\\, PIN1 => OPEN, PIN2
         => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[22]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHADDR[21]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHADDR[23]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/SLEEPINT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/MSSINT[0]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/MSSINT[1]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_38\ : XOR2
      port map(A => \fic_master_trans_0/N_126\, B => 
        \\\fic_master_trans_0_HADDR_[9]\\\, Y => 
        \fic_master_trans_0/I_38\);
    
    \fic_master_trans_0/ahb_states_RNIA6791[0]\ : OR2B
      port map(A => \fic_master_trans_0/ahb_states[0]_net_1\, B
         => \fic_master_trans_0/un1_hreadyout\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMPe\);
    
    \fic_master_trans_0/un2_haddr_temp_I_128\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[28]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[13]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[14]\, Y => 
        \fic_master_trans_0/N_61\);
    
    \mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE2\ : MSS_CCC_GL_IF
      port map(PIN2 => GLMUXINT_GND, PIN3 => GLMUXINT_GND, PIN4
         => GLMUXINT_GND, PIN1 => OPEN, PIN5 => OPEN, PIN2INT => 
        OPEN, PIN3INT => \mss_top_0/MSS_CCC_0/I_MSSCCC/CLKB_INT\, 
        PIN4INT => \mss_top_0/MSS_CCC_0/I_MSSCCC/MODE_INT\, 
        PIN1INT => \mss_top_0/MSS_CCC_0/I_MSSCCC/YB_INT\, PIN5INT
         => \mss_top_0/MSS_CCC_0/I_MSSCCC/GLB_INT\);
    
    \fic_master_trans_0/un2_haddr_temp_I_59\ : AND3
      port map(A => \\\fic_master_trans_0_HADDR_[8]\\\, B => 
        \\\fic_master_trans_0_HADDR_[9]\\\, C => 
        \\\fic_master_trans_0_HADDR_[10]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[5]\);
    
    \fic_master_trans_0/HADDR_TEMP[13]/U1\ : DFN1P0
      port map(D => \fic_master_trans_0/HADDR_TEMP[13]/Y\, CLK
         => \FAB_CLK\, PRE => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[13]\\\);
    
    \mss_top_0/MSS_SPI_1_DI\ : IOPAD_IN
      port map(PAD => SPI_1_DI, Y => \mss_top_0/MSS_SPI_1_DI_Y\);
    
    \fic_master_trans_0/un2_haddr_temp_I_73\ : AX1C
      port map(A => \fic_master_trans_0/DWACT_FINC_E[7]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[6]\, C => 
        \\\fic_master_trans_0_HADDR_[14]\\\, Y => 
        \fic_master_trans_0/I_73\);
    
    \fic_master_trans_0/un2_haddr_temp_I_139\ : AND2
      port map(A => \fic_master_trans_0/DWACT_FINC_E[15]\, B => 
        \\\fic_master_trans_0_HADDR_[23]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[16]\);
    
    \mss_top_0/MSS_ADLIB_INST/U_92\ : MSS_IF
      port map(PIN4 => fic_master_trans_0_HSEL, PIN5 => 
        GLMUXINT_GND, PIN6 => PLLEN_VCC, PIN1 => FABHREADYOUT_c, 
        PIN2 => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWRITEINT_NET\, PIN5INT => 
        OPEN, PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHREADYINT_NET\, PIN1INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET\, PIN2INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRESPINT_NET\, PIN3INT
         => GLMUXINT_GND);
    
    \mss_top_0/MSS_ADLIB_INST/U_37\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[2]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[1]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[3]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[1]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[2]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[3]INT_NET\);
    
    \fic_master_trans_0/HADDR_TEMP[31]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[31]\\\, B => 
        \fic_master_trans_0/I_210\, S => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, Y => 
        \fic_master_trans_0/HADDR_TEMP[31]/Y\);
    
    \mss_top_0/MSS_EMI_0_DB_4\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_4_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_4_Y\, PAD => EMC_DB(4));
    
    \mss_top_0/MSS_ADLIB_INST/U_38\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[5]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[4]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[6]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[4]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[5]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[6]INT_NET\);
    
    \mss_top_0/MSS_EMI_0_CS0_N\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_CS0_N_D\, E => PLLEN_VCC, 
        PAD => EMC_CS0_N);
    
    \fic_master_trans_0/un2_haddr_temp_I_44\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[0]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[2]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[3]\, Y => 
        \fic_master_trans_0/N_121\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNIT638[3]\ : NOR2B
      port map(A => \\\fic_master_trans_0_HWDATA_[3]\\\, B => 
        \\\fic_master_trans_0_HWDATA_[2]\\\, Y => 
        \fic_master_trans_0/un6_hreadyout_2\);
    
    \fic_master_trans_0/HSEL/U0\ : MX2
      port map(A => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, B => 
        fic_master_trans_0_HSEL, S => 
        \fic_master_trans_0/HADDR_TEMP_0_sqmuxa\, Y => 
        \fic_master_trans_0/HSEL/Y\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[6]/U0\ : MX2
      port map(A => \fic_master_trans_0/HWRITE_DATA_TEMP_n6\, B
         => \\\fic_master_trans_0_HWDATA_[6]\\\, S => 
        \fic_master_trans_0/HWRITE_DATA_TEMPe\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP[6]/Y\);
    
    \fic_master_trans_0/HADDR_TEMP[7]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[7]\\\, B => 
        \fic_master_trans_0/I_24\, S => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, Y => 
        \fic_master_trans_0/HADDR_TEMP[7]/Y\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNIMT5G[3]\ : OR2B
      port map(A => \fic_master_trans_0/HWRITE_DATA_TEMP_c1\, B
         => \fic_master_trans_0/un6_hreadyout_2\, Y => 
        \fic_master_trans_0/un6_hreadyout_5\);
    
    \fic_master_trans_0/un2_haddr_temp_I_155\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[29]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[13]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[33]\, Y => 
        \fic_master_trans_0/N_42\);
    
    \mss_top_0/MSS_ADLIB_INST/U_74\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABSDD1CLKINT_NET\, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/FABSDD0CLKINT_NET\, PIN6INT => 
        OPEN, PIN1INT => GLMUXINT_GND, PIN2INT => GLMUXINT_GND, 
        PIN3INT => GLMUXINT_GND);
    
    \fic_master_trans_0/un2_haddr_temp_I_121\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[28]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[13]\, C => 
        \\\fic_master_trans_0_HADDR_[20]\\\, Y => 
        \fic_master_trans_0/N_66\);
    
    \mss_top_0/MSS_MAC_0_MDIO\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_MAC_0_MDIO_D\, E => 
        \mss_top_0/MSS_MAC_0_MDIO_E\, Y => 
        \mss_top_0/MSS_MAC_0_MDIO_Y\, PAD => MAC_MDIO);
    
    \fic_master_trans_0/HADDR_TEMP[8]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[8]\\\, B => 
        \fic_master_trans_0/I_31\, S => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, Y => 
        \fic_master_trans_0/HADDR_TEMP[8]/Y\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HWRITE_DATA_TEMP[1]/Y\, 
        CLK => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q
         => \\\fic_master_trans_0_HWDATA_[1]\\\);
    
    \fic_master_trans_0/HADDR_TEMP[6]/U1\ : DFN1P0
      port map(D => \fic_master_trans_0/HADDR_TEMP[6]/Y\, CLK => 
        \FAB_CLK\, PRE => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[6]\\\);
    
    \mss_top_0/MSS_ADLIB_INST/U_36\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[0]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[18]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[19]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[0]INT_NET\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[2]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HWRITE_DATA_TEMP[2]/Y\, 
        CLK => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q
         => \\\fic_master_trans_0_HWDATA_[2]\\\);
    
    \mss_top_0/MSS_EMI_0_DB_9\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_9_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_9_Y\, PAD => EMC_DB(9));
    
    \mss_top_0/MSS_EMI_0_AB_23\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_23_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(23));
    
    \mss_top_0/MSS_ADLIB_INST/U_33\ : MSS_IF
      port map(PIN4 => \\\fic_master_trans_0_HADDR_[10]\\\, PIN5
         => \\\fic_master_trans_0_HADDR_[9]\\\, PIN6 => 
        \\\fic_master_trans_0_HADDR_[11]\\\, PIN1 => OPEN, PIN2
         => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[10]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHADDR[9]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHADDR[11]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[9]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[10]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[11]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_94\ : AND2
      port map(A => \fic_master_trans_0/DWACT_FINC_E[7]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[9]\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[10]\);
    
    \mss_top_0/MSS_ADLIB_INST/U_64\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL4ENINT_NET\, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL3ENINT_NET\, PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL5ENINT_NET\, PIN1INT => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL3INT_NET\, PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL4INT_NET\, PIN3INT => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL5INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_195\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[29]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[30]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[23]\, Y => 
        \fic_master_trans_0/N_14\);
    
    \fic_master_trans_0/HADDR_TEMP[6]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[6]\\\, B => 
        \fic_master_trans_0/I_20\, S => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, Y => 
        \fic_master_trans_0/HADDR_TEMP[6]/Y\);
    
    \fic_master_trans_0/HADDR_TEMP[22]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[22]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[22]\\\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNINK9O[5]\ : NOR2B
      port map(A => \fic_master_trans_0/HWRITE_DATA_TEMP_c4\, B
         => \\\fic_master_trans_0_HWDATA_[5]\\\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP_c5\);
    
    \mss_top_0/MSS_EMI_0_AB_22\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_22_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(22));
    
    \fic_master_trans_0/HADDR_TEMP[26]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[26]\\\, B => 
        \fic_master_trans_0/I_166\, S => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, Y => 
        \fic_master_trans_0/HADDR_TEMP[26]/Y\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[7]/U0\ : MX2
      port map(A => \fic_master_trans_0/HWRITE_DATA_TEMP_n7\, B
         => \\\fic_master_trans_0_HWDATA_[7]\\\, S => 
        \fic_master_trans_0/HWRITE_DATA_TEMPe\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP[7]/Y\);
    
    \fic_master_trans_0/HADDR_TEMP[12]/U1\ : DFN1P0
      port map(D => \fic_master_trans_0/HADDR_TEMP[12]/Y\, CLK
         => \FAB_CLK\, PRE => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[12]\\\);
    
    \mss_top_0/MSS_MAC_0_RXER\ : IOPAD_IN
      port map(PAD => MAC_RXER, Y => \mss_top_0/MSS_MAC_0_RXER_Y\);
    
    \mss_top_0/MSS_EMI_0_AB_25\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_25_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(25));
    
    \fic_master_trans_0/un2_haddr_temp_I_52\ : AX1C
      port map(A => \\\fic_master_trans_0_HADDR_[10]\\\, B => 
        \fic_master_trans_0/DWACT_FINC_E[4]\, C => 
        \\\fic_master_trans_0_HADDR_[11]\\\, Y => 
        \fic_master_trans_0/I_52\);
    
    \fic_master_trans_0/un2_haddr_temp_I_105\ : XOR2
      port map(A => \fic_master_trans_0/N_78\, B => 
        \\\fic_master_trans_0_HADDR_[19]\\\, Y => 
        \fic_master_trans_0/I_105\);
    
    \mss_top_0/MSS_EMI_0_AB_5\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_5_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(5));
    
    \mss_top_0/MSS_UART_0_TXD\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_UART_0_TXD_D\, E => PLLEN_VCC, 
        PAD => UART_0_TXD);
    
    \fic_master_trans_0/un2_haddr_temp_I_45\ : XOR2
      port map(A => \fic_master_trans_0/N_121\, B => 
        \\\fic_master_trans_0_HADDR_[10]\\\, Y => 
        \fic_master_trans_0/I_45\);
    
    \fic_master_trans_0/HADDR_TEMP[16]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[16]\\\, B => 
        \fic_master_trans_0/I_84\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[16]/Y\);
    
    \mss_top_0/MSS_ADLIB_INST/U_35\ : MSS_IF
      port map(PIN4 => \\\fic_master_trans_0_HADDR_[16]\\\, PIN5
         => \\\fic_master_trans_0_HADDR_[15]\\\, PIN6 => 
        \\\fic_master_trans_0_HADDR_[17]\\\, PIN1 => OPEN, PIN2
         => OPEN, PIN3 => OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[16]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHADDR[15]INT_NET\, 
        PIN6INT => \mss_top_0/MSS_ADLIB_INST/FABHADDR[17]INT_NET\, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[15]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[16]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/MSSHADDR[17]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_209\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[24]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[23]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[25]\, Y => 
        \fic_master_trans_0/N_4\);
    
    \mss_top_0/MSS_MAC_0_RXD_0\ : IOPAD_IN
      port map(PAD => MAC_RXD(0), Y => 
        \mss_top_0/MSS_MAC_0_RXD_0_Y\);
    
    \mss_top_0/MSS_ADLIB_INST/U_CORE\ : MSS_AHB_IP
      generic map(ACT_CONFIG => 1, ACT_FCLK => 80000000,
         ACT_DIE => "IP4X3M1", ACT_PKG => "fg484")

      port map(FCLK => \mss_top_0/MSS_ADLIB_INST_FCLK\, MACCLKCCC
         => \mss_top_0/MSS_ADLIB_INST_MACCLKCCC\, RCOSC => 
        GLMUXINT_GND, MACCLK => GLMUXINT_GND, PLLLOCK => 
        \mss_top_0/MSS_ADLIB_INST_PLLLOCK\, MSSRESETn => 
        \mss_top_0/MSS_RESET_0_MSS_RESET_N_Y\, GPOE(31) => nc47, 
        GPOE(30) => nc34, GPOE(29) => nc9, GPOE(28) => nc13, 
        GPOE(27) => nc23, GPOE(26) => nc33, GPOE(25) => nc16, 
        GPOE(24) => nc26, GPOE(23) => nc45, GPOE(22) => nc27, 
        GPOE(21) => nc17, GPOE(20) => nc36, GPOE(19) => nc48, 
        GPOE(18) => nc37, GPOE(17) => nc5, GPOE(16) => nc52, 
        GPOE(15) => nc51, GPOE(14) => nc4, GPOE(13) => nc42, 
        GPOE(12) => nc41, GPOE(11) => nc25, GPOE(10) => nc15, 
        GPOE(9) => nc35, GPOE(8) => nc49, GPOE(7) => nc28, 
        GPOE(6) => nc18, GPOE(5) => nc38, GPOE(4) => nc1, GPOE(3)
         => nc2, GPOE(2) => nc50, GPOE(1) => nc22, GPOE(0) => 
        nc12, SPI0DO => \mss_top_0/MSS_SPI_0_DO_D\, SPI0DOE => 
        \mss_top_0/MSS_SPI_0_DO_E\, SPI0DI => 
        \mss_top_0/MSS_SPI_0_DI_Y\, SPI0CLKI => 
        \mss_top_0/MSS_SPI_0_CLK_Y\, SPI0CLKO => 
        \mss_top_0/MSS_SPI_0_CLK_D\, SPI0MODE => 
        \mss_top_0/MSS_SPI_0_SS_E\, SPI0SSI => 
        \mss_top_0/MSS_SPI_0_SS_Y\, SPI0SSO(7) => nc21, 
        SPI0SSO(6) => nc11, SPI0SSO(5) => nc3, SPI0SSO(4) => nc32, 
        SPI0SSO(3) => 
        \mss_top_0/MSS_ADLIB_INST/SPI0SSO[3]INT_NET\, SPI0SSO(2)
         => \mss_top_0/MSS_ADLIB_INST/SPI0SSO[2]INT_NET\, 
        SPI0SSO(1) => 
        \mss_top_0/MSS_ADLIB_INST/SPI0SSO[1]INT_NET\, SPI0SSO(0)
         => \mss_top_0/MSS_SPI_0_SS_D\, UART0TXD => 
        \mss_top_0/MSS_UART_0_TXD_D\, UART0RXD => 
        \mss_top_0/MSS_UART_0_RXD_Y\, I2C0SDAI => 
        \mss_top_0/MSS_I2C_0_SDA_Y\, I2C0SDAO => 
        \mss_top_0/MSS_I2C_0_SDA_E\, I2C0SCLI => 
        \mss_top_0/MSS_I2C_0_SCL_Y\, I2C0SCLO => 
        \mss_top_0/MSS_I2C_0_SCL_E\, SPI1DO => 
        \mss_top_0/MSS_SPI_1_DO_D\, SPI1DOE => 
        \mss_top_0/MSS_SPI_1_DO_E\, SPI1DI => 
        \mss_top_0/MSS_SPI_1_DI_Y\, SPI1CLKI => 
        \mss_top_0/MSS_SPI_1_CLK_Y\, SPI1CLKO => 
        \mss_top_0/MSS_SPI_1_CLK_D\, SPI1MODE => 
        \mss_top_0/MSS_SPI_1_SS_E\, SPI1SSI => 
        \mss_top_0/MSS_SPI_1_SS_Y\, SPI1SSO(7) => 
        \mss_top_0/MSS_ADLIB_INST/SPI1SSO[7]INT_NET\, SPI1SSO(6)
         => \mss_top_0/MSS_ADLIB_INST/SPI1SSO[6]INT_NET\, 
        SPI1SSO(5) => 
        \mss_top_0/MSS_ADLIB_INST/SPI1SSO[5]INT_NET\, SPI1SSO(4)
         => \mss_top_0/MSS_ADLIB_INST/SPI1SSO[4]INT_NET\, 
        SPI1SSO(3) => 
        \mss_top_0/MSS_ADLIB_INST/SPI1SSO[3]INT_NET\, SPI1SSO(2)
         => \mss_top_0/MSS_ADLIB_INST/SPI1SSO[2]INT_NET\, 
        SPI1SSO(1) => 
        \mss_top_0/MSS_ADLIB_INST/SPI1SSO[1]INT_NET\, SPI1SSO(0)
         => \mss_top_0/MSS_SPI_1_SS_D\, UART1TXD => 
        \mss_top_0/MSS_UART_1_TXD_D\, UART1RXD => 
        \mss_top_0/MSS_UART_1_RXD_Y\, I2C1SDAI => 
        \mss_top_0/MSS_I2C_1_SDA_Y\, I2C1SDAO => 
        \mss_top_0/MSS_I2C_1_SDA_E\, I2C1SCLI => 
        \mss_top_0/MSS_I2C_1_SCL_Y\, I2C1SCLO => 
        \mss_top_0/MSS_I2C_1_SCL_E\, MACTXD(1) => 
        \mss_top_0/MSS_MAC_0_TXD_1_D\, MACTXD(0) => 
        \mss_top_0/MSS_MAC_0_TXD_0_D\, MACRXD(1) => 
        \mss_top_0/MSS_MAC_0_RXD_1_Y\, MACRXD(0) => 
        \mss_top_0/MSS_MAC_0_RXD_0_Y\, MACTXEN => 
        \mss_top_0/MSS_MAC_0_TXEN_D\, MACCRSDV => 
        \mss_top_0/MSS_MAC_0_CRSDV_Y\, MACRXER => 
        \mss_top_0/MSS_MAC_0_RXER_Y\, MACMDI => 
        \mss_top_0/MSS_MAC_0_MDIO_Y\, MACMDO => 
        \mss_top_0/MSS_MAC_0_MDIO_D\, MACMDEN => 
        \mss_top_0/MSS_MAC_0_MDIO_E\, MACMDC => 
        \mss_top_0/MSS_MAC_0_MDC_D\, EMCCLK => 
        \mss_top_0/MSS_EMI_0_CLK_D\, EMCCLKRTN => 
        \mss_top_0/MSS_EMI_0_CLK_D\, EMCRDB(15) => 
        \mss_top_0/MSS_EMI_0_DB_15_Y\, EMCRDB(14) => 
        \mss_top_0/MSS_EMI_0_DB_14_Y\, EMCRDB(13) => 
        \mss_top_0/MSS_EMI_0_DB_13_Y\, EMCRDB(12) => 
        \mss_top_0/MSS_EMI_0_DB_12_Y\, EMCRDB(11) => 
        \mss_top_0/MSS_EMI_0_DB_11_Y\, EMCRDB(10) => 
        \mss_top_0/MSS_EMI_0_DB_10_Y\, EMCRDB(9) => 
        \mss_top_0/MSS_EMI_0_DB_9_Y\, EMCRDB(8) => 
        \mss_top_0/MSS_EMI_0_DB_8_Y\, EMCRDB(7) => 
        \mss_top_0/MSS_EMI_0_DB_7_Y\, EMCRDB(6) => 
        \mss_top_0/MSS_EMI_0_DB_6_Y\, EMCRDB(5) => 
        \mss_top_0/MSS_EMI_0_DB_5_Y\, EMCRDB(4) => 
        \mss_top_0/MSS_EMI_0_DB_4_Y\, EMCRDB(3) => 
        \mss_top_0/MSS_EMI_0_DB_3_Y\, EMCRDB(2) => 
        \mss_top_0/MSS_EMI_0_DB_2_Y\, EMCRDB(1) => 
        \mss_top_0/MSS_EMI_0_DB_1_Y\, EMCRDB(0) => 
        \mss_top_0/MSS_EMI_0_DB_0_Y\, EMCAB(25) => 
        \mss_top_0/MSS_EMI_0_AB_25_D\, EMCAB(24) => 
        \mss_top_0/MSS_EMI_0_AB_24_D\, EMCAB(23) => 
        \mss_top_0/MSS_EMI_0_AB_23_D\, EMCAB(22) => 
        \mss_top_0/MSS_EMI_0_AB_22_D\, EMCAB(21) => 
        \mss_top_0/MSS_EMI_0_AB_21_D\, EMCAB(20) => 
        \mss_top_0/MSS_EMI_0_AB_20_D\, EMCAB(19) => 
        \mss_top_0/MSS_EMI_0_AB_19_D\, EMCAB(18) => 
        \mss_top_0/MSS_EMI_0_AB_18_D\, EMCAB(17) => 
        \mss_top_0/MSS_EMI_0_AB_17_D\, EMCAB(16) => 
        \mss_top_0/MSS_EMI_0_AB_16_D\, EMCAB(15) => 
        \mss_top_0/MSS_EMI_0_AB_15_D\, EMCAB(14) => 
        \mss_top_0/MSS_EMI_0_AB_14_D\, EMCAB(13) => 
        \mss_top_0/MSS_EMI_0_AB_13_D\, EMCAB(12) => 
        \mss_top_0/MSS_EMI_0_AB_12_D\, EMCAB(11) => 
        \mss_top_0/MSS_EMI_0_AB_11_D\, EMCAB(10) => 
        \mss_top_0/MSS_EMI_0_AB_10_D\, EMCAB(9) => 
        \mss_top_0/MSS_EMI_0_AB_9_D\, EMCAB(8) => 
        \mss_top_0/MSS_EMI_0_AB_8_D\, EMCAB(7) => 
        \mss_top_0/MSS_EMI_0_AB_7_D\, EMCAB(6) => 
        \mss_top_0/MSS_EMI_0_AB_6_D\, EMCAB(5) => 
        \mss_top_0/MSS_EMI_0_AB_5_D\, EMCAB(4) => 
        \mss_top_0/MSS_EMI_0_AB_4_D\, EMCAB(3) => 
        \mss_top_0/MSS_EMI_0_AB_3_D\, EMCAB(2) => 
        \mss_top_0/MSS_EMI_0_AB_2_D\, EMCAB(1) => 
        \mss_top_0/MSS_EMI_0_AB_1_D\, EMCAB(0) => 
        \mss_top_0/MSS_EMI_0_AB_0_D\, EMCWDB(15) => 
        \mss_top_0/MSS_EMI_0_DB_15_D\, EMCWDB(14) => 
        \mss_top_0/MSS_EMI_0_DB_14_D\, EMCWDB(13) => 
        \mss_top_0/MSS_EMI_0_DB_13_D\, EMCWDB(12) => 
        \mss_top_0/MSS_EMI_0_DB_12_D\, EMCWDB(11) => 
        \mss_top_0/MSS_EMI_0_DB_11_D\, EMCWDB(10) => 
        \mss_top_0/MSS_EMI_0_DB_10_D\, EMCWDB(9) => 
        \mss_top_0/MSS_EMI_0_DB_9_D\, EMCWDB(8) => 
        \mss_top_0/MSS_EMI_0_DB_8_D\, EMCWDB(7) => 
        \mss_top_0/MSS_EMI_0_DB_7_D\, EMCWDB(6) => 
        \mss_top_0/MSS_EMI_0_DB_6_D\, EMCWDB(5) => 
        \mss_top_0/MSS_EMI_0_DB_5_D\, EMCWDB(4) => 
        \mss_top_0/MSS_EMI_0_DB_4_D\, EMCWDB(3) => 
        \mss_top_0/MSS_EMI_0_DB_3_D\, EMCWDB(2) => 
        \mss_top_0/MSS_EMI_0_DB_2_D\, EMCWDB(1) => 
        \mss_top_0/MSS_EMI_0_DB_1_D\, EMCWDB(0) => 
        \mss_top_0/MSS_EMI_0_DB_0_D\, EMCRWn => 
        \mss_top_0/MSS_EMI_0_RW_N_D\, EMCCS0n => 
        \mss_top_0/MSS_EMI_0_CS0_N_D\, EMCCS1n => 
        \mss_top_0/MSS_EMI_0_CS1_N_D\, EMCOEN0n => 
        \mss_top_0/MSS_EMI_0_OEN0_N_D\, EMCOEN1n => 
        \mss_top_0/MSS_EMI_0_OEN1_N_D\, EMCBYTEN(1) => 
        \mss_top_0/MSS_EMI_0_BYTEN_1_D\, EMCBYTEN(0) => 
        \mss_top_0/MSS_EMI_0_BYTEN_0_D\, EMCDBOE => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, ADC0 => GLMUXINT_GND, ADC1
         => GLMUXINT_GND, ADC2 => GLMUXINT_GND, ADC3 => 
        GLMUXINT_GND, ADC4 => GLMUXINT_GND, ADC5 => GLMUXINT_GND, 
        ADC6 => GLMUXINT_GND, ADC7 => GLMUXINT_GND, ADC8 => 
        GLMUXINT_GND, ADC9 => GLMUXINT_GND, ADC10 => GLMUXINT_GND, 
        ADC11 => GLMUXINT_GND, SDD0 => OPEN, SDD1 => OPEN, SDD2
         => OPEN, ABPS0 => GLMUXINT_GND, ABPS1 => GLMUXINT_GND, 
        ABPS2 => GLMUXINT_GND, ABPS3 => GLMUXINT_GND, ABPS4 => 
        GLMUXINT_GND, ABPS5 => GLMUXINT_GND, ABPS6 => 
        GLMUXINT_GND, ABPS7 => GLMUXINT_GND, ABPS8 => 
        GLMUXINT_GND, ABPS9 => GLMUXINT_GND, ABPS10 => 
        GLMUXINT_GND, ABPS11 => GLMUXINT_GND, TM0 => GLMUXINT_GND, 
        TM1 => GLMUXINT_GND, TM2 => GLMUXINT_GND, TM3 => 
        GLMUXINT_GND, TM4 => GLMUXINT_GND, TM5 => GLMUXINT_GND, 
        CM0 => GLMUXINT_GND, CM1 => GLMUXINT_GND, CM2 => 
        GLMUXINT_GND, CM3 => GLMUXINT_GND, CM4 => GLMUXINT_GND, 
        CM5 => GLMUXINT_GND, GNDTM0 => GLMUXINT_GND, GNDTM1 => 
        GLMUXINT_GND, GNDTM2 => GLMUXINT_GND, VAREF0 => 
        GLMUXINT_GND, VAREF1 => GLMUXINT_GND, VAREF2 => 
        GLMUXINT_GND, VAREFOUT => OPEN, GNDVAREF => GLMUXINT_GND, 
        PUn => GLMUXINT_GND, MSSHADDR(19) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[19]INT_NET\, 
        MSSHADDR(18) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[18]INT_NET\, 
        MSSHADDR(17) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[17]INT_NET\, 
        MSSHADDR(16) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[16]INT_NET\, 
        MSSHADDR(15) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[15]INT_NET\, 
        MSSHADDR(14) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[14]INT_NET\, 
        MSSHADDR(13) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[13]INT_NET\, 
        MSSHADDR(12) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[12]INT_NET\, 
        MSSHADDR(11) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[11]INT_NET\, 
        MSSHADDR(10) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[10]INT_NET\, 
        MSSHADDR(9) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[9]INT_NET\, 
        MSSHADDR(8) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[8]INT_NET\, 
        MSSHADDR(7) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[7]INT_NET\, 
        MSSHADDR(6) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[6]INT_NET\, 
        MSSHADDR(5) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[5]INT_NET\, 
        MSSHADDR(4) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[4]INT_NET\, 
        MSSHADDR(3) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[3]INT_NET\, 
        MSSHADDR(2) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[2]INT_NET\, 
        MSSHADDR(1) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[1]INT_NET\, 
        MSSHADDR(0) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHADDR[0]INT_NET\, 
        MSSHWDATA(31) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[31]INT_NET\, 
        MSSHWDATA(30) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[30]INT_NET\, 
        MSSHWDATA(29) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[29]INT_NET\, 
        MSSHWDATA(28) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[28]INT_NET\, 
        MSSHWDATA(27) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[27]INT_NET\, 
        MSSHWDATA(26) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[26]INT_NET\, 
        MSSHWDATA(25) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[25]INT_NET\, 
        MSSHWDATA(24) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[24]INT_NET\, 
        MSSHWDATA(23) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[23]INT_NET\, 
        MSSHWDATA(22) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[22]INT_NET\, 
        MSSHWDATA(21) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[21]INT_NET\, 
        MSSHWDATA(20) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[20]INT_NET\, 
        MSSHWDATA(19) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[19]INT_NET\, 
        MSSHWDATA(18) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[18]INT_NET\, 
        MSSHWDATA(17) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[17]INT_NET\, 
        MSSHWDATA(16) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[16]INT_NET\, 
        MSSHWDATA(15) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[15]INT_NET\, 
        MSSHWDATA(14) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[14]INT_NET\, 
        MSSHWDATA(13) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[13]INT_NET\, 
        MSSHWDATA(12) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[12]INT_NET\, 
        MSSHWDATA(11) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[11]INT_NET\, 
        MSSHWDATA(10) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[10]INT_NET\, 
        MSSHWDATA(9) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[9]INT_NET\, 
        MSSHWDATA(8) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[8]INT_NET\, 
        MSSHWDATA(7) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[7]INT_NET\, 
        MSSHWDATA(6) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[6]INT_NET\, 
        MSSHWDATA(5) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[5]INT_NET\, 
        MSSHWDATA(4) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[4]INT_NET\, 
        MSSHWDATA(3) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[3]INT_NET\, 
        MSSHWDATA(2) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[2]INT_NET\, 
        MSSHWDATA(1) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[1]INT_NET\, 
        MSSHWDATA(0) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[0]INT_NET\, 
        MSSHSIZE(1) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHSIZE[1]INT_NET\, 
        MSSHSIZE(0) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHSIZE[0]INT_NET\, 
        MSSHRDATA(31) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[31]INT_NET\, 
        MSSHRDATA(30) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[30]INT_NET\, 
        MSSHRDATA(29) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[29]INT_NET\, 
        MSSHRDATA(28) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[28]INT_NET\, 
        MSSHRDATA(27) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[27]INT_NET\, 
        MSSHRDATA(26) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[26]INT_NET\, 
        MSSHRDATA(25) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[25]INT_NET\, 
        MSSHRDATA(24) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[24]INT_NET\, 
        MSSHRDATA(23) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[23]INT_NET\, 
        MSSHRDATA(22) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[22]INT_NET\, 
        MSSHRDATA(21) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[21]INT_NET\, 
        MSSHRDATA(20) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[20]INT_NET\, 
        MSSHRDATA(19) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[19]INT_NET\, 
        MSSHRDATA(18) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[18]INT_NET\, 
        MSSHRDATA(17) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[17]INT_NET\, 
        MSSHRDATA(16) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[16]INT_NET\, 
        MSSHRDATA(15) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[15]INT_NET\, 
        MSSHRDATA(14) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[14]INT_NET\, 
        MSSHRDATA(13) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[13]INT_NET\, 
        MSSHRDATA(12) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[12]INT_NET\, 
        MSSHRDATA(11) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[11]INT_NET\, 
        MSSHRDATA(10) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[10]INT_NET\, 
        MSSHRDATA(9) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[9]INT_NET\, 
        MSSHRDATA(8) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[8]INT_NET\, 
        MSSHRDATA(7) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[7]INT_NET\, 
        MSSHRDATA(6) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[6]INT_NET\, 
        MSSHRDATA(5) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[5]INT_NET\, 
        MSSHRDATA(4) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[4]INT_NET\, 
        MSSHRDATA(3) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[3]INT_NET\, 
        MSSHRDATA(2) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[2]INT_NET\, 
        MSSHRDATA(1) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[1]INT_NET\, 
        MSSHRDATA(0) => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[0]INT_NET\, 
        FABHADDR(31) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[31]INT_NET\, 
        FABHADDR(30) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[30]INT_NET\, 
        FABHADDR(29) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[29]INT_NET\, 
        FABHADDR(28) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[28]INT_NET\, 
        FABHADDR(27) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[27]INT_NET\, 
        FABHADDR(26) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[26]INT_NET\, 
        FABHADDR(25) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[25]INT_NET\, 
        FABHADDR(24) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[24]INT_NET\, 
        FABHADDR(23) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[23]INT_NET\, 
        FABHADDR(22) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[22]INT_NET\, 
        FABHADDR(21) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[21]INT_NET\, 
        FABHADDR(20) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[20]INT_NET\, 
        FABHADDR(19) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[19]INT_NET\, 
        FABHADDR(18) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[18]INT_NET\, 
        FABHADDR(17) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[17]INT_NET\, 
        FABHADDR(16) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[16]INT_NET\, 
        FABHADDR(15) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[15]INT_NET\, 
        FABHADDR(14) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[14]INT_NET\, 
        FABHADDR(13) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[13]INT_NET\, 
        FABHADDR(12) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[12]INT_NET\, 
        FABHADDR(11) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[11]INT_NET\, 
        FABHADDR(10) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[10]INT_NET\, 
        FABHADDR(9) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[9]INT_NET\, 
        FABHADDR(8) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[8]INT_NET\, 
        FABHADDR(7) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[7]INT_NET\, 
        FABHADDR(6) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[6]INT_NET\, 
        FABHADDR(5) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[5]INT_NET\, 
        FABHADDR(4) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[4]INT_NET\, 
        FABHADDR(3) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[3]INT_NET\, 
        FABHADDR(2) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[2]INT_NET\, 
        FABHADDR(1) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[1]INT_NET\, 
        FABHADDR(0) => 
        \mss_top_0/MSS_ADLIB_INST/FABHADDR[0]INT_NET\, 
        FABHWDATA(31) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[31]INT_NET\, 
        FABHWDATA(30) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[30]INT_NET\, 
        FABHWDATA(29) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[29]INT_NET\, 
        FABHWDATA(28) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[28]INT_NET\, 
        FABHWDATA(27) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[27]INT_NET\, 
        FABHWDATA(26) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[26]INT_NET\, 
        FABHWDATA(25) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[25]INT_NET\, 
        FABHWDATA(24) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[24]INT_NET\, 
        FABHWDATA(23) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[23]INT_NET\, 
        FABHWDATA(22) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[22]INT_NET\, 
        FABHWDATA(21) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[21]INT_NET\, 
        FABHWDATA(20) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[20]INT_NET\, 
        FABHWDATA(19) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[19]INT_NET\, 
        FABHWDATA(18) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[18]INT_NET\, 
        FABHWDATA(17) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[17]INT_NET\, 
        FABHWDATA(16) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[16]INT_NET\, 
        FABHWDATA(15) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[15]INT_NET\, 
        FABHWDATA(14) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[14]INT_NET\, 
        FABHWDATA(13) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[13]INT_NET\, 
        FABHWDATA(12) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[12]INT_NET\, 
        FABHWDATA(11) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[11]INT_NET\, 
        FABHWDATA(10) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[10]INT_NET\, 
        FABHWDATA(9) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[9]INT_NET\, 
        FABHWDATA(8) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[8]INT_NET\, 
        FABHWDATA(7) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[7]INT_NET\, 
        FABHWDATA(6) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[6]INT_NET\, 
        FABHWDATA(5) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[5]INT_NET\, 
        FABHWDATA(4) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[4]INT_NET\, 
        FABHWDATA(3) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[3]INT_NET\, 
        FABHWDATA(2) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[2]INT_NET\, 
        FABHWDATA(1) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[1]INT_NET\, 
        FABHWDATA(0) => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[0]INT_NET\, 
        FABHSIZE(1) => 
        \mss_top_0/MSS_ADLIB_INST/FABHSIZE[1]INT_NET\, 
        FABHSIZE(0) => 
        \mss_top_0/MSS_ADLIB_INST/FABHSIZE[0]INT_NET\, 
        FABHRDATA(31) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[31]INT_NET\, 
        FABHRDATA(30) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[30]INT_NET\, 
        FABHRDATA(29) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[29]INT_NET\, 
        FABHRDATA(28) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[28]INT_NET\, 
        FABHRDATA(27) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[27]INT_NET\, 
        FABHRDATA(26) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[26]INT_NET\, 
        FABHRDATA(25) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[25]INT_NET\, 
        FABHRDATA(24) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[24]INT_NET\, 
        FABHRDATA(23) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[23]INT_NET\, 
        FABHRDATA(22) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[22]INT_NET\, 
        FABHRDATA(21) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[21]INT_NET\, 
        FABHRDATA(20) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[20]INT_NET\, 
        FABHRDATA(19) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[19]INT_NET\, 
        FABHRDATA(18) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[18]INT_NET\, 
        FABHRDATA(17) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[17]INT_NET\, 
        FABHRDATA(16) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[16]INT_NET\, 
        FABHRDATA(15) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[15]INT_NET\, 
        FABHRDATA(14) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[14]INT_NET\, 
        FABHRDATA(13) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[13]INT_NET\, 
        FABHRDATA(12) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[12]INT_NET\, 
        FABHRDATA(11) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[11]INT_NET\, 
        FABHRDATA(10) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[10]INT_NET\, 
        FABHRDATA(9) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[9]INT_NET\, 
        FABHRDATA(8) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[8]INT_NET\, 
        FABHRDATA(7) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[7]INT_NET\, 
        FABHRDATA(6) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[6]INT_NET\, 
        FABHRDATA(5) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[5]INT_NET\, 
        FABHRDATA(4) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[4]INT_NET\, 
        FABHRDATA(3) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[3]INT_NET\, 
        FABHRDATA(2) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[2]INT_NET\, 
        FABHRDATA(1) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[1]INT_NET\, 
        FABHRDATA(0) => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[0]INT_NET\, 
        DMAREADY(1) => 
        \mss_top_0/MSS_ADLIB_INST/DMAREADY[1]INT_NET\, 
        DMAREADY(0) => 
        \mss_top_0/MSS_ADLIB_INST/DMAREADY[0]INT_NET\, MSSINT(7)
         => \mss_top_0/MSS_ADLIB_INST/MSSINT[7]INT_NET\, 
        MSSINT(6) => \mss_top_0/MSS_ADLIB_INST/MSSINT[6]INT_NET\, 
        MSSINT(5) => \mss_top_0/MSS_ADLIB_INST/MSSINT[5]INT_NET\, 
        MSSINT(4) => \mss_top_0/MSS_ADLIB_INST/MSSINT[4]INT_NET\, 
        MSSINT(3) => \mss_top_0/MSS_ADLIB_INST/MSSINT[3]INT_NET\, 
        MSSINT(2) => \mss_top_0/MSS_ADLIB_INST/MSSINT[2]INT_NET\, 
        MSSINT(1) => \mss_top_0/MSS_ADLIB_INST/MSSINT[1]INT_NET\, 
        MSSINT(0) => \mss_top_0/MSS_ADLIB_INST/MSSINT[0]INT_NET\, 
        GPI(31) => \mss_top_0/MSS_ADLIB_INST/GPI[31]INT_NET\, 
        GPI(30) => \mss_top_0/MSS_ADLIB_INST/GPI[30]INT_NET\, 
        GPI(29) => \mss_top_0/MSS_ADLIB_INST/GPI[29]INT_NET\, 
        GPI(28) => \mss_top_0/MSS_ADLIB_INST/GPI[28]INT_NET\, 
        GPI(27) => \mss_top_0/MSS_ADLIB_INST/GPI[27]INT_NET\, 
        GPI(26) => \mss_top_0/MSS_ADLIB_INST/GPI[26]INT_NET\, 
        GPI(25) => \mss_top_0/MSS_ADLIB_INST/GPI[25]INT_NET\, 
        GPI(24) => \mss_top_0/MSS_ADLIB_INST/GPI[24]INT_NET\, 
        GPI(23) => \mss_top_0/MSS_ADLIB_INST/GPI[23]INT_NET\, 
        GPI(22) => \mss_top_0/MSS_ADLIB_INST/GPI[22]INT_NET\, 
        GPI(21) => \mss_top_0/MSS_ADLIB_INST/GPI[21]INT_NET\, 
        GPI(20) => \mss_top_0/MSS_ADLIB_INST/GPI[20]INT_NET\, 
        GPI(19) => \mss_top_0/MSS_ADLIB_INST/GPI[19]INT_NET\, 
        GPI(18) => \mss_top_0/MSS_ADLIB_INST/GPI[18]INT_NET\, 
        GPI(17) => \mss_top_0/MSS_ADLIB_INST/GPI[17]INT_NET\, 
        GPI(16) => \mss_top_0/MSS_ADLIB_INST/GPI[16]INT_NET\, 
        GPI(15) => GLMUXINT_GND, GPI(14) => GLMUXINT_GND, GPI(13)
         => GLMUXINT_GND, GPI(12) => GLMUXINT_GND, GPI(11) => 
        GLMUXINT_GND, GPI(10) => GLMUXINT_GND, GPI(9) => 
        GLMUXINT_GND, GPI(8) => GLMUXINT_GND, GPI(7) => 
        GLMUXINT_GND, GPI(6) => GLMUXINT_GND, GPI(5) => 
        GLMUXINT_GND, GPI(4) => GLMUXINT_GND, GPI(3) => 
        GLMUXINT_GND, GPI(2) => GLMUXINT_GND, GPI(1) => 
        GLMUXINT_GND, GPI(0) => 
        \mss_top_0/MSS_ADLIB_INST/GPI[0]INT_NET\, GPO(31) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[31]INT_NET\, GPO(30) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[30]INT_NET\, GPO(29) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[29]INT_NET\, GPO(28) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[28]INT_NET\, GPO(27) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[27]INT_NET\, GPO(26) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[26]INT_NET\, GPO(25) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[25]INT_NET\, GPO(24) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[24]INT_NET\, GPO(23) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[23]INT_NET\, GPO(22) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[22]INT_NET\, GPO(21) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[21]INT_NET\, GPO(20) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[20]INT_NET\, GPO(19) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[19]INT_NET\, GPO(18) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[18]INT_NET\, GPO(17) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[17]INT_NET\, GPO(16) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[16]INT_NET\, GPO(15) => 
        nc40, GPO(14) => nc31, GPO(13) => nc44, GPO(12) => nc7, 
        GPO(11) => nc6, GPO(10) => nc19, GPO(9) => nc29, GPO(8)
         => nc53, GPO(7) => nc39, GPO(6) => nc8, GPO(5) => nc43, 
        GPO(4) => nc20, GPO(3) => nc10, GPO(2) => nc24, GPO(1)
         => nc14, GPO(0) => 
        \mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET\, MACM2FTXD(1)
         => nc46, MACM2FTXD(0) => nc30, MACF2MRXD(1) => 
        GLMUXINT_GND, MACF2MRXD(0) => GLMUXINT_GND, ACEFLAGS(31)
         => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[31]INT_NET\, 
        ACEFLAGS(30) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[30]INT_NET\, 
        ACEFLAGS(29) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[29]INT_NET\, 
        ACEFLAGS(28) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[28]INT_NET\, 
        ACEFLAGS(27) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[27]INT_NET\, 
        ACEFLAGS(26) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[26]INT_NET\, 
        ACEFLAGS(25) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[25]INT_NET\, 
        ACEFLAGS(24) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[24]INT_NET\, 
        ACEFLAGS(23) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[23]INT_NET\, 
        ACEFLAGS(22) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[22]INT_NET\, 
        ACEFLAGS(21) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[21]INT_NET\, 
        ACEFLAGS(20) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[20]INT_NET\, 
        ACEFLAGS(19) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[19]INT_NET\, 
        ACEFLAGS(18) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[18]INT_NET\, 
        ACEFLAGS(17) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[17]INT_NET\, 
        ACEFLAGS(16) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[16]INT_NET\, 
        ACEFLAGS(15) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[15]INT_NET\, 
        ACEFLAGS(14) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[14]INT_NET\, 
        ACEFLAGS(13) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[13]INT_NET\, 
        ACEFLAGS(12) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[12]INT_NET\, 
        ACEFLAGS(11) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[11]INT_NET\, 
        ACEFLAGS(10) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[10]INT_NET\, 
        ACEFLAGS(9) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[9]INT_NET\, 
        ACEFLAGS(8) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[8]INT_NET\, 
        ACEFLAGS(7) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[7]INT_NET\, 
        ACEFLAGS(6) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[6]INT_NET\, 
        ACEFLAGS(5) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[5]INT_NET\, 
        ACEFLAGS(4) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[4]INT_NET\, 
        ACEFLAGS(3) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[3]INT_NET\, 
        ACEFLAGS(2) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[2]INT_NET\, 
        ACEFLAGS(1) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[1]INT_NET\, 
        ACEFLAGS(0) => 
        \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[0]INT_NET\, UART0CTSn
         => \mss_top_0/MSS_ADLIB_INST/UART0CTSnINT_NET\, 
        UART0DSRn => \mss_top_0/MSS_ADLIB_INST/UART0DSRnINT_NET\, 
        UART0RTSn => \mss_top_0/MSS_ADLIB_INST/UART0RTSnINT_NET\, 
        UART0DTRn => \mss_top_0/MSS_ADLIB_INST/UART0DTRnINT_NET\, 
        UART0RIn => \mss_top_0/MSS_ADLIB_INST/UART0RInINT_NET\, 
        UART0DCDn => \mss_top_0/MSS_ADLIB_INST/UART0DCDnINT_NET\, 
        UART1CTSn => \mss_top_0/MSS_ADLIB_INST/UART1CTSnINT_NET\, 
        UART1DSRn => \mss_top_0/MSS_ADLIB_INST/UART1DSRnINT_NET\, 
        UART1RIn => \mss_top_0/MSS_ADLIB_INST/UART1RInINT_NET\, 
        UART1DCDn => \mss_top_0/MSS_ADLIB_INST/UART1DCDnINT_NET\, 
        I2C0SMBALERTNO => 
        \mss_top_0/MSS_ADLIB_INST/I2C0SMBALERTNOINT_NET\, 
        I2C0BCLK => \mss_top_0/MSS_ADLIB_INST/I2C0BCLKINT_NET\, 
        I2C0SMBALERTNI => 
        \mss_top_0/MSS_ADLIB_INST/I2C0SMBALERTNIINT_NET\, 
        I2C0SMBUSNI => 
        \mss_top_0/MSS_ADLIB_INST/I2C0SMBUSNIINT_NET\, 
        I2C1SMBALERTNO => 
        \mss_top_0/MSS_ADLIB_INST/I2C1SMBALERTNOINT_NET\, 
        I2C1BCLK => \mss_top_0/MSS_ADLIB_INST/I2C1BCLKINT_NET\, 
        I2C1SMBALERTNI => 
        \mss_top_0/MSS_ADLIB_INST/I2C1SMBALERTNIINT_NET\, 
        I2C1SMBUSNI => 
        \mss_top_0/MSS_ADLIB_INST/I2C1SMBUSNIINT_NET\, UART1RTSn
         => \mss_top_0/MSS_ADLIB_INST/UART1RTSnINT_NET\, 
        UART1DTRn => \mss_top_0/MSS_ADLIB_INST/UART1DTRnINT_NET\, 
        TXEV => \mss_top_0/MSS_ADLIB_INST/TXEVINT_NET\, RXEV => 
        \mss_top_0/MSS_ADLIB_INST/RXEVINT_NET\, VRON => 
        \mss_top_0/MSS_ADLIB_INST/VRONINT_NET\, MACM2FTXEN => 
        OPEN, MACF2MCRSDV => GLMUXINT_GND, MACM2FMDEN => OPEN, 
        MACF2MRXER => GLMUXINT_GND, MACM2FMDO => OPEN, MACF2MMDI
         => GLMUXINT_GND, MACM2FMDC => OPEN, I2C0SMBUSNO => 
        \mss_top_0/MSS_ADLIB_INST/I2C0SMBUSNOINT_NET\, 
        I2C1SMBUSNO => 
        \mss_top_0/MSS_ADLIB_INST/I2C1SMBUSNOINT_NET\, CALIBOUT
         => \mss_top_0/MSS_ADLIB_INST/CALIBOUTINT_NET\, CALIBIN
         => \mss_top_0/MSS_ADLIB_INST/CALIBININT_NET\, LVTTL0 => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL0INT_NET\, LVTTL1 => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL1INT_NET\, LVTTL2 => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL2INT_NET\, LVTTL0EN => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL0ENINT_NET\, LVTTL1EN => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL1ENINT_NET\, LVTTL2EN => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL2ENINT_NET\, LVTTL3 => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL3INT_NET\, LVTTL4 => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL4INT_NET\, LVTTL5 => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL5INT_NET\, LVTTL3EN => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL3ENINT_NET\, LVTTL4EN => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL4ENINT_NET\, LVTTL5EN => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL5ENINT_NET\, LVTTL6 => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL6INT_NET\, LVTTL7 => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL7INT_NET\, LVTTL8 => OPEN, 
        LVTTL6EN => \mss_top_0/MSS_ADLIB_INST/LVTTL6ENINT_NET\, 
        LVTTL7EN => \mss_top_0/MSS_ADLIB_INST/LVTTL7ENINT_NET\, 
        LVTTL8EN => OPEN, LVTTL9 => OPEN, LVTTL10 => OPEN, 
        LVTTL11 => OPEN, LVTTL9EN => OPEN, LVTTL10EN => OPEN, 
        LVTTL11EN => OPEN, CMP0 => 
        \mss_top_0/MSS_ADLIB_INST/CMP0INT_NET\, CMP1 => 
        \mss_top_0/MSS_ADLIB_INST/CMP1INT_NET\, CMP2 => 
        \mss_top_0/MSS_ADLIB_INST/CMP2INT_NET\, CMP3 => 
        \mss_top_0/MSS_ADLIB_INST/CMP3INT_NET\, CMP4 => 
        \mss_top_0/MSS_ADLIB_INST/CMP4INT_NET\, CMP5 => 
        \mss_top_0/MSS_ADLIB_INST/CMP5INT_NET\, FABSDD0D => 
        \mss_top_0/MSS_ADLIB_INST/FABSDD0DINT_NET\, FABSDD1D => 
        \mss_top_0/MSS_ADLIB_INST/FABSDD1DINT_NET\, FABSDD2D => 
        OPEN, CMP6 => \mss_top_0/MSS_ADLIB_INST/CMP6INT_NET\, 
        CMP7 => \mss_top_0/MSS_ADLIB_INST/CMP7INT_NET\, CMP8 => 
        OPEN, FABACETRIG => 
        \mss_top_0/MSS_ADLIB_INST/FABACETRIGINT_NET\, CMP9 => 
        OPEN, FABSDD0CLK => 
        \mss_top_0/MSS_ADLIB_INST/FABSDD0CLKINT_NET\, FABSDD1CLK
         => \mss_top_0/MSS_ADLIB_INST/FABSDD1CLKINT_NET\, 
        FABSDD2CLK => OPEN, VCC15GOOD => 
        \mss_top_0/MSS_ADLIB_INST/VCC15GOODINT_NET\, VCC33GOOD
         => \mss_top_0/MSS_ADLIB_INST/VCC33GOODINT_NET\, PUFABn
         => \mss_top_0/MSS_ADLIB_INST/PUFABnINT_NET\, DEEPSLEEP
         => \mss_top_0/MSS_ADLIB_INST/DEEPSLEEPINT_NET\, SLEEP
         => \mss_top_0/MSS_ADLIB_INST/SLEEPINT_NET\, M2FRESETn
         => \mss_top_0/MSS_ADLIB_INST/M2FRESETnINT_NET\, WDINT
         => \mss_top_0/MSS_ADLIB_INST/WDINTINT_NET\, MSSHREADY
         => \mss_top_0/MSS_ADLIB_INST/MSSHREADYINT_NET\, MSSHRESP
         => \mss_top_0/MSS_ADLIB_INST/MSSHRESPINT_NET\, MSSHLOCK
         => \mss_top_0/MSS_ADLIB_INST/MSSHLOCKINT_NET\, 
        FABHMASTLOCK => 
        \mss_top_0/MSS_ADLIB_INST/FABHMASTLOCKINT_NET\, 
        MSSHTRANS1 => 
        \mss_top_0/MSS_ADLIB_INST/MSSHTRANS1INT_NET\, MSSHWRITE
         => \mss_top_0/MSS_ADLIB_INST/MSSHWRITEINT_NET\, FABINT
         => \mss_top_0/MSS_ADLIB_INST/FABINTINT_NET\, FABHTRANS1
         => \mss_top_0/MSS_ADLIB_INST/FABHTRANS1INT_NET\, FABHSEL
         => \mss_top_0/MSS_ADLIB_INST/FABHSELINT_NET\, F2MRESETn
         => \mss_top_0/MSS_ADLIB_INST/F2MRESETnINT_NET\, 
        SYNCCLKFDBK => 
        \mss_top_0/MSS_ADLIB_INST/SYNCCLKFDBKINT_NET\, 
        FABHREADYOUT => 
        \mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET\, FABHRESP
         => \mss_top_0/MSS_ADLIB_INST/FABHRESPINT_NET\, FABHWRITE
         => \mss_top_0/MSS_ADLIB_INST/FABHWRITEINT_NET\, 
        FABHREADY => \mss_top_0/MSS_ADLIB_INST/FABHREADYINT_NET\, 
        CMP10 => OPEN, CMP11 => OPEN);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[6]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HWRITE_DATA_TEMP[6]/Y\, 
        CLK => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q
         => \\\fic_master_trans_0_HWDATA_[6]\\\);
    
    \mss_top_0/MSS_CCC_0/I_XTLOSC\ : MSS_XTLOSC
      port map(XTL => MAINXIN, CLKOUT => 
        \mss_top_0/MSS_CCC_0/N_CLKA_XTLOSC\);
    
    \mss_top_0/MSS_ADLIB_INST/U_42\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => GLMUXINT_GND, PIN2INT => GLMUXINT_GND, PIN3INT
         => GLMUXINT_GND);
    
    \fic_master_trans_0/un2_haddr_temp_I_173\ : XOR2
      port map(A => \fic_master_trans_0/N_30\, B => 
        \\\fic_master_trans_0_HADDR_[27]\\\, Y => 
        \fic_master_trans_0/I_173\);
    
    \mss_top_0/MSS_EMI_0_AB_19\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_19_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(19));
    
    \fic_master_trans_0/HADDR_TEMP[21]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[21]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[21]\\\);
    
    \mss_top_0/MSS_ADLIB_INST/U_8\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/UART0DCDnINT_NET\, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/UART0RInINT_NET\, PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/UART1CTSnINT_NET\, PIN1INT => 
        \mss_top_0/MSS_ADLIB_INST/SPI0SSO[3]INT_NET\, PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/UART0RTSnINT_NET\, PIN3INT => 
        \mss_top_0/MSS_ADLIB_INST/UART0DTRnINT_NET\);
    
    \mss_top_0/MSS_EMI_0_AB_13\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_13_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(13));
    
    \mss_top_0/MSS_EMI_0_OEN1_N\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_OEN1_N_D\, E => 
        PLLEN_VCC, PAD => EMC_OEN1_N);
    
    \fic_master_trans_0/HADDR_TEMP[11]/U1\ : DFN1P0
      port map(D => \fic_master_trans_0/HADDR_TEMP[11]/Y\, CLK
         => \FAB_CLK\, PRE => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[11]\\\);
    
    \mss_top_0/MSS_EMI_0_DB_15\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_15_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_15_Y\, PAD => EMC_DB(15));
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNI7LN21[1]\ : NOR2B
      port map(A => \fic_master_trans_0/un12_hreadyout\, B => 
        FABHREADYOUT_c, Y => \fic_master_trans_0/un9_hreadyout\);
    
    \fic_master_trans_0/HADDR_TEMP[2]/U1\ : DFN1P0
      port map(D => \fic_master_trans_0/HADDR_TEMP[2]/Y\, CLK => 
        \FAB_CLK\, PRE => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[2]\\\);
    
    \mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE0\ : MSS_CCC_IF
      port map(PIN2 => GLMUXINT_GND, PIN3 => GLMUXINT_GND, PIN4
         => GLMUXINT_GND, PIN1 => OPEN, PIN2INT => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/SDIN_INT\, PIN3INT => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/SCLK_INT\, PIN4INT => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/SSHIFT_INT\, PIN1INT => 
        \mss_top_0/MSS_CCC_0/I_MSSCCC/SDOUT_INT\);
    
    \M2F_GPO_0_pad/U0/U1\ : IOTRI_OB_EB
      port map(D => \mss_top_0/MSSINT_GPO_0_A\, E => PLLEN_VCC, 
        DOUT => \M2F_GPO_0_pad/U0/NET1\, EOUT => 
        \M2F_GPO_0_pad/U0/NET2\);
    
    \fic_master_trans_0/un2_haddr_temp_I_125\ : AND2
      port map(A => \\\fic_master_trans_0_HADDR_[20]\\\, B => 
        \\\fic_master_trans_0_HADDR_[21]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[14]\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[1]/U0\ : MX2
      port map(A => \fic_master_trans_0/HWRITE_DATA_TEMP_n1\, B
         => \\\fic_master_trans_0_HWDATA_[1]\\\, S => 
        \fic_master_trans_0/HWRITE_DATA_TEMPe\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP[1]/Y\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[2]/U0\ : MX2
      port map(A => \fic_master_trans_0/HWRITE_DATA_TEMP_n2\, B
         => \\\fic_master_trans_0_HWDATA_[2]\\\, S => 
        \fic_master_trans_0/HWRITE_DATA_TEMPe\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP[2]/Y\);
    
    \mss_top_0/MSS_ADLIB_INST/U_72\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABSDD1DINT_NET\, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/FABSDD0DINT_NET\, PIN6INT => 
        OPEN, PIN1INT => \mss_top_0/MSS_ADLIB_INST/CMP3INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/CMP4INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/CMP5INT_NET\);
    
    \fic_master_trans_0/HSEL_RNO\ : NOR2B
      port map(A => \fic_master_trans_0/ahb_states[0]_net_1\, B
         => \fic_master_trans_0/un9_hreadyout\, Y => 
        \fic_master_trans_0/HADDR_TEMP_0_sqmuxa\);
    
    \mss_top_0/MSS_EMI_0_AB_1\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_1_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(1));
    
    \mss_top_0/MSS_EMI_0_AB_0\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_0_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(0));
    
    \mss_top_0/MSS_ADLIB_INST/U_57\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[29]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[28]INT_NET\, 
        PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[30]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[28]INT_NET\, 
        PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[29]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[30]INT_NET\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP[4]/U0\ : MX2
      port map(A => \fic_master_trans_0/HWRITE_DATA_TEMP_n4\, B
         => \\\fic_master_trans_0_HWDATA_[4]\\\, S => 
        \fic_master_trans_0/HWRITE_DATA_TEMPe\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP[4]/Y\);
    
    \mss_top_0/MSS_EMI_0_AB_12\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_12_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(12));
    
    \mss_top_0/MSS_ADLIB_INST/U_58\ : MSS_IF
      port map(PIN4 => PLLEN_VCC, PIN5 => GLMUXINT_GND, PIN6 => 
        GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => OPEN, 
        PIN4INT => \mss_top_0/MSS_ADLIB_INST/MSSHREADYINT_NET\, 
        PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[31]INT_NET\, PIN6INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHRESPINT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[31]INT_NET\, 
        PIN2INT => GLMUXINT_GND, PIN3INT => GLMUXINT_GND);
    
    \mss_top_0/MSS_EMI_0_AB_15\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_15_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(15));
    
    \fic_master_trans_0/un2_haddr_temp_I_182\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[7]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[9]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[12]\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[30]\);
    
    \mss_top_0/MSS_ADLIB_INST/U_62\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL1ENINT_NET\, PIN5INT => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL0ENINT_NET\, PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL2ENINT_NET\, PIN1INT => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL0INT_NET\, PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL1INT_NET\, PIN3INT => 
        \mss_top_0/MSS_ADLIB_INST/LVTTL2INT_NET\);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNIPM28[0]\ : NOR2B
      port map(A => \\\fic_master_trans_0_HWDATA_[1]\\\, B => 
        \\\fic_master_trans_0_HWDATA_[0]\\\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP_c1\);
    
    \fic_master_trans_0/HADDR_TEMP[22]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[22]\\\, B => 
        \fic_master_trans_0/I_129\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[22]/Y\);
    
    \mss_top_0/MSS_EMI_0_DB_6\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_6_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_6_Y\, PAD => EMC_DB(6));
    
    \mss_top_0/MSS_UART_1_RXD\ : IOPAD_IN
      port map(PAD => UART_1_RXD, Y => 
        \mss_top_0/MSS_UART_1_RXD_Y\);
    
    \mss_top_0/MSS_EMI_0_DB_2\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_2_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_2_Y\, PAD => EMC_DB(2));
    
    \fic_master_trans_0/un2_haddr_temp_I_146\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[15]\, B => 
        \\\fic_master_trans_0_HADDR_[23]\\\, C => 
        \\\fic_master_trans_0_HADDR_[24]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[33]\);
    
    \fic_master_trans_0/HADDR_TEMP[28]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[28]\\\, B => 
        \fic_master_trans_0/I_186\, S => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, Y => 
        \fic_master_trans_0/HADDR_TEMP[28]/Y\);
    
    \fic_master_trans_0/ahb_states[0]\ : DFN1C0
      port map(D => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \fic_master_trans_0/ahb_states[0]_net_1\);
    
    \mss_top_0/MSS_EMI_0_AB_4\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_4_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(4));
    
    \fic_master_trans_0/un2_haddr_temp_I_202\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[24]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[23]\, C => 
        \\\fic_master_trans_0_HADDR_[29]\\\, Y => 
        \fic_master_trans_0/N_9\);
    
    \fic_master_trans_0/HADDR_TEMP[12]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[12]\\\, B => 
        \fic_master_trans_0/I_56\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[12]/Y\);
    
    \mss_top_0/MSS_ADLIB_INST/U_56\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[26]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[25]INT_NET\, 
        PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[27]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[25]INT_NET\, 
        PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[26]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[27]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_90\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[6]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[7]\, C => 
        \fic_master_trans_0/DWACT_FINC_E[9]\, Y => 
        \fic_master_trans_0/N_88\);
    
    \mss_top_0/MSS_SPI_0_DI\ : IOPAD_IN
      port map(PAD => SPI_0_DI, Y => \mss_top_0/MSS_SPI_0_DI_Y\);
    
    \fic_master_trans_0/un2_haddr_temp_I_97\ : AND3
      port map(A => \fic_master_trans_0/DWACT_FINC_E[6]\, B => 
        \fic_master_trans_0/DWACT_FINC_E[10]\, C => 
        \\\fic_master_trans_0_HADDR_[17]\\\, Y => 
        \fic_master_trans_0/N_83\);
    
    \fic_master_trans_0/un2_haddr_temp_I_166\ : XOR2
      port map(A => \fic_master_trans_0/N_35\, B => 
        \\\fic_master_trans_0_HADDR_[26]\\\, Y => 
        \fic_master_trans_0/I_166\);
    
    \mss_top_0/MSS_ADLIB_INST/U_81\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[17]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[18]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[19]INT_NET\);
    
    \fic_master_trans_0/HADDR_TEMP[18]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[18]\\\, B => 
        \fic_master_trans_0/I_98\, S => 
        \fic_master_trans_0/un2_hreadyout_0[0]\, Y => 
        \fic_master_trans_0/HADDR_TEMP[18]/Y\);
    
    \mss_top_0/MSS_ADLIB_INST/U_53\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[17]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[16]INT_NET\, 
        PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[18]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[16]INT_NET\, 
        PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[17]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[18]INT_NET\);
    
    \fic_master_trans_0/HADDR_TEMP[25]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[25]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[25]\\\);
    
    \fic_master_trans_0/un2_haddr_temp_I_31\ : XOR2
      port map(A => \fic_master_trans_0/N_131\, B => 
        \\\fic_master_trans_0_HADDR_[8]\\\, Y => 
        \fic_master_trans_0/I_31\);
    
    \fic_master_trans_0/HADDR_TEMP[15]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[15]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[15]\\\);
    
    \fic_master_trans_0/ahb_states_RNIHRUB2_0[0]\ : MX2
      port map(A => \fic_master_trans_0/un1_hreadyout\, B => 
        \fic_master_trans_0/un9_hreadyout\, S => 
        \fic_master_trans_0/ahb_states[0]_net_1\, Y => 
        \fic_master_trans_0/un2_hreadyout_0[0]\);
    
    \mss_top_0/MSS_EMI_0_AB_9\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_AB_9_D\, E => PLLEN_VCC, 
        PAD => EMC_AB(9));
    
    \mss_top_0/MSS_ADLIB_INST/U_80\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[14]INT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[15]INT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/ACEFLAGS[16]INT_NET\);
    
    \mss_top_0/MSS_ADLIB_INST/U_93\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => OPEN, PIN5INT => OPEN, PIN6INT => OPEN, 
        PIN1INT => \mss_top_0/MSS_ADLIB_INST/I2C0SMBUSNOINT_NET\, 
        PIN2INT => \mss_top_0/MSS_ADLIB_INST/I2C1SMBUSNOINT_NET\, 
        PIN3INT => \mss_top_0/MSS_ADLIB_INST/CALIBOUTINT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_16\ : AND3
      port map(A => \\\fic_master_trans_0_HADDR_[2]\\\, B => 
        \\\fic_master_trans_0_HADDR_[3]\\\, C => 
        \\\fic_master_trans_0_HADDR_[4]\\\, Y => 
        \fic_master_trans_0/DWACT_FINC_E[0]\);
    
    \fic_master_trans_0/HADDR_TEMP[31]/U1\ : DFN1C0
      port map(D => \fic_master_trans_0/HADDR_TEMP[31]/Y\, CLK
         => \FAB_CLK\, CLR => \mss_top_0/MSSINT_GPO_0_A\, Q => 
        \\\fic_master_trans_0_HADDR_[31]\\\);
    
    \FAB_CLK_pad/U0/U0\ : IOPAD_TRI
      port map(D => \FAB_CLK_pad/U0/NET1\, E => 
        \FAB_CLK_pad/U0/NET2\, PAD => FAB_CLK);
    
    \fic_master_trans_0/HWRITE_DATA_TEMP_RNO[5]\ : XOR2
      port map(A => \fic_master_trans_0/HWRITE_DATA_TEMP_c4\, B
         => \\\fic_master_trans_0_HWDATA_[5]\\\, Y => 
        \fic_master_trans_0/HWRITE_DATA_TEMP_n5\);
    
    \mss_top_0/MSS_I2C_1_SCL\ : IOPAD_BI
      port map(D => GLMUXINT_GND, E => 
        \mss_top_0/MSS_I2C_1_SCL_E\, Y => 
        \mss_top_0/MSS_I2C_1_SCL_Y\, PAD => I2C_1_SCL);
    
    \mss_top_0/MSS_EMI_0_OEN0_N\ : IOPAD_TRI
      port map(D => \mss_top_0/MSS_EMI_0_OEN0_N_D\, E => 
        PLLEN_VCC, PAD => EMC_OEN0_N);
    
    \mss_top_0/MSS_ADLIB_INST/U_89\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[26]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/FABHWDATA[25]INT_NET\, 
        PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHWDATA[27]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[25]INT_NET\, 
        PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/FABHRDATA[26]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/FABHRDATA[27]INT_NET\);
    
    \mss_top_0/MSS_ADLIB_INST/U_55\ : MSS_IF
      port map(PIN4 => GLMUXINT_GND, PIN5 => GLMUXINT_GND, PIN6
         => GLMUXINT_GND, PIN1 => OPEN, PIN2 => OPEN, PIN3 => 
        OPEN, PIN4INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[23]INT_NET\, PIN5INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[22]INT_NET\, 
        PIN6INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHRDATA[24]INT_NET\, PIN1INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[22]INT_NET\, 
        PIN2INT => 
        \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[23]INT_NET\, PIN3INT
         => \mss_top_0/MSS_ADLIB_INST/MSSHWDATA[24]INT_NET\);
    
    \fic_master_trans_0/un2_haddr_temp_I_24\ : XOR2
      port map(A => \fic_master_trans_0/N_136\, B => 
        \\\fic_master_trans_0_HADDR_[7]\\\, Y => 
        \fic_master_trans_0/I_24\);
    
    \fic_master_trans_0/HADDR_TEMP[9]/U0\ : MX2
      port map(A => \\\fic_master_trans_0_HADDR_[9]\\\, B => 
        \fic_master_trans_0/I_38\, S => 
        \fic_master_trans_0/ahb_states_RNIHRUB2[0]_net_1\, Y => 
        \fic_master_trans_0/HADDR_TEMP[9]/Y\);
    
    \mss_top_0/MSS_EMI_0_DB_10\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_10_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_10_Y\, PAD => EMC_DB(10));
    
    \mss_top_0/MSS_EMI_0_DB_7\ : IOPAD_BI
      port map(D => \mss_top_0/MSS_EMI_0_DB_7_D\, E => 
        \mss_top_0/MSS_EMI_0_DB_15_E\, Y => 
        \mss_top_0/MSS_EMI_0_DB_7_Y\, PAD => EMC_DB(7));
    
    \FABHREADYOUT_pad/U0/U0\ : IOPAD_TRI
      port map(D => \FABHREADYOUT_pad/U0/NET1\, E => 
        \FABHREADYOUT_pad/U0/NET2\, PAD => FABHREADYOUT);
    
    GND_power_inst1 : GND
      port map( Y => GND_power_net1);

    VCC_power_inst1 : VCC
      port map( Y => VCC_power_net1);


end DEF_ARCH; 
