Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Dec 07 16:54:04 2011


Design: top_level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      8.254
Max Clock-To-Out (ns):      16.310

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      8.883
Max Clock-To-Out (ns):      16.861

Clock Domain:               mss_ccc_gla1
Period (ns):                9.424
Frequency (MHz):            106.112
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.206
External Hold (ns):         4.012
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                25.000
Frequency (MHz):            40.000
Required Period (ns):       20.833
Required Frequency (MHz):   48.001
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               Input_clk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      5.789
Max Clock-To-Out (ns):      9.891

Clock Domain:               FAB_CLK
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          FABHREADYOUT
  Delay (ns):                  5.305
  Slack (ns):
  Arrival (ns):                8.254
  Required (ns):
  Clock to Out (ns):           8.254


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: FABHREADYOUT
  data arrival time                              8.254
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     2.454          cell: ADLIB:MSS_AHB_IP
  5.403                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (r)
               +     0.080          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  5.483                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (r)
               +     0.042          cell: ADLIB:MSS_IF
  5.525                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (r)
               +     1.331          net: FABHREADYOUT_c
  6.856                        FABHREADYOUT_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  7.135                        FABHREADYOUT_pad/U0/U1:DOUT (r)
               +     0.000          net: FABHREADYOUT_pad/U0/NET1
  7.135                        FABHREADYOUT_pad/U0/U0:D (r)
               +     1.119          cell: ADLIB:IOPAD_TRI
  8.254                        FABHREADYOUT_pad/U0/U0:PAD (r)
               +     0.000          net: FABHREADYOUT
  8.254                        FABHREADYOUT (r)
                                    
  8.254                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  N/C
                                    
  N/C                          FABHREADYOUT (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[2]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[2]
  Delay (ns):                  1.097
  Slack (ns):                  1.179
  Arrival (ns):                5.467
  Required (ns):               4.288
  Hold (ns):                   1.339

Path 2
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[0]:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[0]
  Delay (ns):                  1.190
  Slack (ns):                  1.273
  Arrival (ns):                5.560
  Required (ns):               4.287
  Hold (ns):                   1.338

Path 3
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[3]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[3]
  Delay (ns):                  1.198
  Slack (ns):                  1.282
  Arrival (ns):                5.568
  Required (ns):               4.286
  Hold (ns):                   1.337

Path 4
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[5]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[5]
  Delay (ns):                  1.224
  Slack (ns):                  1.305
  Arrival (ns):                5.594
  Required (ns):               4.289
  Hold (ns):                   1.340

Path 5
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[4]
  Delay (ns):                  1.301
  Slack (ns):                  1.384
  Arrival (ns):                5.671
  Required (ns):               4.287
  Hold (ns):                   1.338


Expanded Path 1
  From: fic_master_trans_0/HWRITE_DATA_TEMP[2]/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[2]
  data arrival time                              5.467
  data required time                         -   4.288
  slack                                          1.179
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.335          net: FAB_CLK
  4.370                        fic_master_trans_0/HWRITE_DATA_TEMP[2]/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.619                        fic_master_trans_0/HWRITE_DATA_TEMP[2]/U1:Q (r)
               +     0.609          net: _fic_master_trans_0_HWDATA_[2]_
  5.228                        mss_top_0/MSS_ADLIB_INST/U_48:PIN4 (r)
               +     0.037          cell: ADLIB:MSS_IF
  5.265                        mss_top_0/MSS_ADLIB_INST/U_48:PIN4INT (r)
               +     0.202          net: mss_top_0/MSS_ADLIB_INST/FABHWDATA[2]INT_NET
  5.467                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[2] (r)
                                    
  5.467                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.339          Library hold time: ADLIB:MSS_AHB_IP
  4.288                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[2]
                                    
  4.288                        data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_0
  Delay (ns):                  5.934
  Slack (ns):
  Arrival (ns):                8.883
  Required (ns):
  Clock to Out (ns):           8.883


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: M2F_GPO_0
  data arrival time                              8.883
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     2.949          Clock generation
  2.949
               +     2.091          cell: ADLIB:MSS_AHB_IP
  5.040                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  5.040                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (r)
               +     0.042          cell: ADLIB:MSS_IF
  5.082                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (r)
               +     2.434          net: mss_top_0/MSSINT_GPO_0_A
  7.516                        M2F_GPO_0_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  7.795                        M2F_GPO_0_pad/U0/U1:DOUT (r)
               +     0.000          net: M2F_GPO_0_pad/U0/NET1
  7.795                        M2F_GPO_0_pad/U0/U0:D (r)
               +     1.088          cell: ADLIB:IOPAD_TRI
  8.883                        M2F_GPO_0_pad/U0/U0:PAD (r)
               +     0.000          net: M2F_GPO_0
  8.883                        M2F_GPO_0 (r)
                                    
  8.883                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     2.949          Clock generation
  N/C
                                    
  N/C                          M2F_GPO_0 (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        fic_master_trans_0/HADDR_TEMP[0]:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[0]:D
  Delay (ns):                  0.586
  Slack (ns):                  0.571
  Arrival (ns):                4.946
  Required (ns):               4.375
  Hold (ns):                   0.000

Path 2
  From:                        fic_master_trans_0/HADDR_TEMP[1]:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[1]:D
  Delay (ns):                  0.660
  Slack (ns):                  0.645
  Arrival (ns):                5.020
  Required (ns):               4.375
  Hold (ns):                   0.000

Path 3
  From:                        fic_master_trans_0/ahb_states[0]:CLK
  To:                          fic_master_trans_0/ahb_states[0]:D
  Delay (ns):                  0.780
  Slack (ns):                  0.764
  Arrival (ns):                5.145
  Required (ns):               4.381
  Hold (ns):                   0.000

Path 4
  From:                        fic_master_trans_0/HADDR_TEMP[24]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[24]/U1:D
  Delay (ns):                  0.792
  Slack (ns):                  0.770
  Arrival (ns):                5.188
  Required (ns):               4.418
  Hold (ns):                   0.000

Path 5
  From:                        fic_master_trans_0/HSEL/U1:CLK
  To:                          fic_master_trans_0/HSEL/U1:D
  Delay (ns):                  0.813
  Slack (ns):                  0.796
  Arrival (ns):                5.180
  Required (ns):               4.384
  Hold (ns):                   0.000


Expanded Path 1
  From: fic_master_trans_0/HADDR_TEMP[0]:CLK
  To: fic_master_trans_0/HADDR_TEMP[0]:D
  data arrival time                              4.946
  data required time                         -   4.375
  slack                                          0.571
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.325          net: FAB_CLK
  4.360                        fic_master_trans_0/HADDR_TEMP[0]:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.609                        fic_master_trans_0/HADDR_TEMP[0]:Q (r)
               +     0.337          net: _fic_master_trans_0_HADDR_[0]_
  4.946                        fic_master_trans_0/HADDR_TEMP[0]:D (r)
                                    
  4.946                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.340          net: FAB_CLK
  4.375                        fic_master_trans_0/HADDR_TEMP[0]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.375                        fic_master_trans_0/HADDR_TEMP[0]:D
                                    
  4.375                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HSEL/U1:D
  Delay (ns):                  4.708
  Slack (ns):                  3.273
  Arrival (ns):                7.657
  Required (ns):               4.384
  Hold (ns):                   0.000

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/ahb_states[0]:D
  Delay (ns):                  4.779
  Slack (ns):                  3.347
  Arrival (ns):                7.728
  Required (ns):               4.381
  Hold (ns):                   0.000

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[3]/U1:D
  Delay (ns):                  5.002
  Slack (ns):                  3.564
  Arrival (ns):                7.951
  Required (ns):               4.387
  Hold (ns):                   0.000

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[5]/U1:D
  Delay (ns):                  5.002
  Slack (ns):                  3.564
  Arrival (ns):                7.951
  Required (ns):               4.387
  Hold (ns):                   0.000

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[7]/U1:D
  Delay (ns):                  5.002
  Slack (ns):                  3.567
  Arrival (ns):                7.951
  Required (ns):               4.384
  Hold (ns):                   0.000


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: fic_master_trans_0/HSEL/U1:D
  data arrival time                              7.657
  data required time                         -   4.384
  slack                                          3.273
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     2.454          cell: ADLIB:MSS_AHB_IP
  5.403                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (r)
               +     0.080          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  5.483                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (r)
               +     0.042          cell: ADLIB:MSS_IF
  5.525                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (r)
               +     1.013          net: FABHREADYOUT_c
  6.538                        fic_master_trans_0/HWRITE_DATA_TEMP_RNI7LN21[1]:B (r)
               +     0.221          cell: ADLIB:NOR2B
  6.759                        fic_master_trans_0/HWRITE_DATA_TEMP_RNI7LN21[1]:Y (r)
               +     0.156          net: fic_master_trans_0/un9_hreadyout
  6.915                        fic_master_trans_0/HSEL_RNO:B (r)
               +     0.253          cell: ADLIB:NOR2B
  7.168                        fic_master_trans_0/HSEL_RNO:Y (r)
               +     0.138          net: fic_master_trans_0/HADDR_TEMP_0_sqmuxa
  7.306                        fic_master_trans_0/HSEL/U0:S (r)
               +     0.203          cell: ADLIB:MX2
  7.509                        fic_master_trans_0/HSEL/U0:Y (f)
               +     0.148          net: fic_master_trans_0/HSEL/Y
  7.657                        fic_master_trans_0/HSEL/U1:D (f)
                                    
  7.657                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.349          net: FAB_CLK
  4.384                        fic_master_trans_0/HSEL/U1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.384                        fic_master_trans_0/HSEL/U1:D
                                    
  4.384                        data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_pclk1 to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[15]/U1:CLR
  Delay (ns):                  2.804
  Slack (ns):                  1.335
  Arrival (ns):                5.753
  Required (ns):               4.418
  Hold (ns):

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[8]/U1:PRE
  Delay (ns):                  2.839
  Slack (ns):                  1.407
  Arrival (ns):                5.788
  Required (ns):               4.381
  Hold (ns):

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[5]/U1:PRE
  Delay (ns):                  2.857
  Slack (ns):                  1.422
  Arrival (ns):                5.806
  Required (ns):               4.384
  Hold (ns):

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[19]/U1:CLR
  Delay (ns):                  2.901
  Slack (ns):                  1.439
  Arrival (ns):                5.850
  Required (ns):               4.411
  Hold (ns):

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HADDR_TEMP[4]/U1:PRE
  Delay (ns):                  2.876
  Slack (ns):                  1.441
  Arrival (ns):                5.825
  Required (ns):               4.384
  Hold (ns):


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: fic_master_trans_0/HADDR_TEMP[15]/U1:CLR
  data arrival time                              5.753
  data required time                         -   4.418
  slack                                          1.335
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     2.949          Clock generation
  2.949
               +     2.091          cell: ADLIB:MSS_AHB_IP
  5.040                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  5.040                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (r)
               +     0.042          cell: ADLIB:MSS_IF
  5.082                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (r)
               +     0.671          net: mss_top_0/MSSINT_GPO_0_A
  5.753                        fic_master_trans_0/HADDR_TEMP[15]/U1:CLR (r)
                                    
  5.753                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.383          net: FAB_CLK
  4.418                        fic_master_trans_0/HADDR_TEMP[15]/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  4.418                        fic_master_trans_0/HADDR_TEMP[15]/U1:CLR
                                    
  4.418                        data required time


END SET mss_pclk1 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.277
  Slack (ns):
  Arrival (ns):                0.277
  Required (ns):
  Hold (ns):                   1.294
  External Hold (ns):          4.012


Expanded Path 1
  From: MSS_RESET_N
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.277
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        mss_top_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        mss_top_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: mss_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.277                        mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.277                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.271          net: mss_top_0/GLA0
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.294          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_ccc_gla0

Path 1
  From:                        fic_master_trans_0/HADDR_TEMP[28]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[28]
  Delay (ns):                  0.835
  Slack (ns):                  0.882
  Arrival (ns):                5.198
  Required (ns):               4.316
  Hold (ns):                   1.321

Path 2
  From:                        fic_master_trans_0/HADDR_TEMP[31]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[31]
  Delay (ns):                  0.829
  Slack (ns):                  0.901
  Arrival (ns):                5.188
  Required (ns):               4.287
  Hold (ns):                   1.292

Path 3
  From:                        fic_master_trans_0/HADDR_TEMP[20]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[20]
  Delay (ns):                  0.867
  Slack (ns):                  0.977
  Arrival (ns):                5.263
  Required (ns):               4.286
  Hold (ns):                   1.291

Path 4
  From:                        fic_master_trans_0/HADDR_TEMP[16]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[16]
  Delay (ns):                  0.869
  Slack (ns):                  0.980
  Arrival (ns):                5.265
  Required (ns):               4.285
  Hold (ns):                   1.290

Path 5
  From:                        fic_master_trans_0/HADDR_TEMP[15]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[15]
  Delay (ns):                  0.881
  Slack (ns):                  0.995
  Arrival (ns):                5.277
  Required (ns):               4.282
  Hold (ns):                   1.287


Expanded Path 1
  From: fic_master_trans_0/HADDR_TEMP[28]/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[28]
  data arrival time                              5.198
  data required time                         -   4.316
  slack                                          0.882
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.328          net: FAB_CLK
  4.363                        fic_master_trans_0/HADDR_TEMP[28]/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.612                        fic_master_trans_0/HADDR_TEMP[28]/U1:Q (r)
               +     0.347          net: _fic_master_trans_0_HADDR_[28]_
  4.959                        mss_top_0/MSS_ADLIB_INST/U_46:PIN4 (r)
               +     0.037          cell: ADLIB:MSS_IF
  4.996                        mss_top_0/MSS_ADLIB_INST/U_46:PIN4INT (r)
               +     0.202          net: mss_top_0/MSS_ADLIB_INST/FABHADDR[28]INT_NET
  5.198                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[28] (r)
                                    
  5.198                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.271          net: mss_top_0/GLA0
  2.995                        mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.321          Library hold time: ADLIB:MSS_AHB_IP
  4.316                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[28]
                                    
  4.316                        data required time


END SET mss_ccc_gla1 to mss_ccc_gla0

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain Input_clk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          FAB_CLK
  Delay (ns):                  5.789
  Slack (ns):
  Arrival (ns):                5.789
  Required (ns):
  Clock to Out (ns):           5.789


Expanded Path 1
  From: mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: FAB_CLK
  data arrival time                              5.789
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Input_clk
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     4.035          cell: ADLIB:MSS_CCC_IP
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.387          net: FAB_CLK
  4.422                        FAB_CLK_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  4.701                        FAB_CLK_pad/U0/U1:DOUT (r)
               +     0.000          net: FAB_CLK_pad/U0/NET1
  4.701                        FAB_CLK_pad/U0/U0:D (r)
               +     1.088          cell: ADLIB:IOPAD_TRI
  5.789                        FAB_CLK_pad/U0/U0:PAD (r)
               +     0.000          net: FAB_CLK_c
  5.789                        FAB_CLK (r)
                                    
  5.789                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          Input_clk
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          FAB_CLK (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain FAB_CLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

