Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Dec 07 16:54:04 2011


Design: top_level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      8.254
Max Clock-To-Out (ns):      16.310

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      8.883
Max Clock-To-Out (ns):      16.861

Clock Domain:               mss_ccc_gla1
Period (ns):                9.424
Frequency (MHz):            106.112
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.206
External Hold (ns):         4.012
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                25.000
Frequency (MHz):            40.000
Required Period (ns):       20.833
Required Frequency (MHz):   48.001
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               Input_clk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       50.000
Required Frequency (MHz):   20.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      5.789
Max Clock-To-Out (ns):      9.891

Clock Domain:               FAB_CLK
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          FABHREADYOUT
  Delay (ns):                  12.306
  Slack (ns):
  Arrival (ns):                16.310
  Required (ns):
  Clock to Out (ns):           16.310


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: FABHREADYOUT
  data required time                             N/C
  data arrival time                          -   16.310
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  4.004
               +     5.428          cell: ADLIB:MSS_AHB_IP
  9.432                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (f)
               +     0.191          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  9.623                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (f)
               +     0.088          cell: ADLIB:MSS_IF
  9.711                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (f)
               +     2.630          net: FABHREADYOUT_c
  12.341                       FABHREADYOUT_pad/U0/U1:D (f)
               +     0.600          cell: ADLIB:IOTRI_OB_EB
  12.941                       FABHREADYOUT_pad/U0/U1:DOUT (f)
               +     0.000          net: FABHREADYOUT_pad/U0/NET1
  12.941                       FABHREADYOUT_pad/U0/U0:D (f)
               +     3.369          cell: ADLIB:IOPAD_TRI
  16.310                       FABHREADYOUT_pad/U0/U0:PAD (f)
               +     0.000          net: FABHREADYOUT
  16.310                       FABHREADYOUT (f)
                                    
  16.310                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  N/C
                                    
  N/C                          FABHREADYOUT (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        fic_master_trans_0/HSEL/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  Delay (ns):                  2.467
  Slack (ns):                  4.381
  Arrival (ns):                8.394
  Required (ns):               12.775
  Setup (ns):                  3.729

Path 2
  From:                        fic_master_trans_0/HSEL/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWRITE
  Delay (ns):                  3.677
  Slack (ns):                  5.190
  Arrival (ns):                9.604
  Required (ns):               14.794
  Setup (ns):                  1.710

Path 3
  From:                        fic_master_trans_0/HSEL/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHSIZE[1]
  Delay (ns):                  2.674
  Slack (ns):                  5.405
  Arrival (ns):                8.601
  Required (ns):               14.006
  Setup (ns):                  2.498

Path 4
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[6]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[6]
  Delay (ns):                  3.427
  Slack (ns):                  7.510
  Arrival (ns):                9.354
  Required (ns):               16.864
  Setup (ns):                  -0.360

Path 5
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHWDATA[4]
  Delay (ns):                  2.811
  Slack (ns):                  8.029
  Arrival (ns):                8.743
  Required (ns):               16.772
  Setup (ns):                  -0.268


Expanded Path 1
  From: fic_master_trans_0/HSEL/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
  data required time                             12.775
  data arrival time                          -   8.394
  slack                                          4.381
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.678          net: FAB_CLK
  5.927                        fic_master_trans_0/HSEL/U1:CLK (r)
               +     0.528          cell: ADLIB:DFN1C0
  6.455                        fic_master_trans_0/HSEL/U1:Q (r)
               +     1.860          net: fic_master_trans_0_HSEL
  8.315                        mss_top_0/MSS_ADLIB_INST/U_60:PIN4 (r)
               +     0.079          cell: ADLIB:MSS_IF
  8.394                        mss_top_0/MSS_ADLIB_INST/U_60:PIN4INT (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/FABHTRANS1INT_NET
  8.394                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1 (r)
                                    
  8.394                        data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_fabric_interface_clock
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  16.504
               -     3.729          Library setup time: ADLIB:MSS_AHB_IP
  12.775                       mss_top_0/MSS_ADLIB_INST/U_CORE:FABHTRANS1
                                    
  12.775                       data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          M2F_GPO_0
  Delay (ns):                  12.857
  Slack (ns):
  Arrival (ns):                16.861
  Required (ns):
  Clock to Out (ns):           16.861


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: M2F_GPO_0
  data required time                             N/C
  data arrival time                          -   16.861
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.004          Clock generation
  4.004
               +     4.163          cell: ADLIB:MSS_AHB_IP
  8.167                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (f)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  8.167                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (f)
               +     0.088          cell: ADLIB:MSS_IF
  8.255                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (f)
               +     4.755          net: mss_top_0/MSSINT_GPO_0_A
  13.010                       M2F_GPO_0_pad/U0/U1:D (f)
               +     0.600          cell: ADLIB:IOTRI_OB_EB
  13.610                       M2F_GPO_0_pad/U0/U1:DOUT (f)
               +     0.000          net: M2F_GPO_0_pad/U0/NET1
  13.610                       M2F_GPO_0_pad/U0/U0:D (f)
               +     3.251          cell: ADLIB:IOPAD_TRI
  16.861                       M2F_GPO_0_pad/U0/U0:PAD (f)
               +     0.000          net: M2F_GPO_0
  16.861                       M2F_GPO_0 (f)
                                    
  16.861                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.004          Clock generation
  N/C
                                    
  N/C                          M2F_GPO_0 (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[0]:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[14]/U1:D
  Delay (ns):                  8.943
  Slack (ns):                  3.076
  Arrival (ns):                14.875
  Required (ns):               17.951
  Setup (ns):                  0.522
  Minimum Period (ns):         9.424

Path 2
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLK
  To:                          fic_master_trans_0/HSEL/U1:D
  Delay (ns):                  8.856
  Slack (ns):                  3.149
  Arrival (ns):                14.788
  Required (ns):               17.937
  Setup (ns):                  0.490
  Minimum Period (ns):         9.351

Path 3
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[0]:CLK
  To:                          fic_master_trans_0/HSEL/U1:D
  Delay (ns):                  8.855
  Slack (ns):                  3.150
  Arrival (ns):                14.787
  Required (ns):               17.937
  Setup (ns):                  0.490
  Minimum Period (ns):         9.350

Path 4
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[14]/U1:D
  Delay (ns):                  8.843
  Slack (ns):                  3.181
  Arrival (ns):                14.770
  Required (ns):               17.951
  Setup (ns):                  0.522
  Minimum Period (ns):         9.319

Path 5
  From:                        fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLK
  To:                          fic_master_trans_0/HADDR_TEMP[31]/U1:D
  Delay (ns):                  8.728
  Slack (ns):                  3.228
  Arrival (ns):                14.660
  Required (ns):               17.888
  Setup (ns):                  0.522
  Minimum Period (ns):         9.272


Expanded Path 1
  From: fic_master_trans_0/HWRITE_DATA_TEMP[0]:CLK
  To: fic_master_trans_0/HADDR_TEMP[14]/U1:D
  data required time                             17.951
  data arrival time                          -   14.875
  slack                                          3.076
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.683          net: FAB_CLK
  5.932                        fic_master_trans_0/HWRITE_DATA_TEMP[0]:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  6.603                        fic_master_trans_0/HWRITE_DATA_TEMP[0]:Q (f)
               +     0.409          net: _fic_master_trans_0_HWDATA_[0]_
  7.012                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIPM28[0]:B (f)
               +     0.571          cell: ADLIB:NOR2B
  7.583                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIPM28[0]:Y (f)
               +     1.210          net: fic_master_trans_0/HWRITE_DATA_TEMP_c1
  8.793                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIMT5G[3]:A (f)
               +     0.351          cell: ADLIB:OR2B
  9.144                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIMT5G[3]:Y (r)
               +     0.427          net: fic_master_trans_0/un6_hreadyout_5
  9.571                        fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[5]:B (r)
               +     0.821          cell: ADLIB:OA1
  10.392                       fic_master_trans_0/HWRITE_DATA_TEMP_RNIJUO61[5]:Y (r)
               +     1.541          net: fic_master_trans_0/un1_hreadyout
  11.933                       fic_master_trans_0/ahb_states_RNIHRUB2_0[0]:A (r)
               +     0.517          cell: ADLIB:MX2
  12.450                       fic_master_trans_0/ahb_states_RNIHRUB2_0[0]:Y (r)
               +     1.790          net: fic_master_trans_0/un2_hreadyout_0[0]
  14.240                       fic_master_trans_0/HADDR_TEMP[14]/U0:S (r)
               +     0.339          cell: ADLIB:MX2
  14.579                       fic_master_trans_0/HADDR_TEMP[14]/U0:Y (f)
               +     0.296          net: fic_master_trans_0/HADDR_TEMP[14]/Y
  14.875                       fic_master_trans_0/HADDR_TEMP[14]/U1:D (f)
                                    
  14.875                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.724          net: FAB_CLK
  18.473                       fic_master_trans_0/HADDR_TEMP[14]/U1:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1P0
  17.951                       fic_master_trans_0/HADDR_TEMP[14]/U1:D
                                    
  17.951                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HSEL/U1:D
  Delay (ns):                  12.834
  Slack (ns):                  1.067
  Arrival (ns):                16.838
  Required (ns):               17.905
  Setup (ns):                  0.522

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[31]/U1:D
  Delay (ns):                  12.795
  Slack (ns):                  1.121
  Arrival (ns):                16.799
  Required (ns):               17.920
  Setup (ns):                  0.490

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[27]/U1:D
  Delay (ns):                  12.780
  Slack (ns):                  1.158
  Arrival (ns):                16.784
  Required (ns):               17.942
  Setup (ns):                  0.490

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[30]/U1:D
  Delay (ns):                  12.663
  Slack (ns):                  1.270
  Arrival (ns):                16.667
  Required (ns):               17.937
  Setup (ns):                  0.490

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          fic_master_trans_0/HADDR_TEMP[14]/U1:D
  Delay (ns):                  12.499
  Slack (ns):                  1.480
  Arrival (ns):                16.503
  Required (ns):               17.983
  Setup (ns):                  0.490


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: fic_master_trans_0/HSEL/U1:D
  data required time                             17.905
  data arrival time                          -   16.838
  slack                                          1.067
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  4.004
               +     5.428          cell: ADLIB:MSS_AHB_IP
  9.432                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHREADYOUT (f)
               +     0.191          net: mss_top_0/MSS_ADLIB_INST/FABHREADYOUTINT_NET
  9.623                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1INT (f)
               +     0.088          cell: ADLIB:MSS_IF
  9.711                        mss_top_0/MSS_ADLIB_INST/U_92:PIN1 (f)
               +     1.980          net: FABHREADYOUT_c
  11.691                       fic_master_trans_0/HWRITE_DATA_TEMP_RNI7LN21[1]:B (f)
               +     0.571          cell: ADLIB:NOR2B
  12.262                       fic_master_trans_0/HWRITE_DATA_TEMP_RNI7LN21[1]:Y (f)
               +     1.330          net: fic_master_trans_0/un9_hreadyout
  13.592                       fic_master_trans_0/ahb_states_RNIHRUB2[0]:B (f)
               +     0.563          cell: ADLIB:MX2
  14.155                       fic_master_trans_0/ahb_states_RNIHRUB2[0]:Y (f)
               +     1.860          net: fic_master_trans_0/ahb_states_RNIHRUB2[0]
  16.015                       fic_master_trans_0/HSEL/U0:A (f)
               +     0.527          cell: ADLIB:MX2
  16.542                       fic_master_trans_0/HSEL/U0:Y (f)
               +     0.296          net: fic_master_trans_0/HSEL/Y
  16.838                       fic_master_trans_0/HSEL/U1:D (f)
                                    
  16.838                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.678          net: FAB_CLK
  18.427                       fic_master_trans_0/HSEL/U1:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1C0
  17.905                       fic_master_trans_0/HSEL/U1:D
                                    
  17.905                       data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_pclk1 to mss_ccc_gla1

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLR
  Delay (ns):                  8.538
  Slack (ns):                  5.614
  Arrival (ns):                12.542
  Required (ns):               18.156
  Setup (ns):

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[3]/U1:CLR
  Delay (ns):                  8.538
  Slack (ns):                  5.619
  Arrival (ns):                12.542
  Required (ns):               18.161
  Setup (ns):

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[5]/U1:CLR
  Delay (ns):                  8.538
  Slack (ns):                  5.619
  Arrival (ns):                12.542
  Required (ns):               18.161
  Setup (ns):

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[4]/U1:CLR
  Delay (ns):                  8.538
  Slack (ns):                  5.619
  Arrival (ns):                12.542
  Required (ns):               18.161
  Setup (ns):

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To:                          fic_master_trans_0/HWRITE_DATA_TEMP[0]:CLR
  Delay (ns):                  8.538
  Slack (ns):                  5.619
  Arrival (ns):                12.542
  Required (ns):               18.161
  Setup (ns):


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1
  To: fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLR
  data required time                             18.156
  data arrival time                          -   12.542
  slack                                          5.614
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.004          Clock generation
  4.004
               +     4.440          cell: ADLIB:MSS_AHB_IP
  8.444                        mss_top_0/MSS_ADLIB_INST/U_CORE:GPO[0] (r)
               +     0.000          net: mss_top_0/MSS_ADLIB_INST/GPO[0]INT_NET
  8.444                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1INT (r)
               +     0.089          cell: ADLIB:MSS_IF
  8.533                        mss_top_0/MSS_ADLIB_INST/U_20:PIN1 (r)
               +     4.009          net: mss_top_0/MSSINT_GPO_0_A
  12.542                       fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLR (r)
                                    
  12.542                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.678          net: FAB_CLK
  18.427                       fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1C0
  18.156                       fic_master_trans_0/HWRITE_DATA_TEMP[1]/U1:CLR
                                    
  18.156                       data required time


END SET mss_pclk1 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.139
  External Setup (ns):         -5.206


Expanded Path 1
  From: MSS_RESET_N
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        mss_top_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        mss_top_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: mss_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.459          net: mss_top_0/GLA0
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.139          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_ccc_gla0

Path 1
  From:                        fic_master_trans_0/HADDR_TEMP[10]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[10]
  Delay (ns):                  2.705
  Slack (ns):                  1.313
  Arrival (ns):                8.690
  Required (ns):               10.003
  Setup (ns):                  6.501

Path 2
  From:                        fic_master_trans_0/HADDR_TEMP[8]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[8]
  Delay (ns):                  2.717
  Slack (ns):                  1.570
  Arrival (ns):                8.639
  Required (ns):               10.209
  Setup (ns):                  6.295

Path 3
  From:                        fic_master_trans_0/HADDR_TEMP[17]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[17]
  Delay (ns):                  2.560
  Slack (ns):                  1.608
  Arrival (ns):                8.545
  Required (ns):               10.153
  Setup (ns):                  6.351

Path 4
  From:                        fic_master_trans_0/HADDR_TEMP[12]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[12]
  Delay (ns):                  2.378
  Slack (ns):                  1.701
  Arrival (ns):                8.305
  Required (ns):               10.006
  Setup (ns):                  6.498

Path 5
  From:                        fic_master_trans_0/HADDR_TEMP[21]/U1:CLK
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[21]
  Delay (ns):                  2.583
  Slack (ns):                  1.765
  Arrival (ns):                8.510
  Required (ns):               10.275
  Setup (ns):                  6.229


Expanded Path 1
  From: fic_master_trans_0/HADDR_TEMP[10]/U1:CLK
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[10]
  data required time                             10.003
  data arrival time                          -   8.690
  slack                                          1.313
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.736          net: FAB_CLK
  5.985                        fic_master_trans_0/HADDR_TEMP[10]/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1P0
  6.656                        fic_master_trans_0/HADDR_TEMP[10]/U1:Q (f)
               +     1.247          net: _fic_master_trans_0_HADDR_[10]_
  7.903                        mss_top_0/MSS_ADLIB_INST/U_33:PIN4 (f)
               +     0.190          cell: ADLIB:MSS_IF
  8.093                        mss_top_0/MSS_ADLIB_INST/U_33:PIN4INT (f)
               +     0.597          net: mss_top_0/MSS_ADLIB_INST/FABHADDR[10]INT_NET
  8.690                        mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[10] (f)
                                    
  8.690                        data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla0
               +     0.000          Clock source
  12.500                       mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  16.045
               +     0.459          net: mss_top_0/GLA0
  16.504                       mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -     6.501          Library setup time: ADLIB:MSS_AHB_IP
  10.003                       mss_top_0/MSS_ADLIB_INST/U_CORE:FABHADDR[10]
                                    
  10.003                       data required time


END SET mss_ccc_gla1 to mss_ccc_gla0

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain Input_clk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          FAB_CLK
  Delay (ns):                  9.891
  Slack (ns):
  Arrival (ns):                9.891
  Required (ns):
  Clock to Out (ns):           9.891


Expanded Path 1
  From: mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: FAB_CLK
  data required time                             N/C
  data arrival time                          -   9.891
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Input_clk
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     5.249          cell: ADLIB:MSS_CCC_IP
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (f)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (f)
               +     0.791          net: FAB_CLK
  6.040                        FAB_CLK_pad/U0/U1:D (f)
               +     0.600          cell: ADLIB:IOTRI_OB_EB
  6.640                        FAB_CLK_pad/U0/U1:DOUT (f)
               +     0.000          net: FAB_CLK_pad/U0/NET1
  6.640                        FAB_CLK_pad/U0/U0:D (f)
               +     3.251          cell: ADLIB:IOPAD_TRI
  9.891                        FAB_CLK_pad/U0/U0:PAD (f)
               +     0.000          net: FAB_CLK_c
  9.891                        FAB_CLK (f)
                                    
  9.891                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          Input_clk
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          FAB_CLK (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain FAB_CLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

